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mfd: omap-usb-host: Get rid of unnecessary spinlock
[linux-2.6-block.git] / drivers / mfd / omap-usb-host.c
CommitLineData
17cdd29d
KM		 1/**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#include <linux/kernel.h>
417e206b 20#include <linux/module.h>
17cdd29d
KM		 21#include <linux/types.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
17cdd29d
KM		 24#include <linux/clk.h>
25#include <linux/dma-mapping.h>
c05995c3 26#include <linux/gpio.h>
e8c4a7ac
FB		 27#include <linux/platform_device.h>
28#include <linux/platform_data/usb-omap.h>
1e7fe1a9 29#include <linux/pm_runtime.h>
17cdd29d 30
e8c4a7ac
FB		 31#include "omap-usb.h"
32
a6d3a662 33#define USBHS_DRIVER_NAME "usbhs_omap"
17cdd29d
KM		 34#define OMAP_EHCI_DEVICE "ehci-omap"
35#define OMAP_OHCI_DEVICE "ohci-omap3"
36
37/* OMAP USBHOST Register addresses */
38
17cdd29d
KM		 39/* UHH Register Set */
40#define OMAP_UHH_REVISION (0x00)
41#define OMAP_UHH_SYSCONFIG (0x10)
42#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
43#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
44#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
45#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
46#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
47#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
48
49#define OMAP_UHH_SYSSTATUS (0x14)
50#define OMAP_UHH_HOSTCONFIG (0x40)
51#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
52#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
53#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
54#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
55#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
56#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
57#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
58#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
59#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
60#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
61#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
62#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
63
64/* OMAP4-specific defines */
65#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
66#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
67#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
68#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
69#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
70
71#define OMAP4_P1_MODE_CLEAR (3 << 16)
72#define OMAP4_P1_MODE_TLL (1 << 16)
73#define OMAP4_P1_MODE_HSIC (3 << 16)
74#define OMAP4_P2_MODE_CLEAR (3 << 18)
75#define OMAP4_P2_MODE_TLL (1 << 18)
76#define OMAP4_P2_MODE_HSIC (3 << 18)
77
17cdd29d
KM		 78#define OMAP_UHH_DEBUG_CSR (0x44)
79
80/* Values of UHH_REVISION - Note: these are not given in the TRM */
81#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
82#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
83
84#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
85#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
86
87#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
88#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
89#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
90
91
92struct usbhs_hcd_omap {
d7eaf866 93 int nports;
06ba7dc7 94 struct clk **utmi_clk;
340c64ea
RQ		 95 struct clk **hsic60m_clk;
96 struct clk **hsic480m_clk;
d7eaf866 97
17cdd29d
KM		 98 struct clk *xclk60mhsp1_ck;
99 struct clk *xclk60mhsp2_ck;
06ba7dc7
RQ		 100 struct clk *utmi_p1_gfclk;
101 struct clk *utmi_p2_gfclk;
17cdd29d 102 struct clk *init_60m_fclk;
1e7fe1a9 103 struct clk *ehci_logic_fck;
17cdd29d
KM		 104
105 void __iomem *uhh_base;
17cdd29d 106
9d9c6ae7 107 struct usbhs_omap_platform_data *pdata;
17cdd29d
KM		 108
109 u32 usbhs_rev;
17cdd29d
KM		 110};
111/*-------------------------------------------------------------------------*/
112
113const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
cbb8c220 114static u64 usbhs_dmamask = DMA_BIT_MASK(32);
17cdd29d
KM		 115
116/*-------------------------------------------------------------------------*/
117
118static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
119{
120 __raw_writel(val, base + reg);
121}
122
123static inline u32 usbhs_read(void __iomem *base, u32 reg)
124{
125 return __raw_readl(base + reg);
126}
127
128static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
129{
130 __raw_writeb(val, base + reg);
131}
132
133static inline u8 usbhs_readb(void __iomem *base, u8 reg)
134{
135 return __raw_readb(base + reg);
136}
137
138/*-------------------------------------------------------------------------*/
139
140static struct platform_device *omap_usbhs_alloc_child(const char *name,
141 struct resource *res, int num_resources, void *pdata,
142 size_t pdata_size, struct device *dev)
143{
144 struct platform_device *child;
145 int ret;
146
147 child = platform_device_alloc(name, 0);
148
149 if (!child) {
150 dev_err(dev, "platform_device_alloc %s failed\n", name);
151 goto err_end;
152 }
153
154 ret = platform_device_add_resources(child, res, num_resources);
155 if (ret) {
156 dev_err(dev, "platform_device_add_resources failed\n");
157 goto err_alloc;
158 }
159
160 ret = platform_device_add_data(child, pdata, pdata_size);
161 if (ret) {
162 dev_err(dev, "platform_device_add_data failed\n");
163 goto err_alloc;
164 }
165
166 child->dev.dma_mask = &usbhs_dmamask;
cbb8c220 167 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
17cdd29d
KM		 168 child->dev.parent = dev;
169
170 ret = platform_device_add(child);
171 if (ret) {
172 dev_err(dev, "platform_device_add failed\n");
173 goto err_alloc;
174 }
175
176 return child;
177
178err_alloc:
179 platform_device_put(child);
180
181err_end:
182 return NULL;
183}
184
185static int omap_usbhs_alloc_children(struct platform_device *pdev)
186{
187 struct device *dev = &pdev->dev;
9d9c6ae7 188 struct usbhs_omap_platform_data *pdata = dev->platform_data;
17cdd29d
KM		 189 struct platform_device *ehci;
190 struct platform_device *ohci;
191 struct resource *res;
192 struct resource resources[2];
193 int ret;
194
17cdd29d
KM		 195 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
196 if (!res) {
197 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
198 ret = -ENODEV;
199 goto err_end;
200 }
201 resources[0] = *res;
202
203 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
204 if (!res) {
205 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
206 ret = -ENODEV;
207 goto err_end;
208 }
209 resources[1] = *res;
210
9d9c6ae7
RQ		 211 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
212 sizeof(*pdata), dev);
17cdd29d
KM		 213
214 if (!ehci) {
215 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 216 ret = -ENOMEM;
17cdd29d
KM		 217 goto err_end;
218 }
219
220 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
221 if (!res) {
222 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
223 ret = -ENODEV;
224 goto err_ehci;
225 }
226 resources[0] = *res;
227
228 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
229 if (!res) {
230 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
231 ret = -ENODEV;
232 goto err_ehci;
233 }
234 resources[1] = *res;
235
9d9c6ae7
RQ		 236 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
237 sizeof(*pdata), dev);
17cdd29d
KM		 238 if (!ohci) {
239 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 240 ret = -ENOMEM;
17cdd29d
KM		 241 goto err_ehci;
242 }
243
244 return 0;
245
246err_ehci:
d910774f 247 platform_device_unregister(ehci);
17cdd29d
KM		 248
249err_end:
250 return ret;
251}
252
17cdd29d
KM		 253static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
254{
255 switch (pmode) {
256 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
257 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
258 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
259 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
260 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
261 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
262 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
263 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
264 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
265 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
266 return true;
267
268 default:
269 return false;
270 }
271}
272
1e7fe1a9 273static int usbhs_runtime_resume(struct device *dev)
17cdd29d
KM		 274{
275 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 276 struct usbhs_omap_platform_data *pdata = omap->pdata;
06ba7dc7 277 int i, r;
1e7fe1a9
KM		 278
279 dev_dbg(dev, "usbhs_runtime_resume\n");
17cdd29d 280
4dc2cceb 281 omap_tll_enable();
17cdd29d 282
06ba7dc7 283 if (!IS_ERR(omap->ehci_logic_fck))
1e7fe1a9
KM		 284 clk_enable(omap->ehci_logic_fck);
285
06ba7dc7 286 for (i = 0; i < omap->nports; i++) {
340c64ea
RQ		 287 switch (pdata->port_mode[i]) {
288 case OMAP_EHCI_PORT_MODE_HSIC:
289 if (!IS_ERR(omap->hsic60m_clk[i])) {
290 r = clk_enable(omap->hsic60m_clk[i]);
291 if (r) {
292 dev_err(dev,
293 "Can't enable port %d hsic60m clk:%d\n",
294 i, r);
295 }
296 }
297
298 if (!IS_ERR(omap->hsic480m_clk[i])) {
299 r = clk_enable(omap->hsic480m_clk[i]);
300 if (r) {
301 dev_err(dev,
302 "Can't enable port %d hsic480m clk:%d\n",
303 i, r);
304 }
305 }
306 /* Fall through as HSIC mode needs utmi_clk */
307
308 case OMAP_EHCI_PORT_MODE_TLL:
309 if (!IS_ERR(omap->utmi_clk[i])) {
310 r = clk_enable(omap->utmi_clk[i]);
311 if (r) {
312 dev_err(dev,
313 "Can't enable port %d clk : %d\n",
314 i, r);
315 }
316 }
317 break;
318 default:
319 break;
320 }
06ba7dc7 321 }
1e7fe1a9 322
1e7fe1a9
KM		 323 return 0;
324}
325
326static int usbhs_runtime_suspend(struct device *dev)
327{
328 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 329 struct usbhs_omap_platform_data *pdata = omap->pdata;
06ba7dc7 330 int i;
1e7fe1a9
KM		 331
332 dev_dbg(dev, "usbhs_runtime_suspend\n");
333
06ba7dc7 334 for (i = 0; i < omap->nports; i++) {
340c64ea
RQ		 335 switch (pdata->port_mode[i]) {
336 case OMAP_EHCI_PORT_MODE_HSIC:
337 if (!IS_ERR(omap->hsic60m_clk[i]))
338 clk_disable(omap->hsic60m_clk[i]);
339
340 if (!IS_ERR(omap->hsic480m_clk[i]))
341 clk_disable(omap->hsic480m_clk[i]);
342 /* Fall through as utmi_clks were used in HSIC mode */
343
344 case OMAP_EHCI_PORT_MODE_TLL:
345 if (!IS_ERR(omap->utmi_clk[i]))
346 clk_disable(omap->utmi_clk[i]);
347 break;
348 default:
349 break;
350 }
06ba7dc7 351 }
1e7fe1a9 352
06ba7dc7 353 if (!IS_ERR(omap->ehci_logic_fck))
1e7fe1a9
KM		 354 clk_disable(omap->ehci_logic_fck);
355
4dc2cceb 356 omap_tll_disable();
1e7fe1a9
KM		 357
358 return 0;
359}
360
361static void omap_usbhs_init(struct device *dev)
362{
363 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 364 struct usbhs_omap_platform_data *pdata = omap->pdata;
1e7fe1a9
KM		 365 unsigned reg;
366
367 dev_dbg(dev, "starting TI HSUSB Controller\n");
368
9d9c6ae7
RQ		 369 if (pdata->phy_reset) {
370 if (gpio_is_valid(pdata->reset_gpio_port[0]))
371 gpio_request_one(pdata->reset_gpio_port[0],
c05995c3
RD		 372 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
373
9d9c6ae7
RQ		 374 if (gpio_is_valid(pdata->reset_gpio_port[1]))
375 gpio_request_one(pdata->reset_gpio_port[1],
c05995c3
RD		 376 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
377
378 /* Hold the PHY in RESET for enough time till DIR is high */
379 udelay(10);
380 }
381
760189b3 382 pm_runtime_get_sync(dev);
17cdd29d 383
17cdd29d
KM		 384 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
385 /* setup ULPI bypass and burst configurations */
386 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
387 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
388 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
389 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
390 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
391
392 if (is_omap_usbhs_rev1(omap)) {
393 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
394 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
395 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
396 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
397 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
398 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
399
400 /* Bypass the TLL module for PHY mode operation */
63b68901 401 if (pdata->single_ulpi_bypass) {
17cdd29d
KM		 402 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
403 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
404 is_ehci_phy_mode(pdata->port_mode[1]) ||
405 is_ehci_phy_mode(pdata->port_mode[2]))
406 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
407 else
408 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
409 } else {
410 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
411 if (is_ehci_phy_mode(pdata->port_mode[0]))
412 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
413 else
414 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
415 if (is_ehci_phy_mode(pdata->port_mode[1]))
416 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
417 else
418 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
419 if (is_ehci_phy_mode(pdata->port_mode[2]))
420 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
421 else
422 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
423 }
424 } else if (is_omap_usbhs_rev2(omap)) {
425 /* Clear port mode fields for PHY mode*/
426 reg &= ~OMAP4_P1_MODE_CLEAR;
427 reg &= ~OMAP4_P2_MODE_CLEAR;
428
17cdd29d
KM		 429 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
430 (is_ohci_port(pdata->port_mode[0])))
431 reg |= OMAP4_P1_MODE_TLL;
432 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
433 reg |= OMAP4_P1_MODE_HSIC;
434
435 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
436 (is_ohci_port(pdata->port_mode[1])))
437 reg |= OMAP4_P2_MODE_TLL;
438 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
439 reg |= OMAP4_P2_MODE_HSIC;
440 }
441
442 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
443 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
444
760189b3 445 pm_runtime_put_sync(dev);
9d9c6ae7 446 if (pdata->phy_reset) {
c05995c3
RD		 447 /* Hold the PHY in RESET for enough time till
448 * PHY is settled and ready
449 */
450 udelay(10);
451
9d9c6ae7 452 if (gpio_is_valid(pdata->reset_gpio_port[0]))
c05995c3 453 gpio_set_value_cansleep
9d9c6ae7 454 (pdata->reset_gpio_port[0], 1);
c05995c3 455
9d9c6ae7 456 if (gpio_is_valid(pdata->reset_gpio_port[1]))
c05995c3 457 gpio_set_value_cansleep
9d9c6ae7 458 (pdata->reset_gpio_port[1], 1);
c05995c3 459 }
1e7fe1a9
KM		 460}
461
c05995c3
RD		 462static void omap_usbhs_deinit(struct device *dev)
463{
464 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
9d9c6ae7 465 struct usbhs_omap_platform_data *pdata = omap->pdata;
c05995c3 466
9d9c6ae7
RQ		 467 if (pdata->phy_reset) {
468 if (gpio_is_valid(pdata->reset_gpio_port[0]))
469 gpio_free(pdata->reset_gpio_port[0]);
c05995c3 470
9d9c6ae7
RQ		 471 if (gpio_is_valid(pdata->reset_gpio_port[1]))
472 gpio_free(pdata->reset_gpio_port[1]);
c05995c3
RD		 473 }
474}
475
1e7fe1a9
KM		 476
477/**
478 * usbhs_omap_probe - initialize TI-based HCDs
479 *
480 * Allocates basic resources for this USB host controller.
481 */
f791be49 482static int usbhs_omap_probe(struct platform_device *pdev)
17cdd29d 483{
1e7fe1a9
KM		 484 struct device *dev = &pdev->dev;
485 struct usbhs_omap_platform_data *pdata = dev->platform_data;
486 struct usbhs_hcd_omap *omap;
487 struct resource *res;
488 int ret = 0;
489 int i;
06ba7dc7 490 bool need_logic_fck;
17cdd29d 491
1e7fe1a9
KM		 492 if (!pdata) {
493 dev_err(dev, "Missing platform data\n");
27d4f2c6 494 return -ENODEV;
1e7fe1a9 495 }
17cdd29d 496
27d4f2c6 497 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
1e7fe1a9
KM		 498 if (!omap) {
499 dev_err(dev, "Memory allocation failed\n");
27d4f2c6
RQ		 500 return -ENOMEM;
501 }
502
503 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
504 omap->uhh_base = devm_request_and_ioremap(dev, res);
505 if (!omap->uhh_base) {
506 dev_err(dev, "Resource request/ioremap failed\n");
507 return -EADDRNOTAVAIL;
1e7fe1a9 508 }
17cdd29d 509
9d9c6ae7 510 omap->pdata = pdata;
17cdd29d 511
1e7fe1a9 512 pm_runtime_enable(dev);
17cdd29d 513
d7eaf866
RQ		 514 platform_set_drvdata(pdev, omap);
515 pm_runtime_get_sync(dev);
516
517 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
518
519 /* we need to call runtime suspend before we update omap->nports
520 * to prevent unbalanced clk_disable()
521 */
522 pm_runtime_put_sync(dev);
523
ccac71a7
RQ		 524 /*
525 * If platform data contains nports then use that
526 * else make out number of ports from USBHS revision
527 */
528 if (pdata->nports) {
529 omap->nports = pdata->nports;
530 } else {
531 switch (omap->usbhs_rev) {
532 case OMAP_USBHS_REV1:
533 omap->nports = 3;
534 break;
535 case OMAP_USBHS_REV2:
536 omap->nports = 2;
537 break;
538 default:
539 omap->nports = OMAP3_HS_USB_PORTS;
540 dev_dbg(dev,
541 "USB HOST Rev:0x%d not recognized, assuming %d ports\n",
542 omap->usbhs_rev, omap->nports);
543 break;
544 }
d7eaf866
RQ		 545 }
546
06ba7dc7
RQ		 547 i = sizeof(struct clk *) * omap->nports;
548 omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
340c64ea
RQ		 549 omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
550 omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
551
552 if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) {
06ba7dc7
RQ		 553 dev_err(dev, "Memory allocation failed\n");
554 ret = -ENOMEM;
555 goto err_mem;
556 }
557
558 need_logic_fck = false;
559 for (i = 0; i < omap->nports; i++) {
1e7fe1a9 560 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
06ba7dc7
RQ		 561 is_ehci_hsic_mode(i))
562 need_logic_fck |= true;
563 }
564
565 omap->ehci_logic_fck = ERR_PTR(-EINVAL);
566 if (need_logic_fck) {
567 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
568 if (IS_ERR(omap->ehci_logic_fck)) {
569 ret = PTR_ERR(omap->ehci_logic_fck);
570 dev_dbg(dev, "ehci_logic_fck failed:%d\n", ret);
1e7fe1a9 571 }
06ba7dc7 572 }
17cdd29d 573
06ba7dc7
RQ		 574 omap->utmi_p1_gfclk = clk_get(dev, "utmi_p1_gfclk");
575 if (IS_ERR(omap->utmi_p1_gfclk)) {
576 ret = PTR_ERR(omap->utmi_p1_gfclk);
577 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
578 goto err_p1_gfclk;
579 }
580
581 omap->utmi_p2_gfclk = clk_get(dev, "utmi_p2_gfclk");
582 if (IS_ERR(omap->utmi_p2_gfclk)) {
583 ret = PTR_ERR(omap->utmi_p2_gfclk);
584 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
585 goto err_p2_gfclk;
17cdd29d
KM		 586 }
587
1e7fe1a9
KM		 588 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
589 if (IS_ERR(omap->xclk60mhsp1_ck)) {
590 ret = PTR_ERR(omap->xclk60mhsp1_ck);
591 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
06ba7dc7 592 goto err_xclk60mhsp1;
17cdd29d
KM		 593 }
594
1e7fe1a9
KM		 595 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
596 if (IS_ERR(omap->xclk60mhsp2_ck)) {
597 ret = PTR_ERR(omap->xclk60mhsp2_ck);
598 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
06ba7dc7 599 goto err_xclk60mhsp2;
17cdd29d
KM		 600 }
601
1e7fe1a9
KM		 602 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
603 if (IS_ERR(omap->init_60m_fclk)) {
604 ret = PTR_ERR(omap->init_60m_fclk);
605 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
06ba7dc7
RQ		 606 goto err_init60m;
607 }
608
609 for (i = 0; i < omap->nports; i++) {
340c64ea 610 char clkname[30];
06ba7dc7
RQ		 611
612 /* clock names are indexed from 1*/
613 snprintf(clkname, sizeof(clkname),
614 "usb_host_hs_utmi_p%d_clk", i + 1);
615
616 /* If a clock is not found we won't bail out as not all
617 * platforms have all clocks and we can function without
618 * them
619 */
620 omap->utmi_clk[i] = clk_get(dev, clkname);
621 if (IS_ERR(omap->utmi_clk[i]))
622 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
623 clkname, PTR_ERR(omap->utmi_clk[i]));
340c64ea
RQ		 624
625 snprintf(clkname, sizeof(clkname),
626 "usb_host_hs_hsic480m_p%d_clk", i + 1);
627 omap->hsic480m_clk[i] = clk_get(dev, clkname);
628 if (IS_ERR(omap->hsic480m_clk[i]))
629 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
630 clkname, PTR_ERR(omap->hsic480m_clk[i]));
631
632 snprintf(clkname, sizeof(clkname),
633 "usb_host_hs_hsic60m_p%d_clk", i + 1);
634 omap->hsic60m_clk[i] = clk_get(dev, clkname);
635 if (IS_ERR(omap->hsic60m_clk[i]))
636 dev_dbg(dev, "Failed to get clock : %s : %ld\n",
637 clkname, PTR_ERR(omap->hsic60m_clk[i]));
17cdd29d
KM		 638 }
639
1e7fe1a9
KM		 640 if (is_ehci_phy_mode(pdata->port_mode[0])) {
641 /* for OMAP3 , the clk set paretn fails */
06ba7dc7 642 ret = clk_set_parent(omap->utmi_p1_gfclk,
1e7fe1a9
KM		 643 omap->xclk60mhsp1_ck);
644 if (ret != 0)
645 dev_err(dev, "xclk60mhsp1_ck set parent"
646 "failed error:%d\n", ret);
647 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
06ba7dc7 648 ret = clk_set_parent(omap->utmi_p1_gfclk,
1e7fe1a9
KM		 649 omap->init_60m_fclk);
650 if (ret != 0)
651 dev_err(dev, "init_60m_fclk set parent"
652 "failed error:%d\n", ret);
653 }
17cdd29d 654
1e7fe1a9 655 if (is_ehci_phy_mode(pdata->port_mode[1])) {
06ba7dc7 656 ret = clk_set_parent(omap->utmi_p2_gfclk,
1e7fe1a9
KM		 657 omap->xclk60mhsp2_ck);
658 if (ret != 0)
659 dev_err(dev, "xclk60mhsp2_ck set parent"
660 "failed error:%d\n", ret);
661 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
06ba7dc7 662 ret = clk_set_parent(omap->utmi_p2_gfclk,
1e7fe1a9
KM		 663 omap->init_60m_fclk);
664 if (ret != 0)
665 dev_err(dev, "init_60m_fclk set parent"
666 "failed error:%d\n", ret);
667 }
6eb6fbbf 668
f0447a69 669 omap_usbhs_init(dev);
1e7fe1a9
KM		 670 ret = omap_usbhs_alloc_children(pdev);
671 if (ret) {
672 dev_err(dev, "omap_usbhs_alloc_children failed\n");
673 goto err_alloc;
674 }
675
27d4f2c6 676 return 0;
1e7fe1a9
KM		 677
678err_alloc:
c05995c3 679 omap_usbhs_deinit(&pdev->dev);
1e7fe1a9 680
340c64ea 681 for (i = 0; i < omap->nports; i++) {
06ba7dc7
RQ		 682 if (!IS_ERR(omap->utmi_clk[i]))
683 clk_put(omap->utmi_clk[i]);
340c64ea
RQ		 684 if (!IS_ERR(omap->hsic60m_clk[i]))
685 clk_put(omap->hsic60m_clk[i]);
686 if (!IS_ERR(omap->hsic480m_clk[i]))
687 clk_put(omap->hsic480m_clk[i]);
688 }
1e7fe1a9 689
06ba7dc7 690 clk_put(omap->init_60m_fclk);
1e7fe1a9 691
06ba7dc7 692err_init60m:
1e7fe1a9
KM		 693 clk_put(omap->xclk60mhsp2_ck);
694
06ba7dc7 695err_xclk60mhsp2:
1e7fe1a9
KM		 696 clk_put(omap->xclk60mhsp1_ck);
697
06ba7dc7
RQ		 698err_xclk60mhsp1:
699 clk_put(omap->utmi_p2_gfclk);
1e7fe1a9 700
06ba7dc7
RQ		 701err_p2_gfclk:
702 clk_put(omap->utmi_p1_gfclk);
703
704err_p1_gfclk:
705 if (!IS_ERR(omap->ehci_logic_fck))
706 clk_put(omap->ehci_logic_fck);
707
708err_mem:
1e7fe1a9 709 pm_runtime_disable(dev);
1e7fe1a9 710
1e7fe1a9 711 return ret;
17cdd29d 712}
17cdd29d 713
1e7fe1a9
KM		 714/**
715 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
716 * @pdev: USB Host Controller being removed
717 *
718 * Reverses the effect of usbhs_omap_probe().
719 */
4740f73f 720static int usbhs_omap_remove(struct platform_device *pdev)
17cdd29d 721{
1e7fe1a9 722 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
06ba7dc7 723 int i;
1e7fe1a9 724
c05995c3 725 omap_usbhs_deinit(&pdev->dev);
06ba7dc7 726
340c64ea 727 for (i = 0; i < omap->nports; i++) {
06ba7dc7
RQ		 728 if (!IS_ERR(omap->utmi_clk[i]))
729 clk_put(omap->utmi_clk[i]);
340c64ea
RQ		 730 if (!IS_ERR(omap->hsic60m_clk[i]))
731 clk_put(omap->hsic60m_clk[i]);
732 if (!IS_ERR(omap->hsic480m_clk[i]))
733 clk_put(omap->hsic480m_clk[i]);
734 }
06ba7dc7 735
1e7fe1a9 736 clk_put(omap->init_60m_fclk);
06ba7dc7
RQ		 737 clk_put(omap->utmi_p1_gfclk);
738 clk_put(omap->utmi_p2_gfclk);
1e7fe1a9 739 clk_put(omap->xclk60mhsp2_ck);
1e7fe1a9 740 clk_put(omap->xclk60mhsp1_ck);
06ba7dc7
RQ		 741
742 if (!IS_ERR(omap->ehci_logic_fck))
743 clk_put(omap->ehci_logic_fck);
744
1e7fe1a9 745 pm_runtime_disable(&pdev->dev);
1e7fe1a9
KM		 746
747 return 0;
17cdd29d 748}
1e7fe1a9
KM		 749
750static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
751 .runtime_suspend = usbhs_runtime_suspend,
752 .runtime_resume = usbhs_runtime_resume,
753};
17cdd29d
KM		 754
755static struct platform_driver usbhs_omap_driver = {
756 .driver = {
757 .name = (char *)usbhs_driver_name,
758 .owner = THIS_MODULE,
1e7fe1a9 759 .pm = &usbhsomap_dev_pm_ops,
17cdd29d
KM		 760 },
761 .remove = __exit_p(usbhs_omap_remove),
762};
763
764MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
765MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
766MODULE_LICENSE("GPL v2");
767MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
768
769static int __init omap_usbhs_drvinit(void)
770{
771 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
772}
773
774/*
775 * init before ehci and ohci drivers;
776 * The usbhs core driver should be initialized much before
777 * the omap ehci and ohci probe functions are called.
4dc2cceb
KM		 778 * This usbhs core driver should be initialized after
779 * usb tll driver
17cdd29d 780 */
4dc2cceb 781fs_initcall_sync(omap_usbhs_drvinit);
17cdd29d
KM		 782
783static void __exit omap_usbhs_drvexit(void)
784{
785 platform_driver_unregister(&usbhs_omap_driver);
786}
787module_exit(omap_usbhs_drvexit);
Linux 6.x block layer and io_uring tree(s)