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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6-block.git] / drivers / mfd / omap-usb-host.c
CommitLineData
17cdd29d
KM		 1/**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/clk.h>
25#include <linux/dma-mapping.h>
26#include <linux/spinlock.h>
27#include <linux/gpio.h>
17cdd29d 28#include <plat/usb.h>
7e6502d5 29#include <linux/pm_runtime.h>
17cdd29d
KM		 30
31#define USBHS_DRIVER_NAME "usbhs-omap"
32#define OMAP_EHCI_DEVICE "ehci-omap"
33#define OMAP_OHCI_DEVICE "ohci-omap3"
34
35/* OMAP USBHOST Register addresses */
36
37/* TLL Register Set */
38#define OMAP_USBTLL_REVISION (0x00)
39#define OMAP_USBTLL_SYSCONFIG (0x10)
40#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
41#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
42#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
43#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
44#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
45
46#define OMAP_USBTLL_SYSSTATUS (0x14)
47#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
48
49#define OMAP_USBTLL_IRQSTATUS (0x18)
50#define OMAP_USBTLL_IRQENABLE (0x1C)
51
52#define OMAP_TLL_SHARED_CONF (0x30)
53#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
54#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
55#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
56#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
57#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
58
59#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
60#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
61#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
62#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
63#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
64#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
65#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
66#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
67
68#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
69#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
70#define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
71#define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
72#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
73#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
74#define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
75#define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
76#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
77#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
78
79#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
80#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
81#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
82#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
83#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
84#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
85#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
86#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
87#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
88
89#define OMAP_TLL_CHANNEL_COUNT 3
90#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
91#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
92#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
93
94/* UHH Register Set */
95#define OMAP_UHH_REVISION (0x00)
96#define OMAP_UHH_SYSCONFIG (0x10)
97#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
98#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
99#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
100#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
101#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
102#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
103
104#define OMAP_UHH_SYSSTATUS (0x14)
105#define OMAP_UHH_HOSTCONFIG (0x40)
106#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
107#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
108#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
109#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
110#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
111#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
112#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
113#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
114#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
115#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
116#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
117#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
118
119/* OMAP4-specific defines */
120#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
121#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
122#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
123#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
124#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
125
126#define OMAP4_P1_MODE_CLEAR (3 << 16)
127#define OMAP4_P1_MODE_TLL (1 << 16)
128#define OMAP4_P1_MODE_HSIC (3 << 16)
129#define OMAP4_P2_MODE_CLEAR (3 << 18)
130#define OMAP4_P2_MODE_TLL (1 << 18)
131#define OMAP4_P2_MODE_HSIC (3 << 18)
132
133#define OMAP_REV2_TLL_CHANNEL_COUNT 2
134
135#define OMAP_UHH_DEBUG_CSR (0x44)
136
137/* Values of UHH_REVISION - Note: these are not given in the TRM */
138#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
139#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
140
141#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
142#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
143
144#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
145#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
146#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
147
148
149struct usbhs_hcd_omap {
17cdd29d
KM		 150 struct clk *xclk60mhsp1_ck;
151 struct clk *xclk60mhsp2_ck;
152 struct clk *utmi_p1_fck;
153 struct clk *usbhost_p1_fck;
154 struct clk *usbtll_p1_fck;
155 struct clk *utmi_p2_fck;
156 struct clk *usbhost_p2_fck;
157 struct clk *usbtll_p2_fck;
158 struct clk *init_60m_fclk;
17cdd29d
KM		 159
160 void __iomem *uhh_base;
161 void __iomem *tll_base;
162
163 struct usbhs_omap_platform_data platdata;
164
165 u32 usbhs_rev;
166 spinlock_t lock;
167 int count;
168};
169/*-------------------------------------------------------------------------*/
170
171const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
172static u64 usbhs_dmamask = ~(u32)0;
173
174/*-------------------------------------------------------------------------*/
175
176static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
177{
178 __raw_writel(val, base + reg);
179}
180
181static inline u32 usbhs_read(void __iomem *base, u32 reg)
182{
183 return __raw_readl(base + reg);
184}
185
186static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
187{
188 __raw_writeb(val, base + reg);
189}
190
191static inline u8 usbhs_readb(void __iomem *base, u8 reg)
192{
193 return __raw_readb(base + reg);
194}
195
196/*-------------------------------------------------------------------------*/
197
198static struct platform_device *omap_usbhs_alloc_child(const char *name,
199 struct resource *res, int num_resources, void *pdata,
200 size_t pdata_size, struct device *dev)
201{
202 struct platform_device *child;
203 int ret;
204
205 child = platform_device_alloc(name, 0);
206
207 if (!child) {
208 dev_err(dev, "platform_device_alloc %s failed\n", name);
209 goto err_end;
210 }
211
212 ret = platform_device_add_resources(child, res, num_resources);
213 if (ret) {
214 dev_err(dev, "platform_device_add_resources failed\n");
215 goto err_alloc;
216 }
217
218 ret = platform_device_add_data(child, pdata, pdata_size);
219 if (ret) {
220 dev_err(dev, "platform_device_add_data failed\n");
221 goto err_alloc;
222 }
223
224 child->dev.dma_mask = &usbhs_dmamask;
225 child->dev.coherent_dma_mask = 0xffffffff;
226 child->dev.parent = dev;
227
228 ret = platform_device_add(child);
229 if (ret) {
230 dev_err(dev, "platform_device_add failed\n");
231 goto err_alloc;
232 }
233
234 return child;
235
236err_alloc:
237 platform_device_put(child);
238
239err_end:
240 return NULL;
241}
242
243static int omap_usbhs_alloc_children(struct platform_device *pdev)
244{
245 struct device *dev = &pdev->dev;
246 struct usbhs_hcd_omap *omap;
247 struct ehci_hcd_omap_platform_data *ehci_data;
248 struct ohci_hcd_omap_platform_data *ohci_data;
249 struct platform_device *ehci;
250 struct platform_device *ohci;
251 struct resource *res;
252 struct resource resources[2];
253 int ret;
254
255 omap = platform_get_drvdata(pdev);
256 ehci_data = omap->platdata.ehci_data;
257 ohci_data = omap->platdata.ohci_data;
258
259 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
260 if (!res) {
261 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
262 ret = -ENODEV;
263 goto err_end;
264 }
265 resources[0] = *res;
266
267 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
268 if (!res) {
269 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
270 ret = -ENODEV;
271 goto err_end;
272 }
273 resources[1] = *res;
274
275 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
276 sizeof(*ehci_data), dev);
277
278 if (!ehci) {
279 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 280 ret = -ENOMEM;
17cdd29d
KM		 281 goto err_end;
282 }
283
284 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
285 if (!res) {
286 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
287 ret = -ENODEV;
288 goto err_ehci;
289 }
290 resources[0] = *res;
291
292 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
293 if (!res) {
294 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
295 ret = -ENODEV;
296 goto err_ehci;
297 }
298 resources[1] = *res;
299
300 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
301 sizeof(*ohci_data), dev);
302 if (!ohci) {
303 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 304 ret = -ENOMEM;
17cdd29d
KM		 305 goto err_ehci;
306 }
307
308 return 0;
309
310err_ehci:
d910774f 311 platform_device_unregister(ehci);
17cdd29d
KM		 312
313err_end:
314 return ret;
315}
316
317/**
318 * usbhs_omap_probe - initialize TI-based HCDs
319 *
320 * Allocates basic resources for this USB host controller.
321 */
322static int __devinit usbhs_omap_probe(struct platform_device *pdev)
323{
324 struct device *dev = &pdev->dev;
325 struct usbhs_omap_platform_data *pdata = dev->platform_data;
326 struct usbhs_hcd_omap *omap;
327 struct resource *res;
328 int ret = 0;
329 int i;
330
331 if (!pdata) {
25985edc 332 dev_err(dev, "Missing platform data\n");
17cdd29d
KM		 333 ret = -ENOMEM;
334 goto end_probe;
335 }
336
337 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
338 if (!omap) {
339 dev_err(dev, "Memory allocation failed\n");
340 ret = -ENOMEM;
341 goto end_probe;
342 }
343
344 spin_lock_init(&omap->lock);
345
346 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
347 omap->platdata.port_mode[i] = pdata->port_mode[i];
348
349 omap->platdata.ehci_data = pdata->ehci_data;
350 omap->platdata.ohci_data = pdata->ohci_data;
351
7e6502d5 352 pm_runtime_enable(&pdev->dev);
17cdd29d
KM		 353
354 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
355 if (IS_ERR(omap->utmi_p1_fck)) {
356 ret = PTR_ERR(omap->utmi_p1_fck);
357 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
7e6502d5 358 goto err_end;
17cdd29d
KM		 359 }
360
361 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
362 if (IS_ERR(omap->xclk60mhsp1_ck)) {
363 ret = PTR_ERR(omap->xclk60mhsp1_ck);
364 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
365 goto err_utmi_p1_fck;
366 }
367
368 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
369 if (IS_ERR(omap->utmi_p2_fck)) {
370 ret = PTR_ERR(omap->utmi_p2_fck);
371 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
372 goto err_xclk60mhsp1_ck;
373 }
374
375 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
376 if (IS_ERR(omap->xclk60mhsp2_ck)) {
377 ret = PTR_ERR(omap->xclk60mhsp2_ck);
378 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
379 goto err_utmi_p2_fck;
380 }
381
382 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
383 if (IS_ERR(omap->usbhost_p1_fck)) {
384 ret = PTR_ERR(omap->usbhost_p1_fck);
385 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
386 goto err_xclk60mhsp2_ck;
387 }
388
389 omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
390 if (IS_ERR(omap->usbtll_p1_fck)) {
391 ret = PTR_ERR(omap->usbtll_p1_fck);
392 dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
393 goto err_usbhost_p1_fck;
394 }
395
396 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
397 if (IS_ERR(omap->usbhost_p2_fck)) {
398 ret = PTR_ERR(omap->usbhost_p2_fck);
399 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
400 goto err_usbtll_p1_fck;
401 }
402
403 omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
404 if (IS_ERR(omap->usbtll_p2_fck)) {
405 ret = PTR_ERR(omap->usbtll_p2_fck);
406 dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
407 goto err_usbhost_p2_fck;
408 }
409
410 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
411 if (IS_ERR(omap->init_60m_fclk)) {
412 ret = PTR_ERR(omap->init_60m_fclk);
413 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
414 goto err_usbtll_p2_fck;
415 }
416
417 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
418 if (!res) {
419 dev_err(dev, "UHH EHCI get resource failed\n");
420 ret = -ENODEV;
421 goto err_init_60m_fclk;
422 }
423
424 omap->uhh_base = ioremap(res->start, resource_size(res));
425 if (!omap->uhh_base) {
426 dev_err(dev, "UHH ioremap failed\n");
427 ret = -ENOMEM;
428 goto err_init_60m_fclk;
429 }
430
431 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
432 if (!res) {
433 dev_err(dev, "UHH EHCI get resource failed\n");
434 ret = -ENODEV;
435 goto err_tll;
436 }
437
438 omap->tll_base = ioremap(res->start, resource_size(res));
439 if (!omap->tll_base) {
440 dev_err(dev, "TLL ioremap failed\n");
441 ret = -ENOMEM;
442 goto err_tll;
443 }
444
445 platform_set_drvdata(pdev, omap);
446
447 ret = omap_usbhs_alloc_children(pdev);
448 if (ret) {
449 dev_err(dev, "omap_usbhs_alloc_children failed\n");
450 goto err_alloc;
451 }
452
453 goto end_probe;
454
455err_alloc:
456 iounmap(omap->tll_base);
457
458err_tll:
459 iounmap(omap->uhh_base);
460
461err_init_60m_fclk:
462 clk_put(omap->init_60m_fclk);
463
464err_usbtll_p2_fck:
465 clk_put(omap->usbtll_p2_fck);
466
467err_usbhost_p2_fck:
468 clk_put(omap->usbhost_p2_fck);
469
470err_usbtll_p1_fck:
471 clk_put(omap->usbtll_p1_fck);
472
473err_usbhost_p1_fck:
474 clk_put(omap->usbhost_p1_fck);
475
476err_xclk60mhsp2_ck:
477 clk_put(omap->xclk60mhsp2_ck);
478
479err_utmi_p2_fck:
480 clk_put(omap->utmi_p2_fck);
481
482err_xclk60mhsp1_ck:
483 clk_put(omap->xclk60mhsp1_ck);
484
485err_utmi_p1_fck:
486 clk_put(omap->utmi_p1_fck);
487
17cdd29d 488err_end:
7e6502d5 489 pm_runtime_disable(&pdev->dev);
17cdd29d
KM		 490 kfree(omap);
491
492end_probe:
493 return ret;
494}
495
496/**
497 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
498 * @pdev: USB Host Controller being removed
499 *
500 * Reverses the effect of usbhs_omap_probe().
501 */
502static int __devexit usbhs_omap_remove(struct platform_device *pdev)
503{
504 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
505
506 if (omap->count != 0) {
507 dev_err(&pdev->dev,
508 "Either EHCI or OHCI is still using usbhs core\n");
509 return -EBUSY;
510 }
511
512 iounmap(omap->tll_base);
513 iounmap(omap->uhh_base);
514 clk_put(omap->init_60m_fclk);
515 clk_put(omap->usbtll_p2_fck);
516 clk_put(omap->usbhost_p2_fck);
517 clk_put(omap->usbtll_p1_fck);
518 clk_put(omap->usbhost_p1_fck);
519 clk_put(omap->xclk60mhsp2_ck);
520 clk_put(omap->utmi_p2_fck);
521 clk_put(omap->xclk60mhsp1_ck);
522 clk_put(omap->utmi_p1_fck);
7e6502d5 523 pm_runtime_disable(&pdev->dev);
17cdd29d
KM		 524 kfree(omap);
525
526 return 0;
527}
528
529static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
530{
531 switch (pmode) {
532 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
533 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
534 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
535 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
536 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
537 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
538 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
539 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
540 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
541 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
542 return true;
543
544 default:
545 return false;
546 }
547}
548
549/*
550 * convert the port-mode enum to a value we can use in the FSLSMODE
551 * field of USBTLL_CHANNEL_CONF
552 */
553static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
554{
555 switch (mode) {
556 case OMAP_USBHS_PORT_MODE_UNUSED:
557 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
558 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
559
560 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
561 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
562
563 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
564 return OMAP_TLL_FSLSMODE_3PIN_PHY;
565
566 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
567 return OMAP_TLL_FSLSMODE_4PIN_PHY;
568
569 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
570 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
571
572 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
573 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
574
575 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
576 return OMAP_TLL_FSLSMODE_3PIN_TLL;
577
578 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
579 return OMAP_TLL_FSLSMODE_4PIN_TLL;
580
581 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
582 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
583
584 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
585 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
586 default:
587 pr_warning("Invalid port mode, using default\n");
588 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
589 }
590}
591
592static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
593{
594 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
595 struct usbhs_omap_platform_data *pdata = dev->platform_data;
596 unsigned reg;
597 int i;
598
599 /* Program Common TLL register */
600 reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF);
601 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
602 | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
603 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
604 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
605
606 usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
607
608 /* Enable channels now */
609 for (i = 0; i < tll_channel_count; i++) {
610 reg = usbhs_read(omap->tll_base,
611 OMAP_TLL_CHANNEL_CONF(i));
612
613 if (is_ohci_port(pdata->port_mode[i])) {
614 reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
615 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
616 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
617 } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) {
618
619 /* Disable AutoIdle, BitStuffing and use SDR Mode */
620 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
621 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
622 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
623
624 reg |= (1 << (i + 1));
625 } else
626 continue;
627
628 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
629 usbhs_write(omap->tll_base,
630 OMAP_TLL_CHANNEL_CONF(i), reg);
631
632 usbhs_writeb(omap->tll_base,
633 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
634 }
635}
636
637static int usbhs_enable(struct device *dev)
638{
639 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
640 struct usbhs_omap_platform_data *pdata = &omap->platdata;
641 unsigned long flags = 0;
642 int ret = 0;
17cdd29d
KM		 643 unsigned reg;
644
645 dev_dbg(dev, "starting TI HSUSB Controller\n");
646 if (!pdata) {
647 dev_dbg(dev, "missing platform_data\n");
d11536e4 648 return -ENODEV;
17cdd29d
KM		 649 }
650
651 spin_lock_irqsave(&omap->lock, flags);
652 if (omap->count > 0)
653 goto end_count;
654
7e6502d5 655 pm_runtime_get_sync(dev);
17cdd29d
KM		 656
657 if (pdata->ehci_data->phy_reset) {
658 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
659 gpio_request(pdata->ehci_data->reset_gpio_port[0],
660 "USB1 PHY reset");
661 gpio_direction_output
557f447f 662 (pdata->ehci_data->reset_gpio_port[0], 0);
17cdd29d
KM		 663 }
664
665 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) {
666 gpio_request(pdata->ehci_data->reset_gpio_port[1],
667 "USB2 PHY reset");
668 gpio_direction_output
557f447f 669 (pdata->ehci_data->reset_gpio_port[1], 0);
17cdd29d
KM		 670 }
671
672 /* Hold the PHY in RESET for enough time till DIR is high */
673 udelay(10);
674 }
675
676 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
677 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
678
17cdd29d
KM		 679 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
680 /* setup ULPI bypass and burst configurations */
681 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
682 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
683 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
684 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
685 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
686
687 if (is_omap_usbhs_rev1(omap)) {
688 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
689 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
690 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
691 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
692 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
693 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
694
695 /* Bypass the TLL module for PHY mode operation */
696 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
697 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
698 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
699 is_ehci_phy_mode(pdata->port_mode[1]) ||
700 is_ehci_phy_mode(pdata->port_mode[2]))
701 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
702 else
703 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
704 } else {
705 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
706 if (is_ehci_phy_mode(pdata->port_mode[0]))
707 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
708 else
709 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
710 if (is_ehci_phy_mode(pdata->port_mode[1]))
711 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
712 else
713 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
714 if (is_ehci_phy_mode(pdata->port_mode[2]))
715 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
716 else
717 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
718 }
719 } else if (is_omap_usbhs_rev2(omap)) {
720 /* Clear port mode fields for PHY mode*/
721 reg &= ~OMAP4_P1_MODE_CLEAR;
722 reg &= ~OMAP4_P2_MODE_CLEAR;
723
724 if (is_ehci_phy_mode(pdata->port_mode[0])) {
725 ret = clk_set_parent(omap->utmi_p1_fck,
726 omap->xclk60mhsp1_ck);
727 if (ret != 0) {
728 dev_err(dev, "xclk60mhsp1_ck set parent"
729 "failed error:%d\n", ret);
730 goto err_tll;
731 }
732 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
733 ret = clk_set_parent(omap->utmi_p1_fck,
734 omap->init_60m_fclk);
735 if (ret != 0) {
736 dev_err(dev, "init_60m_fclk set parent"
737 "failed error:%d\n", ret);
738 goto err_tll;
739 }
740 clk_enable(omap->usbhost_p1_fck);
741 clk_enable(omap->usbtll_p1_fck);
742 }
743
744 if (is_ehci_phy_mode(pdata->port_mode[1])) {
745 ret = clk_set_parent(omap->utmi_p2_fck,
746 omap->xclk60mhsp2_ck);
747 if (ret != 0) {
748 dev_err(dev, "xclk60mhsp1_ck set parent"
749 "failed error:%d\n", ret);
750 goto err_tll;
751 }
752 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
753 ret = clk_set_parent(omap->utmi_p2_fck,
754 omap->init_60m_fclk);
755 if (ret != 0) {
756 dev_err(dev, "init_60m_fclk set parent"
757 "failed error:%d\n", ret);
758 goto err_tll;
759 }
760 clk_enable(omap->usbhost_p2_fck);
761 clk_enable(omap->usbtll_p2_fck);
762 }
763
764 clk_enable(omap->utmi_p1_fck);
765 clk_enable(omap->utmi_p2_fck);
766
767 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
768 (is_ohci_port(pdata->port_mode[0])))
769 reg |= OMAP4_P1_MODE_TLL;
770 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
771 reg |= OMAP4_P1_MODE_HSIC;
772
773 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
774 (is_ohci_port(pdata->port_mode[1])))
775 reg |= OMAP4_P2_MODE_TLL;
776 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
777 reg |= OMAP4_P2_MODE_HSIC;
778 }
779
780 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
781 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
782
783 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
784 is_ehci_tll_mode(pdata->port_mode[1]) ||
785 is_ehci_tll_mode(pdata->port_mode[2]) ||
786 (is_ohci_port(pdata->port_mode[0])) ||
787 (is_ohci_port(pdata->port_mode[1])) ||
788 (is_ohci_port(pdata->port_mode[2]))) {
789
790 /* Enable UTMI mode for required TLL channels */
791 if (is_omap_usbhs_rev2(omap))
792 usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT);
793 else
794 usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT);
795 }
796
797 if (pdata->ehci_data->phy_reset) {
798 /* Hold the PHY in RESET for enough time till
799 * PHY is settled and ready
800 */
801 udelay(10);
802
803 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
804 gpio_set_value
557f447f 805 (pdata->ehci_data->reset_gpio_port[0], 1);
17cdd29d
KM		 806
807 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
808 gpio_set_value
557f447f 809 (pdata->ehci_data->reset_gpio_port[1], 1);
17cdd29d
KM		 810 }
811
812end_count:
813 omap->count++;
d11536e4
AL		 814 spin_unlock_irqrestore(&omap->lock, flags);
815 return 0;
17cdd29d
KM		 816
817err_tll:
7e6502d5
KM		 818 pm_runtime_put_sync(dev);
819 spin_unlock_irqrestore(&omap->lock, flags);
17cdd29d
KM		 820 if (pdata->ehci_data->phy_reset) {
821 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
822 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
823
824 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
825 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
826 }
17cdd29d
KM		 827 return ret;
828}
829
830static void usbhs_disable(struct device *dev)
831{
832 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
833 struct usbhs_omap_platform_data *pdata = &omap->platdata;
834 unsigned long flags = 0;
835 unsigned long timeout;
836
837 dev_dbg(dev, "stopping TI HSUSB Controller\n");
838
839 spin_lock_irqsave(&omap->lock, flags);
840
841 if (omap->count == 0)
842 goto end_disble;
843
844 omap->count--;
845
846 if (omap->count != 0)
847 goto end_disble;
848
849 /* Reset OMAP modules for insmod/rmmod to work */
850 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG,
851 is_omap_usbhs_rev2(omap) ?
852 OMAP4_UHH_SYSCONFIG_SOFTRESET :
853 OMAP_UHH_SYSCONFIG_SOFTRESET);
854
855 timeout = jiffies + msecs_to_jiffies(100);
856 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
857 & (1 << 0))) {
858 cpu_relax();
859
860 if (time_after(jiffies, timeout))
861 dev_dbg(dev, "operation timed out\n");
862 }
863
864 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
865 & (1 << 1))) {
866 cpu_relax();
867
868 if (time_after(jiffies, timeout))
869 dev_dbg(dev, "operation timed out\n");
870 }
871
872 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
873 & (1 << 2))) {
874 cpu_relax();
875
876 if (time_after(jiffies, timeout))
877 dev_dbg(dev, "operation timed out\n");
878 }
879
880 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
881
882 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
883 & (1 << 0))) {
884 cpu_relax();
885
886 if (time_after(jiffies, timeout))
887 dev_dbg(dev, "operation timed out\n");
888 }
889
6eb6fbbf
KM		 890 if (is_omap_usbhs_rev2(omap)) {
891 if (is_ehci_tll_mode(pdata->port_mode[0]))
892 clk_enable(omap->usbtll_p1_fck);
893 if (is_ehci_tll_mode(pdata->port_mode[1]))
894 clk_enable(omap->usbtll_p2_fck);
895 clk_disable(omap->utmi_p2_fck);
896 clk_disable(omap->utmi_p1_fck);
17cdd29d
KM		 897 }
898
7e6502d5 899 pm_runtime_put_sync(dev);
17cdd29d 900
6eb6fbbf
KM		 901 /* The gpio_free migh sleep; so unlock the spinlock */
902 spin_unlock_irqrestore(&omap->lock, flags);
903
904 if (pdata->ehci_data->phy_reset) {
905 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
906 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
907
908 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
909 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
910 }
911 return;
912
17cdd29d
KM		 913end_disble:
914 spin_unlock_irqrestore(&omap->lock, flags);
915}
916
917int omap_usbhs_enable(struct device *dev)
918{
919 return usbhs_enable(dev->parent);
920}
921EXPORT_SYMBOL_GPL(omap_usbhs_enable);
922
923void omap_usbhs_disable(struct device *dev)
924{
925 usbhs_disable(dev->parent);
926}
927EXPORT_SYMBOL_GPL(omap_usbhs_disable);
928
929static struct platform_driver usbhs_omap_driver = {
930 .driver = {
931 .name = (char *)usbhs_driver_name,
932 .owner = THIS_MODULE,
933 },
934 .remove = __exit_p(usbhs_omap_remove),
935};
936
937MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
938MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
939MODULE_LICENSE("GPL v2");
940MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
941
942static int __init omap_usbhs_drvinit(void)
943{
944 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
945}
946
947/*
948 * init before ehci and ohci drivers;
949 * The usbhs core driver should be initialized much before
950 * the omap ehci and ohci probe functions are called.
951 */
952fs_initcall(omap_usbhs_drvinit);
953
954static void __exit omap_usbhs_drvexit(void)
955{
956 platform_driver_unregister(&usbhs_omap_driver);
957}
958module_exit(omap_usbhs_drvexit);
Linux 6.x block layer and io_uring tree(s)