[linux-2.6-block.git] / drivers / mfd / ocelot-spi.c

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * SPI core driver for the Ocelot chip family.
 *
 * This driver will handle everything necessary to allow for communication over
 * SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions
 * are to prepare the chip's SPI interface for a specific bus speed, and a host
 * processor's endianness. This will create and distribute regmaps for any
 * children.
 *
 * Copyright 2021-2022 Innovative Advantage Inc.
 *
 * Author: Colin Foster <colin.foster@in-advantage.com>
 */

#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/ioport.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/types.h>
#include <linux/units.h>

#include "ocelot.h"

#define REG_DEV_CPUORG_IF_CTRL		0x0000
#define REG_DEV_CPUORG_IF_CFGSTAT	0x0004

#define CFGSTAT_IF_NUM_VCORE		(0 << 24)
#define CFGSTAT_IF_NUM_VRAP		(1 << 24)
#define CFGSTAT_IF_NUM_SI		(2 << 24)
#define CFGSTAT_IF_NUM_MIIM		(3 << 24)

#define VSC7512_DEVCPU_ORG_RES_START	0x71000000
#define VSC7512_DEVCPU_ORG_RES_SIZE	0x38

#define VSC7512_CHIP_REGS_RES_START	0x71070000
#define VSC7512_CHIP_REGS_RES_SIZE	0x14

static const struct resource vsc7512_dev_cpuorg_resource =
	DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START,
			     VSC7512_DEVCPU_ORG_RES_SIZE,
			     "devcpu_org");

static const struct resource vsc7512_gcb_resource =
	DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START,
			     VSC7512_CHIP_REGS_RES_SIZE,
			     "devcpu_gcb_chip_regs");

static int ocelot_spi_initialize(struct device *dev)
{
	struct ocelot_ddata *ddata = dev_get_drvdata(dev);
	u32 val, check;
	int err;

	val = OCELOT_SPI_BYTE_ORDER;

	/*
	 * The SPI address must be big-endian, but we want the payload to match
	 * our CPU. These are two bits (0 and 1) but they're repeated such that
	 * the write from any configuration will be valid. The four
	 * configurations are:
	 *
	 * 0b00: little-endian, MSB first
	 * |            111111   | 22221111 | 33222222 |
	 * | 76543210 | 54321098 | 32109876 | 10987654 |
	 *
	 * 0b01: big-endian, MSB first
	 * | 33222222 | 22221111 | 111111   |          |
	 * | 10987654 | 32109876 | 54321098 | 76543210 |
	 *
	 * 0b10: little-endian, LSB first
	 * |              111111 | 11112222 | 22222233 |
	 * | 01234567 | 89012345 | 67890123 | 45678901 |
	 *
	 * 0b11: big-endian, LSB first
	 * | 22222233 | 11112222 |   111111 |          |
	 * | 45678901 | 67890123 | 89012345 | 01234567 |
	 */
	err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val);
	if (err)
		return err;

	/*
	 * Apply the number of padding bytes between a read request and the data
	 * payload. Some registers have access times of up to 1us, so if the
	 * first payload bit is shifted out too quickly, the read will fail.
	 */
	val = ddata->spi_padding_bytes;
	err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val);
	if (err)
		return err;

	/*
	 * After we write the interface configuration, read it back here. This
	 * will verify several different things. The first is that the number of
	 * padding bytes actually got written correctly. These are found in bits
	 * 0:3.
	 *
	 * The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT,
	 * and will be set if the register access is too fast. This would be in
	 * the condition that the number of padding bytes is insufficient for
	 * the SPI bus frequency.
	 *
	 * The last check is for bits 31:24, which define the interface by which
	 * the registers are being accessed. Since we're accessing them via the
	 * serial interface, it must return IF_NUM_SI.
	 */
	check = val | CFGSTAT_IF_NUM_SI;

	err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val);
	if (err)
		return err;

	if (check != val)
		return -ENODEV;

	return 0;
}

static const struct regmap_config ocelot_spi_regmap_config = {
	.reg_bits = 24,
	.reg_stride = 4,
	.reg_downshift = 2,
	.val_bits = 32,

	.write_flag_mask = 0x80,

	.use_single_write = true,
	.can_multi_write = false,

	.reg_format_endian = REGMAP_ENDIAN_BIG,
	.val_format_endian = REGMAP_ENDIAN_NATIVE,
};

static int ocelot_spi_regmap_bus_read(void *context, const void *reg, size_t reg_size,
				      void *val, size_t val_size)
{
	struct spi_transfer xfers[3] = {0};
	struct device *dev = context;
	struct ocelot_ddata *ddata;
	struct spi_device *spi;
	struct spi_message msg;
	unsigned int index = 0;

	ddata = dev_get_drvdata(dev);
	spi = to_spi_device(dev);

	xfers[index].tx_buf = reg;
	xfers[index].len = reg_size;
	index++;

	if (ddata->spi_padding_bytes) {
		xfers[index].len = ddata->spi_padding_bytes;
		xfers[index].tx_buf = ddata->dummy_buf;
		xfers[index].dummy_data = 1;
		index++;
	}

	xfers[index].rx_buf = val;
	xfers[index].len = val_size;
	index++;

	spi_message_init_with_transfers(&msg, xfers, index);

	return spi_sync(spi, &msg);
}

static int ocelot_spi_regmap_bus_write(void *context, const void *data, size_t count)
{
	struct device *dev = context;
	struct spi_device *spi = to_spi_device(dev);

	return spi_write(spi, data, count);
}

static const struct regmap_bus ocelot_spi_regmap_bus = {
	.write = ocelot_spi_regmap_bus_write,
	.read = ocelot_spi_regmap_bus_read,
};

struct regmap *ocelot_spi_init_regmap(struct device *dev, const struct resource *res)
{
	struct regmap_config regmap_config;

	memcpy(&regmap_config, &ocelot_spi_regmap_config, sizeof(regmap_config));

	regmap_config.name = res->name;
	regmap_config.max_register = resource_size(res) - 1;
	regmap_config.reg_base = res->start;

	return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, &regmap_config);
}
EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, MFD_OCELOT_SPI);

static int ocelot_spi_probe(struct spi_device *spi)
{
	struct device *dev = &spi->dev;
	struct ocelot_ddata *ddata;
	struct regmap *r;
	int err;

	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
	if (!ddata)
		return -ENOMEM;

	spi_set_drvdata(spi, ddata);

	if (spi->max_speed_hz <= 500000) {
		ddata->spi_padding_bytes = 0;
	} else {
		/*
		 * Calculation taken from the manual for IF_CFGSTAT:IF_CFG.
		 * Register access time is 1us, so we need to configure and send
		 * out enough padding bytes between the read request and data
		 * transmission that lasts at least 1 microsecond.
		 */
		ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8;

		ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL);
		if (!ddata->dummy_buf)
			return -ENOMEM;
	}

	spi->bits_per_word = 8;

	err = spi_setup(spi);
	if (err)
		return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n");

	r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource);
	if (IS_ERR(r))
		return PTR_ERR(r);

	ddata->cpuorg_regmap = r;

	r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource);
	if (IS_ERR(r))
		return PTR_ERR(r);

	ddata->gcb_regmap = r;

	/*
	 * The chip must be set up for SPI before it gets initialized and reset.
	 * This must be done before calling init, and after a chip reset is
	 * performed.
	 */
	err = ocelot_spi_initialize(dev);
	if (err)
		return dev_err_probe(dev, err, "Error initializing SPI bus\n");

	err = ocelot_chip_reset(dev);
	if (err)
		return dev_err_probe(dev, err, "Error resetting device\n");

	/*
	 * A chip reset will clear the SPI configuration, so it needs to be done
	 * again before we can access any registers.
	 */
	err = ocelot_spi_initialize(dev);
	if (err)
		return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n");

	err = ocelot_core_init(dev);
	if (err)
		return dev_err_probe(dev, err, "Error initializing Ocelot core\n");

	return 0;
}

static const struct spi_device_id ocelot_spi_ids[] = {
	{ "vsc7512", 0 },
	{ }
};
MODULE_DEVICE_TABLE(spi, ocelot_spi_ids);

static const struct of_device_id ocelot_spi_of_match[] = {
	{ .compatible = "mscc,vsc7512" },
	{ }
};
MODULE_DEVICE_TABLE(of, ocelot_spi_of_match);

static struct spi_driver ocelot_spi_driver = {
	.driver = {
		.name = "ocelot-soc",
		.of_match_table = ocelot_spi_of_match,
	},
	.id_table = ocelot_spi_ids,
	.probe = ocelot_spi_probe,
};
module_spi_driver(ocelot_spi_driver);

MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver");
MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
MODULE_LICENSE("Dual MIT/GPL");
MODULE_IMPORT_NS(MFD_OCELOT);
Commit	Line	Data
f3e89362 CF	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* SPI core driver for the Ocelot chip family.
	4	*
	5	* This driver will handle everything necessary to allow for communication over
	6	* SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions
	7	* are to prepare the chip's SPI interface for a specific bus speed, and a host
	8	* processor's endianness. This will create and distribute regmaps for any
	9	* children.
	10	*
	11	* Copyright 2021-2022 Innovative Advantage Inc.
	12	*
	13	* Author: Colin Foster <colin.foster@in-advantage.com>
	14	*/
	15
	16	#include <linux/device.h>
	17	#include <linux/err.h>
	18	#include <linux/errno.h>
	19	#include <linux/export.h>
	20	#include <linux/ioport.h>
	21	#include <linux/mod_devicetable.h>
	22	#include <linux/module.h>
	23	#include <linux/regmap.h>
	24	#include <linux/spi/spi.h>
	25	#include <linux/types.h>
	26	#include <linux/units.h>
	27
	28	#include "ocelot.h"
	29
	30	#define REG_DEV_CPUORG_IF_CTRL 0x0000
	31	#define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
	32
	33	#define CFGSTAT_IF_NUM_VCORE (0 << 24)
	34	#define CFGSTAT_IF_NUM_VRAP (1 << 24)
	35	#define CFGSTAT_IF_NUM_SI (2 << 24)
	36	#define CFGSTAT_IF_NUM_MIIM (3 << 24)
	37
	38	#define VSC7512_DEVCPU_ORG_RES_START 0x71000000
	39	#define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
	40
	41	#define VSC7512_CHIP_REGS_RES_START 0x71070000
	42	#define VSC7512_CHIP_REGS_RES_SIZE 0x14
	43
	44	static const struct resource vsc7512_dev_cpuorg_resource =
	45	DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START,
	46	VSC7512_DEVCPU_ORG_RES_SIZE,
	47	"devcpu_org");
	48
	49	static const struct resource vsc7512_gcb_resource =
	50	DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START,
	51	VSC7512_CHIP_REGS_RES_SIZE,
	52	"devcpu_gcb_chip_regs");
	53
	54	static int ocelot_spi_initialize(struct device *dev)
	55	{
	56	struct ocelot_ddata *ddata = dev_get_drvdata(dev);
	57	u32 val, check;
	58	int err;
	59
	60	val = OCELOT_SPI_BYTE_ORDER;
	61
	62	/*
	63	* The SPI address must be big-endian, but we want the payload to match
	64	* our CPU. These are two bits (0 and 1) but they're repeated such that
65	* the write from any configuration will be valid. The four
66	* configurations are:
67	*
68	* 0b00: little-endian, MSB first
69	* \| 111111 \| 22221111 \| 33222222 \|
70	* \| 76543210 \| 54321098 \| 32109876 \| 10987654 \|
71	*
72	* 0b01: big-endian, MSB first
73	* \| 33222222 \| 22221111 \| 111111 \| \|
74	* \| 10987654 \| 32109876 \| 54321098 \| 76543210 \|
75	*
76	* 0b10: little-endian, LSB first
77	* \| 111111 \| 11112222 \| 22222233 \|
78	* \| 01234567 \| 89012345 \| 67890123 \| 45678901 \|
79	*
80	* 0b11: big-endian, LSB first
81	* \| 22222233 \| 11112222 \| 111111 \| \|
82	* \| 45678901 \| 67890123 \| 89012345 \| 01234567 \|
83	*/
84	err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val);
85	if (err)
86	return err;
87
88	/*
89	* Apply the number of padding bytes between a read request and the data
90	* payload. Some registers have access times of up to 1us, so if the
91	* first payload bit is shifted out too quickly, the read will fail.
92	*/
93	val = ddata->spi_padding_bytes;
94	err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val);
95	if (err)
96	return err;
97
98	/*
99	* After we write the interface configuration, read it back here. This
100	* will verify several different things. The first is that the number of
101	* padding bytes actually got written correctly. These are found in bits
102	* 0:3.
103	*
104	* The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT,
105	* and will be set if the register access is too fast. This would be in
106	* the condition that the number of padding bytes is insufficient for
107	* the SPI bus frequency.
108	*
109	* The last check is for bits 31:24, which define the interface by which
110	* the registers are being accessed. Since we're accessing them via the
111	* serial interface, it must return IF_NUM_SI.
112	*/
113	check = val \| CFGSTAT_IF_NUM_SI;
114
115	err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val);
116	if (err)
117	return err;
118
119	if (check != val)
120	return -ENODEV;
121
122	return 0;
123	}
124
125	static const struct regmap_config ocelot_spi_regmap_config = {
126	.reg_bits = 24,
127	.reg_stride = 4,
128	.reg_downshift = 2,
129	.val_bits = 32,
130
131	.write_flag_mask = 0x80,
132
133	.use_single_write = true,
134	.can_multi_write = false,
135
136	.reg_format_endian = REGMAP_ENDIAN_BIG,
137	.val_format_endian = REGMAP_ENDIAN_NATIVE,
138	};
139
140	static int ocelot_spi_regmap_bus_read(void context, const void reg, size_t reg_size,
141	void *val, size_t val_size)
142	{
143	struct spi_transfer xfers[3] = {0};
144	struct device *dev = context;
145	struct ocelot_ddata *ddata;
146	struct spi_device *spi;
147	struct spi_message msg;
148	unsigned int index = 0;
149
150	ddata = dev_get_drvdata(dev);
151	spi = to_spi_device(dev);
152
153	xfers[index].tx_buf = reg;
154	xfers[index].len = reg_size;
155	index++;
156
157	if (ddata->spi_padding_bytes) {
158	xfers[index].len = ddata->spi_padding_bytes;
159	xfers[index].tx_buf = ddata->dummy_buf;
160	xfers[index].dummy_data = 1;
161	index++;
162	}
163
164	xfers[index].rx_buf = val;
165	xfers[index].len = val_size;
166	index++;
167
168	spi_message_init_with_transfers(&msg, xfers, index);
169
170	return spi_sync(spi, &msg);
171	}
172
173	static int ocelot_spi_regmap_bus_write(void context, const void data, size_t count)
174	{
175	struct device *dev = context;
176	struct spi_device *spi = to_spi_device(dev);
177
178	return spi_write(spi, data, count);
179	}
180
181	static const struct regmap_bus ocelot_spi_regmap_bus = {
182	.write = ocelot_spi_regmap_bus_write,
183	.read = ocelot_spi_regmap_bus_read,
184	};
185
186	struct regmap ocelot_spi_init_regmap(struct device dev, const struct resource *res)
187	{
188	struct regmap_config regmap_config;
189
190	memcpy(&regmap_config, &ocelot_spi_regmap_config, sizeof(regmap_config));
191
192	regmap_config.name = res->name;
193	regmap_config.max_register = resource_size(res) - 1;
194	regmap_config.reg_base = res->start;
195
196	return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, &regmap_config);
197	}
198	EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, MFD_OCELOT_SPI);
199
200	static int ocelot_spi_probe(struct spi_device *spi)
201	{
202	struct device *dev = &spi->dev;
203	struct ocelot_ddata *ddata;
204	struct regmap *r;
205	int err;
206
207	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
208	if (!ddata)
209	return -ENOMEM;
210
211	spi_set_drvdata(spi, ddata);
212
213	if (spi->max_speed_hz <= 500000) {
214	ddata->spi_padding_bytes = 0;
215	} else {
216	/*
217	* Calculation taken from the manual for IF_CFGSTAT:IF_CFG.
218	* Register access time is 1us, so we need to configure and send
219	* out enough padding bytes between the read request and data
220	* transmission that lasts at least 1 microsecond.
221	*/
222	ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8;
223
224	ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL);
225	if (!ddata->dummy_buf)
226	return -ENOMEM;
227	}
228
229	spi->bits_per_word = 8;
230
231	err = spi_setup(spi);
232	if (err)
233	return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n");
234
235	r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource);
236	if (IS_ERR(r))
237	return PTR_ERR(r);
238
239	ddata->cpuorg_regmap = r;
240
241	r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource);
242	if (IS_ERR(r))
243	return PTR_ERR(r);
244
245	ddata->gcb_regmap = r;
246
247	/*
248	* The chip must be set up for SPI before it gets initialized and reset.
249	* This must be done before calling init, and after a chip reset is
250	* performed.
251	*/
252	err = ocelot_spi_initialize(dev);
253	if (err)
254	return dev_err_probe(dev, err, "Error initializing SPI bus\n");
255
256	err = ocelot_chip_reset(dev);
257	if (err)
258	return dev_err_probe(dev, err, "Error resetting device\n");
259
260	/*
261	* A chip reset will clear the SPI configuration, so it needs to be done
262	* again before we can access any registers.
263	*/
264	err = ocelot_spi_initialize(dev);
265	if (err)
266	return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n");
267
268	err = ocelot_core_init(dev);
269	if (err)
270	return dev_err_probe(dev, err, "Error initializing Ocelot core\n");
271
272	return 0;
273	}
274
275	static const struct spi_device_id ocelot_spi_ids[] = {
276	{ "vsc7512", 0 },
277	{ }
278	};
02010cf0	279	MODULE_DEVICE_TABLE(spi, ocelot_spi_ids);
f3e89362 CF	280
	281	static const struct of_device_id ocelot_spi_of_match[] = {
	282	{ .compatible = "mscc,vsc7512" },
	283	{ }
	284	};
	285	MODULE_DEVICE_TABLE(of, ocelot_spi_of_match);
	286
	287	static struct spi_driver ocelot_spi_driver = {
	288	.driver = {
	289	.name = "ocelot-soc",
	290	.of_match_table = ocelot_spi_of_match,
	291	},
	292	.id_table = ocelot_spi_ids,
	293	.probe = ocelot_spi_probe,
	294	};
	295	module_spi_driver(ocelot_spi_driver);
	296
	297	MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver");
	298	MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
	299	MODULE_LICENSE("Dual MIT/GPL");
	300	MODULE_IMPORT_NS(MFD_OCELOT);