[linux-block.git] / drivers / mfd / mt6397-irq.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2019 MediaTek Inc.

#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/suspend.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6331/core.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6397/registers.h>

static void mt6397_irq_lock(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);

	mutex_lock(&mt6397->irqlock);
}

static void mt6397_irq_sync_unlock(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);

	regmap_write(mt6397->regmap, mt6397->int_con[0],
		     mt6397->irq_masks_cur[0]);
	regmap_write(mt6397->regmap, mt6397->int_con[1],
		     mt6397->irq_masks_cur[1]);

	mutex_unlock(&mt6397->irqlock);
}

static void mt6397_irq_disable(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	int shift = data->hwirq & 0xf;
	int reg = data->hwirq >> 4;

	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
}

static void mt6397_irq_enable(struct irq_data *data)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	int shift = data->hwirq & 0xf;
	int reg = data->hwirq >> 4;

	mt6397->irq_masks_cur[reg] |= BIT(shift);
}

static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
{
	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	int shift = irq_data->hwirq & 0xf;
	int reg = irq_data->hwirq >> 4;

	if (on)
		mt6397->wake_mask[reg] |= BIT(shift);
	else
		mt6397->wake_mask[reg] &= ~BIT(shift);

	return 0;
}

static struct irq_chip mt6397_irq_chip = {
	.name = "mt6397-irq",
	.irq_bus_lock = mt6397_irq_lock,
	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	.irq_enable = mt6397_irq_enable,
	.irq_disable = mt6397_irq_disable,
	.irq_set_wake = pm_sleep_ptr(mt6397_irq_set_wake),
};

static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
				  int irqbase)
{
	unsigned int status = 0;
	int i, irq, ret;

	ret = regmap_read(mt6397->regmap, reg, &status);
	if (ret) {
		dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
		return;
	}

	for (i = 0; i < 16; i++) {
		if (status & BIT(i)) {
			irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
			if (irq)
				handle_nested_irq(irq);
		}
	}

	regmap_write(mt6397->regmap, reg, status);
}

static irqreturn_t mt6397_irq_thread(int irq, void *data)
{
	struct mt6397_chip *mt6397 = data;

	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);

	return IRQ_HANDLED;
}

static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
				 irq_hw_number_t hw)
{
	struct mt6397_chip *mt6397 = d->host_data;

	irq_set_chip_data(irq, mt6397);
	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	irq_set_nested_thread(irq, 1);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mt6397_irq_domain_ops = {
	.map = mt6397_irq_domain_map,
};

static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
				  unsigned long pm_event, void *unused)
{
	struct mt6397_chip *chip =
		container_of(notifier, struct mt6397_chip, pm_nb);

	switch (pm_event) {
	case PM_SUSPEND_PREPARE:
		regmap_write(chip->regmap,
			     chip->int_con[0], chip->wake_mask[0]);
		regmap_write(chip->regmap,
			     chip->int_con[1], chip->wake_mask[1]);
		enable_irq_wake(chip->irq);
		break;

	case PM_POST_SUSPEND:
		regmap_write(chip->regmap,
			     chip->int_con[0], chip->irq_masks_cur[0]);
		regmap_write(chip->regmap,
			     chip->int_con[1], chip->irq_masks_cur[1]);
		disable_irq_wake(chip->irq);
		break;

	default:
		break;
	}

	return NOTIFY_DONE;
}

int mt6397_irq_init(struct mt6397_chip *chip)
{
	int ret;

	mutex_init(&chip->irqlock);

	switch (chip->chip_id) {
	case MT6323_CHIP_ID:
		chip->int_con[0] = MT6323_INT_CON0;
		chip->int_con[1] = MT6323_INT_CON1;
		chip->int_status[0] = MT6323_INT_STATUS0;
		chip->int_status[1] = MT6323_INT_STATUS1;
		break;
	case MT6331_CHIP_ID:
		chip->int_con[0] = MT6331_INT_CON0;
		chip->int_con[1] = MT6331_INT_CON1;
		chip->int_status[0] = MT6331_INT_STATUS_CON0;
		chip->int_status[1] = MT6331_INT_STATUS_CON1;
		break;
	case MT6391_CHIP_ID:
	case MT6397_CHIP_ID:
		chip->int_con[0] = MT6397_INT_CON0;
		chip->int_con[1] = MT6397_INT_CON1;
		chip->int_status[0] = MT6397_INT_STATUS0;
		chip->int_status[1] = MT6397_INT_STATUS1;
		break;

	default:
		dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
		return -ENODEV;
	}

	/* Mask all interrupt sources */
	regmap_write(chip->regmap, chip->int_con[0], 0x0);
	regmap_write(chip->regmap, chip->int_con[1], 0x0);

	chip->pm_nb.notifier_call = mt6397_irq_pm_notifier;
	chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
						 MT6397_IRQ_NR,
						 &mt6397_irq_domain_ops,
						 chip);
	if (!chip->irq_domain) {
		dev_err(chip->dev, "could not create irq domain\n");
		return -ENOMEM;
	}

	ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
					mt6397_irq_thread, IRQF_ONESHOT,
					"mt6397-pmic", chip);
	if (ret) {
		dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
			chip->irq, ret);
		return ret;
	}

	register_pm_notifier(&chip->pm_nb);
	return 0;
}
Commit	Line	Data
a4872e80 HHW	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright (c) 2019 MediaTek Inc.
	4
	5	#include <linux/interrupt.h>
	6	#include <linux/module.h>
	7	#include <linux/of.h>
	8	#include <linux/of_device.h>
	9	#include <linux/of_irq.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/regmap.h>
4e2e7cfe	12	#include <linux/suspend.h>
a4872e80 HHW	13	#include <linux/mfd/mt6323/core.h>
a4872e80 HHW	14	#include <linux/mfd/mt6323/registers.h>
d9cd0bc6 ADR	15	#include <linux/mfd/mt6331/core.h>
d9cd0bc6 ADR	16	#include <linux/mfd/mt6331/registers.h>
a4872e80 HHW	17	#include <linux/mfd/mt6397/core.h>
	18	#include <linux/mfd/mt6397/registers.h>
	19
	20	static void mt6397_irq_lock(struct irq_data *data)
	21	{
	22	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	23
	24	mutex_lock(&mt6397->irqlock);
	25	}
	26
	27	static void mt6397_irq_sync_unlock(struct irq_data *data)
	28	{
	29	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	30
	31	regmap_write(mt6397->regmap, mt6397->int_con[0],
	32	mt6397->irq_masks_cur[0]);
	33	regmap_write(mt6397->regmap, mt6397->int_con[1],
	34	mt6397->irq_masks_cur[1]);
	35
	36	mutex_unlock(&mt6397->irqlock);
	37	}
	38
	39	static void mt6397_irq_disable(struct irq_data *data)
	40	{
	41	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	42	int shift = data->hwirq & 0xf;
	43	int reg = data->hwirq >> 4;
	44
	45	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
	46	}
	47
	48	static void mt6397_irq_enable(struct irq_data *data)
	49	{
	50	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
	51	int shift = data->hwirq & 0xf;
	52	int reg = data->hwirq >> 4;
	53
	54	mt6397->irq_masks_cur[reg] \|= BIT(shift);
	55	}
	56
a4872e80 HHW	57	static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
	58	{
	59	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
	60	int shift = irq_data->hwirq & 0xf;
	61	int reg = irq_data->hwirq >> 4;
	62
	63	if (on)
	64	mt6397->wake_mask[reg] \|= BIT(shift);
	65	else
	66	mt6397->wake_mask[reg] &= ~BIT(shift);
	67
	68	return 0;
	69	}
a4872e80 HHW	70
	71	static struct irq_chip mt6397_irq_chip = {
	72	.name = "mt6397-irq",
	73	.irq_bus_lock = mt6397_irq_lock,
	74	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
	75	.irq_enable = mt6397_irq_enable,
	76	.irq_disable = mt6397_irq_disable,
e1243e0d	77	.irq_set_wake = pm_sleep_ptr(mt6397_irq_set_wake),
a4872e80 HHW	78	};
	79
	80	static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
	81	int irqbase)
	82	{
4e2e7cfe	83	unsigned int status = 0;
a4872e80 HHW	84	int i, irq, ret;
	85
	86	ret = regmap_read(mt6397->regmap, reg, &status);
	87	if (ret) {
	88	dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
	89	return;
	90	}
	91
	92	for (i = 0; i < 16; i++) {
	93	if (status & BIT(i)) {
	94	irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
	95	if (irq)
	96	handle_nested_irq(irq);
	97	}
	98	}
	99
	100	regmap_write(mt6397->regmap, reg, status);
	101	}
	102
	103	static irqreturn_t mt6397_irq_thread(int irq, void *data)
	104	{
	105	struct mt6397_chip *mt6397 = data;
	106
	107	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
	108	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
	109
	110	return IRQ_HANDLED;
	111	}
	112
	113	static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
	114	irq_hw_number_t hw)
	115	{
	116	struct mt6397_chip *mt6397 = d->host_data;
	117
	118	irq_set_chip_data(irq, mt6397);
	119	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
	120	irq_set_nested_thread(irq, 1);
	121	irq_set_noprobe(irq);
	122
	123	return 0;
	124	}
	125
	126	static const struct irq_domain_ops mt6397_irq_domain_ops = {
	127	.map = mt6397_irq_domain_map,
	128	};
	129
4e2e7cfe HHW	130	static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
	131	unsigned long pm_event, void *unused)
	132	{
	133	struct mt6397_chip *chip =
	134	container_of(notifier, struct mt6397_chip, pm_nb);
	135
	136	switch (pm_event) {
	137	case PM_SUSPEND_PREPARE:
	138	regmap_write(chip->regmap,
	139	chip->int_con[0], chip->wake_mask[0]);
	140	regmap_write(chip->regmap,
	141	chip->int_con[1], chip->wake_mask[1]);
	142	enable_irq_wake(chip->irq);
	143	break;
	144
	145	case PM_POST_SUSPEND:
	146	regmap_write(chip->regmap,
	147	chip->int_con[0], chip->irq_masks_cur[0]);
	148	regmap_write(chip->regmap,
	149	chip->int_con[1], chip->irq_masks_cur[1]);
	150	disable_irq_wake(chip->irq);
	151	break;
	152
	153	default:
	154	break;
	155	}
	156
	157	return NOTIFY_DONE;
	158	}
	159
a4872e80 HHW	160	int mt6397_irq_init(struct mt6397_chip *chip)
	161	{
	162	int ret;
	163
	164	mutex_init(&chip->irqlock);
	165
	166	switch (chip->chip_id) {
	167	case MT6323_CHIP_ID:
	168	chip->int_con[0] = MT6323_INT_CON0;
	169	chip->int_con[1] = MT6323_INT_CON1;
	170	chip->int_status[0] = MT6323_INT_STATUS0;
	171	chip->int_status[1] = MT6323_INT_STATUS1;
	172	break;
d9cd0bc6 ADR	173	case MT6331_CHIP_ID:
	174	chip->int_con[0] = MT6331_INT_CON0;
	175	chip->int_con[1] = MT6331_INT_CON1;
	176	chip->int_status[0] = MT6331_INT_STATUS_CON0;
	177	chip->int_status[1] = MT6331_INT_STATUS_CON1;
	178	break;
a4872e80 HHW	179	case MT6391_CHIP_ID:
	180	case MT6397_CHIP_ID:
	181	chip->int_con[0] = MT6397_INT_CON0;
	182	chip->int_con[1] = MT6397_INT_CON1;
	183	chip->int_status[0] = MT6397_INT_STATUS0;
	184	chip->int_status[1] = MT6397_INT_STATUS1;
	185	break;
	186
	187	default:
	188	dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
	189	return -ENODEV;
	190	}
	191
	192	/* Mask all interrupt sources */
	193	regmap_write(chip->regmap, chip->int_con[0], 0x0);
	194	regmap_write(chip->regmap, chip->int_con[1], 0x0);
	195
4e2e7cfe	196	chip->pm_nb.notifier_call = mt6397_irq_pm_notifier;
a4872e80 HHW	197	chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
	198	MT6397_IRQ_NR,
	199	&mt6397_irq_domain_ops,
	200	chip);
	201	if (!chip->irq_domain) {
	202	dev_err(chip->dev, "could not create irq domain\n");
	203	return -ENOMEM;
	204	}
	205
	206	ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
	207	mt6397_irq_thread, IRQF_ONESHOT,
	208	"mt6397-pmic", chip);
	209	if (ret) {
	210	dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
	211	chip->irq, ret);
	212	return ret;
	213	}
	214
4e2e7cfe	215	register_pm_notifier(&chip->pm_nb);
a4872e80 HHW	216	return 0;
a4872e80 HHW	217	}