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5e742ad6 RK |
1 | /* |
2 | * linux/drivers/mfd/mcp-sa11x0.c | |
3 | * | |
4 | * Copyright (C) 2001-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * SA11x0 MCP (Multimedia Communications Port) driver. | |
11 | * | |
12 | * MCP read/write timeouts from Jordi Colomer, rehacked by rmk. | |
13 | */ | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
45c7f75f | 16 | #include <linux/io.h> |
5e742ad6 RK |
17 | #include <linux/errno.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/spinlock.h> | |
d052d1be | 21 | #include <linux/platform_device.h> |
2796e397 | 22 | #include <linux/pm.h> |
c8602edf | 23 | #include <linux/mfd/mcp.h> |
5e742ad6 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e742ad6 | 26 | #include <asm/mach-types.h> |
a1fd844c | 27 | #include <linux/platform_data/mfd-mcp-sa11x0.h> |
5e742ad6 | 28 | |
c4592ce4 | 29 | #define DRIVER_NAME "sa11x0-mcp" |
5e742ad6 RK |
30 | |
31 | struct mcp_sa11x0 { | |
45c7f75f RK |
32 | void __iomem *base0; |
33 | void __iomem *base1; | |
34 | u32 mccr0; | |
35 | u32 mccr1; | |
5e742ad6 RK |
36 | }; |
37 | ||
45c7f75f RK |
38 | /* Register offsets */ |
39 | #define MCCR0(m) ((m)->base0 + 0x00) | |
40 | #define MCDR0(m) ((m)->base0 + 0x08) | |
41 | #define MCDR1(m) ((m)->base0 + 0x0c) | |
42 | #define MCDR2(m) ((m)->base0 + 0x10) | |
43 | #define MCSR(m) ((m)->base0 + 0x18) | |
44 | #define MCCR1(m) ((m)->base1 + 0x00) | |
45 | ||
5e742ad6 RK |
46 | #define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp)) |
47 | ||
48 | static void | |
49 | mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor) | |
50 | { | |
45c7f75f | 51 | struct mcp_sa11x0 *m = priv(mcp); |
5e742ad6 RK |
52 | |
53 | divisor /= 32; | |
54 | ||
45c7f75f RK |
55 | m->mccr0 &= ~0x00007f00; |
56 | m->mccr0 |= divisor << 8; | |
57 | writel_relaxed(m->mccr0, MCCR0(m)); | |
5e742ad6 RK |
58 | } |
59 | ||
60 | static void | |
61 | mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor) | |
62 | { | |
45c7f75f | 63 | struct mcp_sa11x0 *m = priv(mcp); |
5e742ad6 RK |
64 | |
65 | divisor /= 32; | |
66 | ||
45c7f75f RK |
67 | m->mccr0 &= ~0x0000007f; |
68 | m->mccr0 |= divisor; | |
69 | writel_relaxed(m->mccr0, MCCR0(m)); | |
5e742ad6 RK |
70 | } |
71 | ||
72 | /* | |
73 | * Write data to the device. The bit should be set after 3 subframe | |
74 | * times (each frame is 64 clocks). We wait a maximum of 6 subframes. | |
75 | * We really should try doing something more productive while we | |
76 | * wait. | |
77 | */ | |
78 | static void | |
79 | mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val) | |
80 | { | |
45c7f75f | 81 | struct mcp_sa11x0 *m = priv(mcp); |
5e742ad6 RK |
82 | int ret = -ETIME; |
83 | int i; | |
84 | ||
45c7f75f | 85 | writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m)); |
5e742ad6 RK |
86 | |
87 | for (i = 0; i < 2; i++) { | |
88 | udelay(mcp->rw_timeout); | |
45c7f75f | 89 | if (readl_relaxed(MCSR(m)) & MCSR_CWC) { |
5e742ad6 RK |
90 | ret = 0; |
91 | break; | |
92 | } | |
93 | } | |
94 | ||
95 | if (ret < 0) | |
96 | printk(KERN_WARNING "mcp: write timed out\n"); | |
97 | } | |
98 | ||
99 | /* | |
100 | * Read data from the device. The bit should be set after 3 subframe | |
101 | * times (each frame is 64 clocks). We wait a maximum of 6 subframes. | |
102 | * We really should try doing something more productive while we | |
103 | * wait. | |
104 | */ | |
105 | static unsigned int | |
106 | mcp_sa11x0_read(struct mcp *mcp, unsigned int reg) | |
107 | { | |
45c7f75f | 108 | struct mcp_sa11x0 *m = priv(mcp); |
5e742ad6 RK |
109 | int ret = -ETIME; |
110 | int i; | |
111 | ||
45c7f75f | 112 | writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m)); |
5e742ad6 RK |
113 | |
114 | for (i = 0; i < 2; i++) { | |
115 | udelay(mcp->rw_timeout); | |
45c7f75f RK |
116 | if (readl_relaxed(MCSR(m)) & MCSR_CRC) { |
117 | ret = readl_relaxed(MCDR2(m)) & 0xffff; | |
5e742ad6 RK |
118 | break; |
119 | } | |
120 | } | |
121 | ||
122 | if (ret < 0) | |
123 | printk(KERN_WARNING "mcp: read timed out\n"); | |
124 | ||
125 | return ret; | |
126 | } | |
127 | ||
128 | static void mcp_sa11x0_enable(struct mcp *mcp) | |
129 | { | |
45c7f75f RK |
130 | struct mcp_sa11x0 *m = priv(mcp); |
131 | ||
132 | writel(-1, MCSR(m)); | |
133 | m->mccr0 |= MCCR0_MCE; | |
134 | writel_relaxed(m->mccr0, MCCR0(m)); | |
5e742ad6 RK |
135 | } |
136 | ||
137 | static void mcp_sa11x0_disable(struct mcp *mcp) | |
138 | { | |
45c7f75f RK |
139 | struct mcp_sa11x0 *m = priv(mcp); |
140 | ||
141 | m->mccr0 &= ~MCCR0_MCE; | |
142 | writel_relaxed(m->mccr0, MCCR0(m)); | |
5e742ad6 RK |
143 | } |
144 | ||
145 | /* | |
146 | * Our methods. | |
147 | */ | |
148 | static struct mcp_ops mcp_sa11x0 = { | |
149 | .set_telecom_divisor = mcp_sa11x0_set_telecom_divisor, | |
150 | .set_audio_divisor = mcp_sa11x0_set_audio_divisor, | |
151 | .reg_write = mcp_sa11x0_write, | |
152 | .reg_read = mcp_sa11x0_read, | |
153 | .enable = mcp_sa11x0_enable, | |
154 | .disable = mcp_sa11x0_disable, | |
155 | }; | |
156 | ||
45c7f75f | 157 | static int mcp_sa11x0_probe(struct platform_device *dev) |
5e742ad6 | 158 | { |
45c7f75f RK |
159 | struct mcp_plat_data *data = dev->dev.platform_data; |
160 | struct resource *mem0, *mem1; | |
161 | struct mcp_sa11x0 *m; | |
5e742ad6 RK |
162 | struct mcp *mcp; |
163 | int ret; | |
164 | ||
323cdfc1 | 165 | if (!data) |
5e742ad6 RK |
166 | return -ENODEV; |
167 | ||
45c7f75f RK |
168 | mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0); |
169 | mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1); | |
170 | if (!mem0 || !mem1) | |
171 | return -ENXIO; | |
172 | ||
173 | if (!request_mem_region(mem0->start, resource_size(mem0), | |
174 | DRIVER_NAME)) { | |
175 | ret = -EBUSY; | |
176 | goto err_mem0; | |
177 | } | |
5e742ad6 | 178 | |
45c7f75f RK |
179 | if (!request_mem_region(mem1->start, resource_size(mem1), |
180 | DRIVER_NAME)) { | |
181 | ret = -EBUSY; | |
182 | goto err_mem1; | |
183 | } | |
184 | ||
185 | mcp = mcp_host_alloc(&dev->dev, sizeof(struct mcp_sa11x0)); | |
5e742ad6 RK |
186 | if (!mcp) { |
187 | ret = -ENOMEM; | |
45c7f75f | 188 | goto err_alloc; |
5e742ad6 RK |
189 | } |
190 | ||
191 | mcp->owner = THIS_MODULE; | |
192 | mcp->ops = &mcp_sa11x0; | |
323cdfc1 | 193 | mcp->sclk_rate = data->sclk_rate; |
5e742ad6 | 194 | |
45c7f75f RK |
195 | m = priv(mcp); |
196 | m->mccr0 = data->mccr0 | 0x7f7f; | |
197 | m->mccr1 = data->mccr1; | |
198 | ||
199 | m->base0 = ioremap(mem0->start, resource_size(mem0)); | |
200 | m->base1 = ioremap(mem1->start, resource_size(mem1)); | |
201 | if (!m->base0 || !m->base1) { | |
202 | ret = -ENOMEM; | |
203 | goto err_ioremap; | |
204 | } | |
205 | ||
206 | platform_set_drvdata(dev, mcp); | |
5e742ad6 | 207 | |
323cdfc1 RK |
208 | /* |
209 | * Initialise device. Note that we initially | |
210 | * set the sampling rate to minimum. | |
211 | */ | |
45c7f75f RK |
212 | writel_relaxed(-1, MCSR(m)); |
213 | writel_relaxed(m->mccr1, MCCR1(m)); | |
214 | writel_relaxed(m->mccr0, MCCR0(m)); | |
5e742ad6 RK |
215 | |
216 | /* | |
217 | * Calculate the read/write timeout (us) from the bit clock | |
218 | * rate. This is the period for 3 64-bit frames. Always | |
219 | * round this time up. | |
220 | */ | |
221 | mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) / | |
222 | mcp->sclk_rate; | |
223 | ||
abe06082 | 224 | ret = mcp_host_add(mcp, data->codec_pdata); |
5e742ad6 | 225 | if (ret == 0) |
45c7f75f | 226 | return 0; |
5e742ad6 | 227 | |
45c7f75f | 228 | platform_set_drvdata(dev, NULL); |
5e742ad6 | 229 | |
45c7f75f RK |
230 | err_ioremap: |
231 | iounmap(m->base1); | |
232 | iounmap(m->base0); | |
233 | mcp_host_free(mcp); | |
234 | err_alloc: | |
235 | release_mem_region(mem1->start, resource_size(mem1)); | |
236 | err_mem1: | |
237 | release_mem_region(mem0->start, resource_size(mem0)); | |
238 | err_mem0: | |
5e742ad6 RK |
239 | return ret; |
240 | } | |
241 | ||
216f63c4 | 242 | static int mcp_sa11x0_remove(struct platform_device *dev) |
5e742ad6 | 243 | { |
216f63c4 | 244 | struct mcp *mcp = platform_get_drvdata(dev); |
45c7f75f RK |
245 | struct mcp_sa11x0 *m = priv(mcp); |
246 | struct resource *mem0, *mem1; | |
247 | ||
a4b54acf RK |
248 | if (m->mccr0 & MCCR0_MCE) |
249 | dev_warn(&dev->dev, | |
250 | "device left active (missing disable call?)\n"); | |
251 | ||
45c7f75f RK |
252 | mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0); |
253 | mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1); | |
5e742ad6 | 254 | |
216f63c4 | 255 | platform_set_drvdata(dev, NULL); |
30816ac0 | 256 | mcp_host_del(mcp); |
45c7f75f RK |
257 | iounmap(m->base1); |
258 | iounmap(m->base0); | |
30816ac0 | 259 | mcp_host_free(mcp); |
45c7f75f RK |
260 | release_mem_region(mem1->start, resource_size(mem1)); |
261 | release_mem_region(mem0->start, resource_size(mem0)); | |
5e742ad6 RK |
262 | |
263 | return 0; | |
264 | } | |
265 | ||
2796e397 RK |
266 | #ifdef CONFIG_PM_SLEEP |
267 | static int mcp_sa11x0_suspend(struct device *dev) | |
5e742ad6 | 268 | { |
2796e397 | 269 | struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev)); |
5e742ad6 | 270 | |
a4b54acf RK |
271 | if (m->mccr0 & MCCR0_MCE) |
272 | dev_warn(dev, "device left active (missing disable call?)\n"); | |
273 | ||
45c7f75f | 274 | writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m)); |
9480e307 | 275 | |
5e742ad6 RK |
276 | return 0; |
277 | } | |
278 | ||
2796e397 | 279 | static int mcp_sa11x0_resume(struct device *dev) |
5e742ad6 | 280 | { |
2796e397 | 281 | struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev)); |
5e742ad6 | 282 | |
45c7f75f RK |
283 | writel_relaxed(m->mccr1, MCCR1(m)); |
284 | writel_relaxed(m->mccr0, MCCR0(m)); | |
9480e307 | 285 | |
5e742ad6 RK |
286 | return 0; |
287 | } | |
2796e397 RK |
288 | #endif |
289 | ||
290 | static const struct dev_pm_ops mcp_sa11x0_pm_ops = { | |
a6aecae2 RK |
291 | #ifdef CONFIG_PM_SLEEP |
292 | .suspend = mcp_sa11x0_suspend, | |
293 | .freeze = mcp_sa11x0_suspend, | |
294 | .poweroff = mcp_sa11x0_suspend, | |
295 | .resume_noirq = mcp_sa11x0_resume, | |
296 | .thaw_noirq = mcp_sa11x0_resume, | |
297 | .restore_noirq = mcp_sa11x0_resume, | |
298 | #endif | |
2796e397 | 299 | }; |
5e742ad6 | 300 | |
3ae5eaec | 301 | static struct platform_driver mcp_sa11x0_driver = { |
5e742ad6 RK |
302 | .probe = mcp_sa11x0_probe, |
303 | .remove = mcp_sa11x0_remove, | |
3ae5eaec | 304 | .driver = { |
c4592ce4 RK |
305 | .name = DRIVER_NAME, |
306 | .owner = THIS_MODULE, | |
2796e397 | 307 | .pm = &mcp_sa11x0_pm_ops, |
3ae5eaec | 308 | }, |
5e742ad6 RK |
309 | }; |
310 | ||
311 | /* | |
312 | * This needs re-working | |
313 | */ | |
65349d60 | 314 | module_platform_driver(mcp_sa11x0_driver); |
5e742ad6 | 315 | |
c4592ce4 | 316 | MODULE_ALIAS("platform:" DRIVER_NAME); |
5e742ad6 RK |
317 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
318 | MODULE_DESCRIPTION("SA11x0 multimedia communications port driver"); | |
319 | MODULE_LICENSE("GPL"); |