[linux-2.6-block.git] / drivers / mfd / mc13xxx-core.c

/*
 * Copyright 2009-2010 Pengutronix
 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
 *
 * loosely based on an earlier driver that has
 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License version 2 as published by the
 * Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>

#include "mc13xxx.h"

#define MC13XXX_IRQSTAT0	0
#define MC13XXX_IRQMASK0	1
#define MC13XXX_IRQSTAT1	3
#define MC13XXX_IRQMASK1	4

#define MC13XXX_REVISION	7
#define MC13XXX_REVISION_REVMETAL	(0x07 <<  0)
#define MC13XXX_REVISION_REVFULL	(0x03 <<  3)
#define MC13XXX_REVISION_ICID		(0x07 <<  6)
#define MC13XXX_REVISION_FIN		(0x03 <<  9)
#define MC13XXX_REVISION_FAB		(0x03 << 11)
#define MC13XXX_REVISION_ICIDCODE	(0x3f << 13)

#define MC34708_REVISION_REVMETAL	(0x07 <<  0)
#define MC34708_REVISION_REVFULL	(0x07 <<  3)
#define MC34708_REVISION_FIN		(0x07 <<  6)
#define MC34708_REVISION_FAB		(0x07 <<  9)

#define MC13XXX_PWRCTRL		15
#define MC13XXX_PWRCTRL_WDIRESET	(1 << 12)

#define MC13XXX_ADC1		44
#define MC13XXX_ADC1_ADEN		(1 << 0)
#define MC13XXX_ADC1_RAND		(1 << 1)
#define MC13XXX_ADC1_ADSEL		(1 << 3)
#define MC13XXX_ADC1_ASC		(1 << 20)
#define MC13XXX_ADC1_ADTRIGIGN		(1 << 21)

#define MC13XXX_ADC2		45

void mc13xxx_lock(struct mc13xxx *mc13xxx)
{
	if (!mutex_trylock(&mc13xxx->lock)) {
		dev_dbg(mc13xxx->dev, "wait for %s from %ps\n",
				__func__, __builtin_return_address(0));

		mutex_lock(&mc13xxx->lock);
	}
	dev_dbg(mc13xxx->dev, "%s from %ps\n",
			__func__, __builtin_return_address(0));
}
EXPORT_SYMBOL(mc13xxx_lock);

void mc13xxx_unlock(struct mc13xxx *mc13xxx)
{
	dev_dbg(mc13xxx->dev, "%s from %ps\n",
			__func__, __builtin_return_address(0));
	mutex_unlock(&mc13xxx->lock);
}
EXPORT_SYMBOL(mc13xxx_unlock);

int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
{
	int ret;

	ret = regmap_read(mc13xxx->regmap, offset, val);
	dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);

	return ret;
}
EXPORT_SYMBOL(mc13xxx_reg_read);

int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
{
	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);

	if (val >= BIT(24))
		return -EINVAL;

	return regmap_write(mc13xxx->regmap, offset, val);
}
EXPORT_SYMBOL(mc13xxx_reg_write);

int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
		u32 mask, u32 val)
{
	BUG_ON(val & ~mask);
	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
			offset, val, mask);

	return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
}
EXPORT_SYMBOL(mc13xxx_reg_rmw);

int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
{
	int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);

	disable_irq_nosync(virq);

	return 0;
}
EXPORT_SYMBOL(mc13xxx_irq_mask);

int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
{
	int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);

	enable_irq(virq);

	return 0;
}
EXPORT_SYMBOL(mc13xxx_irq_unmask);

int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
		int *enabled, int *pending)
{
	int ret;
	unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
	unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
	u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);

	if (irq < 0 || irq >= ARRAY_SIZE(mc13xxx->irqs))
		return -EINVAL;

	if (enabled) {
		u32 mask;

		ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
		if (ret)
			return ret;

		*enabled = mask & irqbit;
	}

	if (pending) {
		u32 stat;

		ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
		if (ret)
			return ret;

		*pending = stat & irqbit;
	}

	return 0;
}
EXPORT_SYMBOL(mc13xxx_irq_status);

int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
		irq_handler_t handler, const char *name, void *dev)
{
	int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);

	return devm_request_threaded_irq(mc13xxx->dev, virq, NULL, handler,
					 IRQF_ONESHOT, name, dev);
}
EXPORT_SYMBOL(mc13xxx_irq_request);

int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
{
	int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);

	devm_free_irq(mc13xxx->dev, virq, dev);

	return 0;
}
EXPORT_SYMBOL(mc13xxx_irq_free);

#define maskval(reg, mask)	(((reg) & (mask)) >> __ffs(mask))
static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
{
	dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
			"fin: %d, fab: %d, icid: %d/%d\n",
			mc13xxx->variant->name,
			maskval(revision, MC13XXX_REVISION_REVFULL),
			maskval(revision, MC13XXX_REVISION_REVMETAL),
			maskval(revision, MC13XXX_REVISION_FIN),
			maskval(revision, MC13XXX_REVISION_FAB),
			maskval(revision, MC13XXX_REVISION_ICID),
			maskval(revision, MC13XXX_REVISION_ICIDCODE));
}

static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
{
	dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
			mc13xxx->variant->name,
			maskval(revision, MC34708_REVISION_REVFULL),
			maskval(revision, MC34708_REVISION_REVMETAL),
			maskval(revision, MC34708_REVISION_FIN),
			maskval(revision, MC34708_REVISION_FAB));
}

/* These are only exported for mc13xxx-i2c and mc13xxx-spi */
struct mc13xxx_variant mc13xxx_variant_mc13783 = {
	.name = "mc13783",
	.print_revision = mc13xxx_print_revision,
};
EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);

struct mc13xxx_variant mc13xxx_variant_mc13892 = {
	.name = "mc13892",
	.print_revision = mc13xxx_print_revision,
};
EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);

struct mc13xxx_variant mc13xxx_variant_mc34708 = {
	.name = "mc34708",
	.print_revision = mc34708_print_revision,
};
EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);

static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
{
	return mc13xxx->variant->name;
}

int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
{
	return mc13xxx->flags;
}
EXPORT_SYMBOL(mc13xxx_get_flags);

#define MC13XXX_ADC1_CHAN0_SHIFT	5
#define MC13XXX_ADC1_CHAN1_SHIFT	8
#define MC13783_ADC1_ATO_SHIFT		11
#define MC13783_ADC1_ATOX		(1 << 19)

struct mc13xxx_adcdone_data {
	struct mc13xxx *mc13xxx;
	struct completion done;
};

static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
{
	struct mc13xxx_adcdone_data *adcdone_data = data;

	complete_all(&adcdone_data->done);

	return IRQ_HANDLED;
}

#define MC13XXX_ADC_WORKING (1 << 0)

int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
		unsigned int channel, u8 ato, bool atox,
		unsigned int *sample)
{
	u32 adc0, adc1, old_adc0;
	int i, ret;
	struct mc13xxx_adcdone_data adcdone_data = {
		.mc13xxx = mc13xxx,
	};
	init_completion(&adcdone_data.done);

	dev_dbg(mc13xxx->dev, "%s\n", __func__);

	mc13xxx_lock(mc13xxx);

	if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
		ret = -EBUSY;
		goto out;
	}

	mc13xxx->adcflags |= MC13XXX_ADC_WORKING;

	mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);

	adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
	adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;

	/*
	 * Channels mapped through ADIN7:
	 * 7  - General purpose ADIN7
	 * 16 - UID
	 * 17 - Die temperature
	 */
	if (channel > 7 && channel < 16) {
		adc1 |= MC13XXX_ADC1_ADSEL;
	} else if (channel == 16) {
		adc0 |= MC13XXX_ADC0_ADIN7SEL_UID;
		channel = 7;
	} else if (channel == 17) {
		adc0 |= MC13XXX_ADC0_ADIN7SEL_DIE;
		channel = 7;
	}

	switch (mode) {
	case MC13XXX_ADC_MODE_TS:
		adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
			MC13XXX_ADC0_TSMOD1;
		adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
		break;

	case MC13XXX_ADC_MODE_SINGLE_CHAN:
		adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
		adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
		adc1 |= MC13XXX_ADC1_RAND;
		break;

	case MC13XXX_ADC_MODE_MULT_CHAN:
		adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
		adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
		break;

	default:
		mc13xxx_unlock(mc13xxx);
		return -EINVAL;
	}

	adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
	if (atox)
		adc1 |= MC13783_ADC1_ATOX;

	dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
	mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
			mc13xxx_handler_adcdone, __func__, &adcdone_data);

	mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
	mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);

	mc13xxx_unlock(mc13xxx);

	ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);

	if (!ret)
		ret = -ETIMEDOUT;

	mc13xxx_lock(mc13xxx);

	mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);

	if (ret > 0)
		for (i = 0; i < 4; ++i) {
			ret = mc13xxx_reg_read(mc13xxx,
					MC13XXX_ADC2, &sample[i]);
			if (ret)
				break;
		}

	if (mode == MC13XXX_ADC_MODE_TS)
		/* restore TSMOD */
		mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);

	mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
out:
	mc13xxx_unlock(mc13xxx);

	return ret;
}
EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);

static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
		const char *format, void *pdata, size_t pdata_size)
{
	char buf[30];
	const char *name = mc13xxx_get_chipname(mc13xxx);

	struct mfd_cell cell = {
		.platform_data = pdata,
		.pdata_size = pdata_size,
	};

	/* there is no asnprintf in the kernel :-( */
	if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
		return -E2BIG;

	cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
	if (!cell.name)
		return -ENOMEM;

	return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0,
			       regmap_irq_get_domain(mc13xxx->irq_data));
}

static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
{
	return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
}

#ifdef CONFIG_OF
static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
{
	struct device_node *np = mc13xxx->dev->of_node;

	if (!np)
		return -ENODEV;

	if (of_property_read_bool(np, "fsl,mc13xxx-uses-adc"))
		mc13xxx->flags |= MC13XXX_USE_ADC;

	if (of_property_read_bool(np, "fsl,mc13xxx-uses-codec"))
		mc13xxx->flags |= MC13XXX_USE_CODEC;

	if (of_property_read_bool(np, "fsl,mc13xxx-uses-rtc"))
		mc13xxx->flags |= MC13XXX_USE_RTC;

	if (of_property_read_bool(np, "fsl,mc13xxx-uses-touch"))
		mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;

	return 0;
}
#else
static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
{
	return -ENODEV;
}
#endif

int mc13xxx_common_init(struct device *dev)
{
	struct mc13xxx_platform_data *pdata = dev_get_platdata(dev);
	struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
	u32 revision;
	int i, ret;

	mc13xxx->dev = dev;

	ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
	if (ret)
		return ret;

	mc13xxx->variant->print_revision(mc13xxx, revision);

	ret = mc13xxx_reg_rmw(mc13xxx, MC13XXX_PWRCTRL,
			MC13XXX_PWRCTRL_WDIRESET, MC13XXX_PWRCTRL_WDIRESET);
	if (ret)
		return ret;

	for (i = 0; i < ARRAY_SIZE(mc13xxx->irqs); i++) {
		mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;
		mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG);
	}

	mc13xxx->irq_chip.name = dev_name(dev);
	mc13xxx->irq_chip.status_base = MC13XXX_IRQSTAT0;
	mc13xxx->irq_chip.mask_base = MC13XXX_IRQMASK0;
	mc13xxx->irq_chip.ack_base = MC13XXX_IRQSTAT0;
	mc13xxx->irq_chip.irq_reg_stride = MC13XXX_IRQSTAT1 - MC13XXX_IRQSTAT0;
	mc13xxx->irq_chip.init_ack_masked = true;
	mc13xxx->irq_chip.use_ack = true;
	mc13xxx->irq_chip.num_regs = MC13XXX_IRQ_REG_CNT;
	mc13xxx->irq_chip.irqs = mc13xxx->irqs;
	mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);

	ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
				  0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
	if (ret)
		return ret;

	mutex_init(&mc13xxx->lock);

	if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
		mc13xxx->flags = pdata->flags;

	if (pdata) {
		mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
			&pdata->regulators, sizeof(pdata->regulators));
		mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
				pdata->leds, sizeof(*pdata->leds));
		mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
				pdata->buttons, sizeof(*pdata->buttons));
		if (mc13xxx->flags & MC13XXX_USE_CODEC)
			mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
				pdata->codec, sizeof(*pdata->codec));
		if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
			mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
				&pdata->touch, sizeof(pdata->touch));
	} else {
		mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
		mc13xxx_add_subdevice(mc13xxx, "%s-led");
		mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
		if (mc13xxx->flags & MC13XXX_USE_CODEC)
			mc13xxx_add_subdevice(mc13xxx, "%s-codec");
		if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
			mc13xxx_add_subdevice(mc13xxx, "%s-ts");
	}

	if (mc13xxx->flags & MC13XXX_USE_ADC)
		mc13xxx_add_subdevice(mc13xxx, "%s-adc");

	if (mc13xxx->flags & MC13XXX_USE_RTC)
		mc13xxx_add_subdevice(mc13xxx, "%s-rtc");

	return 0;
}
EXPORT_SYMBOL_GPL(mc13xxx_common_init);

int mc13xxx_common_exit(struct device *dev)
{
	struct mc13xxx *mc13xxx = dev_get_drvdata(dev);

	mfd_remove_devices(dev);
	regmap_del_irq_chip(mc13xxx->irq, mc13xxx->irq_data);
	mutex_destroy(&mc13xxx->lock);

	return 0;
}
EXPORT_SYMBOL_GPL(mc13xxx_common_exit);

MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
8e005935 UKK	1	/*
	2	* Copyright 2009-2010 Pengutronix
	3	* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
	4	*
	5	* loosely based on an earlier driver that has
	6	* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it under
	9	* the terms of the GNU General Public License version 2 as published by the
	10	* Free Software Foundation.
	11	*/
8e005935	12
8e005935	13	#include <linux/module.h>
876989d5 SG	14	#include <linux/of.h>
876989d5 SG	15	#include <linux/of_device.h>
10f9edae AS	16	#include <linux/platform_device.h>
10f9edae AS	17	#include <linux/mfd/core.h>
8e005935	18
a0c7c1d4	19	#include "mc13xxx.h"
8e005935	20
8e005935	21	#define MC13XXX_IRQSTAT0 0
8e005935	22	#define MC13XXX_IRQMASK0 1
8e005935	23	#define MC13XXX_IRQSTAT1 3
8e005935	24	#define MC13XXX_IRQMASK1 4
8e005935 UKK	25
	26	#define MC13XXX_REVISION 7
	27	#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
	28	#define MC13XXX_REVISION_REVFULL (0x03 << 3)
	29	#define MC13XXX_REVISION_ICID (0x07 << 6)
	30	#define MC13XXX_REVISION_FIN (0x03 << 9)
	31	#define MC13XXX_REVISION_FAB (0x03 << 11)
	32	#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
	33
0312e024 UKK	34	#define MC34708_REVISION_REVMETAL (0x07 << 0)
	35	#define MC34708_REVISION_REVFULL (0x07 << 3)
	36	#define MC34708_REVISION_FIN (0x07 << 6)
	37	#define MC34708_REVISION_FAB (0x07 << 9)
	38
34a4958e MP	39	#define MC13XXX_PWRCTRL 15
	40	#define MC13XXX_PWRCTRL_WDIRESET (1 << 12)
	41
fec316d6 UKK	42	#define MC13XXX_ADC1 44
	43	#define MC13XXX_ADC1_ADEN (1 << 0)
	44	#define MC13XXX_ADC1_RAND (1 << 1)
	45	#define MC13XXX_ADC1_ADSEL (1 << 3)
	46	#define MC13XXX_ADC1_ASC (1 << 20)
	47	#define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
8e005935	48
fec316d6	49	#define MC13XXX_ADC2 45
8e005935	50
8e005935 UKK	51	void mc13xxx_lock(struct mc13xxx *mc13xxx)
	52	{
	53	if (!mutex_trylock(&mc13xxx->lock)) {
5d5a7bff	54	dev_dbg(mc13xxx->dev, "wait for %s from %ps\n",
8e005935 UKK	55	__func__, __builtin_return_address(0));
	56
	57	mutex_lock(&mc13xxx->lock);
	58	}
5d5a7bff	59	dev_dbg(mc13xxx->dev, "%s from %ps\n",
8e005935 UKK	60	__func__, __builtin_return_address(0));
	61	}
	62	EXPORT_SYMBOL(mc13xxx_lock);
	63
	64	void mc13xxx_unlock(struct mc13xxx *mc13xxx)
	65	{
5d5a7bff	66	dev_dbg(mc13xxx->dev, "%s from %ps\n",
8e005935 UKK	67	__func__, __builtin_return_address(0));
	68	mutex_unlock(&mc13xxx->lock);
	69	}
	70	EXPORT_SYMBOL(mc13xxx_unlock);
	71
8e005935 UKK	72	int mc13xxx_reg_read(struct mc13xxx mc13xxx, unsigned int offset, u32 val)
8e005935 UKK	73	{
8e005935 UKK	74	int ret;
8e005935 UKK	75
91b5e741	76	ret = regmap_read(mc13xxx->regmap, offset, val);
5006fe54	77	dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
8e005935	78
5006fe54	79	return ret;
8e005935 UKK	80	}
	81	EXPORT_SYMBOL(mc13xxx_reg_read);
	82
	83	int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
	84	{
5006fe54	85	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
8e005935	86
328fe79c	87	if (val >= BIT(24))
8e005935 UKK	88	return -EINVAL;
8e005935 UKK	89
91b5e741	90	return regmap_write(mc13xxx->regmap, offset, val);
8e005935 UKK	91	}
	92	EXPORT_SYMBOL(mc13xxx_reg_write);
	93
	94	int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
	95	u32 mask, u32 val)
	96	{
8e005935	97	BUG_ON(val & ~mask);
91b5e741 MR	98	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
91b5e741 MR	99	offset, val, mask);
8e005935	100
91b5e741	101	return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
8e005935 UKK	102	}
	103	EXPORT_SYMBOL(mc13xxx_reg_rmw);
	104
	105	int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
	106	{
10f9edae	107	int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
8e005935	108
10f9edae	109	disable_irq_nosync(virq);
8e005935	110
10f9edae	111	return 0;
8e005935 UKK	112	}
	113	EXPORT_SYMBOL(mc13xxx_irq_mask);
	114
	115	int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
	116	{
10f9edae	117	int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
8e005935	118
10f9edae	119	enable_irq(virq);
8e005935	120
10f9edae	121	return 0;
8e005935 UKK	122	}
	123	EXPORT_SYMBOL(mc13xxx_irq_unmask);
	124
	125	int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
	126	int enabled, int pending)
	127	{
	128	int ret;
	129	unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
	130	unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
	131	u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
	132
10f9edae	133	if (irq < 0 \|\| irq >= ARRAY_SIZE(mc13xxx->irqs))
8e005935 UKK	134	return -EINVAL;
	135
	136	if (enabled) {
	137	u32 mask;
	138
	139	ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
	140	if (ret)
	141	return ret;
	142
	143	*enabled = mask & irqbit;
	144	}
	145
	146	if (pending) {
	147	u32 stat;
	148
	149	ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
	150	if (ret)
	151	return ret;
	152
	153	*pending = stat & irqbit;
	154	}
	155
	156	return 0;
	157	}
	158	EXPORT_SYMBOL(mc13xxx_irq_status);
	159
8e005935 UKK	160	int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
	161	irq_handler_t handler, const char name, void dev)
	162	{
10f9edae	163	int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
8e005935	164
10f9edae	165	return devm_request_threaded_irq(mc13xxx->dev, virq, NULL, handler,
0b182c28	166	IRQF_ONESHOT, name, dev);
8e005935 UKK	167	}
	168	EXPORT_SYMBOL(mc13xxx_irq_request);
	169
	170	int mc13xxx_irq_free(struct mc13xxx mc13xxx, int irq, void dev)
	171	{
10f9edae	172	int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
8e005935	173
10f9edae	174	devm_free_irq(mc13xxx->dev, virq, dev);
8e005935 UKK	175
	176	return 0;
	177	}
	178	EXPORT_SYMBOL(mc13xxx_irq_free);
	179
8e005935	180	#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
cd0f34b0	181	static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
8e005935	182	{
cd0f34b0 UKK	183	dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
	184	"fin: %d, fab: %d, icid: %d/%d\n",
	185	mc13xxx->variant->name,
	186	maskval(revision, MC13XXX_REVISION_REVFULL),
	187	maskval(revision, MC13XXX_REVISION_REVMETAL),
	188	maskval(revision, MC13XXX_REVISION_FIN),
	189	maskval(revision, MC13XXX_REVISION_FAB),
	190	maskval(revision, MC13XXX_REVISION_ICID),
	191	maskval(revision, MC13XXX_REVISION_ICIDCODE));
	192	}
8e005935	193
0312e024 UKK	194	static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
	195	{
	196	dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
	197	mc13xxx->variant->name,
	198	maskval(revision, MC34708_REVISION_REVFULL),
	199	maskval(revision, MC34708_REVISION_REVMETAL),
	200	maskval(revision, MC34708_REVISION_FIN),
	201	maskval(revision, MC34708_REVISION_FAB));
	202	}
	203
cd0f34b0 UKK	204	/* These are only exported for mc13xxx-i2c and mc13xxx-spi */
	205	struct mc13xxx_variant mc13xxx_variant_mc13783 = {
	206	.name = "mc13783",
	207	.print_revision = mc13xxx_print_revision,
	208	};
	209	EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
8e005935	210
cd0f34b0 UKK	211	struct mc13xxx_variant mc13xxx_variant_mc13892 = {
	212	.name = "mc13892",
	213	.print_revision = mc13xxx_print_revision,
	214	};
	215	EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
8e005935	216
0312e024 UKK	217	struct mc13xxx_variant mc13xxx_variant_mc34708 = {
	218	.name = "mc34708",
	219	.print_revision = mc34708_print_revision,
	220	};
	221	EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
	222
8e005935 UKK	223	static const char mc13xxx_get_chipname(struct mc13xxx mc13xxx)
8e005935 UKK	224	{
cd0f34b0	225	return mc13xxx->variant->name;
8e005935 UKK	226	}
8e005935 UKK	227
8e005935 UKK	228	int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
8e005935 UKK	229	{
876989d5	230	return mc13xxx->flags;
8e005935 UKK	231	}
	232	EXPORT_SYMBOL(mc13xxx_get_flags);
	233
fec316d6 UKK	234	#define MC13XXX_ADC1_CHAN0_SHIFT 5
fec316d6 UKK	235	#define MC13XXX_ADC1_CHAN1_SHIFT 8
1039d762 MT	236	#define MC13783_ADC1_ATO_SHIFT 11
1039d762 MT	237	#define MC13783_ADC1_ATOX (1 << 19)
8e005935 UKK	238
	239	struct mc13xxx_adcdone_data {
	240	struct mc13xxx *mc13xxx;
	241	struct completion done;
	242	};
	243
fec316d6	244	static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
8e005935 UKK	245	{
	246	struct mc13xxx_adcdone_data *adcdone_data = data;
	247
8e005935 UKK	248	complete_all(&adcdone_data->done);
	249
	250	return IRQ_HANDLED;
	251	}
	252
fec316d6	253	#define MC13XXX_ADC_WORKING (1 << 0)
8e005935	254
fec316d6	255	int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
1039d762 MT	256	unsigned int channel, u8 ato, bool atox,
1039d762 MT	257	unsigned int *sample)
8e005935	258	{
8e005935 UKK	259	u32 adc0, adc1, old_adc0;
	260	int i, ret;
	261	struct mc13xxx_adcdone_data adcdone_data = {
	262	.mc13xxx = mc13xxx,
	263	};
	264	init_completion(&adcdone_data.done);
	265
5006fe54	266	dev_dbg(mc13xxx->dev, "%s\n", __func__);
8e005935 UKK	267
	268	mc13xxx_lock(mc13xxx);
	269
fec316d6	270	if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
8e005935 UKK	271	ret = -EBUSY;
	272	goto out;
	273	}
	274
fec316d6	275	mc13xxx->adcflags \|= MC13XXX_ADC_WORKING;
8e005935	276
fec316d6	277	mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
8e005935	278
fec316d6 UKK	279	adc0 = MC13XXX_ADC0_ADINC1 \| MC13XXX_ADC0_ADINC2;
fec316d6 UKK	280	adc1 = MC13XXX_ADC1_ADEN \| MC13XXX_ADC1_ADTRIGIGN \| MC13XXX_ADC1_ASC;
8e005935	281
ed645ccc AG	282	/*
	283	* Channels mapped through ADIN7:
	284	* 7 - General purpose ADIN7
	285	* 16 - UID
	286	* 17 - Die temperature
	287	*/
	288	if (channel > 7 && channel < 16) {
fec316d6	289	adc1 \|= MC13XXX_ADC1_ADSEL;
ed645ccc AG	290	} else if (channel == 16) {
	291	adc0 \|= MC13XXX_ADC0_ADIN7SEL_UID;
	292	channel = 7;
	293	} else if (channel == 17) {
	294	adc0 \|= MC13XXX_ADC0_ADIN7SEL_DIE;
	295	channel = 7;
	296	}
8e005935 UKK	297
8e005935 UKK	298	switch (mode) {
fec316d6 UKK	299	case MC13XXX_ADC_MODE_TS:
	300	adc0 \|= MC13XXX_ADC0_ADREFEN \| MC13XXX_ADC0_TSMOD0 \|
	301	MC13XXX_ADC0_TSMOD1;
	302	adc1 \|= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
8e005935 UKK	303	break;
8e005935 UKK	304
fec316d6	305	case MC13XXX_ADC_MODE_SINGLE_CHAN:
2161891a	306	adc0 \|= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
fec316d6 UKK	307	adc1 \|= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
fec316d6 UKK	308	adc1 \|= MC13XXX_ADC1_RAND;
8e005935 UKK	309	break;
8e005935 UKK	310
fec316d6	311	case MC13XXX_ADC_MODE_MULT_CHAN:
2161891a	312	adc0 \|= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
fec316d6	313	adc1 \|= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
8e005935 UKK	314	break;
	315
	316	default:
fec316d6	317	mc13xxx_unlock(mc13xxx);
8e005935 UKK	318	return -EINVAL;
	319	}
	320
1039d762 MT	321	adc1 \|= ato << MC13783_ADC1_ATO_SHIFT;
	322	if (atox)
	323	adc1 \|= MC13783_ADC1_ATOX;
5006fe54 MR	324
5006fe54 MR	325	dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
fec316d6 UKK	326	mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
fec316d6 UKK	327	mc13xxx_handler_adcdone, __func__, &adcdone_data);
8e005935	328
fec316d6 UKK	329	mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
fec316d6 UKK	330	mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
8e005935 UKK	331
	332	mc13xxx_unlock(mc13xxx);
	333
	334	ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
	335
	336	if (!ret)
	337	ret = -ETIMEDOUT;
	338
	339	mc13xxx_lock(mc13xxx);
	340
fec316d6	341	mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
8e005935 UKK	342
	343	if (ret > 0)
	344	for (i = 0; i < 4; ++i) {
	345	ret = mc13xxx_reg_read(mc13xxx,
fec316d6	346	MC13XXX_ADC2, &sample[i]);
8e005935 UKK	347	if (ret)
	348	break;
	349	}
	350
fec316d6	351	if (mode == MC13XXX_ADC_MODE_TS)
8e005935	352	/* restore TSMOD */
fec316d6	353	mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
8e005935	354
fec316d6	355	mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
8e005935 UKK	356	out:
	357	mc13xxx_unlock(mc13xxx);
	358
	359	return ret;
	360	}
fec316d6	361	EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
8e005935 UKK	362
8e005935 UKK	363	static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
c8a03c96	364	const char format, void pdata, size_t pdata_size)
8e005935 UKK	365	{
	366	char buf[30];
	367	const char *name = mc13xxx_get_chipname(mc13xxx);
	368
	369	struct mfd_cell cell = {
c8a03c96 SO	370	.platform_data = pdata,
c8a03c96 SO	371	.pdata_size = pdata_size,
8e005935 UKK	372	};
	373
	374	/* there is no asnprintf in the kernel :-( */
	375	if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
	376	return -E2BIG;
	377
	378	cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
	379	if (!cell.name)
	380	return -ENOMEM;
	381
10f9edae AS	382	return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0,
10f9edae AS	383	regmap_irq_get_domain(mc13xxx->irq_data));
8e005935 UKK	384	}
	385
	386	static int mc13xxx_add_subdevice(struct mc13xxx mc13xxx, const char format)
	387	{
c8a03c96	388	return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
8e005935 UKK	389	}
8e005935 UKK	390
876989d5 SG	391	#ifdef CONFIG_OF
	392	static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
	393	{
91b5e741	394	struct device_node *np = mc13xxx->dev->of_node;
876989d5 SG	395
	396	if (!np)
	397	return -ENODEV;
	398
505b9e57	399	if (of_property_read_bool(np, "fsl,mc13xxx-uses-adc"))
876989d5 SG	400	mc13xxx->flags \|= MC13XXX_USE_ADC;
876989d5 SG	401
505b9e57	402	if (of_property_read_bool(np, "fsl,mc13xxx-uses-codec"))
876989d5 SG	403	mc13xxx->flags \|= MC13XXX_USE_CODEC;
876989d5 SG	404
505b9e57	405	if (of_property_read_bool(np, "fsl,mc13xxx-uses-rtc"))
876989d5 SG	406	mc13xxx->flags \|= MC13XXX_USE_RTC;
876989d5 SG	407
505b9e57	408	if (of_property_read_bool(np, "fsl,mc13xxx-uses-touch"))
876989d5 SG	409	mc13xxx->flags \|= MC13XXX_USE_TOUCHSCREEN;
	410
	411	return 0;
	412	}
	413	#else
	414	static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
	415	{
	416	return -ENODEV;
	417	}
	418	#endif
	419
db9ef449	420	int mc13xxx_common_init(struct device *dev)
8e005935	421	{
db9ef449 AS	422	struct mc13xxx_platform_data *pdata = dev_get_platdata(dev);
db9ef449 AS	423	struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
cd0f34b0	424	u32 revision;
10f9edae	425	int i, ret;
8e005935	426
db9ef449	427	mc13xxx->dev = dev;
8e005935	428
cd0f34b0	429	ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
5006fe54	430	if (ret)
db9ef449	431	return ret;
8e005935	432
cd0f34b0 UKK	433	mc13xxx->variant->print_revision(mc13xxx, revision);
cd0f34b0 UKK	434
34a4958e MP	435	ret = mc13xxx_reg_rmw(mc13xxx, MC13XXX_PWRCTRL,
	436	MC13XXX_PWRCTRL_WDIRESET, MC13XXX_PWRCTRL_WDIRESET);
	437	if (ret)
	438	return ret;
	439
10f9edae AS	440	for (i = 0; i < ARRAY_SIZE(mc13xxx->irqs); i++) {
	441	mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;
	442	mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG);
	443	}
8e005935	444
10f9edae AS	445	mc13xxx->irq_chip.name = dev_name(dev);
	446	mc13xxx->irq_chip.status_base = MC13XXX_IRQSTAT0;
	447	mc13xxx->irq_chip.mask_base = MC13XXX_IRQMASK0;
	448	mc13xxx->irq_chip.ack_base = MC13XXX_IRQSTAT0;
	449	mc13xxx->irq_chip.irq_reg_stride = MC13XXX_IRQSTAT1 - MC13XXX_IRQSTAT0;
	450	mc13xxx->irq_chip.init_ack_masked = true;
	451	mc13xxx->irq_chip.use_ack = true;
	452	mc13xxx->irq_chip.num_regs = MC13XXX_IRQ_REG_CNT;
	453	mc13xxx->irq_chip.irqs = mc13xxx->irqs;
	454	mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);
	455
	456	ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
	457	0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
8e005935	458	if (ret)
db9ef449	459	return ret;
8e005935	460
48ca9a52 FE	461	mutex_init(&mc13xxx->lock);
48ca9a52 FE	462
876989d5 SG	463	if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
	464	mc13xxx->flags = pdata->flags;
	465
876989d5 SG	466	if (pdata) {
	467	mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
	468	&pdata->regulators, sizeof(pdata->regulators));
c8a03c96 SO	469	mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
c8a03c96 SO	470	pdata->leds, sizeof(*pdata->leds));
30fc7ac3 PR	471	mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
30fc7ac3 PR	472	pdata->buttons, sizeof(*pdata->buttons));
a2ff8459 AS	473	if (mc13xxx->flags & MC13XXX_USE_CODEC)
	474	mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
	475	pdata->codec, sizeof(*pdata->codec));
	476	if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
	477	mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
	478	&pdata->touch, sizeof(pdata->touch));
876989d5 SG	479	} else {
	480	mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
	481	mc13xxx_add_subdevice(mc13xxx, "%s-led");
	482	mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
a2ff8459 AS	483	if (mc13xxx->flags & MC13XXX_USE_CODEC)
	484	mc13xxx_add_subdevice(mc13xxx, "%s-codec");
	485	if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
	486	mc13xxx_add_subdevice(mc13xxx, "%s-ts");
876989d5	487	}
30fc7ac3	488
10f9edae AS	489	if (mc13xxx->flags & MC13XXX_USE_ADC)
	490	mc13xxx_add_subdevice(mc13xxx, "%s-adc");
	491
	492	if (mc13xxx->flags & MC13XXX_USE_RTC)
	493	mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
	494
8e005935 UKK	495	return 0;
8e005935 UKK	496	}
a0c7c1d4	497	EXPORT_SYMBOL_GPL(mc13xxx_common_init);
8e005935	498
db9ef449	499	int mc13xxx_common_exit(struct device *dev)
8e005935	500	{
db9ef449 AS	501	struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
db9ef449 AS	502
db9ef449	503	mfd_remove_devices(dev);
10f9edae	504	regmap_del_irq_chip(mc13xxx->irq, mc13xxx->irq_data);
db9ef449	505	mutex_destroy(&mc13xxx->lock);
8e005935	506
db9ef449	507	return 0;
8e005935	508	}
db9ef449	509	EXPORT_SYMBOL_GPL(mc13xxx_common_exit);
8e005935 UKK	510
	511	MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
	512	MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
	513	MODULE_LICENSE("GPL v2");