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Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas...
[linux-2.6-block.git] / drivers / mfd / mc13xxx-core.c
CommitLineData
8e005935
UKK		 1/*
2 * Copyright 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
11 */
8e005935
UKK		 12
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/mutex.h>
17#include <linux/interrupt.h>
8e005935
UKK		 18#include <linux/mfd/core.h>
19#include <linux/mfd/mc13xxx.h>
876989d5
SG		 20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/of_gpio.h>
8e005935 23
a0c7c1d4 24#include "mc13xxx.h"
8e005935 25
8e005935
UKK		 26#define MC13XXX_IRQSTAT0 0
27#define MC13XXX_IRQSTAT0_ADCDONEI (1 << 0)
28#define MC13XXX_IRQSTAT0_ADCBISDONEI (1 << 1)
29#define MC13XXX_IRQSTAT0_TSI (1 << 2)
30#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
31#define MC13783_IRQSTAT0_WLOWI (1 << 4)
32#define MC13XXX_IRQSTAT0_CHGDETI (1 << 6)
33#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
34#define MC13XXX_IRQSTAT0_CHGREVI (1 << 8)
35#define MC13XXX_IRQSTAT0_CHGSHORTI (1 << 9)
36#define MC13XXX_IRQSTAT0_CCCVI (1 << 10)
37#define MC13XXX_IRQSTAT0_CHGCURRI (1 << 11)
38#define MC13XXX_IRQSTAT0_BPONI (1 << 12)
39#define MC13XXX_IRQSTAT0_LOBATLI (1 << 13)
40#define MC13XXX_IRQSTAT0_LOBATHI (1 << 14)
41#define MC13783_IRQSTAT0_UDPI (1 << 15)
42#define MC13783_IRQSTAT0_USBI (1 << 16)
43#define MC13783_IRQSTAT0_IDI (1 << 19)
44#define MC13783_IRQSTAT0_SE1I (1 << 21)
45#define MC13783_IRQSTAT0_CKDETI (1 << 22)
46#define MC13783_IRQSTAT0_UDMI (1 << 23)
47
48#define MC13XXX_IRQMASK0 1
49#define MC13XXX_IRQMASK0_ADCDONEM MC13XXX_IRQSTAT0_ADCDONEI
50#define MC13XXX_IRQMASK0_ADCBISDONEM MC13XXX_IRQSTAT0_ADCBISDONEI
51#define MC13XXX_IRQMASK0_TSM MC13XXX_IRQSTAT0_TSI
52#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
53#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
54#define MC13XXX_IRQMASK0_CHGDETM MC13XXX_IRQSTAT0_CHGDETI
55#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
56#define MC13XXX_IRQMASK0_CHGREVM MC13XXX_IRQSTAT0_CHGREVI
57#define MC13XXX_IRQMASK0_CHGSHORTM MC13XXX_IRQSTAT0_CHGSHORTI
58#define MC13XXX_IRQMASK0_CCCVM MC13XXX_IRQSTAT0_CCCVI
59#define MC13XXX_IRQMASK0_CHGCURRM MC13XXX_IRQSTAT0_CHGCURRI
60#define MC13XXX_IRQMASK0_BPONM MC13XXX_IRQSTAT0_BPONI
61#define MC13XXX_IRQMASK0_LOBATLM MC13XXX_IRQSTAT0_LOBATLI
62#define MC13XXX_IRQMASK0_LOBATHM MC13XXX_IRQSTAT0_LOBATHI
63#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
64#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
65#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
66#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
67#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
68#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
69
70#define MC13XXX_IRQSTAT1 3
71#define MC13XXX_IRQSTAT1_1HZI (1 << 0)
72#define MC13XXX_IRQSTAT1_TODAI (1 << 1)
73#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
74#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
75#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
76#define MC13XXX_IRQSTAT1_SYSRSTI (1 << 6)
77#define MC13XXX_IRQSTAT1_RTCRSTI (1 << 7)
78#define MC13XXX_IRQSTAT1_PCI (1 << 8)
79#define MC13XXX_IRQSTAT1_WARMI (1 << 9)
80#define MC13XXX_IRQSTAT1_MEMHLDI (1 << 10)
81#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
82#define MC13XXX_IRQSTAT1_THWARNLI (1 << 12)
83#define MC13XXX_IRQSTAT1_THWARNHI (1 << 13)
84#define MC13XXX_IRQSTAT1_CLKI (1 << 14)
85#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
86#define MC13783_IRQSTAT1_MC2BI (1 << 17)
87#define MC13783_IRQSTAT1_HSDETI (1 << 18)
88#define MC13783_IRQSTAT1_HSLI (1 << 19)
89#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
90#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
91
92#define MC13XXX_IRQMASK1 4
93#define MC13XXX_IRQMASK1_1HZM MC13XXX_IRQSTAT1_1HZI
94#define MC13XXX_IRQMASK1_TODAM MC13XXX_IRQSTAT1_TODAI
95#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
96#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
97#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
98#define MC13XXX_IRQMASK1_SYSRSTM MC13XXX_IRQSTAT1_SYSRSTI
99#define MC13XXX_IRQMASK1_RTCRSTM MC13XXX_IRQSTAT1_RTCRSTI
100#define MC13XXX_IRQMASK1_PCM MC13XXX_IRQSTAT1_PCI
101#define MC13XXX_IRQMASK1_WARMM MC13XXX_IRQSTAT1_WARMI
102#define MC13XXX_IRQMASK1_MEMHLDM MC13XXX_IRQSTAT1_MEMHLDI
103#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
104#define MC13XXX_IRQMASK1_THWARNLM MC13XXX_IRQSTAT1_THWARNLI
105#define MC13XXX_IRQMASK1_THWARNHM MC13XXX_IRQSTAT1_THWARNHI
106#define MC13XXX_IRQMASK1_CLKM MC13XXX_IRQSTAT1_CLKI
107#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
108#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
109#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
110#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
111#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
112#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
113
114#define MC13XXX_REVISION 7
115#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
116#define MC13XXX_REVISION_REVFULL (0x03 << 3)
117#define MC13XXX_REVISION_ICID (0x07 << 6)
118#define MC13XXX_REVISION_FIN (0x03 << 9)
119#define MC13XXX_REVISION_FAB (0x03 << 11)
120#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
121
0312e024
UKK		 122#define MC34708_REVISION_REVMETAL (0x07 << 0)
123#define MC34708_REVISION_REVFULL (0x07 << 3)
124#define MC34708_REVISION_FIN (0x07 << 6)
125#define MC34708_REVISION_FAB (0x07 << 9)
126
fec316d6
UKK		 127#define MC13XXX_ADC1 44
128#define MC13XXX_ADC1_ADEN (1 << 0)
129#define MC13XXX_ADC1_RAND (1 << 1)
130#define MC13XXX_ADC1_ADSEL (1 << 3)
131#define MC13XXX_ADC1_ASC (1 << 20)
132#define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
8e005935 133
fec316d6 134#define MC13XXX_ADC2 45
8e005935 135
8e005935
UKK		 136void mc13xxx_lock(struct mc13xxx *mc13xxx)
137{
138 if (!mutex_trylock(&mc13xxx->lock)) {
5006fe54 139 dev_dbg(mc13xxx->dev, "wait for %s from %pf\n",
8e005935
UKK		 140 __func__, __builtin_return_address(0));
141
142 mutex_lock(&mc13xxx->lock);
143 }
5006fe54 144 dev_dbg(mc13xxx->dev, "%s from %pf\n",
8e005935
UKK		 145 __func__, __builtin_return_address(0));
146}
147EXPORT_SYMBOL(mc13xxx_lock);
148
149void mc13xxx_unlock(struct mc13xxx *mc13xxx)
150{
5006fe54 151 dev_dbg(mc13xxx->dev, "%s from %pf\n",
8e005935
UKK		 152 __func__, __builtin_return_address(0));
153 mutex_unlock(&mc13xxx->lock);
154}
155EXPORT_SYMBOL(mc13xxx_unlock);
156
8e005935
UKK		 157int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
158{
8e005935
UKK		 159 int ret;
160
161 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
162
163 if (offset > MC13XXX_NUMREGS)
164 return -EINVAL;
165
91b5e741 166 ret = regmap_read(mc13xxx->regmap, offset, val);
5006fe54 167 dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
8e005935 168
5006fe54 169 return ret;
8e005935
UKK		 170}
171EXPORT_SYMBOL(mc13xxx_reg_read);
172
173int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
174{
8e005935
UKK		 175 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
176
5006fe54 177 dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
8e005935
UKK		 178
179 if (offset > MC13XXX_NUMREGS || val > 0xffffff)
180 return -EINVAL;
181
91b5e741 182 return regmap_write(mc13xxx->regmap, offset, val);
8e005935
UKK		 183}
184EXPORT_SYMBOL(mc13xxx_reg_write);
185
186int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
187 u32 mask, u32 val)
188{
91b5e741 189 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
8e005935 190 BUG_ON(val & ~mask);
91b5e741
MR		 191 dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
192 offset, val, mask);
8e005935 193
91b5e741 194 return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
8e005935
UKK		 195}
196EXPORT_SYMBOL(mc13xxx_reg_rmw);
197
198int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
199{
200 int ret;
201 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
202 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
203 u32 mask;
204
205 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
206 return -EINVAL;
207
208 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
209 if (ret)
210 return ret;
211
212 if (mask & irqbit)
213 /* already masked */
214 return 0;
215
216 return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
217}
218EXPORT_SYMBOL(mc13xxx_irq_mask);
219
220int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
221{
222 int ret;
223 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
224 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
225 u32 mask;
226
227 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
228 return -EINVAL;
229
230 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
231 if (ret)
232 return ret;
233
234 if (!(mask & irqbit))
235 /* already unmasked */
236 return 0;
237
238 return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
239}
240EXPORT_SYMBOL(mc13xxx_irq_unmask);
241
242int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
243 int *enabled, int *pending)
244{
245 int ret;
246 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
247 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
248 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
249
250 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
251 return -EINVAL;
252
253 if (enabled) {
254 u32 mask;
255
256 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
257 if (ret)
258 return ret;
259
260 *enabled = mask & irqbit;
261 }
262
263 if (pending) {
264 u32 stat;
265
266 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
267 if (ret)
268 return ret;
269
270 *pending = stat & irqbit;
271 }
272
273 return 0;
274}
275EXPORT_SYMBOL(mc13xxx_irq_status);
276
277int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
278{
279 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
280 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
281
282 BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
283
284 return mc13xxx_reg_write(mc13xxx, offstat, val);
285}
286EXPORT_SYMBOL(mc13xxx_irq_ack);
287
288int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
289 irq_handler_t handler, const char *name, void *dev)
290{
291 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
292 BUG_ON(!handler);
293
294 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
295 return -EINVAL;
296
297 if (mc13xxx->irqhandler[irq])
298 return -EBUSY;
299
300 mc13xxx->irqhandler[irq] = handler;
301 mc13xxx->irqdata[irq] = dev;
302
303 return 0;
304}
305EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
306
307int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
308 irq_handler_t handler, const char *name, void *dev)
309{
310 int ret;
311
312 ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
313 if (ret)
314 return ret;
315
316 ret = mc13xxx_irq_unmask(mc13xxx, irq);
317 if (ret) {
318 mc13xxx->irqhandler[irq] = NULL;
319 mc13xxx->irqdata[irq] = NULL;
320 return ret;
321 }
322
323 return 0;
324}
325EXPORT_SYMBOL(mc13xxx_irq_request);
326
327int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
328{
329 int ret;
330 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
331
332 if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
333 mc13xxx->irqdata[irq] != dev)
334 return -EINVAL;
335
336 ret = mc13xxx_irq_mask(mc13xxx, irq);
337 if (ret)
338 return ret;
339
340 mc13xxx->irqhandler[irq] = NULL;
341 mc13xxx->irqdata[irq] = NULL;
342
343 return 0;
344}
345EXPORT_SYMBOL(mc13xxx_irq_free);
346
347static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
348{
349 return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
350}
351
352/*
353 * returns: number of handled irqs or negative error
354 * locking: holds mc13xxx->lock
355 */
356static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
357 unsigned int offstat, unsigned int offmask, int baseirq)
358{
359 u32 stat, mask;
360 int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
361 int num_handled = 0;
362
363 if (ret)
364 return ret;
365
366 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
367 if (ret)
368 return ret;
369
370 while (stat & ~mask) {
371 int irq = __ffs(stat & ~mask);
372
373 stat &= ~(1 << irq);
374
375 if (likely(mc13xxx->irqhandler[baseirq + irq])) {
376 irqreturn_t handled;
377
378 handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
379 if (handled == IRQ_HANDLED)
380 num_handled++;
381 } else {
5006fe54 382 dev_err(mc13xxx->dev,
8e005935
UKK		 383 "BUG: irq %u but no handler\n",
384 baseirq + irq);
385
386 mask |= 1 << irq;
387
388 ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
389 }
390 }
391
392 return num_handled;
393}
394
395static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
396{
397 struct mc13xxx *mc13xxx = data;
398 irqreturn_t ret;
399 int handled = 0;
400
401 mc13xxx_lock(mc13xxx);
402
403 ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
404 MC13XXX_IRQMASK0, 0);
405 if (ret > 0)
406 handled = 1;
407
408 ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
409 MC13XXX_IRQMASK1, 24);
410 if (ret > 0)
411 handled = 1;
412
413 mc13xxx_unlock(mc13xxx);
414
415 return IRQ_RETVAL(handled);
416}
417
8e005935 418#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
cd0f34b0 419static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
8e005935 420{
cd0f34b0
UKK		 421 dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
422 "fin: %d, fab: %d, icid: %d/%d\n",
423 mc13xxx->variant->name,
424 maskval(revision, MC13XXX_REVISION_REVFULL),
425 maskval(revision, MC13XXX_REVISION_REVMETAL),
426 maskval(revision, MC13XXX_REVISION_FIN),
427 maskval(revision, MC13XXX_REVISION_FAB),
428 maskval(revision, MC13XXX_REVISION_ICID),
429 maskval(revision, MC13XXX_REVISION_ICIDCODE));
430}
8e005935 431
0312e024
UKK		 432static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
433{
434 dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
435 mc13xxx->variant->name,
436 maskval(revision, MC34708_REVISION_REVFULL),
437 maskval(revision, MC34708_REVISION_REVMETAL),
438 maskval(revision, MC34708_REVISION_FIN),
439 maskval(revision, MC34708_REVISION_FAB));
440}
441
cd0f34b0
UKK		 442/* These are only exported for mc13xxx-i2c and mc13xxx-spi */
443struct mc13xxx_variant mc13xxx_variant_mc13783 = {
444 .name = "mc13783",
445 .print_revision = mc13xxx_print_revision,
446};
447EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
8e005935 448
cd0f34b0
UKK		 449struct mc13xxx_variant mc13xxx_variant_mc13892 = {
450 .name = "mc13892",
451 .print_revision = mc13xxx_print_revision,
452};
453EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
8e005935 454
0312e024
UKK		 455struct mc13xxx_variant mc13xxx_variant_mc34708 = {
456 .name = "mc34708",
457 .print_revision = mc34708_print_revision,
458};
459EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
460
8e005935
UKK		 461static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
462{
cd0f34b0 463 return mc13xxx->variant->name;
8e005935
UKK		 464}
465
8e005935
UKK		 466int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
467{
876989d5 468 return mc13xxx->flags;
8e005935
UKK		 469}
470EXPORT_SYMBOL(mc13xxx_get_flags);
471
fec316d6
UKK		 472#define MC13XXX_ADC1_CHAN0_SHIFT 5
473#define MC13XXX_ADC1_CHAN1_SHIFT 8
1039d762
MT		 474#define MC13783_ADC1_ATO_SHIFT 11
475#define MC13783_ADC1_ATOX (1 << 19)
8e005935
UKK		 476
477struct mc13xxx_adcdone_data {
478 struct mc13xxx *mc13xxx;
479 struct completion done;
480};
481
fec316d6 482static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
8e005935
UKK		 483{
484 struct mc13xxx_adcdone_data *adcdone_data = data;
485
486 mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
487
488 complete_all(&adcdone_data->done);
489
490 return IRQ_HANDLED;
491}
492
fec316d6 493#define MC13XXX_ADC_WORKING (1 << 0)
8e005935 494
fec316d6 495int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
1039d762
MT		 496 unsigned int channel, u8 ato, bool atox,
497 unsigned int *sample)
8e005935 498{
8e005935
UKK		 499 u32 adc0, adc1, old_adc0;
500 int i, ret;
501 struct mc13xxx_adcdone_data adcdone_data = {
502 .mc13xxx = mc13xxx,
503 };
504 init_completion(&adcdone_data.done);
505
5006fe54 506 dev_dbg(mc13xxx->dev, "%s\n", __func__);
8e005935
UKK		 507
508 mc13xxx_lock(mc13xxx);
509
fec316d6 510 if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
8e005935
UKK		 511 ret = -EBUSY;
512 goto out;
513 }
514
fec316d6 515 mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
8e005935 516
fec316d6 517 mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
8e005935 518
fec316d6
UKK		 519 adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
520 adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
8e005935
UKK		 521
522 if (channel > 7)
fec316d6 523 adc1 |= MC13XXX_ADC1_ADSEL;
8e005935
UKK		 524
525 switch (mode) {
fec316d6
UKK		 526 case MC13XXX_ADC_MODE_TS:
527 adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
528 MC13XXX_ADC0_TSMOD1;
529 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
8e005935
UKK		 530 break;
531
fec316d6 532 case MC13XXX_ADC_MODE_SINGLE_CHAN:
2161891a 533 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
fec316d6
UKK		 534 adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
535 adc1 |= MC13XXX_ADC1_RAND;
8e005935
UKK		 536 break;
537
fec316d6 538 case MC13XXX_ADC_MODE_MULT_CHAN:
2161891a 539 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
fec316d6 540 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
8e005935
UKK		 541 break;
542
543 default:
fec316d6 544 mc13xxx_unlock(mc13xxx);
8e005935
UKK		 545 return -EINVAL;
546 }
547
1039d762
MT		 548 adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
549 if (atox)
550 adc1 |= MC13783_ADC1_ATOX;
5006fe54
MR		 551
552 dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
fec316d6
UKK		 553 mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
554 mc13xxx_handler_adcdone, __func__, &adcdone_data);
555 mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
8e005935 556
fec316d6
UKK		 557 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
558 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
8e005935
UKK		 559
560 mc13xxx_unlock(mc13xxx);
561
562 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
563
564 if (!ret)
565 ret = -ETIMEDOUT;
566
567 mc13xxx_lock(mc13xxx);
568
fec316d6 569 mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
8e005935
UKK		 570
571 if (ret > 0)
572 for (i = 0; i < 4; ++i) {
573 ret = mc13xxx_reg_read(mc13xxx,
fec316d6 574 MC13XXX_ADC2, &sample[i]);
8e005935
UKK		 575 if (ret)
576 break;
577 }
578
fec316d6 579 if (mode == MC13XXX_ADC_MODE_TS)
8e005935 580 /* restore TSMOD */
fec316d6 581 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
8e005935 582
fec316d6 583 mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
8e005935
UKK		 584out:
585 mc13xxx_unlock(mc13xxx);
586
587 return ret;
588}
fec316d6 589EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
8e005935
UKK		 590
591static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
c8a03c96 592 const char *format, void *pdata, size_t pdata_size)
8e005935
UKK		 593{
594 char buf[30];
595 const char *name = mc13xxx_get_chipname(mc13xxx);
596
597 struct mfd_cell cell = {
c8a03c96
SO		 598 .platform_data = pdata,
599 .pdata_size = pdata_size,
8e005935
UKK		 600 };
601
602 /* there is no asnprintf in the kernel :-( */
603 if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
604 return -E2BIG;
605
606 cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
607 if (!cell.name)
608 return -ENOMEM;
609
55692af5 610 return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0, NULL);
8e005935
UKK		 611}
612
613static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
614{
c8a03c96 615 return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
8e005935
UKK		 616}
617
876989d5
SG		 618#ifdef CONFIG_OF
619static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
620{
91b5e741 621 struct device_node *np = mc13xxx->dev->of_node;
876989d5
SG		 622
623 if (!np)
624 return -ENODEV;
625
626 if (of_get_property(np, "fsl,mc13xxx-uses-adc", NULL))
627 mc13xxx->flags |= MC13XXX_USE_ADC;
628
629 if (of_get_property(np, "fsl,mc13xxx-uses-codec", NULL))
630 mc13xxx->flags |= MC13XXX_USE_CODEC;
631
632 if (of_get_property(np, "fsl,mc13xxx-uses-rtc", NULL))
633 mc13xxx->flags |= MC13XXX_USE_RTC;
634
635 if (of_get_property(np, "fsl,mc13xxx-uses-touch", NULL))
636 mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
637
638 return 0;
639}
640#else
641static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
642{
643 return -ENODEV;
644}
645#endif
646
a0c7c1d4 647int mc13xxx_common_init(struct mc13xxx *mc13xxx,
5006fe54 648 struct mc13xxx_platform_data *pdata, int irq)
8e005935 649{
8e005935 650 int ret;
cd0f34b0 651 u32 revision;
8e005935 652
8e005935
UKK		 653 mc13xxx_lock(mc13xxx);
654
cd0f34b0 655 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
5006fe54 656 if (ret)
8e005935
UKK		 657 goto err_revision;
658
cd0f34b0
UKK		 659 mc13xxx->variant->print_revision(mc13xxx, revision);
660
8e005935
UKK		 661 /* mask all irqs */
662 ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
663 if (ret)
664 goto err_mask;
665
666 ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
667 if (ret)
668 goto err_mask;
669
5006fe54 670 ret = request_threaded_irq(irq, NULL, mc13xxx_irq_thread,
8e005935
UKK		 671 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
672
673 if (ret) {
674err_mask:
675err_revision:
e1b88eb0 676 mc13xxx_unlock(mc13xxx);
8e005935
UKK		 677 return ret;
678 }
679
5006fe54
MR		 680 mc13xxx->irq = irq;
681
8e005935
UKK		 682 mc13xxx_unlock(mc13xxx);
683
876989d5
SG		 684 if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
685 mc13xxx->flags = pdata->flags;
686
687 if (mc13xxx->flags & MC13XXX_USE_ADC)
8e005935
UKK		 688 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
689
876989d5 690 if (mc13xxx->flags & MC13XXX_USE_CODEC)
e3a0871c
PR		 691 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
692 pdata->codec, sizeof(*pdata->codec));
8e005935 693
876989d5 694 if (mc13xxx->flags & MC13XXX_USE_RTC)
8e005935
UKK		 695 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
696
876989d5 697 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
1039d762
MT		 698 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
699 &pdata->touch, sizeof(pdata->touch));
8e005935 700
876989d5
SG		 701 if (pdata) {
702 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
703 &pdata->regulators, sizeof(pdata->regulators));
c8a03c96
SO		 704 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
705 pdata->leds, sizeof(*pdata->leds));
30fc7ac3
PR		 706 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
707 pdata->buttons, sizeof(*pdata->buttons));
876989d5
SG		 708 } else {
709 mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
710 mc13xxx_add_subdevice(mc13xxx, "%s-led");
711 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
712 }
30fc7ac3 713
8e005935
UKK		 714 return 0;
715}
a0c7c1d4 716EXPORT_SYMBOL_GPL(mc13xxx_common_init);
8e005935 717
a0c7c1d4 718void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
8e005935 719{
5006fe54 720 free_irq(mc13xxx->irq, mc13xxx);
8e005935 721
5006fe54 722 mfd_remove_devices(mc13xxx->dev);
8e005935 723}
a0c7c1d4 724EXPORT_SYMBOL_GPL(mc13xxx_common_cleanup);
8e005935
UKK		 725
726MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
727MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
728MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)