Commit | Line | Data |
---|---|---|
d50f8f33 HZ |
1 | /* |
2 | * Base driver for Maxim MAX8925 | |
3 | * | |
1f1cf8f9 | 4 | * Copyright (C) 2009-2010 Marvell International Ltd. |
d50f8f33 HZ |
5 | * Haojian Zhuang <haojian.zhuang@marvell.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/i2c.h> | |
1f1cf8f9 | 15 | #include <linux/irq.h> |
d50f8f33 HZ |
16 | #include <linux/interrupt.h> |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/mfd/core.h> | |
19 | #include <linux/mfd/max8925.h> | |
20 | ||
1ad99893 HZ |
21 | static struct resource backlight_resources[] = { |
22 | { | |
23 | .name = "max8925-backlight", | |
24 | .start = MAX8925_WLED_MODE_CNTL, | |
25 | .end = MAX8925_WLED_CNTL, | |
26 | .flags = IORESOURCE_IO, | |
27 | }, | |
28 | }; | |
29 | ||
30 | static struct mfd_cell backlight_devs[] = { | |
31 | { | |
32 | .name = "max8925-backlight", | |
33 | .num_resources = 1, | |
34 | .resources = &backlight_resources[0], | |
35 | .id = -1, | |
36 | }, | |
37 | }; | |
38 | ||
39 | static struct resource touch_resources[] = { | |
40 | { | |
41 | .name = "max8925-tsc", | |
42 | .start = MAX8925_TSC_IRQ, | |
43 | .end = MAX8925_ADC_RES_END, | |
44 | .flags = IORESOURCE_IO, | |
45 | }, | |
46 | }; | |
47 | ||
48 | static struct mfd_cell touch_devs[] = { | |
49 | { | |
50 | .name = "max8925-touch", | |
51 | .num_resources = 1, | |
52 | .resources = &touch_resources[0], | |
53 | .id = -1, | |
54 | }, | |
55 | }; | |
56 | ||
1f1cf8f9 HZ |
57 | static struct resource power_supply_resources[] = { |
58 | { | |
59 | .name = "max8925-power", | |
60 | .start = MAX8925_CHG_IRQ1, | |
61 | .end = MAX8925_CHG_IRQ1_MASK, | |
62 | .flags = IORESOURCE_IO, | |
63 | }, | |
64 | }; | |
65 | ||
66 | static struct mfd_cell power_devs[] = { | |
67 | { | |
68 | .name = "max8925-power", | |
69 | .num_resources = 1, | |
70 | .resources = &power_supply_resources[0], | |
71 | .id = -1, | |
72 | }, | |
73 | }; | |
74 | ||
75 | static struct resource rtc_resources[] = { | |
76 | { | |
77 | .name = "max8925-rtc", | |
78 | .start = MAX8925_RTC_IRQ, | |
79 | .end = MAX8925_RTC_IRQ_MASK, | |
80 | .flags = IORESOURCE_IO, | |
81 | }, | |
82 | }; | |
83 | ||
84 | static struct mfd_cell rtc_devs[] = { | |
85 | { | |
86 | .name = "max8925-rtc", | |
87 | .num_resources = 1, | |
88 | .resources = &rtc_resources[0], | |
89 | .id = -1, | |
90 | }, | |
91 | }; | |
92 | ||
1ad99893 HZ |
93 | #define MAX8925_REG_RESOURCE(_start, _end) \ |
94 | { \ | |
95 | .start = MAX8925_##_start, \ | |
96 | .end = MAX8925_##_end, \ | |
97 | .flags = IORESOURCE_IO, \ | |
98 | } | |
99 | ||
100 | static struct resource regulator_resources[] = { | |
101 | MAX8925_REG_RESOURCE(SDCTL1, SDCTL1), | |
102 | MAX8925_REG_RESOURCE(SDCTL2, SDCTL2), | |
103 | MAX8925_REG_RESOURCE(SDCTL3, SDCTL3), | |
104 | MAX8925_REG_RESOURCE(LDOCTL1, LDOCTL1), | |
105 | MAX8925_REG_RESOURCE(LDOCTL2, LDOCTL2), | |
106 | MAX8925_REG_RESOURCE(LDOCTL3, LDOCTL3), | |
107 | MAX8925_REG_RESOURCE(LDOCTL4, LDOCTL4), | |
108 | MAX8925_REG_RESOURCE(LDOCTL5, LDOCTL5), | |
109 | MAX8925_REG_RESOURCE(LDOCTL6, LDOCTL6), | |
110 | MAX8925_REG_RESOURCE(LDOCTL7, LDOCTL7), | |
111 | MAX8925_REG_RESOURCE(LDOCTL8, LDOCTL8), | |
112 | MAX8925_REG_RESOURCE(LDOCTL9, LDOCTL9), | |
113 | MAX8925_REG_RESOURCE(LDOCTL10, LDOCTL10), | |
114 | MAX8925_REG_RESOURCE(LDOCTL11, LDOCTL11), | |
115 | MAX8925_REG_RESOURCE(LDOCTL12, LDOCTL12), | |
116 | MAX8925_REG_RESOURCE(LDOCTL13, LDOCTL13), | |
117 | MAX8925_REG_RESOURCE(LDOCTL14, LDOCTL14), | |
118 | MAX8925_REG_RESOURCE(LDOCTL15, LDOCTL15), | |
119 | MAX8925_REG_RESOURCE(LDOCTL16, LDOCTL16), | |
120 | MAX8925_REG_RESOURCE(LDOCTL17, LDOCTL17), | |
121 | MAX8925_REG_RESOURCE(LDOCTL18, LDOCTL18), | |
122 | MAX8925_REG_RESOURCE(LDOCTL19, LDOCTL19), | |
123 | MAX8925_REG_RESOURCE(LDOCTL20, LDOCTL20), | |
124 | }; | |
125 | ||
126 | #define MAX8925_REG_DEVS(_id) \ | |
127 | { \ | |
128 | .name = "max8925-regulator", \ | |
129 | .num_resources = 1, \ | |
130 | .resources = ®ulator_resources[MAX8925_ID_##_id], \ | |
131 | .id = MAX8925_ID_##_id, \ | |
132 | } | |
133 | ||
134 | static struct mfd_cell regulator_devs[] = { | |
135 | MAX8925_REG_DEVS(SD1), | |
136 | MAX8925_REG_DEVS(SD2), | |
137 | MAX8925_REG_DEVS(SD3), | |
138 | MAX8925_REG_DEVS(LDO1), | |
139 | MAX8925_REG_DEVS(LDO2), | |
140 | MAX8925_REG_DEVS(LDO3), | |
141 | MAX8925_REG_DEVS(LDO4), | |
142 | MAX8925_REG_DEVS(LDO5), | |
143 | MAX8925_REG_DEVS(LDO6), | |
144 | MAX8925_REG_DEVS(LDO7), | |
145 | MAX8925_REG_DEVS(LDO8), | |
146 | MAX8925_REG_DEVS(LDO9), | |
147 | MAX8925_REG_DEVS(LDO10), | |
148 | MAX8925_REG_DEVS(LDO11), | |
149 | MAX8925_REG_DEVS(LDO12), | |
150 | MAX8925_REG_DEVS(LDO13), | |
151 | MAX8925_REG_DEVS(LDO14), | |
152 | MAX8925_REG_DEVS(LDO15), | |
153 | MAX8925_REG_DEVS(LDO16), | |
154 | MAX8925_REG_DEVS(LDO17), | |
155 | MAX8925_REG_DEVS(LDO18), | |
156 | MAX8925_REG_DEVS(LDO19), | |
157 | MAX8925_REG_DEVS(LDO20), | |
158 | }; | |
159 | ||
1f1cf8f9 HZ |
160 | enum { |
161 | FLAGS_ADC = 1, /* register in ADC component */ | |
162 | FLAGS_RTC, /* register in RTC component */ | |
163 | }; | |
164 | ||
165 | struct max8925_irq_data { | |
166 | int reg; | |
167 | int mask_reg; | |
168 | int enable; /* enable or not */ | |
169 | int offs; /* bit offset in mask register */ | |
170 | int flags; | |
171 | int tsc_irq; | |
172 | }; | |
173 | ||
174 | static struct max8925_irq_data max8925_irqs[] = { | |
175 | [MAX8925_IRQ_VCHG_DC_OVP] = { | |
176 | .reg = MAX8925_CHG_IRQ1, | |
177 | .mask_reg = MAX8925_CHG_IRQ1_MASK, | |
178 | .offs = 1 << 0, | |
179 | }, | |
180 | [MAX8925_IRQ_VCHG_DC_F] = { | |
181 | .reg = MAX8925_CHG_IRQ1, | |
182 | .mask_reg = MAX8925_CHG_IRQ1_MASK, | |
183 | .offs = 1 << 1, | |
184 | }, | |
185 | [MAX8925_IRQ_VCHG_DC_R] = { | |
186 | .reg = MAX8925_CHG_IRQ1, | |
187 | .mask_reg = MAX8925_CHG_IRQ1_MASK, | |
188 | .offs = 1 << 2, | |
189 | }, | |
190 | [MAX8925_IRQ_VCHG_USB_OVP] = { | |
191 | .reg = MAX8925_CHG_IRQ1, | |
192 | .mask_reg = MAX8925_CHG_IRQ1_MASK, | |
193 | .offs = 1 << 3, | |
194 | }, | |
195 | [MAX8925_IRQ_VCHG_USB_F] = { | |
196 | .reg = MAX8925_CHG_IRQ1, | |
197 | .mask_reg = MAX8925_CHG_IRQ1_MASK, | |
198 | .offs = 1 << 4, | |
199 | }, | |
200 | [MAX8925_IRQ_VCHG_USB_R] = { | |
201 | .reg = MAX8925_CHG_IRQ1, | |
202 | .mask_reg = MAX8925_CHG_IRQ1_MASK, | |
203 | .offs = 1 << 5, | |
204 | }, | |
205 | [MAX8925_IRQ_VCHG_THM_OK_R] = { | |
206 | .reg = MAX8925_CHG_IRQ2, | |
207 | .mask_reg = MAX8925_CHG_IRQ2_MASK, | |
208 | .offs = 1 << 0, | |
209 | }, | |
210 | [MAX8925_IRQ_VCHG_THM_OK_F] = { | |
211 | .reg = MAX8925_CHG_IRQ2, | |
212 | .mask_reg = MAX8925_CHG_IRQ2_MASK, | |
213 | .offs = 1 << 1, | |
214 | }, | |
215 | [MAX8925_IRQ_VCHG_SYSLOW_F] = { | |
216 | .reg = MAX8925_CHG_IRQ2, | |
217 | .mask_reg = MAX8925_CHG_IRQ2_MASK, | |
218 | .offs = 1 << 2, | |
219 | }, | |
220 | [MAX8925_IRQ_VCHG_SYSLOW_R] = { | |
221 | .reg = MAX8925_CHG_IRQ2, | |
222 | .mask_reg = MAX8925_CHG_IRQ2_MASK, | |
223 | .offs = 1 << 3, | |
224 | }, | |
225 | [MAX8925_IRQ_VCHG_RST] = { | |
226 | .reg = MAX8925_CHG_IRQ2, | |
227 | .mask_reg = MAX8925_CHG_IRQ2_MASK, | |
228 | .offs = 1 << 4, | |
229 | }, | |
230 | [MAX8925_IRQ_VCHG_DONE] = { | |
231 | .reg = MAX8925_CHG_IRQ2, | |
232 | .mask_reg = MAX8925_CHG_IRQ2_MASK, | |
233 | .offs = 1 << 5, | |
234 | }, | |
235 | [MAX8925_IRQ_VCHG_TOPOFF] = { | |
236 | .reg = MAX8925_CHG_IRQ2, | |
237 | .mask_reg = MAX8925_CHG_IRQ2_MASK, | |
238 | .offs = 1 << 6, | |
239 | }, | |
240 | [MAX8925_IRQ_VCHG_TMR_FAULT] = { | |
241 | .reg = MAX8925_CHG_IRQ2, | |
242 | .mask_reg = MAX8925_CHG_IRQ2_MASK, | |
243 | .offs = 1 << 7, | |
244 | }, | |
245 | [MAX8925_IRQ_GPM_RSTIN] = { | |
246 | .reg = MAX8925_ON_OFF_IRQ1, | |
247 | .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, | |
248 | .offs = 1 << 0, | |
249 | }, | |
250 | [MAX8925_IRQ_GPM_MPL] = { | |
251 | .reg = MAX8925_ON_OFF_IRQ1, | |
252 | .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, | |
253 | .offs = 1 << 1, | |
254 | }, | |
255 | [MAX8925_IRQ_GPM_SW_3SEC] = { | |
256 | .reg = MAX8925_ON_OFF_IRQ1, | |
257 | .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, | |
258 | .offs = 1 << 2, | |
259 | }, | |
260 | [MAX8925_IRQ_GPM_EXTON_F] = { | |
261 | .reg = MAX8925_ON_OFF_IRQ1, | |
262 | .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, | |
263 | .offs = 1 << 3, | |
264 | }, | |
265 | [MAX8925_IRQ_GPM_EXTON_R] = { | |
266 | .reg = MAX8925_ON_OFF_IRQ1, | |
267 | .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, | |
268 | .offs = 1 << 4, | |
269 | }, | |
270 | [MAX8925_IRQ_GPM_SW_1SEC] = { | |
271 | .reg = MAX8925_ON_OFF_IRQ1, | |
272 | .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, | |
273 | .offs = 1 << 5, | |
274 | }, | |
275 | [MAX8925_IRQ_GPM_SW_F] = { | |
276 | .reg = MAX8925_ON_OFF_IRQ1, | |
277 | .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, | |
278 | .offs = 1 << 6, | |
279 | }, | |
280 | [MAX8925_IRQ_GPM_SW_R] = { | |
281 | .reg = MAX8925_ON_OFF_IRQ1, | |
282 | .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, | |
283 | .offs = 1 << 7, | |
284 | }, | |
285 | [MAX8925_IRQ_GPM_SYSCKEN_F] = { | |
286 | .reg = MAX8925_ON_OFF_IRQ2, | |
287 | .mask_reg = MAX8925_ON_OFF_IRQ2_MASK, | |
288 | .offs = 1 << 0, | |
289 | }, | |
290 | [MAX8925_IRQ_GPM_SYSCKEN_R] = { | |
291 | .reg = MAX8925_ON_OFF_IRQ2, | |
292 | .mask_reg = MAX8925_ON_OFF_IRQ2_MASK, | |
293 | .offs = 1 << 1, | |
294 | }, | |
295 | [MAX8925_IRQ_RTC_ALARM1] = { | |
296 | .reg = MAX8925_RTC_IRQ, | |
297 | .mask_reg = MAX8925_RTC_IRQ_MASK, | |
298 | .offs = 1 << 2, | |
299 | .flags = FLAGS_RTC, | |
300 | }, | |
301 | [MAX8925_IRQ_RTC_ALARM0] = { | |
302 | .reg = MAX8925_RTC_IRQ, | |
303 | .mask_reg = MAX8925_RTC_IRQ_MASK, | |
304 | .offs = 1 << 3, | |
305 | .flags = FLAGS_RTC, | |
306 | }, | |
307 | [MAX8925_IRQ_TSC_STICK] = { | |
308 | .reg = MAX8925_TSC_IRQ, | |
309 | .mask_reg = MAX8925_TSC_IRQ_MASK, | |
310 | .offs = 1 << 0, | |
311 | .flags = FLAGS_ADC, | |
312 | .tsc_irq = 1, | |
313 | }, | |
314 | [MAX8925_IRQ_TSC_NSTICK] = { | |
315 | .reg = MAX8925_TSC_IRQ, | |
316 | .mask_reg = MAX8925_TSC_IRQ_MASK, | |
317 | .offs = 1 << 1, | |
318 | .flags = FLAGS_ADC, | |
319 | .tsc_irq = 1, | |
320 | }, | |
321 | }; | |
322 | ||
323 | static inline struct max8925_irq_data *irq_to_max8925(struct max8925_chip *chip, | |
324 | int irq) | |
d50f8f33 | 325 | { |
1f1cf8f9 HZ |
326 | return &max8925_irqs[irq - chip->irq_base]; |
327 | } | |
d50f8f33 | 328 | |
1f1cf8f9 HZ |
329 | static irqreturn_t max8925_irq(int irq, void *data) |
330 | { | |
331 | struct max8925_chip *chip = data; | |
332 | struct max8925_irq_data *irq_data; | |
333 | struct i2c_client *i2c; | |
334 | int read_reg = -1, value = 0; | |
335 | int i; | |
336 | ||
337 | for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) { | |
338 | irq_data = &max8925_irqs[i]; | |
339 | /* TSC IRQ should be serviced in max8925_tsc_irq() */ | |
340 | if (irq_data->tsc_irq) | |
341 | continue; | |
342 | if (irq_data->flags == FLAGS_RTC) | |
343 | i2c = chip->rtc; | |
344 | else if (irq_data->flags == FLAGS_ADC) | |
345 | i2c = chip->adc; | |
346 | else | |
347 | i2c = chip->i2c; | |
348 | if (read_reg != irq_data->reg) { | |
349 | read_reg = irq_data->reg; | |
350 | value = max8925_reg_read(i2c, irq_data->reg); | |
d50f8f33 | 351 | } |
1f1cf8f9 HZ |
352 | if (value & irq_data->enable) |
353 | handle_nested_irq(chip->irq_base + i); | |
d50f8f33 | 354 | } |
1f1cf8f9 | 355 | return IRQ_HANDLED; |
d50f8f33 HZ |
356 | } |
357 | ||
1f1cf8f9 | 358 | static irqreturn_t max8925_tsc_irq(int irq, void *data) |
d50f8f33 | 359 | { |
1f1cf8f9 HZ |
360 | struct max8925_chip *chip = data; |
361 | struct max8925_irq_data *irq_data; | |
362 | struct i2c_client *i2c; | |
363 | int read_reg = -1, value = 0; | |
364 | int i; | |
365 | ||
366 | for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) { | |
367 | irq_data = &max8925_irqs[i]; | |
368 | /* non TSC IRQ should be serviced in max8925_irq() */ | |
369 | if (!irq_data->tsc_irq) | |
370 | continue; | |
371 | if (irq_data->flags == FLAGS_RTC) | |
372 | i2c = chip->rtc; | |
373 | else if (irq_data->flags == FLAGS_ADC) | |
374 | i2c = chip->adc; | |
375 | else | |
376 | i2c = chip->i2c; | |
377 | if (read_reg != irq_data->reg) { | |
378 | read_reg = irq_data->reg; | |
379 | value = max8925_reg_read(i2c, irq_data->reg); | |
380 | } | |
381 | if (value & irq_data->enable) | |
382 | handle_nested_irq(chip->irq_base + i); | |
383 | } | |
384 | return IRQ_HANDLED; | |
d50f8f33 HZ |
385 | } |
386 | ||
1f1cf8f9 | 387 | static void max8925_irq_lock(unsigned int irq) |
d50f8f33 | 388 | { |
1f1cf8f9 | 389 | struct max8925_chip *chip = get_irq_chip_data(irq); |
d50f8f33 | 390 | |
1f1cf8f9 | 391 | mutex_lock(&chip->irq_lock); |
d50f8f33 HZ |
392 | } |
393 | ||
1f1cf8f9 | 394 | static void max8925_irq_sync_unlock(unsigned int irq) |
d50f8f33 | 395 | { |
1f1cf8f9 HZ |
396 | struct max8925_chip *chip = get_irq_chip_data(irq); |
397 | struct max8925_irq_data *irq_data; | |
398 | static unsigned char cache_chg[2] = {0xff, 0xff}; | |
399 | static unsigned char cache_on[2] = {0xff, 0xff}; | |
400 | static unsigned char cache_rtc = 0xff, cache_tsc = 0xff; | |
401 | unsigned char irq_chg[2], irq_on[2]; | |
402 | unsigned char irq_rtc, irq_tsc; | |
403 | int i; | |
404 | ||
405 | /* Load cached value. In initial, all IRQs are masked */ | |
406 | irq_chg[0] = cache_chg[0]; | |
407 | irq_chg[1] = cache_chg[1]; | |
408 | irq_on[0] = cache_on[0]; | |
409 | irq_on[1] = cache_on[1]; | |
410 | irq_rtc = cache_rtc; | |
411 | irq_tsc = cache_tsc; | |
412 | for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) { | |
413 | irq_data = &max8925_irqs[i]; | |
414 | switch (irq_data->mask_reg) { | |
415 | case MAX8925_CHG_IRQ1_MASK: | |
416 | irq_chg[0] &= irq_data->enable; | |
417 | break; | |
418 | case MAX8925_CHG_IRQ2_MASK: | |
419 | irq_chg[1] &= irq_data->enable; | |
420 | break; | |
421 | case MAX8925_ON_OFF_IRQ1_MASK: | |
422 | irq_on[0] &= irq_data->enable; | |
423 | break; | |
424 | case MAX8925_ON_OFF_IRQ2_MASK: | |
425 | irq_on[1] &= irq_data->enable; | |
426 | break; | |
427 | case MAX8925_RTC_IRQ_MASK: | |
428 | irq_rtc &= irq_data->enable; | |
429 | break; | |
430 | case MAX8925_TSC_IRQ_MASK: | |
431 | irq_tsc &= irq_data->enable; | |
432 | break; | |
433 | default: | |
434 | dev_err(chip->dev, "wrong IRQ\n"); | |
435 | break; | |
436 | } | |
437 | } | |
438 | /* update mask into registers */ | |
439 | if (cache_chg[0] != irq_chg[0]) { | |
440 | cache_chg[0] = irq_chg[0]; | |
441 | max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, | |
442 | irq_chg[0]); | |
443 | } | |
444 | if (cache_chg[1] != irq_chg[1]) { | |
445 | cache_chg[1] = irq_chg[1]; | |
446 | max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, | |
447 | irq_chg[1]); | |
448 | } | |
449 | if (cache_on[0] != irq_on[0]) { | |
450 | cache_on[0] = irq_on[0]; | |
451 | max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, | |
452 | irq_on[0]); | |
453 | } | |
454 | if (cache_on[1] != irq_on[1]) { | |
455 | cache_on[1] = irq_on[1]; | |
456 | max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, | |
457 | irq_on[1]); | |
458 | } | |
459 | if (cache_rtc != irq_rtc) { | |
460 | cache_rtc = irq_rtc; | |
461 | max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc); | |
462 | } | |
463 | if (cache_tsc != irq_tsc) { | |
464 | cache_tsc = irq_tsc; | |
465 | max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc); | |
466 | } | |
d50f8f33 | 467 | |
1f1cf8f9 | 468 | mutex_unlock(&chip->irq_lock); |
d50f8f33 HZ |
469 | } |
470 | ||
1f1cf8f9 | 471 | static void max8925_irq_enable(unsigned int irq) |
d50f8f33 | 472 | { |
1f1cf8f9 HZ |
473 | struct max8925_chip *chip = get_irq_chip_data(irq); |
474 | max8925_irqs[irq - chip->irq_base].enable | |
475 | = max8925_irqs[irq - chip->irq_base].offs; | |
d50f8f33 HZ |
476 | } |
477 | ||
1f1cf8f9 | 478 | static void max8925_irq_disable(unsigned int irq) |
d50f8f33 | 479 | { |
1f1cf8f9 HZ |
480 | struct max8925_chip *chip = get_irq_chip_data(irq); |
481 | max8925_irqs[irq - chip->irq_base].enable = 0; | |
d50f8f33 | 482 | } |
d50f8f33 | 483 | |
1f1cf8f9 HZ |
484 | static struct irq_chip max8925_irq_chip = { |
485 | .name = "max8925", | |
486 | .bus_lock = max8925_irq_lock, | |
487 | .bus_sync_unlock = max8925_irq_sync_unlock, | |
488 | .enable = max8925_irq_enable, | |
489 | .disable = max8925_irq_disable, | |
490 | }; | |
491 | ||
492 | static int max8925_irq_init(struct max8925_chip *chip, int irq, | |
493 | struct max8925_platform_data *pdata) | |
d50f8f33 | 494 | { |
1f1cf8f9 HZ |
495 | unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT; |
496 | struct irq_desc *desc; | |
497 | int i, ret; | |
498 | int __irq; | |
499 | ||
500 | if (!pdata || !pdata->irq_base) { | |
501 | dev_warn(chip->dev, "No interrupt support on IRQ base\n"); | |
d50f8f33 | 502 | return -EINVAL; |
1f1cf8f9 HZ |
503 | } |
504 | /* clear all interrupts */ | |
505 | max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1); | |
506 | max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2); | |
507 | max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1); | |
508 | max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2); | |
509 | max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ); | |
510 | max8925_reg_read(chip->adc, MAX8925_TSC_IRQ); | |
511 | /* mask all interrupts */ | |
512 | max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0); | |
513 | max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0); | |
514 | max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff); | |
515 | max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff); | |
516 | max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff); | |
517 | max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff); | |
518 | max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff); | |
519 | max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0xff); | |
520 | ||
521 | mutex_init(&chip->irq_lock); | |
522 | chip->core_irq = irq; | |
523 | chip->irq_base = pdata->irq_base; | |
524 | desc = irq_to_desc(chip->core_irq); | |
525 | ||
526 | /* register with genirq */ | |
527 | for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) { | |
528 | __irq = i + chip->irq_base; | |
529 | set_irq_chip_data(__irq, chip); | |
530 | set_irq_chip_and_handler(__irq, &max8925_irq_chip, | |
531 | handle_edge_irq); | |
532 | set_irq_nested_thread(__irq, 1); | |
533 | #ifdef CONFIG_ARM | |
534 | set_irq_flags(__irq, IRQF_VALID); | |
535 | #else | |
536 | set_irq_noprobe(__irq); | |
537 | #endif | |
538 | } | |
539 | if (!irq) { | |
540 | dev_warn(chip->dev, "No interrupt support on core IRQ\n"); | |
541 | goto tsc_irq; | |
542 | } | |
d50f8f33 | 543 | |
1f1cf8f9 HZ |
544 | ret = request_threaded_irq(irq, NULL, max8925_irq, flags, |
545 | "max8925", chip); | |
546 | if (ret) { | |
547 | dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret); | |
548 | chip->core_irq = 0; | |
549 | } | |
550 | tsc_irq: | |
551 | if (!pdata->tsc_irq) { | |
552 | dev_warn(chip->dev, "No interrupt support on TSC IRQ\n"); | |
553 | return 0; | |
554 | } | |
555 | chip->tsc_irq = pdata->tsc_irq; | |
556 | ||
557 | ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq, | |
558 | flags, "max8925-tsc", chip); | |
559 | if (ret) { | |
560 | dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret); | |
561 | chip->tsc_irq = 0; | |
562 | } | |
d50f8f33 HZ |
563 | return 0; |
564 | } | |
d50f8f33 | 565 | |
1f1cf8f9 HZ |
566 | int __devinit max8925_device_init(struct max8925_chip *chip, |
567 | struct max8925_platform_data *pdata) | |
d50f8f33 HZ |
568 | { |
569 | int ret; | |
570 | ||
1f1cf8f9 HZ |
571 | max8925_irq_init(chip, chip->i2c->irq, pdata); |
572 | ||
573 | if (pdata && (pdata->power || pdata->touch)) { | |
574 | /* enable ADC to control internal reference */ | |
575 | max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1); | |
576 | /* enable internal reference for ADC */ | |
577 | max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2); | |
578 | /* check for internal reference IRQ */ | |
579 | do { | |
580 | ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ); | |
581 | } while (ret & MAX8925_NREF_OK); | |
582 | /* enaable ADC scheduler, interval is 1 second */ | |
583 | max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2); | |
d50f8f33 | 584 | } |
d50f8f33 | 585 | |
1f1cf8f9 HZ |
586 | /* enable Momentary Power Loss */ |
587 | max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4); | |
1ad99893 | 588 | |
1f1cf8f9 HZ |
589 | ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0], |
590 | ARRAY_SIZE(rtc_devs), | |
591 | &rtc_resources[0], 0); | |
1ad99893 | 592 | if (ret < 0) { |
1f1cf8f9 HZ |
593 | dev_err(chip->dev, "Failed to add rtc subdev\n"); |
594 | goto out; | |
595 | } | |
596 | if (pdata && pdata->regulator[0]) { | |
597 | ret = mfd_add_devices(chip->dev, 0, ®ulator_devs[0], | |
598 | ARRAY_SIZE(regulator_devs), | |
599 | ®ulator_resources[0], 0); | |
600 | if (ret < 0) { | |
601 | dev_err(chip->dev, "Failed to add regulator subdev\n"); | |
602 | goto out_dev; | |
603 | } | |
1ad99893 HZ |
604 | } |
605 | ||
606 | if (pdata && pdata->backlight) { | |
607 | ret = mfd_add_devices(chip->dev, 0, &backlight_devs[0], | |
608 | ARRAY_SIZE(backlight_devs), | |
609 | &backlight_resources[0], 0); | |
610 | if (ret < 0) { | |
611 | dev_err(chip->dev, "Failed to add backlight subdev\n"); | |
612 | goto out_dev; | |
613 | } | |
614 | } | |
d50f8f33 | 615 | |
1f1cf8f9 HZ |
616 | if (pdata && pdata->power) { |
617 | ret = mfd_add_devices(chip->dev, 0, &power_devs[0], | |
618 | ARRAY_SIZE(power_devs), | |
619 | &power_supply_resources[0], 0); | |
620 | if (ret < 0) { | |
621 | dev_err(chip->dev, "Failed to add power supply " | |
622 | "subdev\n"); | |
623 | goto out_dev; | |
624 | } | |
d50f8f33 | 625 | } |
1ad99893 HZ |
626 | |
627 | if (pdata && pdata->touch) { | |
628 | ret = mfd_add_devices(chip->dev, 0, &touch_devs[0], | |
629 | ARRAY_SIZE(touch_devs), | |
630 | &touch_resources[0], 0); | |
631 | if (ret < 0) { | |
632 | dev_err(chip->dev, "Failed to add touch subdev\n"); | |
1f1cf8f9 | 633 | goto out_dev; |
1ad99893 HZ |
634 | } |
635 | } | |
1f1cf8f9 | 636 | |
1ad99893 | 637 | return 0; |
1f1cf8f9 HZ |
638 | out_dev: |
639 | mfd_remove_devices(chip->dev); | |
d50f8f33 HZ |
640 | out: |
641 | return ret; | |
642 | } | |
643 | ||
1f1cf8f9 | 644 | void __devexit max8925_device_exit(struct max8925_chip *chip) |
d50f8f33 | 645 | { |
1f1cf8f9 HZ |
646 | if (chip->core_irq) |
647 | free_irq(chip->core_irq, chip); | |
648 | if (chip->tsc_irq) | |
649 | free_irq(chip->tsc_irq, chip); | |
1ad99893 | 650 | mfd_remove_devices(chip->dev); |
d50f8f33 HZ |
651 | } |
652 | ||
1f1cf8f9 | 653 | |
d50f8f33 HZ |
654 | MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925"); |
655 | MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com"); | |
656 | MODULE_LICENSE("GPL"); |