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Merge tag 'for-6.3/dm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/device...
[linux-block.git] / drivers / mfd / max77620.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
327156c5
LD		 2/*
3 * Maxim MAX77620 MFD Driver
4 *
5 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Laxman Dewangan <ldewangan@nvidia.com>
9 * Chaitanya Bandi <bandik@nvidia.com>
10 * Mallikarjun Kasoju <mkasoju@nvidia.com>
327156c5
LD		 11 */
12
13/****************** Teminology used in driver ********************
14 * Here are some terminology used from datasheet for quick reference:
15 * Flexible Power Sequence (FPS):
16 * The Flexible Power Sequencer (FPS) allows each regulator to power up under
17 * hardware or software control. Additionally, each regulator can power on
18 * independently or among a group of other regulators with an adjustable
19 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
20 * be programmed to be part of a sequence allowing external regulators to be
21 * sequenced along with internal regulators. 32KHz clock can be programmed to
22 * be part of a sequence.
23 * There is 3 FPS confguration registers and all resources are configured to
24 * any of these FPS or no FPS.
25 */
26
27#include <linux/i2c.h>
28#include <linux/interrupt.h>
29#include <linux/mfd/core.h>
30#include <linux/mfd/max77620.h>
c1fe7c45 31#include <linux/init.h>
327156c5
LD		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/regmap.h>
35#include <linux/slab.h>
36
744b1310
DO		 37static struct max77620_chip *max77620_scratch;
38
2be59755 39static const struct resource gpio_resources[] = {
327156c5
LD		 40 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
41};
42
2be59755 43static const struct resource power_resources[] = {
327156c5
LD		 44 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
45};
46
2be59755 47static const struct resource rtc_resources[] = {
327156c5
LD		 48 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
49};
50
2be59755 51static const struct resource thermal_resources[] = {
327156c5
LD		 52 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
53 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
54};
55
56static const struct regmap_irq max77620_top_irqs[] = {
57 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
58 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
59 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
60 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
61 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
62 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
63 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
64 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
65 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
66 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
67};
68
69static const struct mfd_cell max77620_children[] = {
70 { .name = "max77620-pinctrl", },
71 { .name = "max77620-clock", },
72 { .name = "max77620-pmic", },
73 { .name = "max77620-watchdog", },
74 {
75 .name = "max77620-gpio",
76 .resources = gpio_resources,
77 .num_resources = ARRAY_SIZE(gpio_resources),
78 }, {
79 .name = "max77620-rtc",
80 .resources = rtc_resources,
81 .num_resources = ARRAY_SIZE(rtc_resources),
82 }, {
83 .name = "max77620-power",
84 .resources = power_resources,
85 .num_resources = ARRAY_SIZE(power_resources),
86 }, {
87 .name = "max77620-thermal",
88 .resources = thermal_resources,
89 .num_resources = ARRAY_SIZE(thermal_resources),
90 },
91};
92
93static const struct mfd_cell max20024_children[] = {
94 { .name = "max20024-pinctrl", },
95 { .name = "max77620-clock", },
96 { .name = "max20024-pmic", },
97 { .name = "max77620-watchdog", },
98 {
99 .name = "max77620-gpio",
100 .resources = gpio_resources,
101 .num_resources = ARRAY_SIZE(gpio_resources),
102 }, {
103 .name = "max77620-rtc",
104 .resources = rtc_resources,
105 .num_resources = ARRAY_SIZE(rtc_resources),
106 }, {
107 .name = "max20024-power",
108 .resources = power_resources,
109 .num_resources = ARRAY_SIZE(power_resources),
110 },
111};
112
4c58f701
DO		 113static const struct mfd_cell max77663_children[] = {
114 { .name = "max77620-pinctrl", },
115 { .name = "max77620-clock", },
116 { .name = "max77663-pmic", },
117 { .name = "max77620-watchdog", },
118 {
119 .name = "max77620-gpio",
120 .resources = gpio_resources,
121 .num_resources = ARRAY_SIZE(gpio_resources),
122 }, {
123 .name = "max77620-rtc",
124 .resources = rtc_resources,
125 .num_resources = ARRAY_SIZE(rtc_resources),
126 }, {
127 .name = "max77663-power",
128 .resources = power_resources,
129 .num_resources = ARRAY_SIZE(power_resources),
130 },
131};
132
327156c5
LD		 133static const struct regmap_range max77620_readable_ranges[] = {
134 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
135};
136
137static const struct regmap_access_table max77620_readable_table = {
138 .yes_ranges = max77620_readable_ranges,
139 .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
140};
141
142static const struct regmap_range max20024_readable_ranges[] = {
143 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
144 regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
145};
146
147static const struct regmap_access_table max20024_readable_table = {
148 .yes_ranges = max20024_readable_ranges,
149 .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
150};
151
152static const struct regmap_range max77620_writable_ranges[] = {
153 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
154};
155
156static const struct regmap_access_table max77620_writable_table = {
157 .yes_ranges = max77620_writable_ranges,
158 .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
159};
160
161static const struct regmap_range max77620_cacheable_ranges[] = {
162 regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
163 regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
164};
165
166static const struct regmap_access_table max77620_volatile_table = {
167 .no_ranges = max77620_cacheable_ranges,
168 .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
169};
170
171static const struct regmap_config max77620_regmap_config = {
172 .name = "power-slave",
173 .reg_bits = 8,
174 .val_bits = 8,
175 .max_register = MAX77620_REG_DVSSD4 + 1,
176 .cache_type = REGCACHE_RBTREE,
177 .rd_table = &max77620_readable_table,
178 .wr_table = &max77620_writable_table,
179 .volatile_table = &max77620_volatile_table,
12e5bf75 180 .use_single_write = true,
327156c5
LD		 181};
182
183static const struct regmap_config max20024_regmap_config = {
184 .name = "power-slave",
185 .reg_bits = 8,
186 .val_bits = 8,
187 .max_register = MAX20024_REG_MAX_ADD + 1,
188 .cache_type = REGCACHE_RBTREE,
189 .rd_table = &max20024_readable_table,
190 .wr_table = &max77620_writable_table,
191 .volatile_table = &max77620_volatile_table,
192};
193
4c58f701
DO		 194static const struct regmap_range max77663_readable_ranges[] = {
195 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
196};
197
198static const struct regmap_access_table max77663_readable_table = {
199 .yes_ranges = max77663_readable_ranges,
200 .n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges),
201};
202
203static const struct regmap_range max77663_writable_ranges[] = {
204 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
205};
206
207static const struct regmap_access_table max77663_writable_table = {
208 .yes_ranges = max77663_writable_ranges,
209 .n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges),
210};
211
212static const struct regmap_config max77663_regmap_config = {
213 .name = "power-slave",
214 .reg_bits = 8,
215 .val_bits = 8,
216 .max_register = MAX77620_REG_CID5 + 1,
217 .cache_type = REGCACHE_RBTREE,
218 .rd_table = &max77663_readable_table,
219 .wr_table = &max77663_writable_table,
220 .volatile_table = &max77620_volatile_table,
221};
222
3df140d1
LD		 223/*
224 * MAX77620 and MAX20024 has the following steps of the interrupt handling
225 * for TOP interrupts:
226 * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.
227 * 2. Read IRQTOP and service the interrupt.
228 * 3. Once all interrupts has been checked and serviced, the interrupt service
229 * routine un-masks the hardware interrupt line by clearing GLBLM.
230 */
231static int max77620_irq_global_mask(void *irq_drv_data)
232{
233 struct max77620_chip *chip = irq_drv_data;
234 int ret;
235
236 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
237 MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);
238 if (ret < 0)
239 dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
240
241 return ret;
242}
243
244static int max77620_irq_global_unmask(void *irq_drv_data)
245{
246 struct max77620_chip *chip = irq_drv_data;
247 int ret;
248
249 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
250 MAX77620_GLBLM_MASK, 0);
251 if (ret < 0)
252 dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
253
254 return ret;
255}
256
257static struct regmap_irq_chip max77620_top_irq_chip = {
258 .name = "max77620-top",
259 .irqs = max77620_top_irqs,
260 .num_irqs = ARRAY_SIZE(max77620_top_irqs),
261 .num_regs = 2,
262 .status_base = MAX77620_REG_IRQTOP,
263 .mask_base = MAX77620_REG_IRQTOPM,
264 .handle_pre_irq = max77620_irq_global_mask,
265 .handle_post_irq = max77620_irq_global_unmask,
266};
267
327156c5
LD		 268/* max77620_get_fps_period_reg_value: Get FPS bit field value from
269 * requested periods.
270 * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
271 * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
272 * 160, 320, 540, 1280 and 2560 microseconds.
273 * The FPS register has 3 bits field to set the FPS period as
274 * bits max77620 max20024
275 * 000 40 20
276 * 001 80 40
277 * :::
278*/
279static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
280 int tperiod)
281{
282 int fps_min_period;
283 int i;
284
285 switch (chip->chip_id) {
286 case MAX20024:
287 fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
288 break;
289 case MAX77620:
290 fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
82d8eb40 291 break;
4c58f701
DO		 292 case MAX77663:
293 fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
294 break;
327156c5
LD		 295 default:
296 return -EINVAL;
297 }
298
299 for (i = 0; i < 7; i++) {
300 if (fps_min_period >= tperiod)
301 return i;
302 fps_min_period *= 2;
303 }
304
305 return i;
306}
307
308/* max77620_config_fps: Configure FPS configuration registers
309 * based on platform specific information.
310 */
311static int max77620_config_fps(struct max77620_chip *chip,
312 struct device_node *fps_np)
313{
314 struct device *dev = chip->dev;
315 unsigned int mask = 0, config = 0;
316 u32 fps_max_period;
317 u32 param_val;
318 int tperiod, fps_id;
319 int ret;
320 char fps_name[10];
321
322 switch (chip->chip_id) {
323 case MAX20024:
324 fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
325 break;
326 case MAX77620:
327 fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
82d8eb40 328 break;
4c58f701
DO		 329 case MAX77663:
330 fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
331 break;
327156c5
LD		 332 default:
333 return -EINVAL;
334 }
335
336 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
337 sprintf(fps_name, "fps%d", fps_id);
38df91cc 338 if (of_node_name_eq(fps_np, fps_name))
327156c5
LD		 339 break;
340 }
341
342 if (fps_id == MAX77620_FPS_COUNT) {
75a11072 343 dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np);
327156c5
LD		 344 return -EINVAL;
345 }
346
347 ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
348 &param_val);
349 if (!ret) {
350 mask |= MAX77620_FPS_TIME_PERIOD_MASK;
351 chip->shutdown_fps_period[fps_id] = min(param_val,
352 fps_max_period);
353 tperiod = max77620_get_fps_period_reg_value(chip,
354 chip->shutdown_fps_period[fps_id]);
355 config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
356 }
357
358 ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
359 &param_val);
360 if (!ret)
361 chip->suspend_fps_period[fps_id] = min(param_val,
362 fps_max_period);
363
364 ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
365 &param_val);
366 if (!ret) {
367 if (param_val > 2) {
368 dev_err(dev, "FPS%d event-source invalid\n", fps_id);
369 return -EINVAL;
370 }
371 mask |= MAX77620_FPS_EN_SRC_MASK;
372 config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
373 if (param_val == 2) {
374 mask |= MAX77620_FPS_ENFPS_SW_MASK;
375 config |= MAX77620_FPS_ENFPS_SW;
376 }
377 }
378
379 if (!chip->sleep_enable && !chip->enable_global_lpm) {
380 ret = of_property_read_u32(fps_np,
381 "maxim,device-state-on-disabled-event",
382 &param_val);
383 if (!ret) {
384 if (param_val == 0)
385 chip->sleep_enable = true;
386 else if (param_val == 1)
387 chip->enable_global_lpm = true;
388 }
389 }
390
391 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
392 mask, config);
393 if (ret < 0) {
394 dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
395 return ret;
396 }
397
398 return 0;
399}
400
401static int max77620_initialise_fps(struct max77620_chip *chip)
402{
403 struct device *dev = chip->dev;
404 struct device_node *fps_np, *fps_child;
405 u8 config;
406 int fps_id;
407 int ret;
408
409 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
410 chip->shutdown_fps_period[fps_id] = -1;
411 chip->suspend_fps_period[fps_id] = -1;
412 }
413
414 fps_np = of_get_child_by_name(dev->of_node, "fps");
415 if (!fps_np)
416 goto skip_fps;
417
418 for_each_child_of_node(fps_np, fps_child) {
419 ret = max77620_config_fps(chip, fps_child);
197df18f
ND		 420 if (ret < 0) {
421 of_node_put(fps_child);
1520669c 422 of_node_put(fps_np);
327156c5 423 return ret;
197df18f 424 }
327156c5 425 }
1520669c 426 of_node_put(fps_np);
327156c5
LD		 427
428 config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
429 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
430 MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
431 if (ret < 0) {
432 dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
433 return ret;
434 }
435
436skip_fps:
4c58f701
DO		 437 if (chip->chip_id == MAX77663)
438 return 0;
439
327156c5
LD		 440 /* Enable wake on EN0 pin */
441 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
442 MAX77620_ONOFFCNFG2_WK_EN0,
443 MAX77620_ONOFFCNFG2_WK_EN0);
444 if (ret < 0) {
445 dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
446 return ret;
447 }
448
449 /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
450 if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
451 config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
452 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
453 config, config);
454 if (ret < 0) {
455 dev_err(dev, "Failed to update SLPEN: %d\n", ret);
456 return ret;
457 }
458 }
459
460 return 0;
461}
462
463static int max77620_read_es_version(struct max77620_chip *chip)
464{
465 unsigned int val;
466 u8 cid_val[6];
467 int i;
468 int ret;
469
470 for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
471 ret = regmap_read(chip->rmap, i, &val);
472 if (ret < 0) {
473 dev_err(chip->dev, "Failed to read CID: %d\n", ret);
474 return ret;
475 }
476 dev_dbg(chip->dev, "CID%d: 0x%02x\n",
477 i - MAX77620_REG_CID0, val);
478 cid_val[i - MAX77620_REG_CID0] = val;
479 }
480
481 /* CID4 is OTP Version and CID5 is ES version */
482 dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
483 cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
484
485 return ret;
486}
487
744b1310
DO		 488static void max77620_pm_power_off(void)
489{
490 struct max77620_chip *chip = max77620_scratch;
491
492 regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
493 MAX77620_ONOFFCNFG1_SFT_RST,
494 MAX77620_ONOFFCNFG1_SFT_RST);
495}
496
773fb98f 497static int max77620_probe(struct i2c_client *client)
327156c5 498{
773fb98f 499 const struct i2c_device_id *id = i2c_client_get_device_id(client);
327156c5
LD		 500 const struct regmap_config *rmap_config;
501 struct max77620_chip *chip;
502 const struct mfd_cell *mfd_cells;
503 int n_mfd_cells;
744b1310 504 bool pm_off;
327156c5
LD		 505 int ret;
506
507 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
508 if (!chip)
509 return -ENOMEM;
510
511 i2c_set_clientdata(client, chip);
512 chip->dev = &client->dev;
327156c5
LD		 513 chip->chip_irq = client->irq;
514 chip->chip_id = (enum max77620_chip_id)id->driver_data;
515
516 switch (chip->chip_id) {
517 case MAX77620:
518 mfd_cells = max77620_children;
519 n_mfd_cells = ARRAY_SIZE(max77620_children);
520 rmap_config = &max77620_regmap_config;
521 break;
522 case MAX20024:
523 mfd_cells = max20024_children;
524 n_mfd_cells = ARRAY_SIZE(max20024_children);
525 rmap_config = &max20024_regmap_config;
526 break;
4c58f701
DO		 527 case MAX77663:
528 mfd_cells = max77663_children;
529 n_mfd_cells = ARRAY_SIZE(max77663_children);
530 rmap_config = &max77663_regmap_config;
531 break;
327156c5
LD		 532 default:
533 dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
534 return -EINVAL;
535 }
536
537 chip->rmap = devm_regmap_init_i2c(client, rmap_config);
538 if (IS_ERR(chip->rmap)) {
539 ret = PTR_ERR(chip->rmap);
9165dabb 540 dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);
327156c5
LD		 541 return ret;
542 }
543
544 ret = max77620_read_es_version(chip);
545 if (ret < 0)
546 return ret;
547
3df140d1 548 max77620_top_irq_chip.irq_drv_data = chip;
327156c5 549 ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
7f0e60c7
TR		 550 IRQF_ONESHOT | IRQF_SHARED, 0,
551 &max77620_top_irq_chip,
327156c5
LD		 552 &chip->top_irq_data);
553 if (ret < 0) {
554 dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
555 return ret;
556 }
557
558 ret = max77620_initialise_fps(chip);
559 if (ret < 0)
560 return ret;
561
562 ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
563 mfd_cells, n_mfd_cells, NULL, 0,
564 regmap_irq_get_domain(chip->top_irq_data));
565 if (ret < 0) {
566 dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
567 return ret;
568 }
569
744b1310
DO		 570 pm_off = of_device_is_system_power_controller(client->dev.of_node);
571 if (pm_off && !pm_power_off) {
572 max77620_scratch = chip;
573 pm_power_off = max77620_pm_power_off;
574 }
575
327156c5
LD		 576 return 0;
577}
578
327156c5
LD		 579static int max77620_set_fps_period(struct max77620_chip *chip,
580 int fps_id, int time_period)
581{
582 int period = max77620_get_fps_period_reg_value(chip, time_period);
583 int ret;
584
585 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
586 MAX77620_FPS_TIME_PERIOD_MASK,
587 period << MAX77620_FPS_TIME_PERIOD_SHIFT);
588 if (ret < 0) {
589 dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
590 return ret;
591 }
592
593 return 0;
594}
595
596static int max77620_i2c_suspend(struct device *dev)
597{
598 struct max77620_chip *chip = dev_get_drvdata(dev);
599 struct i2c_client *client = to_i2c_client(dev);
600 unsigned int config;
601 int fps;
602 int ret;
603
604 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
605 if (chip->suspend_fps_period[fps] < 0)
606 continue;
607
608 ret = max77620_set_fps_period(chip, fps,
609 chip->suspend_fps_period[fps]);
610 if (ret < 0)
611 return ret;
612 }
613
614 /*
615 * For MAX20024: No need to configure SLPEN on suspend as
616 * it will be configured on Init.
617 */
618 if (chip->chip_id == MAX20024)
619 goto out;
620
621 config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
622 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
623 MAX77620_ONOFFCNFG1_SLPEN,
624 config);
625 if (ret < 0) {
626 dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
627 return ret;
628 }
629
4c58f701
DO		 630 if (chip->chip_id == MAX77663)
631 goto out;
632
327156c5
LD		 633 /* Disable WK_EN0 */
634 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
635 MAX77620_ONOFFCNFG2_WK_EN0, 0);
636 if (ret < 0) {
637 dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
638 return ret;
639 }
640
641out:
642 disable_irq(client->irq);
643
644 return 0;
645}
646
647static int max77620_i2c_resume(struct device *dev)
648{
649 struct max77620_chip *chip = dev_get_drvdata(dev);
650 struct i2c_client *client = to_i2c_client(dev);
651 int ret;
652 int fps;
653
654 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
655 if (chip->shutdown_fps_period[fps] < 0)
656 continue;
657
658 ret = max77620_set_fps_period(chip, fps,
659 chip->shutdown_fps_period[fps]);
660 if (ret < 0)
661 return ret;
662 }
663
664 /*
665 * For MAX20024: No need to configure WKEN0 on resume as
666 * it is configured on Init.
667 */
4c58f701 668 if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)
327156c5
LD		 669 goto out;
670
671 /* Enable WK_EN0 */
672 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
673 MAX77620_ONOFFCNFG2_WK_EN0,
674 MAX77620_ONOFFCNFG2_WK_EN0);
675 if (ret < 0) {
676 dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
677 return ret;
678 }
679
680out:
681 enable_irq(client->irq);
682
683 return 0;
684}
327156c5
LD		 685
686static const struct i2c_device_id max77620_id[] = {
687 {"max77620", MAX77620},
688 {"max20024", MAX20024},
4c58f701 689 {"max77663", MAX77663},
327156c5
LD		 690 {},
691};
327156c5 692
9b990dc9
PC		 693static DEFINE_SIMPLE_DEV_PM_OPS(max77620_pm_ops,
694 max77620_i2c_suspend, max77620_i2c_resume);
327156c5
LD		 695
696static struct i2c_driver max77620_driver = {
697 .driver = {
698 .name = "max77620",
9b990dc9 699 .pm = pm_sleep_ptr(&max77620_pm_ops),
327156c5 700 },
773fb98f 701 .probe_new = max77620_probe,
327156c5
LD		 702 .id_table = max77620_id,
703};
c1fe7c45 704builtin_i2c_driver(max77620_driver);
Linux 6.x block layer and io_uring tree(s)