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9f806850 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e82c60ae DT |
2 | /* |
3 | * lpc_sch.c - LPC interface for Intel Poulsbo SCH | |
4 | * | |
5 | * LPC bridge function of the Intel SCH contains many other | |
6 | * functional units, such as Interrupt controllers, Timers, | |
7 | * Power Management, System Management, GPIO, RTC, and LPC | |
8 | * Configuration Registers. | |
9 | * | |
10 | * Copyright (c) 2010 CompuLab Ltd | |
85de80e8 | 11 | * Copyright (c) 2014 Intel Corp. |
e82c60ae | 12 | * Author: Denis Turischev <denis@compulab.co.il> |
e82c60ae DT |
13 | */ |
14 | ||
e82c60ae DT |
15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/acpi.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/mfd/core.h> | |
21 | ||
22 | #define SMBASE 0x40 | |
23 | #define SMBUS_IO_SIZE 64 | |
24 | ||
25 | #define GPIOBASE 0x44 | |
26 | #define GPIO_IO_SIZE 64 | |
8ee3c2a7 | 27 | #define GPIO_IO_SIZE_CENTERTON 128 |
e82c60ae | 28 | |
ec689a8a AS |
29 | /* Intel Quark X1000 GPIO IRQ Number */ |
30 | #define GPIO_IRQ_QUARK_X1000 9 | |
31 | ||
19921ef6 AS |
32 | #define WDTBASE 0x84 |
33 | #define WDT_IO_SIZE 64 | |
34 | ||
b24512c8 AS |
35 | enum sch_chipsets { |
36 | LPC_SCH = 0, /* Intel Poulsbo SCH */ | |
37 | LPC_ITC, /* Intel Tunnel Creek */ | |
38 | LPC_CENTERTON, /* Intel Centerton */ | |
ec689a8a | 39 | LPC_QUARK_X1000, /* Intel Quark X1000 */ |
e82c60ae DT |
40 | }; |
41 | ||
b24512c8 AS |
42 | struct lpc_sch_info { |
43 | unsigned int io_size_smbus; | |
44 | unsigned int io_size_gpio; | |
45 | unsigned int io_size_wdt; | |
ec689a8a | 46 | int irq_gpio; |
e82c60ae DT |
47 | }; |
48 | ||
b24512c8 AS |
49 | static struct lpc_sch_info sch_chipset_info[] = { |
50 | [LPC_SCH] = { | |
51 | .io_size_smbus = SMBUS_IO_SIZE, | |
52 | .io_size_gpio = GPIO_IO_SIZE, | |
ec689a8a | 53 | .irq_gpio = -1, |
b24512c8 AS |
54 | }, |
55 | [LPC_ITC] = { | |
56 | .io_size_smbus = SMBUS_IO_SIZE, | |
57 | .io_size_gpio = GPIO_IO_SIZE, | |
58 | .io_size_wdt = WDT_IO_SIZE, | |
ec689a8a | 59 | .irq_gpio = -1, |
b24512c8 AS |
60 | }, |
61 | [LPC_CENTERTON] = { | |
62 | .io_size_smbus = SMBUS_IO_SIZE, | |
63 | .io_size_gpio = GPIO_IO_SIZE_CENTERTON, | |
64 | .io_size_wdt = WDT_IO_SIZE, | |
ec689a8a AS |
65 | .irq_gpio = -1, |
66 | }, | |
67 | [LPC_QUARK_X1000] = { | |
68 | .io_size_gpio = GPIO_IO_SIZE, | |
69 | .irq_gpio = GPIO_IRQ_QUARK_X1000, | |
c68a8658 | 70 | .io_size_wdt = WDT_IO_SIZE, |
b24512c8 | 71 | }, |
19921ef6 AS |
72 | }; |
73 | ||
36fcd06c | 74 | static const struct pci_device_id lpc_sch_ids[] = { |
b24512c8 AS |
75 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC), LPC_SCH }, |
76 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC), LPC_ITC }, | |
77 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB), LPC_CENTERTON }, | |
ec689a8a | 78 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB), LPC_QUARK_X1000 }, |
e82c60ae DT |
79 | { 0, } |
80 | }; | |
81 | MODULE_DEVICE_TABLE(pci, lpc_sch_ids); | |
82 | ||
b24512c8 AS |
83 | #define LPC_NO_RESOURCE 1 |
84 | #define LPC_SKIP_RESOURCE 2 | |
85 | ||
86 | static int lpc_sch_get_io(struct pci_dev *pdev, int where, const char *name, | |
87 | struct resource *res, int size) | |
e82c60ae DT |
88 | { |
89 | unsigned int base_addr_cfg; | |
90 | unsigned short base_addr; | |
91 | ||
b24512c8 AS |
92 | if (size == 0) |
93 | return LPC_NO_RESOURCE; | |
94 | ||
95 | pci_read_config_dword(pdev, where, &base_addr_cfg); | |
5829e9b6 DH |
96 | base_addr = 0; |
97 | if (!(base_addr_cfg & (1 << 31))) | |
b24512c8 AS |
98 | dev_warn(&pdev->dev, "Decode of the %s I/O range disabled\n", |
99 | name); | |
5829e9b6 DH |
100 | else |
101 | base_addr = (unsigned short)base_addr_cfg; | |
e82c60ae | 102 | |
e82c60ae | 103 | if (base_addr == 0) { |
b24512c8 AS |
104 | dev_warn(&pdev->dev, "I/O space for %s uninitialized\n", name); |
105 | return LPC_SKIP_RESOURCE; | |
e82c60ae DT |
106 | } |
107 | ||
b24512c8 AS |
108 | res->start = base_addr; |
109 | res->end = base_addr + size - 1; | |
110 | res->flags = IORESOURCE_IO; | |
e967f77d | 111 | |
b24512c8 AS |
112 | return 0; |
113 | } | |
19921ef6 | 114 | |
b24512c8 | 115 | static int lpc_sch_populate_cell(struct pci_dev *pdev, int where, |
ec689a8a AS |
116 | const char *name, int size, int irq, |
117 | int id, struct mfd_cell *cell) | |
b24512c8 AS |
118 | { |
119 | struct resource *res; | |
120 | int ret; | |
19921ef6 | 121 | |
ec689a8a | 122 | res = devm_kcalloc(&pdev->dev, 2, sizeof(*res), GFP_KERNEL); |
b24512c8 AS |
123 | if (!res) |
124 | return -ENOMEM; | |
125 | ||
126 | ret = lpc_sch_get_io(pdev, where, name, res, size); | |
127 | if (ret) | |
128 | return ret; | |
129 | ||
130 | memset(cell, 0, sizeof(*cell)); | |
131 | ||
132 | cell->name = name; | |
133 | cell->resources = res; | |
134 | cell->num_resources = 1; | |
135 | cell->ignore_resource_conflicts = true; | |
136 | cell->id = id; | |
137 | ||
ec689a8a AS |
138 | /* Check if we need to add an IRQ resource */ |
139 | if (irq < 0) | |
140 | return 0; | |
141 | ||
142 | res++; | |
143 | ||
144 | res->start = irq; | |
145 | res->end = irq; | |
146 | res->flags = IORESOURCE_IRQ; | |
147 | ||
148 | cell->num_resources++; | |
149 | ||
b24512c8 AS |
150 | return 0; |
151 | } | |
152 | ||
153 | static int lpc_sch_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
154 | { | |
155 | struct mfd_cell lpc_sch_cells[3]; | |
156 | struct lpc_sch_info *info = &sch_chipset_info[id->driver_data]; | |
157 | unsigned int cells = 0; | |
158 | int ret; | |
159 | ||
160 | ret = lpc_sch_populate_cell(dev, SMBASE, "isch_smbus", | |
ec689a8a | 161 | info->io_size_smbus, -1, |
b24512c8 AS |
162 | id->device, &lpc_sch_cells[cells]); |
163 | if (ret < 0) | |
164 | return ret; | |
165 | if (ret == 0) | |
166 | cells++; | |
167 | ||
168 | ret = lpc_sch_populate_cell(dev, GPIOBASE, "sch_gpio", | |
ec689a8a | 169 | info->io_size_gpio, info->irq_gpio, |
b24512c8 AS |
170 | id->device, &lpc_sch_cells[cells]); |
171 | if (ret < 0) | |
172 | return ret; | |
173 | if (ret == 0) | |
174 | cells++; | |
175 | ||
176 | ret = lpc_sch_populate_cell(dev, WDTBASE, "ie6xx_wdt", | |
ec689a8a | 177 | info->io_size_wdt, -1, |
b24512c8 AS |
178 | id->device, &lpc_sch_cells[cells]); |
179 | if (ret < 0) | |
180 | return ret; | |
181 | if (ret == 0) | |
182 | cells++; | |
19921ef6 | 183 | |
5829e9b6 DH |
184 | if (cells == 0) { |
185 | dev_err(&dev->dev, "All decode registers disabled.\n"); | |
186 | return -ENODEV; | |
19921ef6 AS |
187 | } |
188 | ||
bde3e706 | 189 | return mfd_add_devices(&dev->dev, 0, lpc_sch_cells, cells, NULL, 0, NULL); |
e82c60ae DT |
190 | } |
191 | ||
4740f73f | 192 | static void lpc_sch_remove(struct pci_dev *dev) |
e82c60ae DT |
193 | { |
194 | mfd_remove_devices(&dev->dev); | |
195 | } | |
196 | ||
197 | static struct pci_driver lpc_sch_driver = { | |
198 | .name = "lpc_sch", | |
199 | .id_table = lpc_sch_ids, | |
200 | .probe = lpc_sch_probe, | |
84449216 | 201 | .remove = lpc_sch_remove, |
e82c60ae DT |
202 | }; |
203 | ||
38a36f5a | 204 | module_pci_driver(lpc_sch_driver); |
e82c60ae DT |
205 | |
206 | MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>"); | |
207 | MODULE_DESCRIPTION("LPC interface for Intel Poulsbo SCH"); | |
208 | MODULE_LICENSE("GPL"); |