Commit | Line | Data |
---|---|---|
9f806850 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
4630b130 AS |
2 | /* |
3 | * lpc_ich.c - LPC interface for Intel ICH | |
4 | * | |
5 | * LPC bridge function of the Intel ICH contains many other | |
6 | * functional units, such as Interrupt controllers, Timers, | |
7 | * Power Management, System Management, GPIO, RTC, and LPC | |
8 | * Configuration Registers. | |
9 | * | |
10 | * This driver is derived from lpc_sch. | |
7064d7d8 TJN |
11 | * |
12 | * Copyright (c) 2017, 2021-2022 Intel Corporation | |
4630b130 AS |
13 | * Copyright (c) 2011 Extreme Engineering Solution, Inc. |
14 | * Author: Aaron Sierra <asierra@xes-inc.com> | |
15 | * | |
4630b130 AS |
16 | * This driver supports the following I/O Controller hubs: |
17 | * (See the intel documentation on http://developer.intel.com.) | |
18 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) | |
19 | * document number 290687-002, 298242-027: 82801BA (ICH2) | |
20 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) | |
21 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) | |
22 | * document number 290744-001, 290745-025: 82801DB (ICH4) | |
23 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) | |
24 | * document number 273599-001, 273645-002: 82801E (C-ICH) | |
25 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) | |
26 | * document number 300641-004, 300884-013: 6300ESB | |
27 | * document number 301473-002, 301474-026: 82801F (ICH6) | |
28 | * document number 313082-001, 313075-006: 631xESB, 632xESB | |
29 | * document number 307013-003, 307014-024: 82801G (ICH7) | |
30 | * document number 322896-001, 322897-001: NM10 | |
31 | * document number 313056-003, 313057-017: 82801H (ICH8) | |
32 | * document number 316972-004, 316973-012: 82801I (ICH9) | |
33 | * document number 319973-002, 319974-002: 82801J (ICH10) | |
34 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) | |
35 | * document number 320066-003, 320257-008: EP80597 (IICH) | |
36 | * document number 324645-001, 324646-001: Cougar Point (CPT) | |
4630b130 AS |
37 | */ |
38 | ||
39 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
40 | ||
4630b130 AS |
41 | #include <linux/kernel.h> |
42 | #include <linux/module.h> | |
43 | #include <linux/errno.h> | |
44 | #include <linux/acpi.h> | |
45 | #include <linux/pci.h> | |
7064d7d8 | 46 | #include <linux/pinctrl/pinctrl.h> |
4630b130 AS |
47 | #include <linux/mfd/core.h> |
48 | #include <linux/mfd/lpc_ich.h> | |
420b54de | 49 | #include <linux/platform_data/itco_wdt.h> |
55979319 | 50 | #include <linux/platform_data/x86/p2sb.h> |
4630b130 AS |
51 | |
52 | #define ACPIBASE 0x40 | |
53 | #define ACPIBASE_GPE_OFF 0x28 | |
54 | #define ACPIBASE_GPE_END 0x2f | |
887c8ec7 AS |
55 | #define ACPIBASE_SMI_OFF 0x30 |
56 | #define ACPIBASE_SMI_END 0x33 | |
eb71d4de PT |
57 | #define ACPIBASE_PMC_OFF 0x08 |
58 | #define ACPIBASE_PMC_END 0x0c | |
887c8ec7 AS |
59 | #define ACPIBASE_TCO_OFF 0x60 |
60 | #define ACPIBASE_TCO_END 0x7f | |
eb71d4de | 61 | #define ACPICTRL_PMCBASE 0x44 |
4630b130 | 62 | |
887c8ec7 AS |
63 | #define ACPIBASE_GCS_OFF 0x3410 |
64 | #define ACPIBASE_GCS_END 0x3414 | |
65 | ||
ff00d7a3 MW |
66 | #define SPIBASE_BYT 0x54 |
67 | #define SPIBASE_BYT_SZ 512 | |
68 | #define SPIBASE_BYT_EN BIT(1) | |
cd149eff MW |
69 | #define BYT_BCR 0xfc |
70 | #define BYT_BCR_WPD BIT(0) | |
ff00d7a3 MW |
71 | |
72 | #define SPIBASE_LPT 0x3800 | |
73 | #define SPIBASE_LPT_SZ 512 | |
74 | #define BCR 0xdc | |
75 | #define BCR_WPD BIT(0) | |
76 | ||
01560f6b AS |
77 | #define GPIOBASE_ICH0 0x58 |
78 | #define GPIOCTRL_ICH0 0x5C | |
79 | #define GPIOBASE_ICH6 0x48 | |
80 | #define GPIOCTRL_ICH6 0x4C | |
4630b130 | 81 | |
887c8ec7 AS |
82 | #define RCBABASE 0xf0 |
83 | ||
84 | #define wdt_io_res(i) wdt_res(0, i) | |
85 | #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) | |
86 | #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) | |
87 | ||
01560f6b AS |
88 | struct lpc_ich_priv { |
89 | int chipset; | |
429b941a PT |
90 | |
91 | int abase; /* ACPI base */ | |
eb71d4de | 92 | int actrl_pbase; /* ACPI control or PMC base */ |
429b941a PT |
93 | int gbase; /* GPIO base */ |
94 | int gctrl; /* GPIO control */ | |
95 | ||
eb71d4de PT |
96 | int abase_save; /* Cached ACPI base value */ |
97 | int actrl_pbase_save; /* Cached ACPI control or PMC base value */ | |
429b941a | 98 | int gctrl_save; /* Cached GPIO control value */ |
01560f6b | 99 | }; |
4630b130 | 100 | |
887c8ec7 AS |
101 | static struct resource wdt_ich_res[] = { |
102 | /* ACPI - TCO */ | |
103 | { | |
104 | .flags = IORESOURCE_IO, | |
105 | }, | |
106 | /* ACPI - SMI */ | |
107 | { | |
108 | .flags = IORESOURCE_IO, | |
109 | }, | |
eb71d4de | 110 | /* GCS or PMC */ |
887c8ec7 AS |
111 | { |
112 | .flags = IORESOURCE_MEM, | |
113 | }, | |
114 | }; | |
115 | ||
4630b130 AS |
116 | static struct resource gpio_ich_res[] = { |
117 | /* GPIO */ | |
118 | { | |
119 | .flags = IORESOURCE_IO, | |
120 | }, | |
121 | /* ACPI - GPE0 */ | |
122 | { | |
123 | .flags = IORESOURCE_IO, | |
124 | }, | |
125 | }; | |
126 | ||
ff00d7a3 MW |
127 | static struct resource intel_spi_res[] = { |
128 | { | |
129 | .flags = IORESOURCE_MEM, | |
130 | } | |
131 | }; | |
132 | ||
3dab794f AS |
133 | static struct mfd_cell lpc_ich_wdt_cell = { |
134 | .name = "iTCO_wdt", | |
135 | .num_resources = ARRAY_SIZE(wdt_ich_res), | |
136 | .resources = wdt_ich_res, | |
137 | .ignore_resource_conflicts = true, | |
4630b130 AS |
138 | }; |
139 | ||
3dab794f AS |
140 | static struct mfd_cell lpc_ich_gpio_cell = { |
141 | .name = "gpio_ich", | |
142 | .num_resources = ARRAY_SIZE(gpio_ich_res), | |
143 | .resources = gpio_ich_res, | |
144 | .ignore_resource_conflicts = true, | |
4630b130 AS |
145 | }; |
146 | ||
7064d7d8 TJN |
147 | #define APL_GPIO_NORTH 0 |
148 | #define APL_GPIO_NORTHWEST 1 | |
149 | #define APL_GPIO_WEST 2 | |
150 | #define APL_GPIO_SOUTHWEST 3 | |
151 | #define APL_GPIO_NR_DEVICES 4 | |
152 | ||
153 | /* Offset data for Apollo Lake GPIO controllers */ | |
154 | static resource_size_t apl_gpio_offsets[APL_GPIO_NR_DEVICES] = { | |
155 | [APL_GPIO_NORTH] = 0xc50000, | |
156 | [APL_GPIO_NORTHWEST] = 0xc40000, | |
157 | [APL_GPIO_WEST] = 0xc70000, | |
158 | [APL_GPIO_SOUTHWEST] = 0xc00000, | |
159 | }; | |
160 | ||
161 | #define APL_GPIO_RESOURCE_SIZE 0x1000 | |
162 | ||
163 | #define APL_GPIO_IRQ 14 | |
164 | ||
165 | static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = { | |
166 | [APL_GPIO_NORTH] = { | |
167 | DEFINE_RES_MEM(0, 0), | |
168 | DEFINE_RES_IRQ(APL_GPIO_IRQ), | |
169 | }, | |
170 | [APL_GPIO_NORTHWEST] = { | |
171 | DEFINE_RES_MEM(0, 0), | |
172 | DEFINE_RES_IRQ(APL_GPIO_IRQ), | |
173 | }, | |
174 | [APL_GPIO_WEST] = { | |
175 | DEFINE_RES_MEM(0, 0), | |
176 | DEFINE_RES_IRQ(APL_GPIO_IRQ), | |
177 | }, | |
178 | [APL_GPIO_SOUTHWEST] = { | |
179 | DEFINE_RES_MEM(0, 0), | |
180 | DEFINE_RES_IRQ(APL_GPIO_IRQ), | |
181 | }, | |
182 | }; | |
183 | ||
184 | static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = { | |
185 | [APL_GPIO_NORTH] = { | |
186 | .name = "apollolake-pinctrl", | |
187 | .id = APL_GPIO_NORTH, | |
188 | .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]), | |
189 | .resources = apl_gpio_resources[APL_GPIO_NORTH], | |
190 | .ignore_resource_conflicts = true, | |
191 | }, | |
192 | [APL_GPIO_NORTHWEST] = { | |
193 | .name = "apollolake-pinctrl", | |
194 | .id = APL_GPIO_NORTHWEST, | |
195 | .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]), | |
196 | .resources = apl_gpio_resources[APL_GPIO_NORTHWEST], | |
197 | .ignore_resource_conflicts = true, | |
198 | }, | |
199 | [APL_GPIO_WEST] = { | |
200 | .name = "apollolake-pinctrl", | |
201 | .id = APL_GPIO_WEST, | |
202 | .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]), | |
203 | .resources = apl_gpio_resources[APL_GPIO_WEST], | |
204 | .ignore_resource_conflicts = true, | |
205 | }, | |
206 | [APL_GPIO_SOUTHWEST] = { | |
207 | .name = "apollolake-pinctrl", | |
208 | .id = APL_GPIO_SOUTHWEST, | |
209 | .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]), | |
210 | .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST], | |
211 | .ignore_resource_conflicts = true, | |
212 | }, | |
213 | }; | |
ff00d7a3 MW |
214 | |
215 | static struct mfd_cell lpc_ich_spi_cell = { | |
216 | .name = "intel-spi", | |
217 | .num_resources = ARRAY_SIZE(intel_spi_res), | |
218 | .resources = intel_spi_res, | |
219 | .ignore_resource_conflicts = true, | |
220 | }; | |
221 | ||
4630b130 AS |
222 | /* chipset related info */ |
223 | enum lpc_chipsets { | |
224 | LPC_ICH = 0, /* ICH */ | |
225 | LPC_ICH0, /* ICH0 */ | |
226 | LPC_ICH2, /* ICH2 */ | |
227 | LPC_ICH2M, /* ICH2-M */ | |
228 | LPC_ICH3, /* ICH3-S */ | |
229 | LPC_ICH3M, /* ICH3-M */ | |
230 | LPC_ICH4, /* ICH4 */ | |
231 | LPC_ICH4M, /* ICH4-M */ | |
232 | LPC_CICH, /* C-ICH */ | |
233 | LPC_ICH5, /* ICH5 & ICH5R */ | |
234 | LPC_6300ESB, /* 6300ESB */ | |
235 | LPC_ICH6, /* ICH6 & ICH6R */ | |
236 | LPC_ICH6M, /* ICH6-M */ | |
237 | LPC_ICH6W, /* ICH6W & ICH6RW */ | |
238 | LPC_631XESB, /* 631xESB/632xESB */ | |
239 | LPC_ICH7, /* ICH7 & ICH7R */ | |
240 | LPC_ICH7DH, /* ICH7DH */ | |
241 | LPC_ICH7M, /* ICH7-M & ICH7-U */ | |
242 | LPC_ICH7MDH, /* ICH7-M DH */ | |
243 | LPC_NM10, /* NM10 */ | |
244 | LPC_ICH8, /* ICH8 & ICH8R */ | |
245 | LPC_ICH8DH, /* ICH8DH */ | |
246 | LPC_ICH8DO, /* ICH8DO */ | |
247 | LPC_ICH8M, /* ICH8M */ | |
248 | LPC_ICH8ME, /* ICH8M-E */ | |
249 | LPC_ICH9, /* ICH9 */ | |
250 | LPC_ICH9R, /* ICH9R */ | |
251 | LPC_ICH9DH, /* ICH9DH */ | |
252 | LPC_ICH9DO, /* ICH9DO */ | |
253 | LPC_ICH9M, /* ICH9M */ | |
254 | LPC_ICH9ME, /* ICH9M-E */ | |
255 | LPC_ICH10, /* ICH10 */ | |
256 | LPC_ICH10R, /* ICH10R */ | |
257 | LPC_ICH10D, /* ICH10D */ | |
258 | LPC_ICH10DO, /* ICH10DO */ | |
259 | LPC_PCH, /* PCH Desktop Full Featured */ | |
260 | LPC_PCHM, /* PCH Mobile Full Featured */ | |
261 | LPC_P55, /* P55 */ | |
262 | LPC_PM55, /* PM55 */ | |
263 | LPC_H55, /* H55 */ | |
264 | LPC_QM57, /* QM57 */ | |
265 | LPC_H57, /* H57 */ | |
266 | LPC_HM55, /* HM55 */ | |
267 | LPC_Q57, /* Q57 */ | |
268 | LPC_HM57, /* HM57 */ | |
269 | LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ | |
270 | LPC_QS57, /* QS57 */ | |
271 | LPC_3400, /* 3400 */ | |
272 | LPC_3420, /* 3420 */ | |
273 | LPC_3450, /* 3450 */ | |
274 | LPC_EP80579, /* EP80579 */ | |
275 | LPC_CPT, /* Cougar Point */ | |
276 | LPC_CPTD, /* Cougar Point Desktop */ | |
277 | LPC_CPTM, /* Cougar Point Mobile */ | |
278 | LPC_PBG, /* Patsburg */ | |
279 | LPC_DH89XXCC, /* DH89xxCC */ | |
280 | LPC_PPT, /* Panther Point */ | |
281 | LPC_LPT, /* Lynx Point */ | |
7fb9c1a4 | 282 | LPC_LPT_LP, /* Lynx Point-LP */ |
6e6680e3 | 283 | LPC_WBG, /* Wellsburg */ |
8477128f | 284 | LPC_AVN, /* Avoton SoC */ |
6111ec70 | 285 | LPC_BAYTRAIL, /* Bay Trail SoC */ |
283aae8a | 286 | LPC_COLETO, /* Coleto Creek */ |
5e90169c | 287 | LPC_WPT_LP, /* Wildcat Point-LP */ |
ff0c9da0 | 288 | LPC_BRASWELL, /* Braswell SoC */ |
6223a309 | 289 | LPC_LEWISBURG, /* Lewisburg */ |
fea31042 | 290 | LPC_9S, /* 9 Series */ |
87eb832a | 291 | LPC_APL, /* Apollo Lake SoC */ |
a6450cb0 | 292 | LPC_GLK, /* Gemini Lake SoC */ |
f36c1f62 | 293 | LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/ |
4630b130 AS |
294 | }; |
295 | ||
a1ca138f | 296 | static struct lpc_ich_info lpc_chipset_info[] = { |
4630b130 AS |
297 | [LPC_ICH] = { |
298 | .name = "ICH", | |
887c8ec7 | 299 | .iTCO_version = 1, |
4630b130 AS |
300 | }, |
301 | [LPC_ICH0] = { | |
302 | .name = "ICH0", | |
887c8ec7 | 303 | .iTCO_version = 1, |
4630b130 AS |
304 | }, |
305 | [LPC_ICH2] = { | |
306 | .name = "ICH2", | |
887c8ec7 | 307 | .iTCO_version = 1, |
4630b130 AS |
308 | }, |
309 | [LPC_ICH2M] = { | |
310 | .name = "ICH2-M", | |
887c8ec7 | 311 | .iTCO_version = 1, |
4630b130 AS |
312 | }, |
313 | [LPC_ICH3] = { | |
314 | .name = "ICH3-S", | |
887c8ec7 | 315 | .iTCO_version = 1, |
4630b130 AS |
316 | }, |
317 | [LPC_ICH3M] = { | |
318 | .name = "ICH3-M", | |
887c8ec7 | 319 | .iTCO_version = 1, |
4630b130 AS |
320 | }, |
321 | [LPC_ICH4] = { | |
322 | .name = "ICH4", | |
887c8ec7 | 323 | .iTCO_version = 1, |
4630b130 AS |
324 | }, |
325 | [LPC_ICH4M] = { | |
326 | .name = "ICH4-M", | |
887c8ec7 | 327 | .iTCO_version = 1, |
4630b130 AS |
328 | }, |
329 | [LPC_CICH] = { | |
330 | .name = "C-ICH", | |
887c8ec7 | 331 | .iTCO_version = 1, |
4630b130 AS |
332 | }, |
333 | [LPC_ICH5] = { | |
334 | .name = "ICH5 or ICH5R", | |
887c8ec7 | 335 | .iTCO_version = 1, |
4630b130 AS |
336 | }, |
337 | [LPC_6300ESB] = { | |
338 | .name = "6300ESB", | |
887c8ec7 | 339 | .iTCO_version = 1, |
4630b130 AS |
340 | }, |
341 | [LPC_ICH6] = { | |
342 | .name = "ICH6 or ICH6R", | |
887c8ec7 | 343 | .iTCO_version = 2, |
4630b130 AS |
344 | .gpio_version = ICH_V6_GPIO, |
345 | }, | |
346 | [LPC_ICH6M] = { | |
347 | .name = "ICH6-M", | |
887c8ec7 | 348 | .iTCO_version = 2, |
4630b130 AS |
349 | .gpio_version = ICH_V6_GPIO, |
350 | }, | |
351 | [LPC_ICH6W] = { | |
352 | .name = "ICH6W or ICH6RW", | |
887c8ec7 | 353 | .iTCO_version = 2, |
4630b130 AS |
354 | .gpio_version = ICH_V6_GPIO, |
355 | }, | |
356 | [LPC_631XESB] = { | |
357 | .name = "631xESB/632xESB", | |
887c8ec7 | 358 | .iTCO_version = 2, |
4630b130 AS |
359 | .gpio_version = ICH_V6_GPIO, |
360 | }, | |
361 | [LPC_ICH7] = { | |
362 | .name = "ICH7 or ICH7R", | |
887c8ec7 | 363 | .iTCO_version = 2, |
4630b130 AS |
364 | .gpio_version = ICH_V7_GPIO, |
365 | }, | |
366 | [LPC_ICH7DH] = { | |
367 | .name = "ICH7DH", | |
887c8ec7 | 368 | .iTCO_version = 2, |
4630b130 AS |
369 | .gpio_version = ICH_V7_GPIO, |
370 | }, | |
371 | [LPC_ICH7M] = { | |
372 | .name = "ICH7-M or ICH7-U", | |
887c8ec7 | 373 | .iTCO_version = 2, |
4630b130 AS |
374 | .gpio_version = ICH_V7_GPIO, |
375 | }, | |
376 | [LPC_ICH7MDH] = { | |
377 | .name = "ICH7-M DH", | |
887c8ec7 | 378 | .iTCO_version = 2, |
4630b130 AS |
379 | .gpio_version = ICH_V7_GPIO, |
380 | }, | |
381 | [LPC_NM10] = { | |
382 | .name = "NM10", | |
887c8ec7 | 383 | .iTCO_version = 2, |
117bbfe2 | 384 | .gpio_version = ICH_V7_GPIO, |
4630b130 AS |
385 | }, |
386 | [LPC_ICH8] = { | |
387 | .name = "ICH8 or ICH8R", | |
887c8ec7 | 388 | .iTCO_version = 2, |
4630b130 AS |
389 | .gpio_version = ICH_V7_GPIO, |
390 | }, | |
391 | [LPC_ICH8DH] = { | |
392 | .name = "ICH8DH", | |
887c8ec7 | 393 | .iTCO_version = 2, |
4630b130 AS |
394 | .gpio_version = ICH_V7_GPIO, |
395 | }, | |
396 | [LPC_ICH8DO] = { | |
397 | .name = "ICH8DO", | |
887c8ec7 | 398 | .iTCO_version = 2, |
4630b130 AS |
399 | .gpio_version = ICH_V7_GPIO, |
400 | }, | |
401 | [LPC_ICH8M] = { | |
402 | .name = "ICH8M", | |
887c8ec7 | 403 | .iTCO_version = 2, |
4630b130 AS |
404 | .gpio_version = ICH_V7_GPIO, |
405 | }, | |
406 | [LPC_ICH8ME] = { | |
407 | .name = "ICH8M-E", | |
887c8ec7 | 408 | .iTCO_version = 2, |
4630b130 AS |
409 | .gpio_version = ICH_V7_GPIO, |
410 | }, | |
411 | [LPC_ICH9] = { | |
412 | .name = "ICH9", | |
887c8ec7 | 413 | .iTCO_version = 2, |
4630b130 AS |
414 | .gpio_version = ICH_V9_GPIO, |
415 | }, | |
416 | [LPC_ICH9R] = { | |
417 | .name = "ICH9R", | |
887c8ec7 | 418 | .iTCO_version = 2, |
4630b130 AS |
419 | .gpio_version = ICH_V9_GPIO, |
420 | }, | |
421 | [LPC_ICH9DH] = { | |
422 | .name = "ICH9DH", | |
887c8ec7 | 423 | .iTCO_version = 2, |
4630b130 AS |
424 | .gpio_version = ICH_V9_GPIO, |
425 | }, | |
426 | [LPC_ICH9DO] = { | |
427 | .name = "ICH9DO", | |
887c8ec7 | 428 | .iTCO_version = 2, |
4630b130 AS |
429 | .gpio_version = ICH_V9_GPIO, |
430 | }, | |
431 | [LPC_ICH9M] = { | |
432 | .name = "ICH9M", | |
887c8ec7 | 433 | .iTCO_version = 2, |
4630b130 AS |
434 | .gpio_version = ICH_V9_GPIO, |
435 | }, | |
436 | [LPC_ICH9ME] = { | |
437 | .name = "ICH9M-E", | |
887c8ec7 | 438 | .iTCO_version = 2, |
4630b130 AS |
439 | .gpio_version = ICH_V9_GPIO, |
440 | }, | |
441 | [LPC_ICH10] = { | |
442 | .name = "ICH10", | |
887c8ec7 | 443 | .iTCO_version = 2, |
4630b130 AS |
444 | .gpio_version = ICH_V10CONS_GPIO, |
445 | }, | |
446 | [LPC_ICH10R] = { | |
447 | .name = "ICH10R", | |
887c8ec7 | 448 | .iTCO_version = 2, |
4630b130 AS |
449 | .gpio_version = ICH_V10CONS_GPIO, |
450 | }, | |
451 | [LPC_ICH10D] = { | |
452 | .name = "ICH10D", | |
887c8ec7 | 453 | .iTCO_version = 2, |
4630b130 AS |
454 | .gpio_version = ICH_V10CORP_GPIO, |
455 | }, | |
456 | [LPC_ICH10DO] = { | |
457 | .name = "ICH10DO", | |
887c8ec7 | 458 | .iTCO_version = 2, |
4630b130 AS |
459 | .gpio_version = ICH_V10CORP_GPIO, |
460 | }, | |
461 | [LPC_PCH] = { | |
462 | .name = "PCH Desktop Full Featured", | |
887c8ec7 | 463 | .iTCO_version = 2, |
4630b130 AS |
464 | .gpio_version = ICH_V5_GPIO, |
465 | }, | |
466 | [LPC_PCHM] = { | |
467 | .name = "PCH Mobile Full Featured", | |
887c8ec7 | 468 | .iTCO_version = 2, |
4630b130 AS |
469 | .gpio_version = ICH_V5_GPIO, |
470 | }, | |
471 | [LPC_P55] = { | |
472 | .name = "P55", | |
887c8ec7 | 473 | .iTCO_version = 2, |
4630b130 AS |
474 | .gpio_version = ICH_V5_GPIO, |
475 | }, | |
476 | [LPC_PM55] = { | |
477 | .name = "PM55", | |
887c8ec7 | 478 | .iTCO_version = 2, |
4630b130 AS |
479 | .gpio_version = ICH_V5_GPIO, |
480 | }, | |
481 | [LPC_H55] = { | |
482 | .name = "H55", | |
887c8ec7 | 483 | .iTCO_version = 2, |
4630b130 AS |
484 | .gpio_version = ICH_V5_GPIO, |
485 | }, | |
486 | [LPC_QM57] = { | |
487 | .name = "QM57", | |
887c8ec7 | 488 | .iTCO_version = 2, |
4630b130 AS |
489 | .gpio_version = ICH_V5_GPIO, |
490 | }, | |
491 | [LPC_H57] = { | |
492 | .name = "H57", | |
887c8ec7 | 493 | .iTCO_version = 2, |
4630b130 AS |
494 | .gpio_version = ICH_V5_GPIO, |
495 | }, | |
496 | [LPC_HM55] = { | |
497 | .name = "HM55", | |
887c8ec7 | 498 | .iTCO_version = 2, |
4630b130 AS |
499 | .gpio_version = ICH_V5_GPIO, |
500 | }, | |
501 | [LPC_Q57] = { | |
502 | .name = "Q57", | |
887c8ec7 | 503 | .iTCO_version = 2, |
4630b130 AS |
504 | .gpio_version = ICH_V5_GPIO, |
505 | }, | |
506 | [LPC_HM57] = { | |
507 | .name = "HM57", | |
887c8ec7 | 508 | .iTCO_version = 2, |
4630b130 AS |
509 | .gpio_version = ICH_V5_GPIO, |
510 | }, | |
511 | [LPC_PCHMSFF] = { | |
512 | .name = "PCH Mobile SFF Full Featured", | |
887c8ec7 | 513 | .iTCO_version = 2, |
4630b130 AS |
514 | .gpio_version = ICH_V5_GPIO, |
515 | }, | |
516 | [LPC_QS57] = { | |
517 | .name = "QS57", | |
887c8ec7 | 518 | .iTCO_version = 2, |
4630b130 AS |
519 | .gpio_version = ICH_V5_GPIO, |
520 | }, | |
521 | [LPC_3400] = { | |
522 | .name = "3400", | |
887c8ec7 | 523 | .iTCO_version = 2, |
4630b130 AS |
524 | .gpio_version = ICH_V5_GPIO, |
525 | }, | |
526 | [LPC_3420] = { | |
527 | .name = "3420", | |
887c8ec7 | 528 | .iTCO_version = 2, |
4630b130 AS |
529 | .gpio_version = ICH_V5_GPIO, |
530 | }, | |
531 | [LPC_3450] = { | |
532 | .name = "3450", | |
887c8ec7 | 533 | .iTCO_version = 2, |
4630b130 AS |
534 | .gpio_version = ICH_V5_GPIO, |
535 | }, | |
536 | [LPC_EP80579] = { | |
537 | .name = "EP80579", | |
887c8ec7 | 538 | .iTCO_version = 2, |
4630b130 AS |
539 | }, |
540 | [LPC_CPT] = { | |
541 | .name = "Cougar Point", | |
887c8ec7 | 542 | .iTCO_version = 2, |
4630b130 AS |
543 | .gpio_version = ICH_V5_GPIO, |
544 | }, | |
545 | [LPC_CPTD] = { | |
546 | .name = "Cougar Point Desktop", | |
887c8ec7 | 547 | .iTCO_version = 2, |
4630b130 AS |
548 | .gpio_version = ICH_V5_GPIO, |
549 | }, | |
550 | [LPC_CPTM] = { | |
551 | .name = "Cougar Point Mobile", | |
887c8ec7 | 552 | .iTCO_version = 2, |
4630b130 AS |
553 | .gpio_version = ICH_V5_GPIO, |
554 | }, | |
555 | [LPC_PBG] = { | |
556 | .name = "Patsburg", | |
887c8ec7 | 557 | .iTCO_version = 2, |
4630b130 AS |
558 | }, |
559 | [LPC_DH89XXCC] = { | |
560 | .name = "DH89xxCC", | |
887c8ec7 | 561 | .iTCO_version = 2, |
ef0eea5b | 562 | .gpio_version = ICH_V5_GPIO, |
4630b130 AS |
563 | }, |
564 | [LPC_PPT] = { | |
565 | .name = "Panther Point", | |
887c8ec7 | 566 | .iTCO_version = 2, |
62cf2cdb | 567 | .gpio_version = ICH_V5_GPIO, |
4630b130 AS |
568 | }, |
569 | [LPC_LPT] = { | |
570 | .name = "Lynx Point", | |
887c8ec7 | 571 | .iTCO_version = 2, |
e420d6a1 | 572 | .gpio_version = ICH_V5_GPIO, |
ff00d7a3 | 573 | .spi_type = INTEL_SPI_LPT, |
4630b130 | 574 | }, |
7fb9c1a4 JR |
575 | [LPC_LPT_LP] = { |
576 | .name = "Lynx Point_LP", | |
577 | .iTCO_version = 2, | |
ff00d7a3 | 578 | .spi_type = INTEL_SPI_LPT, |
7fb9c1a4 | 579 | }, |
6e6680e3 JR |
580 | [LPC_WBG] = { |
581 | .name = "Wellsburg", | |
582 | .iTCO_version = 2, | |
583 | }, | |
8477128f JR |
584 | [LPC_AVN] = { |
585 | .name = "Avoton SoC", | |
c48cf598 | 586 | .iTCO_version = 3, |
facd9939 | 587 | .gpio_version = AVOTON_GPIO, |
07d70913 | 588 | .spi_type = INTEL_SPI_BYT, |
8477128f | 589 | }, |
6111ec70 PT |
590 | [LPC_BAYTRAIL] = { |
591 | .name = "Bay Trail SoC", | |
592 | .iTCO_version = 3, | |
ff00d7a3 | 593 | .spi_type = INTEL_SPI_BYT, |
6111ec70 | 594 | }, |
283aae8a SH |
595 | [LPC_COLETO] = { |
596 | .name = "Coleto Creek", | |
597 | .iTCO_version = 2, | |
598 | }, | |
5e90169c | 599 | [LPC_WPT_LP] = { |
a8822df9 | 600 | .name = "Wildcat Point_LP", |
5e90169c | 601 | .iTCO_version = 2, |
ff00d7a3 | 602 | .spi_type = INTEL_SPI_LPT, |
5e90169c | 603 | }, |
ff0c9da0 AC |
604 | [LPC_BRASWELL] = { |
605 | .name = "Braswell SoC", | |
606 | .iTCO_version = 3, | |
ff00d7a3 | 607 | .spi_type = INTEL_SPI_BYT, |
ff0c9da0 | 608 | }, |
6223a309 AY |
609 | [LPC_LEWISBURG] = { |
610 | .name = "Lewisburg", | |
611 | .iTCO_version = 2, | |
612 | }, | |
fea31042 JR |
613 | [LPC_9S] = { |
614 | .name = "9 Series", | |
615 | .iTCO_version = 2, | |
e420d6a1 | 616 | .gpio_version = ICH_V5_GPIO, |
fea31042 | 617 | }, |
87eb832a MW |
618 | [LPC_APL] = { |
619 | .name = "Apollo Lake SoC", | |
e93c1021 | 620 | .iTCO_version = 5, |
87eb832a MW |
621 | .spi_type = INTEL_SPI_BXT, |
622 | }, | |
a6450cb0 MW |
623 | [LPC_GLK] = { |
624 | .name = "Gemini Lake SoC", | |
625 | .spi_type = INTEL_SPI_BXT, | |
626 | }, | |
f36c1f62 PK |
627 | [LPC_COUGARMOUNTAIN] = { |
628 | .name = "Cougar Mountain SoC", | |
629 | .iTCO_version = 3, | |
630 | }, | |
4630b130 AS |
631 | }; |
632 | ||
633 | /* | |
634 | * This data only exists for exporting the supported PCI ids | |
635 | * via MODULE_DEVICE_TABLE. We do not actually register a | |
636 | * pci_driver, because the I/O Controller Hub has also other | |
637 | * functions that probably will be registered by other drivers. | |
638 | */ | |
36fcd06c | 639 | static const struct pci_device_id lpc_ich_ids[] = { |
aec9038e AS |
640 | { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL}, |
641 | { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, | |
642 | { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, | |
643 | { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, | |
644 | { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, | |
645 | { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, | |
646 | { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, | |
647 | { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, | |
648 | { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, | |
649 | { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, | |
650 | { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, | |
651 | { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, | |
652 | { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, | |
653 | { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, | |
654 | { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, | |
655 | { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, | |
656 | { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, | |
657 | { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, | |
658 | { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, | |
659 | { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, | |
660 | { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, | |
661 | { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, | |
662 | { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, | |
663 | { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, | |
664 | { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, | |
665 | { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, | |
666 | { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, | |
667 | { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, | |
668 | { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, | |
669 | { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, | |
670 | { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, | |
671 | { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, | |
672 | { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, | |
673 | { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, | |
674 | { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, | |
675 | { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, | |
676 | { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, | |
677 | { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, | |
678 | { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, | |
679 | { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, | |
680 | { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, | |
681 | { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, | |
682 | { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, | |
683 | { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, | |
684 | { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, | |
685 | { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, | |
686 | { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, | |
687 | { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, | |
688 | { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, | |
689 | { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, | |
690 | { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, | |
691 | { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, | |
692 | { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, | |
693 | { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, | |
694 | { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, | |
695 | { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, | |
696 | { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, | |
697 | { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, | |
698 | { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, | |
699 | { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, | |
700 | { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, | |
701 | { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, | |
702 | { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, | |
703 | { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, | |
704 | { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, | |
705 | { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, | |
706 | { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, | |
707 | { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, | |
708 | { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, | |
709 | { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, | |
710 | { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL}, | |
711 | { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, | |
712 | { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, | |
4630b130 AS |
713 | { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, |
714 | { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, | |
715 | { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, | |
716 | { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, | |
72715757 | 717 | { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, |
4630b130 AS |
718 | { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, |
719 | { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, | |
720 | { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, | |
721 | { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, | |
4630b130 AS |
722 | { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, |
723 | { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, | |
724 | { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, | |
725 | { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, | |
726 | { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, | |
727 | { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, | |
728 | { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, | |
729 | { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, | |
730 | { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, | |
731 | { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, | |
732 | { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, | |
733 | { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, | |
734 | { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, | |
735 | { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, | |
736 | { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, | |
737 | { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, | |
738 | { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, | |
739 | { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, | |
740 | { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, | |
741 | { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, | |
742 | { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, | |
4630b130 | 743 | { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, |
72715757 | 744 | { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, |
4630b130 | 745 | { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, |
4630b130 | 746 | { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, |
72715757 | 747 | { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, |
4630b130 | 748 | { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, |
72715757 | 749 | { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, |
4630b130 AS |
750 | { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, |
751 | { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, | |
752 | { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, | |
4630b130 AS |
753 | { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, |
754 | { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, | |
72715757 | 755 | { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, |
4630b130 | 756 | { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, |
72715757 AS |
757 | { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, |
758 | { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, | |
a6450cb0 | 759 | { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK}, |
f36c1f62 | 760 | { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN}, |
72715757 | 761 | { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, |
4630b130 | 762 | { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, |
72715757 | 763 | { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, |
4630b130 | 764 | { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, |
4630b130 AS |
765 | { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, |
766 | { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, | |
767 | { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, | |
768 | { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, | |
769 | { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, | |
770 | { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, | |
771 | { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, | |
772 | { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, | |
773 | { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, | |
774 | { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, | |
775 | { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, | |
776 | { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, | |
777 | { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, | |
778 | { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, | |
779 | { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, | |
780 | { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, | |
87eb832a | 781 | { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL}, |
4630b130 AS |
782 | { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, |
783 | { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, | |
784 | { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, | |
785 | { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, | |
786 | { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, | |
787 | { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, | |
788 | { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, | |
789 | { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, | |
790 | { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, | |
791 | { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, | |
792 | { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, | |
793 | { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, | |
794 | { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, | |
795 | { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, | |
796 | { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, | |
797 | { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, | |
798 | { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, | |
799 | { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, | |
800 | { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, | |
801 | { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, | |
802 | { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, | |
803 | { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, | |
804 | { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, | |
805 | { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, | |
806 | { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, | |
807 | { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, | |
808 | { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, | |
809 | { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, | |
810 | { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, | |
811 | { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, | |
812 | { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, | |
813 | { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, | |
aec9038e AS |
814 | { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S}, |
815 | { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S}, | |
816 | { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S}, | |
817 | { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S}, | |
818 | { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S}, | |
6e6680e3 JR |
819 | { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, |
820 | { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, | |
821 | { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, | |
822 | { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, | |
823 | { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, | |
824 | { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, | |
825 | { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, | |
826 | { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, | |
827 | { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, | |
828 | { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, | |
829 | { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, | |
830 | { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, | |
831 | { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, | |
832 | { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, | |
833 | { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, | |
834 | { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, | |
835 | { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, | |
836 | { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, | |
837 | { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, | |
838 | { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, | |
839 | { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, | |
840 | { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, | |
841 | { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, | |
842 | { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, | |
843 | { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, | |
844 | { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, | |
845 | { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, | |
846 | { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, | |
847 | { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, | |
848 | { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, | |
849 | { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, | |
850 | { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, | |
aec9038e AS |
851 | { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, |
852 | { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, | |
853 | { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, | |
854 | { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, | |
855 | { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, | |
856 | { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, | |
857 | { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, | |
858 | { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, | |
5e90169c JR |
859 | { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, |
860 | { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, | |
861 | { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, | |
862 | { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, | |
863 | { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, | |
864 | { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, | |
865 | { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, | |
6223a309 AY |
866 | { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG}, |
867 | { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG}, | |
868 | { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG}, | |
869 | { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG}, | |
870 | { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG}, | |
871 | { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG}, | |
872 | { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG}, | |
873 | { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG}, | |
874 | { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG}, | |
4630b130 AS |
875 | { 0, }, /* End of list */ |
876 | }; | |
877 | MODULE_DEVICE_TABLE(pci, lpc_ich_ids); | |
878 | ||
879 | static void lpc_ich_restore_config_space(struct pci_dev *dev) | |
880 | { | |
01560f6b AS |
881 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
882 | ||
eb71d4de PT |
883 | if (priv->abase_save >= 0) { |
884 | pci_write_config_byte(dev, priv->abase, priv->abase_save); | |
885 | priv->abase_save = -1; | |
886 | } | |
887 | ||
888 | if (priv->actrl_pbase_save >= 0) { | |
889 | pci_write_config_byte(dev, priv->actrl_pbase, | |
890 | priv->actrl_pbase_save); | |
891 | priv->actrl_pbase_save = -1; | |
4630b130 AS |
892 | } |
893 | ||
429b941a PT |
894 | if (priv->gctrl_save >= 0) { |
895 | pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); | |
896 | priv->gctrl_save = -1; | |
4630b130 AS |
897 | } |
898 | } | |
899 | ||
f791be49 | 900 | static void lpc_ich_enable_acpi_space(struct pci_dev *dev) |
4630b130 | 901 | { |
01560f6b | 902 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
903 | u8 reg_save; |
904 | ||
eb71d4de PT |
905 | switch (lpc_chipset_info[priv->chipset].iTCO_version) { |
906 | case 3: | |
907 | /* | |
908 | * Some chipsets (eg Avoton) enable the ACPI space in the | |
909 | * ACPI BASE register. | |
910 | */ | |
911 | pci_read_config_byte(dev, priv->abase, ®_save); | |
912 | pci_write_config_byte(dev, priv->abase, reg_save | 0x2); | |
913 | priv->abase_save = reg_save; | |
914 | break; | |
915 | default: | |
916 | /* | |
917 | * Most chipsets enable the ACPI space in the ACPI control | |
918 | * register. | |
919 | */ | |
920 | pci_read_config_byte(dev, priv->actrl_pbase, ®_save); | |
921 | pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); | |
922 | priv->actrl_pbase_save = reg_save; | |
923 | break; | |
924 | } | |
4630b130 AS |
925 | } |
926 | ||
f791be49 | 927 | static void lpc_ich_enable_gpio_space(struct pci_dev *dev) |
4630b130 | 928 | { |
01560f6b | 929 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
930 | u8 reg_save; |
931 | ||
429b941a PT |
932 | pci_read_config_byte(dev, priv->gctrl, ®_save); |
933 | pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); | |
934 | priv->gctrl_save = reg_save; | |
4630b130 AS |
935 | } |
936 | ||
eb71d4de PT |
937 | static void lpc_ich_enable_pmc_space(struct pci_dev *dev) |
938 | { | |
939 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); | |
940 | u8 reg_save; | |
941 | ||
942 | pci_read_config_byte(dev, priv->actrl_pbase, ®_save); | |
943 | pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); | |
944 | ||
945 | priv->actrl_pbase_save = reg_save; | |
946 | } | |
947 | ||
420b54de | 948 | static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev) |
4630b130 | 949 | { |
420b54de | 950 | struct itco_wdt_platform_data *pdata; |
01560f6b | 951 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
420b54de | 952 | struct lpc_ich_info *info; |
3dab794f | 953 | struct mfd_cell *cell = &lpc_ich_wdt_cell; |
420b54de MF |
954 | |
955 | pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); | |
956 | if (!pdata) | |
957 | return -ENOMEM; | |
958 | ||
959 | info = &lpc_chipset_info[priv->chipset]; | |
960 | ||
961 | pdata->version = info->iTCO_version; | |
6a32d399 | 962 | strscpy(pdata->name, info->name, sizeof(pdata->name)); |
420b54de MF |
963 | |
964 | cell->platform_data = pdata; | |
965 | cell->pdata_size = sizeof(*pdata); | |
966 | return 0; | |
967 | } | |
968 | ||
969 | static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev) | |
970 | { | |
971 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); | |
3dab794f | 972 | struct mfd_cell *cell = &lpc_ich_gpio_cell; |
01560f6b AS |
973 | |
974 | cell->platform_data = &lpc_chipset_info[priv->chipset]; | |
4630b130 AS |
975 | cell->pdata_size = sizeof(struct lpc_ich_info); |
976 | } | |
977 | ||
4f600ada JD |
978 | /* |
979 | * We don't check for resource conflict globally. There are 2 or 3 independent | |
980 | * GPIO groups and it's enough to have access to one of these to instantiate | |
981 | * the device. | |
982 | */ | |
f791be49 | 983 | static int lpc_ich_check_conflict_gpio(struct resource *res) |
4f600ada JD |
984 | { |
985 | int ret; | |
986 | u8 use_gpio = 0; | |
987 | ||
988 | if (resource_size(res) >= 0x50 && | |
989 | !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) | |
990 | use_gpio |= 1 << 2; | |
991 | ||
992 | if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) | |
993 | use_gpio |= 1 << 1; | |
994 | ||
995 | ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); | |
996 | if (!ret) | |
997 | use_gpio |= 1 << 0; | |
998 | ||
999 | return use_gpio ? use_gpio : ret; | |
1000 | } | |
1001 | ||
01560f6b | 1002 | static int lpc_ich_init_gpio(struct pci_dev *dev) |
4630b130 | 1003 | { |
01560f6b | 1004 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
1005 | u32 base_addr_cfg; |
1006 | u32 base_addr; | |
1007 | int ret; | |
1008 | bool acpi_conflict = false; | |
1009 | struct resource *res; | |
1010 | ||
1011 | /* Setup power management base register */ | |
429b941a | 1012 | pci_read_config_dword(dev, priv->abase, &base_addr_cfg); |
4630b130 AS |
1013 | base_addr = base_addr_cfg & 0x0000ff80; |
1014 | if (!base_addr) { | |
0c418844 | 1015 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); |
3dab794f | 1016 | lpc_ich_gpio_cell.num_resources--; |
4630b130 AS |
1017 | goto gpe0_done; |
1018 | } | |
1019 | ||
1020 | res = &gpio_ich_res[ICH_RES_GPE0]; | |
1021 | res->start = base_addr + ACPIBASE_GPE_OFF; | |
1022 | res->end = base_addr + ACPIBASE_GPE_END; | |
1023 | ret = acpi_check_resource_conflict(res); | |
1024 | if (ret) { | |
1025 | /* | |
1026 | * This isn't fatal for the GPIO, but we have to make sure that | |
1027 | * the platform_device subsystem doesn't see this resource | |
1028 | * or it will register an invalid region. | |
1029 | */ | |
3dab794f | 1030 | lpc_ich_gpio_cell.num_resources--; |
4630b130 AS |
1031 | acpi_conflict = true; |
1032 | } else { | |
1033 | lpc_ich_enable_acpi_space(dev); | |
1034 | } | |
1035 | ||
1036 | gpe0_done: | |
1037 | /* Setup GPIO base register */ | |
429b941a | 1038 | pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); |
4630b130 AS |
1039 | base_addr = base_addr_cfg & 0x0000ff80; |
1040 | if (!base_addr) { | |
0c418844 | 1041 | dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); |
4630b130 AS |
1042 | ret = -ENODEV; |
1043 | goto gpio_done; | |
1044 | } | |
1045 | ||
1046 | /* Older devices provide fewer GPIO and have a smaller resource size. */ | |
1047 | res = &gpio_ich_res[ICH_RES_GPIO]; | |
1048 | res->start = base_addr; | |
01560f6b | 1049 | switch (lpc_chipset_info[priv->chipset].gpio_version) { |
4630b130 AS |
1050 | case ICH_V5_GPIO: |
1051 | case ICH_V10CORP_GPIO: | |
1052 | res->end = res->start + 128 - 1; | |
1053 | break; | |
1054 | default: | |
1055 | res->end = res->start + 64 - 1; | |
1056 | break; | |
1057 | } | |
1058 | ||
4f600ada JD |
1059 | ret = lpc_ich_check_conflict_gpio(res); |
1060 | if (ret < 0) { | |
4630b130 AS |
1061 | /* this isn't necessarily fatal for the GPIO */ |
1062 | acpi_conflict = true; | |
1063 | goto gpio_done; | |
1064 | } | |
01560f6b | 1065 | lpc_chipset_info[priv->chipset].use_gpio = ret; |
4630b130 AS |
1066 | lpc_ich_enable_gpio_space(dev); |
1067 | ||
420b54de | 1068 | lpc_ich_finalize_gpio_cell(dev); |
1abf25a2 | 1069 | ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, |
3dab794f | 1070 | &lpc_ich_gpio_cell, 1, NULL, 0, NULL); |
4630b130 AS |
1071 | |
1072 | gpio_done: | |
1073 | if (acpi_conflict) | |
1074 | pr_warn("Resource conflict(s) found affecting %s\n", | |
3dab794f | 1075 | lpc_ich_gpio_cell.name); |
4630b130 AS |
1076 | return ret; |
1077 | } | |
1078 | ||
01560f6b | 1079 | static int lpc_ich_init_wdt(struct pci_dev *dev) |
887c8ec7 | 1080 | { |
01560f6b | 1081 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
887c8ec7 AS |
1082 | u32 base_addr_cfg; |
1083 | u32 base_addr; | |
1084 | int ret; | |
887c8ec7 AS |
1085 | struct resource *res; |
1086 | ||
3413f702 MW |
1087 | /* If we have ACPI based watchdog use that instead */ |
1088 | if (acpi_has_watchdog()) | |
1089 | return -ENODEV; | |
1090 | ||
887c8ec7 | 1091 | /* Setup power management base register */ |
429b941a | 1092 | pci_read_config_dword(dev, priv->abase, &base_addr_cfg); |
887c8ec7 AS |
1093 | base_addr = base_addr_cfg & 0x0000ff80; |
1094 | if (!base_addr) { | |
0c418844 | 1095 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); |
887c8ec7 AS |
1096 | ret = -ENODEV; |
1097 | goto wdt_done; | |
1098 | } | |
1099 | ||
1100 | res = wdt_io_res(ICH_RES_IO_TCO); | |
1101 | res->start = base_addr + ACPIBASE_TCO_OFF; | |
1102 | res->end = base_addr + ACPIBASE_TCO_END; | |
887c8ec7 AS |
1103 | |
1104 | res = wdt_io_res(ICH_RES_IO_SMI); | |
1105 | res->start = base_addr + ACPIBASE_SMI_OFF; | |
1106 | res->end = base_addr + ACPIBASE_SMI_END; | |
092369ef | 1107 | |
887c8ec7 AS |
1108 | lpc_ich_enable_acpi_space(dev); |
1109 | ||
1110 | /* | |
eb71d4de | 1111 | * iTCO v2: |
887c8ec7 AS |
1112 | * Get the Memory-Mapped GCS register. To get access to it |
1113 | * we have to read RCBA from PCI Config space 0xf0 and use | |
1114 | * it as base. GCS = RCBA + ICH6_GCS(0x3410). | |
eb71d4de PT |
1115 | * |
1116 | * iTCO v3: | |
1117 | * Get the Power Management Configuration register. To get access | |
1118 | * to it we have to read the PMC BASE from config space and address | |
1119 | * the register at offset 0x8. | |
887c8ec7 | 1120 | */ |
01560f6b | 1121 | if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { |
e294bc91 | 1122 | /* Don't register iomem for TCO ver 1 */ |
3dab794f | 1123 | lpc_ich_wdt_cell.num_resources--; |
eb71d4de | 1124 | } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { |
887c8ec7 AS |
1125 | pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); |
1126 | base_addr = base_addr_cfg & 0xffffc000; | |
1127 | if (!(base_addr_cfg & 1)) { | |
0c418844 PB |
1128 | dev_notice(&dev->dev, "RCBA is disabled by " |
1129 | "hardware/BIOS, device disabled\n"); | |
887c8ec7 AS |
1130 | ret = -ENODEV; |
1131 | goto wdt_done; | |
1132 | } | |
eb71d4de | 1133 | res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); |
887c8ec7 AS |
1134 | res->start = base_addr + ACPIBASE_GCS_OFF; |
1135 | res->end = base_addr + ACPIBASE_GCS_END; | |
eb71d4de PT |
1136 | } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { |
1137 | lpc_ich_enable_pmc_space(dev); | |
1138 | pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg); | |
1139 | base_addr = base_addr_cfg & 0xfffffe00; | |
1140 | ||
1141 | res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); | |
1142 | res->start = base_addr + ACPIBASE_PMC_OFF; | |
1143 | res->end = base_addr + ACPIBASE_PMC_END; | |
887c8ec7 AS |
1144 | } |
1145 | ||
420b54de MF |
1146 | ret = lpc_ich_finalize_wdt_cell(dev); |
1147 | if (ret) | |
1148 | goto wdt_done; | |
1149 | ||
1abf25a2 | 1150 | ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, |
3dab794f | 1151 | &lpc_ich_wdt_cell, 1, NULL, 0, NULL); |
887c8ec7 AS |
1152 | |
1153 | wdt_done: | |
887c8ec7 AS |
1154 | return ret; |
1155 | } | |
1156 | ||
7064d7d8 TJN |
1157 | static int lpc_ich_init_pinctrl(struct pci_dev *dev) |
1158 | { | |
1159 | struct resource base; | |
1160 | unsigned int i; | |
1161 | int ret; | |
1162 | ||
1163 | /* Check, if GPIO has been exported as an ACPI device */ | |
1164 | if (acpi_dev_present("INT3452", NULL, -1)) | |
1165 | return -EEXIST; | |
1166 | ||
1167 | ret = p2sb_bar(dev->bus, 0, &base); | |
1168 | if (ret) | |
1169 | return ret; | |
1170 | ||
1171 | for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) { | |
1172 | struct resource *mem = &apl_gpio_resources[i][0]; | |
1173 | resource_size_t offset = apl_gpio_offsets[i]; | |
1174 | ||
1175 | /* Fill MEM resource */ | |
1176 | mem->start = base.start + offset; | |
1177 | mem->end = base.start + offset + APL_GPIO_RESOURCE_SIZE - 1; | |
1178 | mem->flags = base.flags; | |
1179 | } | |
1180 | ||
1181 | return mfd_add_devices(&dev->dev, 0, apl_gpio_devices, | |
1182 | ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL); | |
1183 | } | |
1184 | ||
cd149eff MW |
1185 | static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data) |
1186 | { | |
1187 | u32 val; | |
1188 | ||
1189 | val = readl(base + BYT_BCR); | |
1190 | if (!(val & BYT_BCR_WPD)) { | |
1191 | val |= BYT_BCR_WPD; | |
1192 | writel(val, base + BYT_BCR); | |
1193 | val = readl(base + BYT_BCR); | |
1194 | } | |
1195 | ||
1196 | return val & BYT_BCR_WPD; | |
1197 | } | |
1198 | ||
6e3b29db | 1199 | static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn) |
cd149eff | 1200 | { |
cd149eff MW |
1201 | u32 bcr; |
1202 | ||
6e3b29db | 1203 | pci_bus_read_config_dword(bus, devfn, BCR, &bcr); |
cd149eff MW |
1204 | if (!(bcr & BCR_WPD)) { |
1205 | bcr |= BCR_WPD; | |
6e3b29db AS |
1206 | pci_bus_write_config_dword(bus, devfn, BCR, bcr); |
1207 | pci_bus_read_config_dword(bus, devfn, BCR, &bcr); | |
cd149eff MW |
1208 | } |
1209 | ||
1210 | return bcr & BCR_WPD; | |
1211 | } | |
1212 | ||
6e3b29db | 1213 | static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data) |
cd149eff | 1214 | { |
6e3b29db | 1215 | struct pci_dev *pdev = data; |
cd149eff | 1216 | |
6e3b29db AS |
1217 | return lpc_ich_set_writeable(pdev->bus, pdev->devfn); |
1218 | } | |
cd149eff | 1219 | |
6e3b29db AS |
1220 | static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data) |
1221 | { | |
1222 | struct pci_dev *pdev = data; | |
1223 | ||
1224 | return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2)); | |
cd149eff MW |
1225 | } |
1226 | ||
ff00d7a3 MW |
1227 | static int lpc_ich_init_spi(struct pci_dev *dev) |
1228 | { | |
1229 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); | |
1230 | struct resource *res = &intel_spi_res[0]; | |
1231 | struct intel_spi_boardinfo *info; | |
cd149eff | 1232 | u32 spi_base, rcba; |
55979319 | 1233 | int ret; |
ff00d7a3 MW |
1234 | |
1235 | info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); | |
1236 | if (!info) | |
1237 | return -ENOMEM; | |
1238 | ||
1239 | info->type = lpc_chipset_info[priv->chipset].spi_type; | |
1240 | ||
1241 | switch (info->type) { | |
1242 | case INTEL_SPI_BYT: | |
1243 | pci_read_config_dword(dev, SPIBASE_BYT, &spi_base); | |
1244 | if (spi_base & SPIBASE_BYT_EN) { | |
1245 | res->start = spi_base & ~(SPIBASE_BYT_SZ - 1); | |
1246 | res->end = res->start + SPIBASE_BYT_SZ - 1; | |
cd149eff MW |
1247 | |
1248 | info->set_writeable = lpc_ich_byt_set_writeable; | |
ff00d7a3 MW |
1249 | } |
1250 | break; | |
1251 | ||
1252 | case INTEL_SPI_LPT: | |
1253 | pci_read_config_dword(dev, RCBABASE, &rcba); | |
1254 | if (rcba & 1) { | |
1255 | spi_base = round_down(rcba, SPIBASE_LPT_SZ); | |
1256 | res->start = spi_base + SPIBASE_LPT; | |
1257 | res->end = res->start + SPIBASE_LPT_SZ - 1; | |
1258 | ||
cd149eff MW |
1259 | info->set_writeable = lpc_ich_lpt_set_writeable; |
1260 | info->data = dev; | |
ff00d7a3 MW |
1261 | } |
1262 | break; | |
1263 | ||
55979319 | 1264 | case INTEL_SPI_BXT: |
87eb832a MW |
1265 | /* |
1266 | * The P2SB is hidden by BIOS and we need to unhide it in | |
1267 | * order to read BAR of the SPI flash device. Once that is | |
1268 | * done we hide it again. | |
1269 | */ | |
55979319 AS |
1270 | ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res); |
1271 | if (ret) | |
1272 | return ret; | |
87eb832a | 1273 | |
55979319 AS |
1274 | info->set_writeable = lpc_ich_bxt_set_writeable; |
1275 | info->data = dev; | |
87eb832a | 1276 | break; |
87eb832a | 1277 | |
ff00d7a3 MW |
1278 | default: |
1279 | return -EINVAL; | |
1280 | } | |
1281 | ||
1282 | if (!res->start) | |
1283 | return -ENODEV; | |
1284 | ||
1285 | lpc_ich_spi_cell.platform_data = info; | |
1286 | lpc_ich_spi_cell.pdata_size = sizeof(*info); | |
1287 | ||
1288 | return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE, | |
1289 | &lpc_ich_spi_cell, 1, NULL, 0, NULL); | |
1290 | } | |
1291 | ||
f791be49 | 1292 | static int lpc_ich_probe(struct pci_dev *dev, |
4630b130 AS |
1293 | const struct pci_device_id *id) |
1294 | { | |
01560f6b | 1295 | struct lpc_ich_priv *priv; |
4630b130 AS |
1296 | int ret; |
1297 | bool cell_added = false; | |
1298 | ||
ff7109fa AS |
1299 | priv = devm_kzalloc(&dev->dev, |
1300 | sizeof(struct lpc_ich_priv), GFP_KERNEL); | |
01560f6b AS |
1301 | if (!priv) |
1302 | return -ENOMEM; | |
1303 | ||
1304 | priv->chipset = id->driver_data; | |
01560f6b | 1305 | |
eb71d4de PT |
1306 | priv->actrl_pbase_save = -1; |
1307 | priv->abase_save = -1; | |
1308 | ||
429b941a | 1309 | priv->abase = ACPIBASE; |
eb71d4de | 1310 | priv->actrl_pbase = ACPICTRL_PMCBASE; |
429b941a PT |
1311 | |
1312 | priv->gctrl_save = -1; | |
01560f6b | 1313 | if (priv->chipset <= LPC_ICH5) { |
429b941a PT |
1314 | priv->gbase = GPIOBASE_ICH0; |
1315 | priv->gctrl = GPIOCTRL_ICH0; | |
01560f6b | 1316 | } else { |
429b941a PT |
1317 | priv->gbase = GPIOBASE_ICH6; |
1318 | priv->gctrl = GPIOCTRL_ICH6; | |
01560f6b AS |
1319 | } |
1320 | ||
1321 | pci_set_drvdata(dev, priv); | |
1322 | ||
f0776b8c PT |
1323 | if (lpc_chipset_info[priv->chipset].iTCO_version) { |
1324 | ret = lpc_ich_init_wdt(dev); | |
1325 | if (!ret) | |
1326 | cell_added = true; | |
1327 | } | |
887c8ec7 | 1328 | |
f0776b8c PT |
1329 | if (lpc_chipset_info[priv->chipset].gpio_version) { |
1330 | ret = lpc_ich_init_gpio(dev); | |
1331 | if (!ret) | |
1332 | cell_added = true; | |
1333 | } | |
4630b130 | 1334 | |
7064d7d8 TJN |
1335 | if (priv->chipset == LPC_APL) { |
1336 | ret = lpc_ich_init_pinctrl(dev); | |
1337 | if (!ret) | |
1338 | cell_added = true; | |
1339 | } | |
1340 | ||
ff00d7a3 MW |
1341 | if (lpc_chipset_info[priv->chipset].spi_type) { |
1342 | ret = lpc_ich_init_spi(dev); | |
1343 | if (!ret) | |
1344 | cell_added = true; | |
1345 | } | |
1346 | ||
4630b130 AS |
1347 | /* |
1348 | * We only care if at least one or none of the cells registered | |
1349 | * successfully. | |
1350 | */ | |
1351 | if (!cell_added) { | |
0c418844 | 1352 | dev_warn(&dev->dev, "No MFD cells added\n"); |
4630b130 AS |
1353 | lpc_ich_restore_config_space(dev); |
1354 | return -ENODEV; | |
1355 | } | |
1356 | ||
1357 | return 0; | |
1358 | } | |
1359 | ||
4740f73f | 1360 | static void lpc_ich_remove(struct pci_dev *dev) |
4630b130 AS |
1361 | { |
1362 | mfd_remove_devices(&dev->dev); | |
1363 | lpc_ich_restore_config_space(dev); | |
1364 | } | |
1365 | ||
1366 | static struct pci_driver lpc_ich_driver = { | |
1367 | .name = "lpc_ich", | |
1368 | .id_table = lpc_ich_ids, | |
1369 | .probe = lpc_ich_probe, | |
84449216 | 1370 | .remove = lpc_ich_remove, |
4630b130 AS |
1371 | }; |
1372 | ||
b4d0fe9c | 1373 | module_pci_driver(lpc_ich_driver); |
4630b130 AS |
1374 | |
1375 | MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); | |
1376 | MODULE_DESCRIPTION("LPC interface for Intel ICH"); | |
1377 | MODULE_LICENSE("GPL"); |