[linux-2.6-block.git] / drivers / mfd / intel_soc_pmic_bxtwc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MFD core driver for Intel Broxton Whiskey Cove PMIC
 *
 * Copyright (C) 2015 Intel Corporation. All rights reserved.
 */

#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/mfd/intel_soc_pmic_bxtwc.h>
#include <linux/module.h>

#include <asm/intel_pmc_ipc.h>

/* PMIC device registers */
#define REG_ADDR_MASK		0xFF00
#define REG_ADDR_SHIFT		8
#define REG_OFFSET_MASK		0xFF

/* Interrupt Status Registers */
#define BXTWC_IRQLVL1		0x4E02

#define BXTWC_PWRBTNIRQ		0x4E03
#define BXTWC_THRM0IRQ		0x4E04
#define BXTWC_THRM1IRQ		0x4E05
#define BXTWC_THRM2IRQ		0x4E06
#define BXTWC_BCUIRQ		0x4E07
#define BXTWC_ADCIRQ		0x4E08
#define BXTWC_CHGR0IRQ		0x4E09
#define BXTWC_CHGR1IRQ		0x4E0A
#define BXTWC_GPIOIRQ0		0x4E0B
#define BXTWC_GPIOIRQ1		0x4E0C
#define BXTWC_CRITIRQ		0x4E0D
#define BXTWC_TMUIRQ		0x4FB6

/* Interrupt MASK Registers */
#define BXTWC_MIRQLVL1		0x4E0E
#define BXTWC_MIRQLVL1_MCHGR	BIT(5)

#define BXTWC_MPWRBTNIRQ	0x4E0F
#define BXTWC_MTHRM0IRQ		0x4E12
#define BXTWC_MTHRM1IRQ		0x4E13
#define BXTWC_MTHRM2IRQ		0x4E14
#define BXTWC_MBCUIRQ		0x4E15
#define BXTWC_MADCIRQ		0x4E16
#define BXTWC_MCHGR0IRQ		0x4E17
#define BXTWC_MCHGR1IRQ		0x4E18
#define BXTWC_MGPIO0IRQ		0x4E19
#define BXTWC_MGPIO1IRQ		0x4E1A
#define BXTWC_MCRITIRQ		0x4E1B
#define BXTWC_MTMUIRQ		0x4FB7

/* Whiskey Cove PMIC share same ACPI ID between different platforms */
#define BROXTON_PMIC_WC_HRV	4

enum bxtwc_irqs {
	BXTWC_PWRBTN_LVL1_IRQ = 0,
	BXTWC_TMU_LVL1_IRQ,
	BXTWC_THRM_LVL1_IRQ,
	BXTWC_BCU_LVL1_IRQ,
	BXTWC_ADC_LVL1_IRQ,
	BXTWC_CHGR_LVL1_IRQ,
	BXTWC_GPIO_LVL1_IRQ,
	BXTWC_CRIT_LVL1_IRQ,
};

enum bxtwc_irqs_pwrbtn {
	BXTWC_PWRBTN_IRQ = 0,
	BXTWC_UIBTN_IRQ,
};

enum bxtwc_irqs_bcu {
	BXTWC_BCU_IRQ = 0,
};

enum bxtwc_irqs_adc {
	BXTWC_ADC_IRQ = 0,
};

enum bxtwc_irqs_chgr {
	BXTWC_USBC_IRQ = 0,
	BXTWC_CHGR0_IRQ,
	BXTWC_CHGR1_IRQ,
};

enum bxtwc_irqs_tmu {
	BXTWC_TMU_IRQ = 0,
};

enum bxtwc_irqs_crit {
	BXTWC_CRIT_IRQ = 0,
};

static const struct regmap_irq bxtwc_regmap_irqs[] = {
	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
	REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
	REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
	REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
	REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
	REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
	REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
};

static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, 0x01),
};

static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
};

static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
};

static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, 0x20),
	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
};

static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
};

static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
	.name = "bxtwc_irq_chip",
	.status_base = BXTWC_IRQLVL1,
	.mask_base = BXTWC_MIRQLVL1,
	.irqs = bxtwc_regmap_irqs,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
	.num_regs = 1,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
	.name = "bxtwc_irq_chip_pwrbtn",
	.status_base = BXTWC_PWRBTNIRQ,
	.mask_base = BXTWC_MPWRBTNIRQ,
	.irqs = bxtwc_regmap_irqs_pwrbtn,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),
	.num_regs = 1,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
	.name = "bxtwc_irq_chip_tmu",
	.status_base = BXTWC_TMUIRQ,
	.mask_base = BXTWC_MTMUIRQ,
	.irqs = bxtwc_regmap_irqs_tmu,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
	.num_regs = 1,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
	.name = "bxtwc_irq_chip_bcu",
	.status_base = BXTWC_BCUIRQ,
	.mask_base = BXTWC_MBCUIRQ,
	.irqs = bxtwc_regmap_irqs_bcu,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
	.num_regs = 1,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
	.name = "bxtwc_irq_chip_adc",
	.status_base = BXTWC_ADCIRQ,
	.mask_base = BXTWC_MADCIRQ,
	.irqs = bxtwc_regmap_irqs_adc,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
	.num_regs = 1,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
	.name = "bxtwc_irq_chip_chgr",
	.status_base = BXTWC_CHGR0IRQ,
	.mask_base = BXTWC_MCHGR0IRQ,
	.irqs = bxtwc_regmap_irqs_chgr,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
	.num_regs = 2,
};

static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
	.name = "bxtwc_irq_chip_crit",
	.status_base = BXTWC_CRITIRQ,
	.mask_base = BXTWC_MCRITIRQ,
	.irqs = bxtwc_regmap_irqs_crit,
	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
	.num_regs = 1,
};

static struct resource gpio_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
};

static struct resource adc_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
};

static struct resource usbc_resources[] = {
	DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
};

static struct resource charger_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
};

static struct resource thermal_resources[] = {
	DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
};

static struct resource bcu_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
};

static struct resource tmu_resources[] = {
	DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
};

static struct mfd_cell bxt_wc_dev[] = {
	{
		.name = "bxt_wcove_gpadc",
		.num_resources = ARRAY_SIZE(adc_resources),
		.resources = adc_resources,
	},
	{
		.name = "bxt_wcove_thermal",
		.num_resources = ARRAY_SIZE(thermal_resources),
		.resources = thermal_resources,
	},
	{
		.name = "bxt_wcove_usbc",
		.num_resources = ARRAY_SIZE(usbc_resources),
		.resources = usbc_resources,
	},
	{
		.name = "bxt_wcove_ext_charger",
		.num_resources = ARRAY_SIZE(charger_resources),
		.resources = charger_resources,
	},
	{
		.name = "bxt_wcove_bcu",
		.num_resources = ARRAY_SIZE(bcu_resources),
		.resources = bcu_resources,
	},
	{
		.name = "bxt_wcove_tmu",
		.num_resources = ARRAY_SIZE(tmu_resources),
		.resources = tmu_resources,
	},

	{
		.name = "bxt_wcove_gpio",
		.num_resources = ARRAY_SIZE(gpio_resources),
		.resources = gpio_resources,
	},
	{
		.name = "bxt_wcove_region",
	},
};

static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
				    unsigned int *val)
{
	int ret;
	int i2c_addr;
	u8 ipc_in[2];
	u8 ipc_out[4];
	struct intel_soc_pmic *pmic = context;

	if (!pmic)
		return -EINVAL;

	if (reg & REG_ADDR_MASK)
		i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	else
		i2c_addr = BXTWC_DEVICE1_ADDR;

	reg &= REG_OFFSET_MASK;

	ipc_in[0] = reg;
	ipc_in[1] = i2c_addr;
	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
			PMC_IPC_PMIC_ACCESS_READ,
			ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
	if (ret) {
		dev_err(pmic->dev, "Failed to read from PMIC\n");
		return ret;
	}
	*val = ipc_out[0];

	return 0;
}

static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
				       unsigned int val)
{
	int ret;
	int i2c_addr;
	u8 ipc_in[3];
	struct intel_soc_pmic *pmic = context;

	if (!pmic)
		return -EINVAL;

	if (reg & REG_ADDR_MASK)
		i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
	else
		i2c_addr = BXTWC_DEVICE1_ADDR;

	reg &= REG_OFFSET_MASK;

	ipc_in[0] = reg;
	ipc_in[1] = i2c_addr;
	ipc_in[2] = val;
	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
			PMC_IPC_PMIC_ACCESS_WRITE,
			ipc_in, sizeof(ipc_in), NULL, 0);
	if (ret) {
		dev_err(pmic->dev, "Failed to write to PMIC\n");
		return ret;
	}

	return 0;
}

/* sysfs interfaces to r/w PMIC registers, required by initial script */
static unsigned long bxtwc_reg_addr;
static ssize_t bxtwc_reg_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
}

static ssize_t bxtwc_reg_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
		dev_err(dev, "Invalid register address\n");
		return -EINVAL;
	}
	return (ssize_t)count;
}

static ssize_t bxtwc_val_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	int ret;
	unsigned int val;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
	if (ret < 0) {
		dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
		return -EIO;
	}

	return sprintf(buf, "0x%02x\n", val);
}

static ssize_t bxtwc_val_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	int ret;
	unsigned int val;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	ret = kstrtouint(buf, 0, &val);
	if (ret)
		return ret;

	ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
	if (ret) {
		dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
			val, bxtwc_reg_addr);
		return -EIO;
	}
	return count;
}

static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store);
static struct attribute *bxtwc_attrs[] = {
	&dev_attr_addr.attr,
	&dev_attr_val.attr,
	NULL
};

static const struct attribute_group bxtwc_group = {
	.attrs = bxtwc_attrs,
};

static const struct regmap_config bxtwc_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.reg_write = regmap_ipc_byte_reg_write,
	.reg_read = regmap_ipc_byte_reg_read,
};

static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
				struct regmap_irq_chip_data *pdata,
				int pirq, int irq_flags,
				const struct regmap_irq_chip *chip,
				struct regmap_irq_chip_data **data)
{
	int irq;

	irq = regmap_irq_get_virq(pdata, pirq);
	if (irq < 0) {
		dev_err(pmic->dev,
			"Failed to get parent vIRQ(%d) for chip %s, ret:%d\n",
			pirq, chip->name, irq);
		return irq;
	}

	return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
					0, chip, data);
}

static int bxtwc_probe(struct platform_device *pdev)
{
	int ret;
	acpi_handle handle;
	acpi_status status;
	unsigned long long hrv;
	struct intel_soc_pmic *pmic;

	handle = ACPI_HANDLE(&pdev->dev);
	status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
	if (ACPI_FAILURE(status)) {
		dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
		return -ENODEV;
	}
	if (hrv != BROXTON_PMIC_WC_HRV) {
		dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
			hrv);
		return -ENODEV;
	}

	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	if (!pmic)
		return -ENOMEM;

	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
		dev_err(&pdev->dev, "Invalid IRQ\n");
		return ret;
	}
	pmic->irq = ret;

	dev_set_drvdata(&pdev->dev, pmic);
	pmic->dev = &pdev->dev;

	pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
					&bxtwc_regmap_config);
	if (IS_ERR(pmic->regmap)) {
		ret = PTR_ERR(pmic->regmap);
		dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
		return ret;
	}

	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
				       IRQF_ONESHOT | IRQF_SHARED,
				       0, &bxtwc_regmap_irq_chip,
				       &pmic->irq_chip_data);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add IRQ chip\n");
		return ret;
	}

	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
					 BXTWC_PWRBTN_LVL1_IRQ,
					 IRQF_ONESHOT,
					 &bxtwc_regmap_irq_chip_pwrbtn,
					 &pmic->irq_chip_data_pwrbtn);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add PWRBTN IRQ chip\n");
		return ret;
	}

	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
					 BXTWC_TMU_LVL1_IRQ,
					 IRQF_ONESHOT,
					 &bxtwc_regmap_irq_chip_tmu,
					 &pmic->irq_chip_data_tmu);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
		return ret;
	}

	/* Add chained IRQ handler for BCU IRQs */
	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
					 BXTWC_BCU_LVL1_IRQ,
					 IRQF_ONESHOT,
					 &bxtwc_regmap_irq_chip_bcu,
					 &pmic->irq_chip_data_bcu);


	if (ret) {
		dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
		return ret;
	}

	/* Add chained IRQ handler for ADC IRQs */
	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
					 BXTWC_ADC_LVL1_IRQ,
					 IRQF_ONESHOT,
					 &bxtwc_regmap_irq_chip_adc,
					 &pmic->irq_chip_data_adc);


	if (ret) {
		dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
		return ret;
	}

	/* Add chained IRQ handler for CHGR IRQs */
	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
					 BXTWC_CHGR_LVL1_IRQ,
					 IRQF_ONESHOT,
					 &bxtwc_regmap_irq_chip_chgr,
					 &pmic->irq_chip_data_chgr);


	if (ret) {
		dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
		return ret;
	}

	/* Add chained IRQ handler for CRIT IRQs */
	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
					 BXTWC_CRIT_LVL1_IRQ,
					 IRQF_ONESHOT,
					 &bxtwc_regmap_irq_chip_crit,
					 &pmic->irq_chip_data_crit);


	if (ret) {
		dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n");
		return ret;
	}

	ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
				   ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add devices\n");
		return ret;
	}

	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
	if (ret) {
		dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
		return ret;
	}

	/*
	 * There is known hw bug. Upon reset BIT 5 of register
	 * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
	 * later it's set to 1(masked) automatically by hardware. So we
	 * have the software workaround here to unmaksed it in order to let
	 * charger interrutp work.
	 */
	regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
				BXTWC_MIRQLVL1_MCHGR, 0);

	return 0;
}

static int bxtwc_remove(struct platform_device *pdev)
{
	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);

	return 0;
}

static void bxtwc_shutdown(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);

	disable_irq(pmic->irq);
}

#ifdef CONFIG_PM_SLEEP
static int bxtwc_suspend(struct device *dev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	disable_irq(pmic->irq);

	return 0;
}

static int bxtwc_resume(struct device *dev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	enable_irq(pmic->irq);
	return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);

static const struct acpi_device_id bxtwc_acpi_ids[] = {
	{ "INT34D3", },
	{ }
};
MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);

static struct platform_driver bxtwc_driver = {
	.probe = bxtwc_probe,
	.remove	= bxtwc_remove,
	.shutdown = bxtwc_shutdown,
	.driver	= {
		.name	= "BXTWC PMIC",
		.pm     = &bxtwc_pm_ops,
		.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
	},
};

module_platform_driver(bxtwc_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");
Commit	Line	Data
26c7e05a	1	// SPDX-License-Identifier: GPL-2.0
39d047c0 QZ	2	/*
	3	* MFD core driver for Intel Broxton Whiskey Cove PMIC
	4	*
	5	* Copyright (C) 2015 Intel Corporation. All rights reserved.
39d047c0 QZ	6	*/
39d047c0 QZ	7
39d047c0	8	#include <linux/acpi.h>
39d047c0	9	#include <linux/delay.h>
51eeee8e	10	#include <linux/err.h>
39d047c0 QZ	11	#include <linux/interrupt.h>
	12	#include <linux/kernel.h>
	13	#include <linux/mfd/core.h>
f1e34ad8	14	#include <linux/mfd/intel_soc_pmic.h>
0c227c51	15	#include <linux/mfd/intel_soc_pmic_bxtwc.h>
51eeee8e AS	16	#include <linux/module.h>
51eeee8e AS	17
39d047c0 QZ	18	#include <asm/intel_pmc_ipc.h>
	19
	20	/* PMIC device registers */
	21	#define REG_ADDR_MASK 0xFF00
	22	#define REG_ADDR_SHIFT 8
	23	#define REG_OFFSET_MASK 0xFF
	24
	25	/* Interrupt Status Registers */
	26	#define BXTWC_IRQLVL1 0x4E02
39d047c0	27
9f8ddee1	28	#define BXTWC_PWRBTNIRQ 0x4E03
39d047c0 QZ	29	#define BXTWC_THRM0IRQ 0x4E04
	30	#define BXTWC_THRM1IRQ 0x4E05
	31	#define BXTWC_THRM2IRQ 0x4E06
	32	#define BXTWC_BCUIRQ 0x4E07
	33	#define BXTWC_ADCIRQ 0x4E08
	34	#define BXTWC_CHGR0IRQ 0x4E09
	35	#define BXTWC_CHGR1IRQ 0x4E0A
	36	#define BXTWC_GPIOIRQ0 0x4E0B
	37	#define BXTWC_GPIOIRQ1 0x4E0C
	38	#define BXTWC_CRITIRQ 0x4E0D
957ae509	39	#define BXTWC_TMUIRQ 0x4FB6
39d047c0 QZ	40
	41	/* Interrupt MASK Registers */
	42	#define BXTWC_MIRQLVL1 0x4E0E
9c6235c8 BG	43	#define BXTWC_MIRQLVL1_MCHGR BIT(5)
9c6235c8 BG	44
9f8ddee1	45	#define BXTWC_MPWRBTNIRQ 0x4E0F
39d047c0 QZ	46	#define BXTWC_MTHRM0IRQ 0x4E12
	47	#define BXTWC_MTHRM1IRQ 0x4E13
	48	#define BXTWC_MTHRM2IRQ 0x4E14
	49	#define BXTWC_MBCUIRQ 0x4E15
	50	#define BXTWC_MADCIRQ 0x4E16
	51	#define BXTWC_MCHGR0IRQ 0x4E17
	52	#define BXTWC_MCHGR1IRQ 0x4E18
	53	#define BXTWC_MGPIO0IRQ 0x4E19
	54	#define BXTWC_MGPIO1IRQ 0x4E1A
	55	#define BXTWC_MCRITIRQ 0x4E1B
957ae509	56	#define BXTWC_MTMUIRQ 0x4FB7
39d047c0 QZ	57
	58	/* Whiskey Cove PMIC share same ACPI ID between different platforms */
	59	#define BROXTON_PMIC_WC_HRV 4
	60
39d047c0	61	enum bxtwc_irqs {
39d047c0 QZ	62	BXTWC_PWRBTN_LVL1_IRQ = 0,
	63	BXTWC_TMU_LVL1_IRQ,
	64	BXTWC_THRM_LVL1_IRQ,
	65	BXTWC_BCU_LVL1_IRQ,
	66	BXTWC_ADC_LVL1_IRQ,
	67	BXTWC_CHGR_LVL1_IRQ,
	68	BXTWC_GPIO_LVL1_IRQ,
	69	BXTWC_CRIT_LVL1_IRQ,
9f8ddee1	70	};
39d047c0	71
9f8ddee1 AS	72	enum bxtwc_irqs_pwrbtn {
	73	BXTWC_PWRBTN_IRQ = 0,
	74	BXTWC_UIBTN_IRQ,
39d047c0 QZ	75	};
39d047c0 QZ	76
57129044	77	enum bxtwc_irqs_bcu {
c4949630	78	BXTWC_BCU_IRQ = 0,
57129044 KS	79	};
	80
	81	enum bxtwc_irqs_adc {
	82	BXTWC_ADC_IRQ = 0,
	83	};
	84
	85	enum bxtwc_irqs_chgr {
	86	BXTWC_USBC_IRQ = 0,
39d047c0 QZ	87	BXTWC_CHGR0_IRQ,
39d047c0 QZ	88	BXTWC_CHGR1_IRQ,
4533d855 KS	89	};
	90
	91	enum bxtwc_irqs_tmu {
	92	BXTWC_TMU_IRQ = 0,
39d047c0 QZ	93	};
39d047c0 QZ	94
57129044 KS	95	enum bxtwc_irqs_crit {
	96	BXTWC_CRIT_IRQ = 0,
	97	};
	98
39d047c0 QZ	99	static const struct regmap_irq bxtwc_regmap_irqs[] = {
	100	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
	101	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
	102	REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
	103	REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
	104	REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
	105	REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
	106	REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
	107	REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
9f8ddee1 AS	108	};
	109
	110	static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
	111	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, 0x01),
39d047c0 QZ	112	};
39d047c0 QZ	113
57129044	114	static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
c4949630	115	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
57129044 KS	116	};
	117
	118	static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
	119	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
	120	};
	121
	122	static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
9f8ddee1	123	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, 0x20),
57129044 KS	124	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
57129044 KS	125	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
39d047c0 QZ	126	};
39d047c0 QZ	127
957ae509 NB	128	static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
	129	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
	130	};
	131
57129044 KS	132	static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
	133	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
	134	};
	135
39d047c0 QZ	136	static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
	137	.name = "bxtwc_irq_chip",
	138	.status_base = BXTWC_IRQLVL1,
	139	.mask_base = BXTWC_MIRQLVL1,
	140	.irqs = bxtwc_regmap_irqs,
	141	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
9f8ddee1 AS	142	.num_regs = 1,
	143	};
	144
	145	static struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
	146	.name = "bxtwc_irq_chip_pwrbtn",
	147	.status_base = BXTWC_PWRBTNIRQ,
	148	.mask_base = BXTWC_MPWRBTNIRQ,
	149	.irqs = bxtwc_regmap_irqs_pwrbtn,
	150	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),
	151	.num_regs = 1,
39d047c0 QZ	152	};
39d047c0 QZ	153
957ae509 NB	154	static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
	155	.name = "bxtwc_irq_chip_tmu",
	156	.status_base = BXTWC_TMUIRQ,
	157	.mask_base = BXTWC_MTMUIRQ,
	158	.irqs = bxtwc_regmap_irqs_tmu,
	159	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
	160	.num_regs = 1,
	161	};
	162
57129044 KS	163	static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
	164	.name = "bxtwc_irq_chip_bcu",
	165	.status_base = BXTWC_BCUIRQ,
	166	.mask_base = BXTWC_MBCUIRQ,
	167	.irqs = bxtwc_regmap_irqs_bcu,
	168	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
	169	.num_regs = 1,
	170	};
	171
	172	static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
	173	.name = "bxtwc_irq_chip_adc",
	174	.status_base = BXTWC_ADCIRQ,
	175	.mask_base = BXTWC_MADCIRQ,
	176	.irqs = bxtwc_regmap_irqs_adc,
	177	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
	178	.num_regs = 1,
	179	};
	180
	181	static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
	182	.name = "bxtwc_irq_chip_chgr",
	183	.status_base = BXTWC_CHGR0IRQ,
	184	.mask_base = BXTWC_MCHGR0IRQ,
	185	.irqs = bxtwc_regmap_irqs_chgr,
	186	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
	187	.num_regs = 2,
	188	};
	189
	190	static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
	191	.name = "bxtwc_irq_chip_crit",
	192	.status_base = BXTWC_CRITIRQ,
	193	.mask_base = BXTWC_MCRITIRQ,
	194	.irqs = bxtwc_regmap_irqs_crit,
	195	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
	196	.num_regs = 1,
	197	};
	198
39d047c0	199	static struct resource gpio_resources[] = {
a1d28c59	200	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
39d047c0 QZ	201	};
	202
	203	static struct resource adc_resources[] = {
	204	DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
	205	};
	206
9c6235c8	207	static struct resource usbc_resources[] = {
96007020	208	DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
9c6235c8 BG	209	};
9c6235c8 BG	210
39d047c0 QZ	211	static struct resource charger_resources[] = {
	212	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
	213	DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
	214	};
	215
	216	static struct resource thermal_resources[] = {
c4949630	217	DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
39d047c0 QZ	218	};
	219
	220	static struct resource bcu_resources[] = {
	221	DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
	222	};
	223
957ae509 NB	224	static struct resource tmu_resources[] = {
	225	DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
	226	};
	227
39d047c0 QZ	228	static struct mfd_cell bxt_wc_dev[] = {
	229	{
	230	.name = "bxt_wcove_gpadc",
	231	.num_resources = ARRAY_SIZE(adc_resources),
	232	.resources = adc_resources,
	233	},
	234	{
	235	.name = "bxt_wcove_thermal",
	236	.num_resources = ARRAY_SIZE(thermal_resources),
	237	.resources = thermal_resources,
	238	},
9c6235c8 BG	239	{
	240	.name = "bxt_wcove_usbc",
	241	.num_resources = ARRAY_SIZE(usbc_resources),
	242	.resources = usbc_resources,
	243	},
39d047c0 QZ	244	{
	245	.name = "bxt_wcove_ext_charger",
	246	.num_resources = ARRAY_SIZE(charger_resources),
	247	.resources = charger_resources,
	248	},
	249	{
	250	.name = "bxt_wcove_bcu",
	251	.num_resources = ARRAY_SIZE(bcu_resources),
	252	.resources = bcu_resources,
	253	},
957ae509 NB	254	{
	255	.name = "bxt_wcove_tmu",
	256	.num_resources = ARRAY_SIZE(tmu_resources),
	257	.resources = tmu_resources,
	258	},
	259
39d047c0 QZ	260	{
	261	.name = "bxt_wcove_gpio",
	262	.num_resources = ARRAY_SIZE(gpio_resources),
	263	.resources = gpio_resources,
	264	},
	265	{
	266	.name = "bxt_wcove_region",
	267	},
	268	};
	269
	270	static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
	271	unsigned int *val)
	272	{
	273	int ret;
	274	int i2c_addr;
	275	u8 ipc_in[2];
	276	u8 ipc_out[4];
	277	struct intel_soc_pmic *pmic = context;
	278
b4ccc4d2 KS	279	if (!pmic)
	280	return -EINVAL;
	281
39d047c0 QZ	282	if (reg & REG_ADDR_MASK)
39d047c0 QZ	283	i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
b4ccc4d2	284	else
39d047c0	285	i2c_addr = BXTWC_DEVICE1_ADDR;
b4ccc4d2	286
39d047c0 QZ	287	reg &= REG_OFFSET_MASK;
	288
	289	ipc_in[0] = reg;
	290	ipc_in[1] = i2c_addr;
	291	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
	292	PMC_IPC_PMIC_ACCESS_READ,
	293	ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
	294	if (ret) {
	295	dev_err(pmic->dev, "Failed to read from PMIC\n");
	296	return ret;
	297	}
	298	*val = ipc_out[0];
	299
	300	return 0;
	301	}
	302
	303	static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
	304	unsigned int val)
	305	{
	306	int ret;
	307	int i2c_addr;
	308	u8 ipc_in[3];
	309	struct intel_soc_pmic *pmic = context;
	310
b4ccc4d2 KS	311	if (!pmic)
	312	return -EINVAL;
	313
39d047c0 QZ	314	if (reg & REG_ADDR_MASK)
39d047c0 QZ	315	i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
b4ccc4d2	316	else
39d047c0	317	i2c_addr = BXTWC_DEVICE1_ADDR;
b4ccc4d2	318
39d047c0 QZ	319	reg &= REG_OFFSET_MASK;
	320
	321	ipc_in[0] = reg;
	322	ipc_in[1] = i2c_addr;
	323	ipc_in[2] = val;
	324	ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
	325	PMC_IPC_PMIC_ACCESS_WRITE,
	326	ipc_in, sizeof(ipc_in), NULL, 0);
	327	if (ret) {
	328	dev_err(pmic->dev, "Failed to write to PMIC\n");
	329	return ret;
	330	}
	331
	332	return 0;
	333	}
	334
	335	/* sysfs interfaces to r/w PMIC registers, required by initial script */
	336	static unsigned long bxtwc_reg_addr;
	337	static ssize_t bxtwc_reg_show(struct device *dev,
	338	struct device_attribute attr, char buf)
	339	{
	340	return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
	341	}
	342
	343	static ssize_t bxtwc_reg_store(struct device *dev,
	344	struct device_attribute attr, const char buf, size_t count)
	345	{
	346	if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
	347	dev_err(dev, "Invalid register address\n");
	348	return -EINVAL;
	349	}
	350	return (ssize_t)count;
	351	}
	352
	353	static ssize_t bxtwc_val_show(struct device *dev,
	354	struct device_attribute attr, char buf)
	355	{
	356	int ret;
	357	unsigned int val;
	358	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	359
	360	ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
	361	if (ret < 0) {
	362	dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
	363	return -EIO;
	364	}
	365
	366	return sprintf(buf, "0x%02x\n", val);
	367	}
	368
	369	static ssize_t bxtwc_val_store(struct device *dev,
	370	struct device_attribute attr, const char buf, size_t count)
	371	{
	372	int ret;
	373	unsigned int val;
	374	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	375
f3a654c5 DC	376	ret = kstrtouint(buf, 0, &val);
	377	if (ret)
	378	return ret;
39d047c0 QZ	379
	380	ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
	381	if (ret) {
	382	dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
	383	val, bxtwc_reg_addr);
	384	return -EIO;
	385	}
	386	return count;
	387	}
	388
	389	static DEVICE_ATTR(addr, S_IWUSR \| S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
	390	static DEVICE_ATTR(val, S_IWUSR \| S_IRUSR, bxtwc_val_show, bxtwc_val_store);
	391	static struct attribute *bxtwc_attrs[] = {
	392	&dev_attr_addr.attr,
	393	&dev_attr_val.attr,
	394	NULL
	395	};
	396
	397	static const struct attribute_group bxtwc_group = {
	398	.attrs = bxtwc_attrs,
	399	};
	400
	401	static const struct regmap_config bxtwc_regmap_config = {
	402	.reg_bits = 16,
	403	.val_bits = 8,
	404	.reg_write = regmap_ipc_byte_reg_write,
	405	.reg_read = regmap_ipc_byte_reg_read,
	406	};
	407
57129044 KS	408	static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
	409	struct regmap_irq_chip_data *pdata,
	410	int pirq, int irq_flags,
	411	const struct regmap_irq_chip *chip,
	412	struct regmap_irq_chip_data **data)
	413	{
	414	int irq;
	415
	416	irq = regmap_irq_get_virq(pdata, pirq);
	417	if (irq < 0) {
	418	dev_err(pmic->dev,
	419	"Failed to get parent vIRQ(%d) for chip %s, ret:%d\n",
	420	pirq, chip->name, irq);
	421	return irq;
	422	}
	423
	424	return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
	425	0, chip, data);
	426	}
	427
39d047c0 QZ	428	static int bxtwc_probe(struct platform_device *pdev)
	429	{
	430	int ret;
	431	acpi_handle handle;
	432	acpi_status status;
	433	unsigned long long hrv;
	434	struct intel_soc_pmic *pmic;
	435
	436	handle = ACPI_HANDLE(&pdev->dev);
	437	status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
	438	if (ACPI_FAILURE(status)) {
	439	dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
	440	return -ENODEV;
	441	}
	442	if (hrv != BROXTON_PMIC_WC_HRV) {
	443	dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
	444	hrv);
	445	return -ENODEV;
	446	}
	447
	448	pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
	449	if (!pmic)
	450	return -ENOMEM;
	451
	452	ret = platform_get_irq(pdev, 0);
	453	if (ret < 0) {
	454	dev_err(&pdev->dev, "Invalid IRQ\n");
	455	return ret;
	456	}
	457	pmic->irq = ret;
	458
	459	dev_set_drvdata(&pdev->dev, pmic);
	460	pmic->dev = &pdev->dev;
	461
	462	pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
	463	&bxtwc_regmap_config);
	464	if (IS_ERR(pmic->regmap)) {
	465	ret = PTR_ERR(pmic->regmap);
	466	dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
	467	return ret;
	468	}
	469
5131f072 KS	470	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
	471	IRQF_ONESHOT \| IRQF_SHARED,
	472	0, &bxtwc_regmap_irq_chip,
	473	&pmic->irq_chip_data);
39d047c0 QZ	474	if (ret) {
	475	dev_err(&pdev->dev, "Failed to add IRQ chip\n");
	476	return ret;
	477	}
	478
9f8ddee1 AS	479	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
	480	BXTWC_PWRBTN_LVL1_IRQ,
	481	IRQF_ONESHOT,
	482	&bxtwc_regmap_irq_chip_pwrbtn,
	483	&pmic->irq_chip_data_pwrbtn);
	484	if (ret) {
	485	dev_err(&pdev->dev, "Failed to add PWRBTN IRQ chip\n");
	486	return ret;
	487	}
	488
57129044 KS	489	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
	490	BXTWC_TMU_LVL1_IRQ,
	491	IRQF_ONESHOT,
	492	&bxtwc_regmap_irq_chip_tmu,
	493	&pmic->irq_chip_data_tmu);
39d047c0	494	if (ret) {
57129044	495	dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
5131f072	496	return ret;
39d047c0 QZ	497	}
39d047c0 QZ	498
57129044 KS	499	/* Add chained IRQ handler for BCU IRQs */
	500	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
	501	BXTWC_BCU_LVL1_IRQ,
	502	IRQF_ONESHOT,
	503	&bxtwc_regmap_irq_chip_bcu,
	504	&pmic->irq_chip_data_bcu);
	505
	506
957ae509	507	if (ret) {
57129044 KS	508	dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
	509	return ret;
	510	}
	511
	512	/* Add chained IRQ handler for ADC IRQs */
	513	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
	514	BXTWC_ADC_LVL1_IRQ,
	515	IRQF_ONESHOT,
	516	&bxtwc_regmap_irq_chip_adc,
	517	&pmic->irq_chip_data_adc);
	518
	519
	520	if (ret) {
	521	dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
	522	return ret;
	523	}
	524
	525	/* Add chained IRQ handler for CHGR IRQs */
	526	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
	527	BXTWC_CHGR_LVL1_IRQ,
	528	IRQF_ONESHOT,
	529	&bxtwc_regmap_irq_chip_chgr,
	530	&pmic->irq_chip_data_chgr);
	531
	532
	533	if (ret) {
	534	dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
	535	return ret;
	536	}
	537
	538	/* Add chained IRQ handler for CRIT IRQs */
	539	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
	540	BXTWC_CRIT_LVL1_IRQ,
	541	IRQF_ONESHOT,
	542	&bxtwc_regmap_irq_chip_crit,
	543	&pmic->irq_chip_data_crit);
	544
	545
	546	if (ret) {
	547	dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n");
5131f072	548	return ret;
957ae509 NB	549	}
957ae509 NB	550
5131f072 KS	551	ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
5131f072 KS	552	ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
39d047c0 QZ	553	if (ret) {
39d047c0 QZ	554	dev_err(&pdev->dev, "Failed to add devices\n");
5131f072	555	return ret;
39d047c0 QZ	556	}
	557
	558	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
	559	if (ret) {
	560	dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
5131f072	561	return ret;
39d047c0 QZ	562	}
39d047c0 QZ	563
9c6235c8 BG	564	/*
	565	* There is known hw bug. Upon reset BIT 5 of register
	566	* BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
	567	* later it's set to 1(masked) automatically by hardware. So we
	568	* have the software workaround here to unmaksed it in order to let
	569	* charger interrutp work.
	570	*/
	571	regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
	572	BXTWC_MIRQLVL1_MCHGR, 0);
	573
39d047c0	574	return 0;
39d047c0 QZ	575	}
	576
	577	static int bxtwc_remove(struct platform_device *pdev)
	578	{
39d047c0	579	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
39d047c0 QZ	580
	581	return 0;
	582	}
	583
	584	static void bxtwc_shutdown(struct platform_device *pdev)
	585	{
	586	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
	587
	588	disable_irq(pmic->irq);
	589	}
	590
	591	#ifdef CONFIG_PM_SLEEP
	592	static int bxtwc_suspend(struct device *dev)
	593	{
	594	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	595
	596	disable_irq(pmic->irq);
	597
	598	return 0;
	599	}
	600
	601	static int bxtwc_resume(struct device *dev)
	602	{
	603	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	604
	605	enable_irq(pmic->irq);
	606	return 0;
	607	}
	608	#endif
	609	static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
	610
	611	static const struct acpi_device_id bxtwc_acpi_ids[] = {
	612	{ "INT34D3", },
	613	{ }
	614	};
f57576e7	615	MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
39d047c0 QZ	616
	617	static struct platform_driver bxtwc_driver = {
	618	.probe = bxtwc_probe,
	619	.remove = bxtwc_remove,
	620	.shutdown = bxtwc_shutdown,
	621	.driver = {
	622	.name = "BXTWC PMIC",
	623	.pm = &bxtwc_pm_ops,
	624	.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
	625	},
	626	};
	627
	628	module_platform_driver(bxtwc_driver);
	629
	630	MODULE_LICENSE("GPL v2");
	631	MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");