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39d047c0 QZ |
1 | /* |
2 | * MFD core driver for Intel Broxton Whiskey Cove PMIC | |
3 | * | |
4 | * Copyright (C) 2015 Intel Corporation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/acpi.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mfd/core.h> | |
23 | #include <linux/mfd/intel_bxtwc.h> | |
24 | #include <asm/intel_pmc_ipc.h> | |
25 | ||
26 | /* PMIC device registers */ | |
27 | #define REG_ADDR_MASK 0xFF00 | |
28 | #define REG_ADDR_SHIFT 8 | |
29 | #define REG_OFFSET_MASK 0xFF | |
30 | ||
31 | /* Interrupt Status Registers */ | |
32 | #define BXTWC_IRQLVL1 0x4E02 | |
33 | #define BXTWC_PWRBTNIRQ 0x4E03 | |
34 | ||
35 | #define BXTWC_THRM0IRQ 0x4E04 | |
36 | #define BXTWC_THRM1IRQ 0x4E05 | |
37 | #define BXTWC_THRM2IRQ 0x4E06 | |
38 | #define BXTWC_BCUIRQ 0x4E07 | |
39 | #define BXTWC_ADCIRQ 0x4E08 | |
40 | #define BXTWC_CHGR0IRQ 0x4E09 | |
41 | #define BXTWC_CHGR1IRQ 0x4E0A | |
42 | #define BXTWC_GPIOIRQ0 0x4E0B | |
43 | #define BXTWC_GPIOIRQ1 0x4E0C | |
44 | #define BXTWC_CRITIRQ 0x4E0D | |
45 | ||
46 | /* Interrupt MASK Registers */ | |
47 | #define BXTWC_MIRQLVL1 0x4E0E | |
48 | #define BXTWC_MPWRTNIRQ 0x4E0F | |
49 | ||
9c6235c8 BG |
50 | #define BXTWC_MIRQLVL1_MCHGR BIT(5) |
51 | ||
39d047c0 QZ |
52 | #define BXTWC_MTHRM0IRQ 0x4E12 |
53 | #define BXTWC_MTHRM1IRQ 0x4E13 | |
54 | #define BXTWC_MTHRM2IRQ 0x4E14 | |
55 | #define BXTWC_MBCUIRQ 0x4E15 | |
56 | #define BXTWC_MADCIRQ 0x4E16 | |
57 | #define BXTWC_MCHGR0IRQ 0x4E17 | |
58 | #define BXTWC_MCHGR1IRQ 0x4E18 | |
59 | #define BXTWC_MGPIO0IRQ 0x4E19 | |
60 | #define BXTWC_MGPIO1IRQ 0x4E1A | |
61 | #define BXTWC_MCRITIRQ 0x4E1B | |
62 | ||
63 | /* Whiskey Cove PMIC share same ACPI ID between different platforms */ | |
64 | #define BROXTON_PMIC_WC_HRV 4 | |
65 | ||
66 | /* Manage in two IRQ chips since mask registers are not consecutive */ | |
67 | enum bxtwc_irqs { | |
68 | /* Level 1 */ | |
69 | BXTWC_PWRBTN_LVL1_IRQ = 0, | |
70 | BXTWC_TMU_LVL1_IRQ, | |
71 | BXTWC_THRM_LVL1_IRQ, | |
72 | BXTWC_BCU_LVL1_IRQ, | |
73 | BXTWC_ADC_LVL1_IRQ, | |
74 | BXTWC_CHGR_LVL1_IRQ, | |
75 | BXTWC_GPIO_LVL1_IRQ, | |
76 | BXTWC_CRIT_LVL1_IRQ, | |
77 | ||
78 | /* Level 2 */ | |
79 | BXTWC_PWRBTN_IRQ, | |
80 | }; | |
81 | ||
82 | enum bxtwc_irqs_level2 { | |
83 | /* Level 2 */ | |
84 | BXTWC_THRM0_IRQ = 0, | |
85 | BXTWC_THRM1_IRQ, | |
86 | BXTWC_THRM2_IRQ, | |
87 | BXTWC_BCU_IRQ, | |
88 | BXTWC_ADC_IRQ, | |
89 | BXTWC_CHGR0_IRQ, | |
90 | BXTWC_CHGR1_IRQ, | |
91 | BXTWC_GPIO0_IRQ, | |
92 | BXTWC_GPIO1_IRQ, | |
93 | BXTWC_CRIT_IRQ, | |
94 | }; | |
95 | ||
96 | static const struct regmap_irq bxtwc_regmap_irqs[] = { | |
97 | REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)), | |
98 | REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)), | |
99 | REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)), | |
100 | REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)), | |
101 | REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)), | |
102 | REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)), | |
103 | REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)), | |
104 | REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)), | |
105 | REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03), | |
106 | }; | |
107 | ||
108 | static const struct regmap_irq bxtwc_regmap_irqs_level2[] = { | |
109 | REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff), | |
110 | REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf), | |
111 | REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff), | |
112 | REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f), | |
113 | REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff), | |
9c6235c8 | 114 | REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x3f), |
39d047c0 QZ |
115 | REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f), |
116 | REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff), | |
117 | REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f), | |
118 | REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03), | |
119 | }; | |
120 | ||
121 | static struct regmap_irq_chip bxtwc_regmap_irq_chip = { | |
122 | .name = "bxtwc_irq_chip", | |
123 | .status_base = BXTWC_IRQLVL1, | |
124 | .mask_base = BXTWC_MIRQLVL1, | |
125 | .irqs = bxtwc_regmap_irqs, | |
126 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs), | |
127 | .num_regs = 2, | |
128 | }; | |
129 | ||
130 | static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = { | |
131 | .name = "bxtwc_irq_chip_level2", | |
132 | .status_base = BXTWC_THRM0IRQ, | |
133 | .mask_base = BXTWC_MTHRM0IRQ, | |
134 | .irqs = bxtwc_regmap_irqs_level2, | |
135 | .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2), | |
136 | .num_regs = 10, | |
137 | }; | |
138 | ||
139 | static struct resource gpio_resources[] = { | |
140 | DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"), | |
141 | DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"), | |
142 | }; | |
143 | ||
144 | static struct resource adc_resources[] = { | |
145 | DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"), | |
146 | }; | |
147 | ||
9c6235c8 BG |
148 | static struct resource usbc_resources[] = { |
149 | DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "USBC"), | |
150 | }; | |
151 | ||
39d047c0 QZ |
152 | static struct resource charger_resources[] = { |
153 | DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"), | |
154 | DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"), | |
155 | }; | |
156 | ||
157 | static struct resource thermal_resources[] = { | |
158 | DEFINE_RES_IRQ(BXTWC_THRM0_IRQ), | |
159 | DEFINE_RES_IRQ(BXTWC_THRM1_IRQ), | |
160 | DEFINE_RES_IRQ(BXTWC_THRM2_IRQ), | |
161 | }; | |
162 | ||
163 | static struct resource bcu_resources[] = { | |
164 | DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"), | |
165 | }; | |
166 | ||
167 | static struct mfd_cell bxt_wc_dev[] = { | |
168 | { | |
169 | .name = "bxt_wcove_gpadc", | |
170 | .num_resources = ARRAY_SIZE(adc_resources), | |
171 | .resources = adc_resources, | |
172 | }, | |
173 | { | |
174 | .name = "bxt_wcove_thermal", | |
175 | .num_resources = ARRAY_SIZE(thermal_resources), | |
176 | .resources = thermal_resources, | |
177 | }, | |
9c6235c8 BG |
178 | { |
179 | .name = "bxt_wcove_usbc", | |
180 | .num_resources = ARRAY_SIZE(usbc_resources), | |
181 | .resources = usbc_resources, | |
182 | }, | |
39d047c0 QZ |
183 | { |
184 | .name = "bxt_wcove_ext_charger", | |
185 | .num_resources = ARRAY_SIZE(charger_resources), | |
186 | .resources = charger_resources, | |
187 | }, | |
188 | { | |
189 | .name = "bxt_wcove_bcu", | |
190 | .num_resources = ARRAY_SIZE(bcu_resources), | |
191 | .resources = bcu_resources, | |
192 | }, | |
193 | { | |
194 | .name = "bxt_wcove_gpio", | |
195 | .num_resources = ARRAY_SIZE(gpio_resources), | |
196 | .resources = gpio_resources, | |
197 | }, | |
198 | { | |
199 | .name = "bxt_wcove_region", | |
200 | }, | |
201 | }; | |
202 | ||
203 | static int regmap_ipc_byte_reg_read(void *context, unsigned int reg, | |
204 | unsigned int *val) | |
205 | { | |
206 | int ret; | |
207 | int i2c_addr; | |
208 | u8 ipc_in[2]; | |
209 | u8 ipc_out[4]; | |
210 | struct intel_soc_pmic *pmic = context; | |
211 | ||
212 | if (reg & REG_ADDR_MASK) | |
213 | i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; | |
214 | else { | |
215 | i2c_addr = BXTWC_DEVICE1_ADDR; | |
216 | if (!i2c_addr) { | |
217 | dev_err(pmic->dev, "I2C address not set\n"); | |
218 | return -EINVAL; | |
219 | } | |
220 | } | |
221 | reg &= REG_OFFSET_MASK; | |
222 | ||
223 | ipc_in[0] = reg; | |
224 | ipc_in[1] = i2c_addr; | |
225 | ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS, | |
226 | PMC_IPC_PMIC_ACCESS_READ, | |
227 | ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1); | |
228 | if (ret) { | |
229 | dev_err(pmic->dev, "Failed to read from PMIC\n"); | |
230 | return ret; | |
231 | } | |
232 | *val = ipc_out[0]; | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | static int regmap_ipc_byte_reg_write(void *context, unsigned int reg, | |
238 | unsigned int val) | |
239 | { | |
240 | int ret; | |
241 | int i2c_addr; | |
242 | u8 ipc_in[3]; | |
243 | struct intel_soc_pmic *pmic = context; | |
244 | ||
245 | if (reg & REG_ADDR_MASK) | |
246 | i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; | |
247 | else { | |
248 | i2c_addr = BXTWC_DEVICE1_ADDR; | |
249 | if (!i2c_addr) { | |
250 | dev_err(pmic->dev, "I2C address not set\n"); | |
251 | return -EINVAL; | |
252 | } | |
253 | } | |
254 | reg &= REG_OFFSET_MASK; | |
255 | ||
256 | ipc_in[0] = reg; | |
257 | ipc_in[1] = i2c_addr; | |
258 | ipc_in[2] = val; | |
259 | ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS, | |
260 | PMC_IPC_PMIC_ACCESS_WRITE, | |
261 | ipc_in, sizeof(ipc_in), NULL, 0); | |
262 | if (ret) { | |
263 | dev_err(pmic->dev, "Failed to write to PMIC\n"); | |
264 | return ret; | |
265 | } | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | /* sysfs interfaces to r/w PMIC registers, required by initial script */ | |
271 | static unsigned long bxtwc_reg_addr; | |
272 | static ssize_t bxtwc_reg_show(struct device *dev, | |
273 | struct device_attribute *attr, char *buf) | |
274 | { | |
275 | return sprintf(buf, "0x%lx\n", bxtwc_reg_addr); | |
276 | } | |
277 | ||
278 | static ssize_t bxtwc_reg_store(struct device *dev, | |
279 | struct device_attribute *attr, const char *buf, size_t count) | |
280 | { | |
281 | if (kstrtoul(buf, 0, &bxtwc_reg_addr)) { | |
282 | dev_err(dev, "Invalid register address\n"); | |
283 | return -EINVAL; | |
284 | } | |
285 | return (ssize_t)count; | |
286 | } | |
287 | ||
288 | static ssize_t bxtwc_val_show(struct device *dev, | |
289 | struct device_attribute *attr, char *buf) | |
290 | { | |
291 | int ret; | |
292 | unsigned int val; | |
293 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); | |
294 | ||
295 | ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val); | |
296 | if (ret < 0) { | |
297 | dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr); | |
298 | return -EIO; | |
299 | } | |
300 | ||
301 | return sprintf(buf, "0x%02x\n", val); | |
302 | } | |
303 | ||
304 | static ssize_t bxtwc_val_store(struct device *dev, | |
305 | struct device_attribute *attr, const char *buf, size_t count) | |
306 | { | |
307 | int ret; | |
308 | unsigned int val; | |
309 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); | |
310 | ||
f3a654c5 DC |
311 | ret = kstrtouint(buf, 0, &val); |
312 | if (ret) | |
313 | return ret; | |
39d047c0 QZ |
314 | |
315 | ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val); | |
316 | if (ret) { | |
317 | dev_err(dev, "Failed to write value 0x%02x to address 0x%lx", | |
318 | val, bxtwc_reg_addr); | |
319 | return -EIO; | |
320 | } | |
321 | return count; | |
322 | } | |
323 | ||
324 | static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store); | |
325 | static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store); | |
326 | static struct attribute *bxtwc_attrs[] = { | |
327 | &dev_attr_addr.attr, | |
328 | &dev_attr_val.attr, | |
329 | NULL | |
330 | }; | |
331 | ||
332 | static const struct attribute_group bxtwc_group = { | |
333 | .attrs = bxtwc_attrs, | |
334 | }; | |
335 | ||
336 | static const struct regmap_config bxtwc_regmap_config = { | |
337 | .reg_bits = 16, | |
338 | .val_bits = 8, | |
339 | .reg_write = regmap_ipc_byte_reg_write, | |
340 | .reg_read = regmap_ipc_byte_reg_read, | |
341 | }; | |
342 | ||
343 | static int bxtwc_probe(struct platform_device *pdev) | |
344 | { | |
345 | int ret; | |
346 | acpi_handle handle; | |
347 | acpi_status status; | |
348 | unsigned long long hrv; | |
349 | struct intel_soc_pmic *pmic; | |
350 | ||
351 | handle = ACPI_HANDLE(&pdev->dev); | |
352 | status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv); | |
353 | if (ACPI_FAILURE(status)) { | |
354 | dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n"); | |
355 | return -ENODEV; | |
356 | } | |
357 | if (hrv != BROXTON_PMIC_WC_HRV) { | |
358 | dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n", | |
359 | hrv); | |
360 | return -ENODEV; | |
361 | } | |
362 | ||
363 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); | |
364 | if (!pmic) | |
365 | return -ENOMEM; | |
366 | ||
367 | ret = platform_get_irq(pdev, 0); | |
368 | if (ret < 0) { | |
369 | dev_err(&pdev->dev, "Invalid IRQ\n"); | |
370 | return ret; | |
371 | } | |
372 | pmic->irq = ret; | |
373 | ||
374 | dev_set_drvdata(&pdev->dev, pmic); | |
375 | pmic->dev = &pdev->dev; | |
376 | ||
377 | pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic, | |
378 | &bxtwc_regmap_config); | |
379 | if (IS_ERR(pmic->regmap)) { | |
380 | ret = PTR_ERR(pmic->regmap); | |
381 | dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret); | |
382 | return ret; | |
383 | } | |
384 | ||
385 | ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, | |
386 | IRQF_ONESHOT | IRQF_SHARED, | |
387 | 0, &bxtwc_regmap_irq_chip, | |
388 | &pmic->irq_chip_data); | |
389 | if (ret) { | |
390 | dev_err(&pdev->dev, "Failed to add IRQ chip\n"); | |
391 | return ret; | |
392 | } | |
393 | ||
394 | ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, | |
395 | IRQF_ONESHOT | IRQF_SHARED, | |
396 | 0, &bxtwc_regmap_irq_chip_level2, | |
397 | &pmic->irq_chip_data_level2); | |
398 | if (ret) { | |
399 | dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n"); | |
400 | goto err_irq_chip_level2; | |
401 | } | |
402 | ||
403 | ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev, | |
404 | ARRAY_SIZE(bxt_wc_dev), NULL, 0, | |
405 | NULL); | |
406 | if (ret) { | |
407 | dev_err(&pdev->dev, "Failed to add devices\n"); | |
408 | goto err_mfd; | |
409 | } | |
410 | ||
411 | ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group); | |
412 | if (ret) { | |
413 | dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret); | |
414 | goto err_sysfs; | |
415 | } | |
416 | ||
9c6235c8 BG |
417 | /* |
418 | * There is known hw bug. Upon reset BIT 5 of register | |
419 | * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However, | |
420 | * later it's set to 1(masked) automatically by hardware. So we | |
421 | * have the software workaround here to unmaksed it in order to let | |
422 | * charger interrutp work. | |
423 | */ | |
424 | regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, | |
425 | BXTWC_MIRQLVL1_MCHGR, 0); | |
426 | ||
39d047c0 QZ |
427 | return 0; |
428 | ||
429 | err_sysfs: | |
430 | mfd_remove_devices(&pdev->dev); | |
431 | err_mfd: | |
432 | regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2); | |
433 | err_irq_chip_level2: | |
434 | regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data); | |
435 | ||
436 | return ret; | |
437 | } | |
438 | ||
439 | static int bxtwc_remove(struct platform_device *pdev) | |
440 | { | |
441 | struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev); | |
442 | ||
443 | sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group); | |
444 | mfd_remove_devices(&pdev->dev); | |
445 | regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data); | |
446 | regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2); | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
451 | static void bxtwc_shutdown(struct platform_device *pdev) | |
452 | { | |
453 | struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev); | |
454 | ||
455 | disable_irq(pmic->irq); | |
456 | } | |
457 | ||
458 | #ifdef CONFIG_PM_SLEEP | |
459 | static int bxtwc_suspend(struct device *dev) | |
460 | { | |
461 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); | |
462 | ||
463 | disable_irq(pmic->irq); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
468 | static int bxtwc_resume(struct device *dev) | |
469 | { | |
470 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); | |
471 | ||
472 | enable_irq(pmic->irq); | |
473 | return 0; | |
474 | } | |
475 | #endif | |
476 | static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume); | |
477 | ||
478 | static const struct acpi_device_id bxtwc_acpi_ids[] = { | |
479 | { "INT34D3", }, | |
480 | { } | |
481 | }; | |
482 | MODULE_DEVICE_TABLE(acpi, pmic_acpi_ids); | |
483 | ||
484 | static struct platform_driver bxtwc_driver = { | |
485 | .probe = bxtwc_probe, | |
486 | .remove = bxtwc_remove, | |
487 | .shutdown = bxtwc_shutdown, | |
488 | .driver = { | |
489 | .name = "BXTWC PMIC", | |
490 | .pm = &bxtwc_pm_ops, | |
491 | .acpi_match_table = ACPI_PTR(bxtwc_acpi_ids), | |
492 | }, | |
493 | }; | |
494 | ||
495 | module_platform_driver(bxtwc_driver); | |
496 | ||
497 | MODULE_LICENSE("GPL v2"); | |
498 | MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>"); |