[linux-2.6-block.git] / drivers / mfd / intel_msic.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for Intel MSIC
 *
 * Copyright (C) 2011, Intel Corporation
 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
 */

#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_msic.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <asm/intel_scu_ipc.h>

#define MSIC_VENDOR(id)		((id >> 6) & 3)
#define MSIC_VERSION(id)	(id & 0x3f)
#define MSIC_MAJOR(id)		('A' + ((id >> 3) & 7))
#define MSIC_MINOR(id)		(id & 7)

/*
 * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
 * Since IRQ block starts from address 0x002 we need to subtract that from
 * the actual IRQ status register address.
 */
#define MSIC_IRQ_STATUS(x)	(INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
#define MSIC_IRQ_STATUS_ACCDET	MSIC_IRQ_STATUS(INTEL_MSIC_ACCDET)

/*
 * The SCU hardware has limitation of 16 bytes per read/write buffer on
 * Medfield.
 */
#define SCU_IPC_RWBUF_LIMIT	16

/**
 * struct intel_msic - an MSIC MFD instance
 * @pdev: pointer to the platform device
 * @vendor: vendor ID
 * @version: chip version
 * @irq_base: base address of the mapped MSIC SRAM interrupt tree
 */
struct intel_msic {
	struct platform_device		*pdev;
	unsigned			vendor;
	unsigned			version;
	void __iomem			*irq_base;
};

static struct resource msic_touch_resources[] = {
	DEFINE_RES_IRQ(0),
};

static struct resource msic_adc_resources[] = {
	DEFINE_RES_IRQ(0),
};

static struct resource msic_battery_resources[] = {
	DEFINE_RES_IRQ(0),
};

static struct resource msic_gpio_resources[] = {
	DEFINE_RES_IRQ(0),
};

static struct resource msic_audio_resources[] = {
	DEFINE_RES_IRQ_NAMED(0, "IRQ"),
	/*
	 * We will pass IRQ_BASE to the driver now but this can be removed
	 * when/if the driver starts to use intel_msic_irq_read().
	 */
	DEFINE_RES_MEM_NAMED(MSIC_IRQ_STATUS_ACCDET, 1, "IRQ_BASE"),
};

static struct resource msic_hdmi_resources[] = {
	DEFINE_RES_IRQ(0),
};

static struct resource msic_thermal_resources[] = {
	DEFINE_RES_IRQ(0),
};

static struct resource msic_power_btn_resources[] = {
	DEFINE_RES_IRQ(0),
};

static struct resource msic_ocd_resources[] = {
	DEFINE_RES_IRQ(0),
};

/*
 * Devices that are part of the MSIC and are available via firmware
 * populated SFI DEVS table.
 */
static struct mfd_cell msic_devs[] = {
	[INTEL_MSIC_BLOCK_TOUCH]	= {
		.name			= "msic_touch",
		.num_resources		= ARRAY_SIZE(msic_touch_resources),
		.resources		= msic_touch_resources,
	},
	[INTEL_MSIC_BLOCK_ADC]		= {
		.name			= "msic_adc",
		.num_resources		= ARRAY_SIZE(msic_adc_resources),
		.resources		= msic_adc_resources,
	},
	[INTEL_MSIC_BLOCK_BATTERY]	= {
		.name			= "msic_battery",
		.num_resources		= ARRAY_SIZE(msic_battery_resources),
		.resources		= msic_battery_resources,
	},
	[INTEL_MSIC_BLOCK_GPIO]		= {
		.name			= "msic_gpio",
		.num_resources		= ARRAY_SIZE(msic_gpio_resources),
		.resources		= msic_gpio_resources,
	},
	[INTEL_MSIC_BLOCK_AUDIO]	= {
		.name			= "msic_audio",
		.num_resources		= ARRAY_SIZE(msic_audio_resources),
		.resources		= msic_audio_resources,
	},
	[INTEL_MSIC_BLOCK_HDMI]		= {
		.name			= "msic_hdmi",
		.num_resources		= ARRAY_SIZE(msic_hdmi_resources),
		.resources		= msic_hdmi_resources,
	},
	[INTEL_MSIC_BLOCK_THERMAL]	= {
		.name			= "msic_thermal",
		.num_resources		= ARRAY_SIZE(msic_thermal_resources),
		.resources		= msic_thermal_resources,
	},
	[INTEL_MSIC_BLOCK_POWER_BTN]	= {
		.name			= "msic_power_btn",
		.num_resources		= ARRAY_SIZE(msic_power_btn_resources),
		.resources		= msic_power_btn_resources,
	},
	[INTEL_MSIC_BLOCK_OCD]		= {
		.name			= "msic_ocd",
		.num_resources		= ARRAY_SIZE(msic_ocd_resources),
		.resources		= msic_ocd_resources,
	},
};

/*
 * Other MSIC related devices which are not directly available via SFI DEVS
 * table. These can be pseudo devices, regulators etc. which are needed for
 * different purposes.
 *
 * These devices appear only after the MSIC driver itself is initialized so
 * we can guarantee that the SCU IPC interface is ready.
 */
static const struct mfd_cell msic_other_devs[] = {
	/* Audio codec in the MSIC */
	{
		.id			= -1,
		.name			= "sn95031",
	},
};

/**
 * intel_msic_reg_read - read a single MSIC register
 * @reg: register to read
 * @val: register value is placed here
 *
 * Read a single register from MSIC. Returns %0 on success and negative
 * errno in case of failure.
 *
 * Function may sleep.
 */
int intel_msic_reg_read(unsigned short reg, u8 *val)
{
	return intel_scu_ipc_ioread8(reg, val);
}
EXPORT_SYMBOL_GPL(intel_msic_reg_read);

/**
 * intel_msic_reg_write - write a single MSIC register
 * @reg: register to write
 * @val: value to write to that register
 *
 * Write a single MSIC register. Returns 0 on success and negative
 * errno in case of failure.
 *
 * Function may sleep.
 */
int intel_msic_reg_write(unsigned short reg, u8 val)
{
	return intel_scu_ipc_iowrite8(reg, val);
}
EXPORT_SYMBOL_GPL(intel_msic_reg_write);

/**
 * intel_msic_reg_update - update a single MSIC register
 * @reg: register to update
 * @val: value to write to the register
 * @mask: specifies which of the bits are updated (%0 = don't update,
 *        %1 = update)
 *
 * Perform an update to a register @reg. @mask is used to specify which
 * bits are updated. Returns %0 in case of success and negative errno in
 * case of failure.
 *
 * Function may sleep.
 */
int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask)
{
	return intel_scu_ipc_update_register(reg, val, mask);
}
EXPORT_SYMBOL_GPL(intel_msic_reg_update);

/**
 * intel_msic_bulk_read - read an array of registers
 * @reg: array of register addresses to read
 * @buf: array where the read values are placed
 * @count: number of registers to read
 *
 * Function reads @count registers from the MSIC using addresses passed in
 * @reg. Read values are placed in @buf. Reads are performed atomically
 * wrt. MSIC.
 *
 * Returns %0 in case of success and negative errno in case of failure.
 *
 * Function may sleep.
 */
int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count)
{
	if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
		return -EINVAL;

	return intel_scu_ipc_readv(reg, buf, count);
}
EXPORT_SYMBOL_GPL(intel_msic_bulk_read);

/**
 * intel_msic_bulk_write - write an array of values to the MSIC registers
 * @reg: array of registers to write
 * @buf: values to write to each register
 * @count: number of registers to write
 *
 * Function writes @count registers in @buf to MSIC. Writes are performed
 * atomically wrt MSIC. Returns %0 in case of success and negative errno in
 * case of failure.
 *
 * Function may sleep.
 */
int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count)
{
	if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
		return -EINVAL;

	return intel_scu_ipc_writev(reg, buf, count);
}
EXPORT_SYMBOL_GPL(intel_msic_bulk_write);

/**
 * intel_msic_irq_read - read a register from an MSIC interrupt tree
 * @msic: MSIC instance
 * @reg: interrupt register (between %INTEL_MSIC_IRQLVL1 and
 *	 %INTEL_MSIC_RESETIRQ2)
 * @val: value of the register is placed here
 *
 * This function can be used by an MSIC subdevice interrupt handler to read
 * a register value from the MSIC interrupt tree. In this way subdevice
 * drivers don't have to map in the interrupt tree themselves but can just
 * call this function instead.
 *
 * Function doesn't sleep and is callable from interrupt context.
 *
 * Returns %-EINVAL if @reg is outside of the allowed register region.
 */
int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val)
{
	if (WARN_ON(reg < INTEL_MSIC_IRQLVL1 || reg > INTEL_MSIC_RESETIRQ2))
		return -EINVAL;

	*val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1));
	return 0;
}
EXPORT_SYMBOL_GPL(intel_msic_irq_read);

static int intel_msic_init_devices(struct intel_msic *msic)
{
	struct platform_device *pdev = msic->pdev;
	struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
	int ret, i;

	if (pdata->gpio) {
		struct mfd_cell *cell = &msic_devs[INTEL_MSIC_BLOCK_GPIO];

		cell->platform_data = pdata->gpio;
		cell->pdata_size = sizeof(*pdata->gpio);
	}

	if (pdata->ocd) {
		unsigned gpio = pdata->ocd->gpio;

		ret = devm_gpio_request_one(&pdev->dev, gpio,
					GPIOF_IN, "ocd_gpio");
		if (ret) {
			dev_err(&pdev->dev, "failed to register OCD GPIO\n");
			return ret;
		}

		ret = gpio_to_irq(gpio);
		if (ret < 0) {
			dev_err(&pdev->dev, "no IRQ number for OCD GPIO\n");
			return ret;
		}

		/* Update the IRQ number for the OCD */
		pdata->irq[INTEL_MSIC_BLOCK_OCD] = ret;
	}

	for (i = 0; i < ARRAY_SIZE(msic_devs); i++) {
		if (!pdata->irq[i])
			continue;

		ret = mfd_add_devices(&pdev->dev, -1, &msic_devs[i], 1, NULL,
				      pdata->irq[i], NULL);
		if (ret)
			goto fail;
	}

	ret = mfd_add_devices(&pdev->dev, 0, msic_other_devs,
			      ARRAY_SIZE(msic_other_devs), NULL, 0, NULL);
	if (ret)
		goto fail;

	return 0;

fail:
	mfd_remove_devices(&pdev->dev);

	return ret;
}

static void intel_msic_remove_devices(struct intel_msic *msic)
{
	struct platform_device *pdev = msic->pdev;

	mfd_remove_devices(&pdev->dev);
}

static int intel_msic_probe(struct platform_device *pdev)
{
	struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct intel_msic *msic;
	struct resource *res;
	u8 id0, id1;
	int ret;

	if (!pdata) {
		dev_err(&pdev->dev, "no platform data passed\n");
		return -EINVAL;
	}

	/* First validate that we have an MSIC in place */
	ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID0, &id0);
	if (ret) {
		dev_err(&pdev->dev, "failed to identify the MSIC chip (ID0)\n");
		return -ENXIO;
	}

	ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID1, &id1);
	if (ret) {
		dev_err(&pdev->dev, "failed to identify the MSIC chip (ID1)\n");
		return -ENXIO;
	}

	if (MSIC_VENDOR(id0) != MSIC_VENDOR(id1)) {
		dev_err(&pdev->dev, "invalid vendor ID: %x, %x\n", id0, id1);
		return -ENXIO;
	}

	msic = devm_kzalloc(&pdev->dev, sizeof(*msic), GFP_KERNEL);
	if (!msic)
		return -ENOMEM;

	msic->vendor = MSIC_VENDOR(id0);
	msic->version = MSIC_VERSION(id0);
	msic->pdev = pdev;

	/*
	 * Map in the MSIC interrupt tree area in SRAM. This is exposed to
	 * the clients via intel_msic_irq_read().
	 */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	msic->irq_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(msic->irq_base))
		return PTR_ERR(msic->irq_base);

	platform_set_drvdata(pdev, msic);

	ret = intel_msic_init_devices(msic);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize MSIC devices\n");
		return ret;
	}

	dev_info(&pdev->dev, "Intel MSIC version %c%d (vendor %#x)\n",
		 MSIC_MAJOR(msic->version), MSIC_MINOR(msic->version),
		 msic->vendor);

	return 0;
}

static int intel_msic_remove(struct platform_device *pdev)
{
	struct intel_msic *msic = platform_get_drvdata(pdev);

	intel_msic_remove_devices(msic);

	return 0;
}

static struct platform_driver intel_msic_driver = {
	.probe		= intel_msic_probe,
	.remove		= intel_msic_remove,
	.driver		= {
		.name	= "intel_msic",
	},
};
builtin_platform_driver(intel_msic_driver);
Commit	Line	Data
26c7e05a	1	// SPDX-License-Identifier: GPL-2.0
1f5a371c MW	2	/*
	3	* Driver for Intel MSIC
	4	*
	5	* Copyright (C) 2011, Intel Corporation
	6	* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
1f5a371c MW	7	*/
1f5a371c MW	8
6c2db1c6	9	#include <linux/err.h>
1f5a371c	10	#include <linux/gpio.h>
5f6cb769	11	#include <linux/io.h>
b3fe9c5c	12	#include <linux/init.h>
1f5a371c MW	13	#include <linux/mfd/core.h>
	14	#include <linux/mfd/intel_msic.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/slab.h>
	17
	18	#include <asm/intel_scu_ipc.h>
	19
	20	#define MSIC_VENDOR(id) ((id >> 6) & 3)
	21	#define MSIC_VERSION(id) (id & 0x3f)
	22	#define MSIC_MAJOR(id) ('A' + ((id >> 3) & 7))
	23	#define MSIC_MINOR(id) (id & 7)
	24
	25	/*
	26	* MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
b39fc890	27	* Since IRQ block starts from address 0x002 we need to subtract that from
1f5a371c MW	28	* the actual IRQ status register address.
	29	*/
	30	#define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
	31	#define MSIC_IRQ_STATUS_ACCDET MSIC_IRQ_STATUS(INTEL_MSIC_ACCDET)
	32
	33	/*
	34	* The SCU hardware has limitation of 16 bytes per read/write buffer on
	35	* Medfield.
	36	*/
	37	#define SCU_IPC_RWBUF_LIMIT 16
	38
	39	/**
	40	* struct intel_msic - an MSIC MFD instance
	41	* @pdev: pointer to the platform device
	42	* @vendor: vendor ID
	43	* @version: chip version
	44	* @irq_base: base address of the mapped MSIC SRAM interrupt tree
	45	*/
	46	struct intel_msic {
	47	struct platform_device *pdev;
	48	unsigned vendor;
	49	unsigned version;
	50	void __iomem *irq_base;
	51	};
	52
	53	static struct resource msic_touch_resources[] = {
95d617b4	54	DEFINE_RES_IRQ(0),
1f5a371c MW	55	};
	56
	57	static struct resource msic_adc_resources[] = {
95d617b4	58	DEFINE_RES_IRQ(0),
1f5a371c MW	59	};
	60
	61	static struct resource msic_battery_resources[] = {
95d617b4	62	DEFINE_RES_IRQ(0),
1f5a371c MW	63	};
	64
	65	static struct resource msic_gpio_resources[] = {
95d617b4	66	DEFINE_RES_IRQ(0),
1f5a371c MW	67	};
	68
	69	static struct resource msic_audio_resources[] = {
95d617b4	70	DEFINE_RES_IRQ_NAMED(0, "IRQ"),
1f5a371c MW	71	/*
	72	* We will pass IRQ_BASE to the driver now but this can be removed
	73	* when/if the driver starts to use intel_msic_irq_read().
	74	*/
95d617b4	75	DEFINE_RES_MEM_NAMED(MSIC_IRQ_STATUS_ACCDET, 1, "IRQ_BASE"),
1f5a371c MW	76	};
	77
	78	static struct resource msic_hdmi_resources[] = {
95d617b4	79	DEFINE_RES_IRQ(0),
1f5a371c MW	80	};
	81
	82	static struct resource msic_thermal_resources[] = {
95d617b4	83	DEFINE_RES_IRQ(0),
1f5a371c MW	84	};
	85
	86	static struct resource msic_power_btn_resources[] = {
95d617b4	87	DEFINE_RES_IRQ(0),
1f5a371c MW	88	};
	89
	90	static struct resource msic_ocd_resources[] = {
95d617b4	91	DEFINE_RES_IRQ(0),
1f5a371c MW	92	};
	93
	94	/*
	95	* Devices that are part of the MSIC and are available via firmware
	96	* populated SFI DEVS table.
	97	*/
	98	static struct mfd_cell msic_devs[] = {
	99	[INTEL_MSIC_BLOCK_TOUCH] = {
	100	.name = "msic_touch",
	101	.num_resources = ARRAY_SIZE(msic_touch_resources),
	102	.resources = msic_touch_resources,
	103	},
	104	[INTEL_MSIC_BLOCK_ADC] = {
	105	.name = "msic_adc",
	106	.num_resources = ARRAY_SIZE(msic_adc_resources),
	107	.resources = msic_adc_resources,
	108	},
	109	[INTEL_MSIC_BLOCK_BATTERY] = {
	110	.name = "msic_battery",
	111	.num_resources = ARRAY_SIZE(msic_battery_resources),
	112	.resources = msic_battery_resources,
	113	},
	114	[INTEL_MSIC_BLOCK_GPIO] = {
	115	.name = "msic_gpio",
	116	.num_resources = ARRAY_SIZE(msic_gpio_resources),
	117	.resources = msic_gpio_resources,
	118	},
	119	[INTEL_MSIC_BLOCK_AUDIO] = {
	120	.name = "msic_audio",
	121	.num_resources = ARRAY_SIZE(msic_audio_resources),
	122	.resources = msic_audio_resources,
	123	},
	124	[INTEL_MSIC_BLOCK_HDMI] = {
	125	.name = "msic_hdmi",
	126	.num_resources = ARRAY_SIZE(msic_hdmi_resources),
	127	.resources = msic_hdmi_resources,
	128	},
	129	[INTEL_MSIC_BLOCK_THERMAL] = {
	130	.name = "msic_thermal",
	131	.num_resources = ARRAY_SIZE(msic_thermal_resources),
	132	.resources = msic_thermal_resources,
	133	},
	134	[INTEL_MSIC_BLOCK_POWER_BTN] = {
	135	.name = "msic_power_btn",
	136	.num_resources = ARRAY_SIZE(msic_power_btn_resources),
	137	.resources = msic_power_btn_resources,
	138	},
	139	[INTEL_MSIC_BLOCK_OCD] = {
	140	.name = "msic_ocd",
	141	.num_resources = ARRAY_SIZE(msic_ocd_resources),
	142	.resources = msic_ocd_resources,
	143	},
	144	};
	145
	146	/*
	147	* Other MSIC related devices which are not directly available via SFI DEVS
	148	* table. These can be pseudo devices, regulators etc. which are needed for
	149	* different purposes.
	150	*
	151	* These devices appear only after the MSIC driver itself is initialized so
	152	* we can guarantee that the SCU IPC interface is ready.
	153	*/
cf3c7cf6	154	static const struct mfd_cell msic_other_devs[] = {
1f5a371c MW	155	/* Audio codec in the MSIC */
	156	{
	157	.id = -1,
	158	.name = "sn95031",
	159	},
	160	};
	161
	162	/**
	163	* intel_msic_reg_read - read a single MSIC register
	164	* @reg: register to read
	165	* @val: register value is placed here
	166	*
	167	* Read a single register from MSIC. Returns %0 on success and negative
	168	* errno in case of failure.
	169	*
	170	* Function may sleep.
	171	*/
	172	int intel_msic_reg_read(unsigned short reg, u8 *val)
	173	{
	174	return intel_scu_ipc_ioread8(reg, val);
	175	}
	176	EXPORT_SYMBOL_GPL(intel_msic_reg_read);
	177
	178	/**
	179	* intel_msic_reg_write - write a single MSIC register
	180	* @reg: register to write
	181	* @val: value to write to that register
	182	*
	183	* Write a single MSIC register. Returns 0 on success and negative
	184	* errno in case of failure.
	185	*
	186	* Function may sleep.
	187	*/
	188	int intel_msic_reg_write(unsigned short reg, u8 val)
	189	{
	190	return intel_scu_ipc_iowrite8(reg, val);
	191	}
	192	EXPORT_SYMBOL_GPL(intel_msic_reg_write);
	193
	194	/**
	195	* intel_msic_reg_update - update a single MSIC register
	196	* @reg: register to update
	197	* @val: value to write to the register
	198	* @mask: specifies which of the bits are updated (%0 = don't update,
	199	* %1 = update)
	200	*
	201	* Perform an update to a register @reg. @mask is used to specify which
	202	* bits are updated. Returns %0 in case of success and negative errno in
	203	* case of failure.
	204	*
	205	* Function may sleep.
	206	*/
	207	int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask)
	208	{
	209	return intel_scu_ipc_update_register(reg, val, mask);
	210	}
	211	EXPORT_SYMBOL_GPL(intel_msic_reg_update);
	212
	213	/**
	214	* intel_msic_bulk_read - read an array of registers
	215	* @reg: array of register addresses to read
	216	* @buf: array where the read values are placed
	217	* @count: number of registers to read
	218	*
219	* Function reads @count registers from the MSIC using addresses passed in
220	* @reg. Read values are placed in @buf. Reads are performed atomically
221	* wrt. MSIC.
222	*
223	* Returns %0 in case of success and negative errno in case of failure.
224	*
225	* Function may sleep.
226	*/
227	int intel_msic_bulk_read(unsigned short reg, u8 buf, size_t count)
228	{
229	if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
230	return -EINVAL;
231
232	return intel_scu_ipc_readv(reg, buf, count);
233	}
234	EXPORT_SYMBOL_GPL(intel_msic_bulk_read);
235
236	/**
237	* intel_msic_bulk_write - write an array of values to the MSIC registers
238	* @reg: array of registers to write
239	* @buf: values to write to each register
240	* @count: number of registers to write
241	*
242	* Function writes @count registers in @buf to MSIC. Writes are performed
243	* atomically wrt MSIC. Returns %0 in case of success and negative errno in
244	* case of failure.
245	*
246	* Function may sleep.
247	*/
248	int intel_msic_bulk_write(unsigned short reg, u8 buf, size_t count)
249	{
250	if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
251	return -EINVAL;
252
253	return intel_scu_ipc_writev(reg, buf, count);
254	}
255	EXPORT_SYMBOL_GPL(intel_msic_bulk_write);
256
257	/**
258	* intel_msic_irq_read - read a register from an MSIC interrupt tree
259	* @msic: MSIC instance
260	* @reg: interrupt register (between %INTEL_MSIC_IRQLVL1 and
261	* %INTEL_MSIC_RESETIRQ2)
262	* @val: value of the register is placed here
263	*
264	* This function can be used by an MSIC subdevice interrupt handler to read
265	* a register value from the MSIC interrupt tree. In this way subdevice
266	* drivers don't have to map in the interrupt tree themselves but can just
267	* call this function instead.
268	*
269	* Function doesn't sleep and is callable from interrupt context.
270	*
271	* Returns %-EINVAL if @reg is outside of the allowed register region.
272	*/
273	int intel_msic_irq_read(struct intel_msic msic, unsigned short reg, u8 val)
274	{
275	if (WARN_ON(reg < INTEL_MSIC_IRQLVL1 \|\| reg > INTEL_MSIC_RESETIRQ2))
276	return -EINVAL;
277
278	*val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1));
279	return 0;
280	}
281	EXPORT_SYMBOL_GPL(intel_msic_irq_read);
282
f791be49	283	static int intel_msic_init_devices(struct intel_msic *msic)
1f5a371c MW	284	{
1f5a371c MW	285	struct platform_device *pdev = msic->pdev;
334a41ce	286	struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
1f5a371c MW	287	int ret, i;
	288
	289	if (pdata->gpio) {
	290	struct mfd_cell *cell = &msic_devs[INTEL_MSIC_BLOCK_GPIO];
	291
	292	cell->platform_data = pdata->gpio;
	293	cell->pdata_size = sizeof(*pdata->gpio);
	294	}
	295
	296	if (pdata->ocd) {
	297	unsigned gpio = pdata->ocd->gpio;
	298
54d34920 JH	299	ret = devm_gpio_request_one(&pdev->dev, gpio,
54d34920 JH	300	GPIOF_IN, "ocd_gpio");
1f5a371c MW	301	if (ret) {
	302	dev_err(&pdev->dev, "failed to register OCD GPIO\n");
	303	return ret;
	304	}
	305
	306	ret = gpio_to_irq(gpio);
	307	if (ret < 0) {
	308	dev_err(&pdev->dev, "no IRQ number for OCD GPIO\n");
1f5a371c MW	309	return ret;
	310	}
	311
	312	/* Update the IRQ number for the OCD */
	313	pdata->irq[INTEL_MSIC_BLOCK_OCD] = ret;
	314	}
	315
	316	for (i = 0; i < ARRAY_SIZE(msic_devs); i++) {
	317	if (!pdata->irq[i])
	318	continue;
	319
	320	ret = mfd_add_devices(&pdev->dev, -1, &msic_devs[i], 1, NULL,
0848c94f	321	pdata->irq[i], NULL);
1f5a371c MW	322	if (ret)
	323	goto fail;
	324	}
	325
	326	ret = mfd_add_devices(&pdev->dev, 0, msic_other_devs,
0848c94f	327	ARRAY_SIZE(msic_other_devs), NULL, 0, NULL);
1f5a371c MW	328	if (ret)
	329	goto fail;
	330
	331	return 0;
	332
	333	fail:
	334	mfd_remove_devices(&pdev->dev);
1f5a371c MW	335
	336	return ret;
	337	}
	338
4740f73f	339	static void intel_msic_remove_devices(struct intel_msic *msic)
1f5a371c MW	340	{
1f5a371c MW	341	struct platform_device *pdev = msic->pdev;
1f5a371c MW	342
1f5a371c MW	343	mfd_remove_devices(&pdev->dev);
1f5a371c MW	344	}
1f5a371c MW	345
f791be49	346	static int intel_msic_probe(struct platform_device *pdev)
1f5a371c	347	{
334a41ce	348	struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
1f5a371c MW	349	struct intel_msic *msic;
	350	struct resource *res;
	351	u8 id0, id1;
	352	int ret;
	353
	354	if (!pdata) {
	355	dev_err(&pdev->dev, "no platform data passed\n");
	356	return -EINVAL;
	357	}
	358
	359	/* First validate that we have an MSIC in place */
	360	ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID0, &id0);
	361	if (ret) {
	362	dev_err(&pdev->dev, "failed to identify the MSIC chip (ID0)\n");
	363	return -ENXIO;
	364	}
	365
	366	ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID1, &id1);
	367	if (ret) {
	368	dev_err(&pdev->dev, "failed to identify the MSIC chip (ID1)\n");
	369	return -ENXIO;
	370	}
	371
	372	if (MSIC_VENDOR(id0) != MSIC_VENDOR(id1)) {
	373	dev_err(&pdev->dev, "invalid vendor ID: %x, %x\n", id0, id1);
	374	return -ENXIO;
	375	}
	376
465c29d3	377	msic = devm_kzalloc(&pdev->dev, sizeof(*msic), GFP_KERNEL);
1f5a371c MW	378	if (!msic)
	379	return -ENOMEM;
	380
	381	msic->vendor = MSIC_VENDOR(id0);
	382	msic->version = MSIC_VERSION(id0);
	383	msic->pdev = pdev;
	384
	385	/*
	386	* Map in the MSIC interrupt tree area in SRAM. This is exposed to
	387	* the clients via intel_msic_irq_read().
	388	*/
	389	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6c2db1c6 TR	390	msic->irq_base = devm_ioremap_resource(&pdev->dev, res);
	391	if (IS_ERR(msic->irq_base))
	392	return PTR_ERR(msic->irq_base);
1f5a371c MW	393
	394	platform_set_drvdata(pdev, msic);
	395
	396	ret = intel_msic_init_devices(msic);
	397	if (ret) {
	398	dev_err(&pdev->dev, "failed to initialize MSIC devices\n");
465c29d3	399	return ret;
1f5a371c MW	400	}
	401
	402	dev_info(&pdev->dev, "Intel MSIC version %c%d (vendor %#x)\n",
	403	MSIC_MAJOR(msic->version), MSIC_MINOR(msic->version),
	404	msic->vendor);
	405
	406	return 0;
1f5a371c MW	407	}
1f5a371c MW	408
4740f73f	409	static int intel_msic_remove(struct platform_device *pdev)
1f5a371c MW	410	{
1f5a371c MW	411	struct intel_msic *msic = platform_get_drvdata(pdev);
1f5a371c MW	412
1f5a371c MW	413	intel_msic_remove_devices(msic);
1f5a371c MW	414
	415	return 0;
	416	}
	417
	418	static struct platform_driver intel_msic_driver = {
	419	.probe = intel_msic_probe,
84449216	420	.remove = intel_msic_remove,
1f5a371c MW	421	.driver = {
1f5a371c MW	422	.name = "intel_msic",
1f5a371c MW	423	},
1f5a371c MW	424	};
b3fe9c5c	425	builtin_platform_driver(intel_msic_driver);