[linux-2.6-block.git] / drivers / mfd / intel-lpss.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Intel Sunrisepoint LPSS core support.
 *
 * Copyright (C) 2015, Intel Corporation
 *
 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *          Mika Westerberg <mika.westerberg@linux.intel.com>
 *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
 *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/idr.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/pm_qos.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/io-64-nonatomic-lo-hi.h>

#include <linux/dma/idma64.h>

#include "intel-lpss.h"

#define LPSS_DEV_OFFSET		0x000
#define LPSS_DEV_SIZE		0x200
#define LPSS_PRIV_OFFSET	0x200
#define LPSS_PRIV_SIZE		0x100
#define LPSS_PRIV_REG_COUNT	(LPSS_PRIV_SIZE / 4)
#define LPSS_IDMA64_OFFSET	0x800
#define LPSS_IDMA64_SIZE	0x800

/* Offsets from lpss->priv */
#define LPSS_PRIV_RESETS		0x04
#define LPSS_PRIV_RESETS_IDMA		BIT(2)
#define LPSS_PRIV_RESETS_FUNC		0x3

#define LPSS_PRIV_ACTIVELTR		0x10
#define LPSS_PRIV_IDLELTR		0x14

#define LPSS_PRIV_LTR_REQ		BIT(15)
#define LPSS_PRIV_LTR_SCALE_MASK	GENMASK(11, 10)
#define LPSS_PRIV_LTR_SCALE_1US		(2 << 10)
#define LPSS_PRIV_LTR_SCALE_32US	(3 << 10)
#define LPSS_PRIV_LTR_VALUE_MASK	GENMASK(9, 0)

#define LPSS_PRIV_SSP_REG		0x20
#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN	BIT(0)

#define LPSS_PRIV_REMAP_ADDR		0x40

#define LPSS_PRIV_CAPS			0xfc
#define LPSS_PRIV_CAPS_NO_IDMA		BIT(8)
#define LPSS_PRIV_CAPS_TYPE_MASK	GENMASK(7, 4)
#define LPSS_PRIV_CAPS_TYPE_SHIFT	4

/* This matches the type field in CAPS register */
enum intel_lpss_dev_type {
	LPSS_DEV_I2C = 0,
	LPSS_DEV_UART,
	LPSS_DEV_SPI,
};

struct intel_lpss {
	const struct intel_lpss_platform_info *info;
	enum intel_lpss_dev_type type;
	struct clk *clk;
	struct clk_lookup *clock;
	struct mfd_cell *cell;
	struct device *dev;
	void __iomem *priv;
	u32 priv_ctx[LPSS_PRIV_REG_COUNT];
	int devid;
	u32 caps;
	u32 active_ltr;
	u32 idle_ltr;
	struct dentry *debugfs;
};

static const struct resource intel_lpss_dev_resources[] = {
	DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
	DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
	DEFINE_RES_IRQ(0),
};

static const struct resource intel_lpss_idma64_resources[] = {
	DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
	DEFINE_RES_IRQ(0),
};

/*
 * Cells needs to be ordered so that the iDMA is created first. This is
 * because we need to be sure the DMA is available when the host controller
 * driver is probed.
 */
static const struct mfd_cell intel_lpss_idma64_cell = {
	.name = LPSS_IDMA64_DRIVER_NAME,
	.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
	.resources = intel_lpss_idma64_resources,
};

static const struct mfd_cell intel_lpss_i2c_cell = {
	.name = "i2c_designware",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static const struct mfd_cell intel_lpss_uart_cell = {
	.name = "dw-apb-uart",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static const struct mfd_cell intel_lpss_spi_cell = {
	.name = "pxa2xx-spi",
	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	.resources = intel_lpss_dev_resources,
};

static DEFINE_IDA(intel_lpss_devid_ida);
static struct dentry *intel_lpss_debugfs;

static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
{
	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
}

static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
{
	struct dentry *dir;

	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
	if (IS_ERR(dir))
		return PTR_ERR(dir);

	/* Cache the values into lpss structure */
	intel_lpss_cache_ltr(lpss);

	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);

	lpss->debugfs = dir;
	return 0;
}

static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
{
	debugfs_remove_recursive(lpss->debugfs);
}

static void intel_lpss_ltr_set(struct device *dev, s32 val)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);
	u32 ltr;

	/*
	 * Program latency tolerance (LTR) accordingly what has been asked
	 * by the PM QoS layer or disable it in case we were passed
	 * negative value or PM_QOS_LATENCY_ANY.
	 */
	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);

	if (val == PM_QOS_LATENCY_ANY || val < 0) {
		ltr &= ~LPSS_PRIV_LTR_REQ;
	} else {
		ltr |= LPSS_PRIV_LTR_REQ;
		ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
		ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;

		if (val > LPSS_PRIV_LTR_VALUE_MASK)
			ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
		else
			ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
	}

	if (ltr == lpss->active_ltr)
		return;

	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);

	/* Cache the values into lpss structure */
	intel_lpss_cache_ltr(lpss);
}

static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
{
	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
	dev_pm_qos_expose_latency_tolerance(lpss->dev);
}

static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
{
	dev_pm_qos_hide_latency_tolerance(lpss->dev);
	lpss->dev->power.set_latency_tolerance = NULL;
}

static int intel_lpss_assign_devs(struct intel_lpss *lpss)
{
	const struct mfd_cell *cell;
	unsigned int type;

	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
	type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;

	switch (type) {
	case LPSS_DEV_I2C:
		cell = &intel_lpss_i2c_cell;
		break;
	case LPSS_DEV_UART:
		cell = &intel_lpss_uart_cell;
		break;
	case LPSS_DEV_SPI:
		cell = &intel_lpss_spi_cell;
		break;
	default:
		return -ENODEV;
	}

	lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
	if (!lpss->cell)
		return -ENOMEM;

	lpss->type = type;

	return 0;
}

static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
{
	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
}

static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
{
	resource_size_t addr = lpss->info->mem->start;

	lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
}

static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
{
	u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;

	/* Bring out the device from reset */
	writel(value, lpss->priv + LPSS_PRIV_RESETS);
}

static void intel_lpss_init_dev(const struct intel_lpss *lpss)
{
	u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;

	/* Set the device in reset state */
	writel(0, lpss->priv + LPSS_PRIV_RESETS);

	intel_lpss_deassert_reset(lpss);

	intel_lpss_set_remap_addr(lpss);

	if (!intel_lpss_has_idma(lpss))
		return;

	/* Make sure that SPI multiblock DMA transfers are re-enabled */
	if (lpss->type == LPSS_DEV_SPI)
		writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
}

static void intel_lpss_unregister_clock_tree(struct clk *clk)
{
	struct clk *parent;

	while (clk) {
		parent = clk_get_parent(clk);
		clk_unregister(clk);
		clk = parent;
	}
}

static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
					     const char *devname,
					     struct clk **clk)
{
	char name[32];
	struct clk *tmp = *clk;

	snprintf(name, sizeof(name), "%s-enable", devname);
	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
				lpss->priv, 0, 0, NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);

	snprintf(name, sizeof(name), "%s-div", devname);
	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
					      0, lpss->priv, 1, 15, 16, 15, 0,
					      NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);
	*clk = tmp;

	snprintf(name, sizeof(name), "%s-update", devname);
	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
				CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
	if (IS_ERR(tmp))
		return PTR_ERR(tmp);
	*clk = tmp;

	return 0;
}

static int intel_lpss_register_clock(struct intel_lpss *lpss)
{
	const struct mfd_cell *cell = lpss->cell;
	struct clk *clk;
	char devname[24];
	int ret;

	if (!lpss->info->clk_rate)
		return 0;

	/* Root clock */
	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
				      lpss->info->clk_rate);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);

	/*
	 * Support for clock divider only if it has some preset value.
	 * Otherwise we assume that the divider is not used.
	 */
	if (lpss->type != LPSS_DEV_I2C) {
		ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
		if (ret)
			goto err_clk_register;
	}

	ret = -ENOMEM;

	/* Clock for the host controller */
	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
	if (!lpss->clock)
		goto err_clk_register;

	lpss->clk = clk;

	return 0;

err_clk_register:
	intel_lpss_unregister_clock_tree(clk);

	return ret;
}

static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
{
	if (IS_ERR_OR_NULL(lpss->clk))
		return;

	clkdev_drop(lpss->clock);
	intel_lpss_unregister_clock_tree(lpss->clk);
}

int intel_lpss_probe(struct device *dev,
		     const struct intel_lpss_platform_info *info)
{
	struct intel_lpss *lpss;
	int ret;

	if (!info || !info->mem || info->irq <= 0)
		return -EINVAL;

	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
	if (!lpss)
		return -ENOMEM;

	lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
				  LPSS_PRIV_SIZE);
	if (!lpss->priv)
		return -ENOMEM;

	lpss->info = info;
	lpss->dev = dev;
	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);

	dev_set_drvdata(dev, lpss);

	ret = intel_lpss_assign_devs(lpss);
	if (ret)
		return ret;

	lpss->cell->properties = info->properties;

	intel_lpss_init_dev(lpss);

	lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
	if (lpss->devid < 0)
		return lpss->devid;

	ret = intel_lpss_register_clock(lpss);
	if (ret)
		goto err_clk_register;

	intel_lpss_ltr_expose(lpss);

	ret = intel_lpss_debugfs_add(lpss);
	if (ret)
		dev_warn(dev, "Failed to create debugfs entries\n");

	if (intel_lpss_has_idma(lpss)) {
		ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
				      1, info->mem, info->irq, NULL);
		if (ret)
			dev_warn(dev, "Failed to add %s, fallback to PIO\n",
				 LPSS_IDMA64_DRIVER_NAME);
	}

	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
			      1, info->mem, info->irq, NULL);
	if (ret)
		goto err_remove_ltr;

	dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);

	return 0;

err_remove_ltr:
	intel_lpss_debugfs_remove(lpss);
	intel_lpss_ltr_hide(lpss);
	intel_lpss_unregister_clock(lpss);

err_clk_register:
	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);

	return ret;
}
EXPORT_SYMBOL_GPL(intel_lpss_probe);

void intel_lpss_remove(struct device *dev)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);

	mfd_remove_devices(dev);
	intel_lpss_debugfs_remove(lpss);
	intel_lpss_ltr_hide(lpss);
	intel_lpss_unregister_clock(lpss);
	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
}
EXPORT_SYMBOL_GPL(intel_lpss_remove);

static int resume_lpss_device(struct device *dev, void *data)
{
	if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
		pm_runtime_resume(dev);

	return 0;
}

int intel_lpss_prepare(struct device *dev)
{
	/*
	 * Resume both child devices before entering system sleep. This
	 * ensures that they are in proper state before they get suspended.
	 */
	device_for_each_child_reverse(dev, NULL, resume_lpss_device);
	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_prepare);

int intel_lpss_suspend(struct device *dev)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);
	unsigned int i;

	/* Save device context */
	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
		lpss->priv_ctx[i] = readl(lpss->priv + i * 4);

	/*
	 * If the device type is not UART, then put the controller into
	 * reset. UART cannot be put into reset since S3/S0ix fail when
	 * no_console_suspend flag is enabled.
	 */
	if (lpss->type != LPSS_DEV_UART)
		writel(0, lpss->priv + LPSS_PRIV_RESETS);

	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_suspend);

int intel_lpss_resume(struct device *dev)
{
	struct intel_lpss *lpss = dev_get_drvdata(dev);
	unsigned int i;

	intel_lpss_deassert_reset(lpss);

	/* Restore device context */
	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
		writel(lpss->priv_ctx[i], lpss->priv + i * 4);

	return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_resume);

static int __init intel_lpss_init(void)
{
	intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
	return 0;
}
module_init(intel_lpss_init);

static void __exit intel_lpss_exit(void)
{
	ida_destroy(&intel_lpss_devid_ida);
	debugfs_remove(intel_lpss_debugfs);
}
module_exit(intel_lpss_exit);

MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
MODULE_DESCRIPTION("Intel LPSS core driver");
MODULE_LICENSE("GPL v2");
/*
 * Ensure the DMA driver is loaded before the host controller device appears,
 * so that the host controller driver can request its DMA channels as early
 * as possible.
 *
 * If the DMA module is not there that's OK as well.
 */
MODULE_SOFTDEP("pre: platform:" LPSS_IDMA64_DRIVER_NAME);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
4b45efe8 AS	2	/*
	3	* Intel Sunrisepoint LPSS core support.
	4	*
	5	* Copyright (C) 2015, Intel Corporation
	6	*
	7	* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	8	* Mika Westerberg <mika.westerberg@linux.intel.com>
	9	* Heikki Krogerus <heikki.krogerus@linux.intel.com>
	10	* Jarkko Nikula <jarkko.nikula@linux.intel.com>
4b45efe8 AS	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/clkdev.h>
	15	#include <linux/clk-provider.h>
	16	#include <linux/debugfs.h>
	17	#include <linux/idr.h>
62e59c4e	18	#include <linux/io.h>
4b45efe8 AS	19	#include <linux/ioport.h>
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/mfd/core.h>
	23	#include <linux/pm_qos.h>
	24	#include <linux/pm_runtime.h>
e15ad215	25	#include <linux/property.h>
4b45efe8	26	#include <linux/seq_file.h>
9cf5c095	27	#include <linux/io-64-nonatomic-lo-hi.h>
689d4453	28
ffcfc20f AS	29	#include <linux/dma/idma64.h>
ffcfc20f AS	30
4b45efe8 AS	31	#include "intel-lpss.h"
	32
	33	#define LPSS_DEV_OFFSET 0x000
	34	#define LPSS_DEV_SIZE 0x200
	35	#define LPSS_PRIV_OFFSET 0x200
	36	#define LPSS_PRIV_SIZE 0x100
41a3da2b	37	#define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
4b45efe8 AS	38	#define LPSS_IDMA64_OFFSET 0x800
	39	#define LPSS_IDMA64_SIZE 0x800
	40
	41	/* Offsets from lpss->priv */
	42	#define LPSS_PRIV_RESETS 0x04
f3b23e5a AS	43	#define LPSS_PRIV_RESETS_IDMA BIT(2)
f3b23e5a AS	44	#define LPSS_PRIV_RESETS_FUNC 0x3
4b45efe8 AS	45
	46	#define LPSS_PRIV_ACTIVELTR 0x10
	47	#define LPSS_PRIV_IDLELTR 0x14
	48
	49	#define LPSS_PRIV_LTR_REQ BIT(15)
cbd1c5c4 AS	50	#define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10)
	51	#define LPSS_PRIV_LTR_SCALE_1US (2 << 10)
	52	#define LPSS_PRIV_LTR_SCALE_32US (3 << 10)
	53	#define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0)
4b45efe8 AS	54
	55	#define LPSS_PRIV_SSP_REG 0x20
	56	#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
	57
689d4453	58	#define LPSS_PRIV_REMAP_ADDR 0x40
4b45efe8 AS	59
	60	#define LPSS_PRIV_CAPS 0xfc
	61	#define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
cbd1c5c4	62	#define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4)
4b45efe8	63	#define LPSS_PRIV_CAPS_TYPE_SHIFT 4
4b45efe8 AS	64
	65	/* This matches the type field in CAPS register */
	66	enum intel_lpss_dev_type {
	67	LPSS_DEV_I2C = 0,
	68	LPSS_DEV_UART,
	69	LPSS_DEV_SPI,
	70	};
	71
	72	struct intel_lpss {
	73	const struct intel_lpss_platform_info *info;
	74	enum intel_lpss_dev_type type;
	75	struct clk *clk;
	76	struct clk_lookup *clock;
e15ad215	77	struct mfd_cell *cell;
4b45efe8 AS	78	struct device *dev;
4b45efe8 AS	79	void __iomem *priv;
41a3da2b	80	u32 priv_ctx[LPSS_PRIV_REG_COUNT];
4b45efe8 AS	81	int devid;
	82	u32 caps;
	83	u32 active_ltr;
	84	u32 idle_ltr;
	85	struct dentry *debugfs;
	86	};
	87
	88	static const struct resource intel_lpss_dev_resources[] = {
	89	DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
	90	DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
	91	DEFINE_RES_IRQ(0),
	92	};
	93
	94	static const struct resource intel_lpss_idma64_resources[] = {
	95	DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
	96	DEFINE_RES_IRQ(0),
	97	};
	98
4b45efe8 AS	99	/*
	100	* Cells needs to be ordered so that the iDMA is created first. This is
	101	* because we need to be sure the DMA is available when the host controller
	102	* driver is probed.
	103	*/
	104	static const struct mfd_cell intel_lpss_idma64_cell = {
	105	.name = LPSS_IDMA64_DRIVER_NAME,
	106	.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
	107	.resources = intel_lpss_idma64_resources,
	108	};
	109
	110	static const struct mfd_cell intel_lpss_i2c_cell = {
	111	.name = "i2c_designware",
	112	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	113	.resources = intel_lpss_dev_resources,
	114	};
	115
	116	static const struct mfd_cell intel_lpss_uart_cell = {
	117	.name = "dw-apb-uart",
	118	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	119	.resources = intel_lpss_dev_resources,
	120	};
	121
	122	static const struct mfd_cell intel_lpss_spi_cell = {
	123	.name = "pxa2xx-spi",
	124	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
	125	.resources = intel_lpss_dev_resources,
	126	};
	127
	128	static DEFINE_IDA(intel_lpss_devid_ida);
	129	static struct dentry *intel_lpss_debugfs;
	130
4b45efe8 AS	131	static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
	132	{
	133	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
	134	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
	135	}
	136
	137	static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
	138	{
	139	struct dentry *dir;
	140
	141	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
	142	if (IS_ERR(dir))
	143	return PTR_ERR(dir);
	144
	145	/* Cache the values into lpss structure */
	146	intel_lpss_cache_ltr(lpss);
	147
	148	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
	149	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
	150	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
	151
	152	lpss->debugfs = dir;
	153	return 0;
	154	}
	155
	156	static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
	157	{
	158	debugfs_remove_recursive(lpss->debugfs);
	159	}
	160
	161	static void intel_lpss_ltr_set(struct device *dev, s32 val)
	162	{
	163	struct intel_lpss *lpss = dev_get_drvdata(dev);
	164	u32 ltr;
	165
	166	/*
	167	* Program latency tolerance (LTR) accordingly what has been asked
	168	* by the PM QoS layer or disable it in case we were passed
	169	* negative value or PM_QOS_LATENCY_ANY.
	170	*/
	171	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
	172
	173	if (val == PM_QOS_LATENCY_ANY \|\| val < 0) {
	174	ltr &= ~LPSS_PRIV_LTR_REQ;
	175	} else {
	176	ltr \|= LPSS_PRIV_LTR_REQ;
	177	ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
	178	ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
	179
	180	if (val > LPSS_PRIV_LTR_VALUE_MASK)
	181	ltr \|= LPSS_PRIV_LTR_SCALE_32US \| val >> 5;
	182	else
	183	ltr \|= LPSS_PRIV_LTR_SCALE_1US \| val;
	184	}
	185
	186	if (ltr == lpss->active_ltr)
	187	return;
	188
	189	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
	190	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
	191
	192	/* Cache the values into lpss structure */
	193	intel_lpss_cache_ltr(lpss);
	194	}
195
196	static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
197	{
198	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
199	dev_pm_qos_expose_latency_tolerance(lpss->dev);
200	}
201
202	static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
203	{
204	dev_pm_qos_hide_latency_tolerance(lpss->dev);
205	lpss->dev->power.set_latency_tolerance = NULL;
206	}
207
208	static int intel_lpss_assign_devs(struct intel_lpss *lpss)
209	{
e15ad215	210	const struct mfd_cell *cell;
4b45efe8 AS	211	unsigned int type;
	212
	213	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
	214	type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
	215
	216	switch (type) {
	217	case LPSS_DEV_I2C:
e15ad215	218	cell = &intel_lpss_i2c_cell;
4b45efe8 AS	219	break;
4b45efe8 AS	220	case LPSS_DEV_UART:
e15ad215	221	cell = &intel_lpss_uart_cell;
4b45efe8 AS	222	break;
4b45efe8 AS	223	case LPSS_DEV_SPI:
e15ad215	224	cell = &intel_lpss_spi_cell;
4b45efe8 AS	225	break;
	226	default:
	227	return -ENODEV;
	228	}
	229
e15ad215 MW	230	lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
	231	if (!lpss->cell)
	232	return -ENOMEM;
	233
4b45efe8 AS	234	lpss->type = type;
	235
	236	return 0;
	237	}
	238
	239	static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
	240	{
	241	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
	242	}
	243
	244	static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
	245	{
	246	resource_size_t addr = lpss->info->mem->start;
	247
689d4453	248	lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
4b45efe8 AS	249	}
	250
	251	static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
	252	{
	253	u32 value = LPSS_PRIV_RESETS_FUNC \| LPSS_PRIV_RESETS_IDMA;
	254
	255	/* Bring out the device from reset */
	256	writel(value, lpss->priv + LPSS_PRIV_RESETS);
	257	}
	258
	259	static void intel_lpss_init_dev(const struct intel_lpss *lpss)
	260	{
	261	u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
	262
dad06532 BW	263	/* Set the device in reset state */
	264	writel(0, lpss->priv + LPSS_PRIV_RESETS);
	265
4b45efe8 AS	266	intel_lpss_deassert_reset(lpss);
4b45efe8 AS	267
d28b6252 AS	268	intel_lpss_set_remap_addr(lpss);
d28b6252 AS	269
4b45efe8 AS	270	if (!intel_lpss_has_idma(lpss))
	271	return;
	272
4b45efe8 AS	273	/* Make sure that SPI multiblock DMA transfers are re-enabled */
	274	if (lpss->type == LPSS_DEV_SPI)
	275	writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
	276	}
	277
	278	static void intel_lpss_unregister_clock_tree(struct clk *clk)
	279	{
	280	struct clk *parent;
	281
	282	while (clk) {
	283	parent = clk_get_parent(clk);
	284	clk_unregister(clk);
	285	clk = parent;
	286	}
	287	}
	288
	289	static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
	290	const char *devname,
	291	struct clk **clk)
	292	{
	293	char name[32];
	294	struct clk tmp = clk;
	295
	296	snprintf(name, sizeof(name), "%s-enable", devname);
	297	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
	298	lpss->priv, 0, 0, NULL);
	299	if (IS_ERR(tmp))
	300	return PTR_ERR(tmp);
	301
	302	snprintf(name, sizeof(name), "%s-div", devname);
	303	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
	304	0, lpss->priv, 1, 15, 16, 15, 0,
	305	NULL);
	306	if (IS_ERR(tmp))
	307	return PTR_ERR(tmp);
	308	*clk = tmp;
	309
	310	snprintf(name, sizeof(name), "%s-update", devname);
	311	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
	312	CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
	313	if (IS_ERR(tmp))
	314	return PTR_ERR(tmp);
	315	*clk = tmp;
	316
	317	return 0;
	318	}
	319
	320	static int intel_lpss_register_clock(struct intel_lpss *lpss)
	321	{
	322	const struct mfd_cell *cell = lpss->cell;
	323	struct clk *clk;
	324	char devname[24];
	325	int ret;
	326
	327	if (!lpss->info->clk_rate)
	328	return 0;
	329
	330	/* Root clock */
0f7e70e7 SB	331	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
0f7e70e7 SB	332	lpss->info->clk_rate);
4b45efe8 AS	333	if (IS_ERR(clk))
	334	return PTR_ERR(clk);
	335
	336	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
	337
	338	/*
	339	* Support for clock divider only if it has some preset value.
	340	* Otherwise we assume that the divider is not used.
	341	*/
	342	if (lpss->type != LPSS_DEV_I2C) {
	343	ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
	344	if (ret)
	345	goto err_clk_register;
	346	}
	347
	348	ret = -ENOMEM;
	349
	350	/* Clock for the host controller */
	351	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
	352	if (!lpss->clock)
	353	goto err_clk_register;
	354
	355	lpss->clk = clk;
	356
	357	return 0;
	358
	359	err_clk_register:
	360	intel_lpss_unregister_clock_tree(clk);
	361
	362	return ret;
	363	}
	364
	365	static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
	366	{
	367	if (IS_ERR_OR_NULL(lpss->clk))
	368	return;
	369
	370	clkdev_drop(lpss->clock);
	371	intel_lpss_unregister_clock_tree(lpss->clk);
	372	}
	373
	374	int intel_lpss_probe(struct device *dev,
	375	const struct intel_lpss_platform_info *info)
	376	{
	377	struct intel_lpss *lpss;
	378	int ret;
	379
	380	if (!info \|\| !info->mem \|\| info->irq <= 0)
	381	return -EINVAL;
	382
	383	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
	384	if (!lpss)
	385	return -ENOMEM;
	386
a8ff78f7	387	lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
4b45efe8 AS	388	LPSS_PRIV_SIZE);
	389	if (!lpss->priv)
	390	return -ENOMEM;
	391
	392	lpss->info = info;
	393	lpss->dev = dev;
	394	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
	395
	396	dev_set_drvdata(dev, lpss);
	397
	398	ret = intel_lpss_assign_devs(lpss);
	399	if (ret)
	400	return ret;
	401
f4d05266	402	lpss->cell->properties = info->properties;
e15ad215	403
4b45efe8 AS	404	intel_lpss_init_dev(lpss);
	405
	406	lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
	407	if (lpss->devid < 0)
	408	return lpss->devid;
	409
	410	ret = intel_lpss_register_clock(lpss);
	411	if (ret)
	412	goto err_clk_register;
	413
	414	intel_lpss_ltr_expose(lpss);
	415
	416	ret = intel_lpss_debugfs_add(lpss);
	417	if (ret)
	418	dev_warn(dev, "Failed to create debugfs entries\n");
	419
	420	if (intel_lpss_has_idma(lpss)) {
4b45efe8 AS	421	ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
	422	1, info->mem, info->irq, NULL);
	423	if (ret)
	424	dev_warn(dev, "Failed to add %s, fallback to PIO\n",
	425	LPSS_IDMA64_DRIVER_NAME);
	426	}
	427
	428	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
	429	1, info->mem, info->irq, NULL);
	430	if (ret)
	431	goto err_remove_ltr;
	432
8425ec7f RW	433	dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
8425ec7f RW	434
4b45efe8 AS	435	return 0;
	436
	437	err_remove_ltr:
	438	intel_lpss_debugfs_remove(lpss);
	439	intel_lpss_ltr_hide(lpss);
84cb36ca	440	intel_lpss_unregister_clock(lpss);
4b45efe8 AS	441
	442	err_clk_register:
	443	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
	444
	445	return ret;
	446	}
	447	EXPORT_SYMBOL_GPL(intel_lpss_probe);
	448
	449	void intel_lpss_remove(struct device *dev)
	450	{
	451	struct intel_lpss *lpss = dev_get_drvdata(dev);
	452
	453	mfd_remove_devices(dev);
	454	intel_lpss_debugfs_remove(lpss);
	455	intel_lpss_ltr_hide(lpss);
	456	intel_lpss_unregister_clock(lpss);
	457	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
	458	}
	459	EXPORT_SYMBOL_GPL(intel_lpss_remove);
	460
	461	static int resume_lpss_device(struct device dev, void data)
	462	{
8425ec7f RW	463	if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
	464	pm_runtime_resume(dev);
	465
4b45efe8 AS	466	return 0;
	467	}
	468
	469	int intel_lpss_prepare(struct device *dev)
	470	{
	471	/*
	472	* Resume both child devices before entering system sleep. This
	473	* ensures that they are in proper state before they get suspended.
	474	*/
	475	device_for_each_child_reverse(dev, NULL, resume_lpss_device);
	476	return 0;
	477	}
	478	EXPORT_SYMBOL_GPL(intel_lpss_prepare);
	479
	480	int intel_lpss_suspend(struct device *dev)
	481	{
41a3da2b HK	482	struct intel_lpss *lpss = dev_get_drvdata(dev);
	483	unsigned int i;
	484
	485	/* Save device context */
	486	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
	487	lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
	488
0b471aaa FS	489	/*
	490	* If the device type is not UART, then put the controller into
	491	* reset. UART cannot be put into reset since S3/S0ix fail when
	492	* no_console_suspend flag is enabled.
	493	*/
	494	if (lpss->type != LPSS_DEV_UART)
	495	writel(0, lpss->priv + LPSS_PRIV_RESETS);
	496
4b45efe8 AS	497	return 0;
	498	}
	499	EXPORT_SYMBOL_GPL(intel_lpss_suspend);
	500
	501	int intel_lpss_resume(struct device *dev)
	502	{
	503	struct intel_lpss *lpss = dev_get_drvdata(dev);
41a3da2b	504	unsigned int i;
4b45efe8	505
41a3da2b HK	506	intel_lpss_deassert_reset(lpss);
	507
	508	/* Restore device context */
	509	for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
	510	writel(lpss->priv_ctx[i], lpss->priv + i * 4);
4b45efe8 AS	511
	512	return 0;
	513	}
	514	EXPORT_SYMBOL_GPL(intel_lpss_resume);
	515
	516	static int __init intel_lpss_init(void)
	517	{
	518	intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
	519	return 0;
	520	}
	521	module_init(intel_lpss_init);
	522
	523	static void __exit intel_lpss_exit(void)
	524	{
02f36911	525	ida_destroy(&intel_lpss_devid_ida);
4b45efe8 AS	526	debugfs_remove(intel_lpss_debugfs);
	527	}
	528	module_exit(intel_lpss_exit);
	529
	530	MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
	531	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
	532	MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
	533	MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
	534	MODULE_DESCRIPTION("Intel LPSS core driver");
	535	MODULE_LICENSE("GPL v2");
569fac74 AS	536	/*
	537	* Ensure the DMA driver is loaded before the host controller device appears,
	538	* so that the host controller driver can request its DMA channels as early
	539	* as possible.
	540	*
	541	* If the DMA module is not there that's OK as well.
	542	*/
	543	MODULE_SOFTDEP("pre: platform:" LPSS_IDMA64_DRIVER_NAME);