[linux-2.6-block.git] / drivers / mfd / ezx-pcap.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Motorola PCAP2 as present in EZX phones
 *
 * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
 * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/ezx-pcap.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#define PCAP_ADC_MAXQ		8
struct pcap_adc_request {
	u8 bank;
	u8 ch[2];
	u32 flags;
	void (*callback)(void *, u16[]);
	void *data;
};

struct pcap_adc_sync_request {
	u16 res[2];
	struct completion completion;
};

struct pcap_chip {
	struct spi_device *spi;

	/* IO */
	u32 buf;
	struct mutex io_mutex;

	/* IRQ */
	unsigned int irq_base;
	u32 msr;
	struct work_struct isr_work;
	struct work_struct msr_work;
	struct workqueue_struct *workqueue;

	/* ADC */
	struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
	u8 adc_head;
	u8 adc_tail;
	struct mutex adc_mutex;
};

/* IO */
static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
{
	struct spi_transfer t;
	struct spi_message m;
	int status;

	memset(&t, 0, sizeof(t));
	spi_message_init(&m);
	t.len = sizeof(u32);
	spi_message_add_tail(&t, &m);

	pcap->buf = *data;
	t.tx_buf = (u8 *) &pcap->buf;
	t.rx_buf = (u8 *) &pcap->buf;
	status = spi_sync(pcap->spi, &m);

	if (status == 0)
		*data = pcap->buf;

	return status;
}

int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
{
	int ret;

	mutex_lock(&pcap->io_mutex);
	value &= PCAP_REGISTER_VALUE_MASK;
	value |= PCAP_REGISTER_WRITE_OP_BIT
		| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	ret = ezx_pcap_putget(pcap, &value);
	mutex_unlock(&pcap->io_mutex);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_write);

int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
{
	int ret;

	mutex_lock(&pcap->io_mutex);
	*value = PCAP_REGISTER_READ_OP_BIT
		| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	ret = ezx_pcap_putget(pcap, value);
	mutex_unlock(&pcap->io_mutex);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_read);

int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
{
	int ret;
	u32 tmp = PCAP_REGISTER_READ_OP_BIT |
		(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	mutex_lock(&pcap->io_mutex);
	ret = ezx_pcap_putget(pcap, &tmp);
	if (ret)
		goto out_unlock;

	tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
	tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
		(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	ret = ezx_pcap_putget(pcap, &tmp);
out_unlock:
	mutex_unlock(&pcap->io_mutex);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);

/* IRQ */
int irq_to_pcap(struct pcap_chip *pcap, int irq)
{
	return irq - pcap->irq_base;
}
EXPORT_SYMBOL_GPL(irq_to_pcap);

int pcap_to_irq(struct pcap_chip *pcap, int irq)
{
	return pcap->irq_base + irq;
}
EXPORT_SYMBOL_GPL(pcap_to_irq);

static void pcap_mask_irq(struct irq_data *d)
{
	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);

	pcap->msr |= 1 << irq_to_pcap(pcap, d->irq);
	queue_work(pcap->workqueue, &pcap->msr_work);
}

static void pcap_unmask_irq(struct irq_data *d)
{
	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);

	pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
	queue_work(pcap->workqueue, &pcap->msr_work);
}

static struct irq_chip pcap_irq_chip = {
	.name		= "pcap",
	.irq_disable	= pcap_mask_irq,
	.irq_mask	= pcap_mask_irq,
	.irq_unmask	= pcap_unmask_irq,
};

static void pcap_msr_work(struct work_struct *work)
{
	struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);

	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
}

static void pcap_isr_work(struct work_struct *work)
{
	struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
	struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
	u32 msr, isr, int_sel, service;
	int irq;

	do {
		ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
		ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);

		/* We can't service/ack irqs that are assigned to port 2 */
		if (!(pdata->config & PCAP_SECOND_PORT)) {
			ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
			isr &= ~int_sel;
		}

		ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
		ezx_pcap_write(pcap, PCAP_REG_ISR, isr);

		local_irq_disable();
		service = isr & ~msr;
		for (irq = pcap->irq_base; service; service >>= 1, irq++) {
			if (service & 1)
				generic_handle_irq(irq);
		}
		local_irq_enable();
		ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
	} while (gpio_get_value(pdata->gpio));
}

static void pcap_irq_handler(struct irq_desc *desc)
{
	struct pcap_chip *pcap = irq_desc_get_handler_data(desc);

	desc->irq_data.chip->irq_ack(&desc->irq_data);
	queue_work(pcap->workqueue, &pcap->isr_work);
}

/* ADC */
void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
{
	u32 tmp;

	mutex_lock(&pcap->adc_mutex);
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	mutex_unlock(&pcap->adc_mutex);
}
EXPORT_SYMBOL_GPL(pcap_set_ts_bits);

static void pcap_disable_adc(struct pcap_chip *pcap)
{
	u32 tmp;

	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
}

static void pcap_adc_trigger(struct pcap_chip *pcap)
{
	u32 tmp;
	u8 head;

	mutex_lock(&pcap->adc_mutex);
	head = pcap->adc_head;
	if (!pcap->adc_queue[head]) {
		/* queue is empty, save power */
		pcap_disable_adc(pcap);
		mutex_unlock(&pcap->adc_mutex);
		return;
	}
	/* start conversion on requested bank, save TS_M bits */
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;

	if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
		tmp |= PCAP_ADC_AD_SEL1;

	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	mutex_unlock(&pcap->adc_mutex);
	ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
}

static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
{
	struct pcap_chip *pcap = _pcap;
	struct pcap_adc_request *req;
	u16 res[2];
	u32 tmp;

	mutex_lock(&pcap->adc_mutex);
	req = pcap->adc_queue[pcap->adc_head];

	if (WARN(!req, "adc irq without pending request\n")) {
		mutex_unlock(&pcap->adc_mutex);
		return IRQ_HANDLED;
	}

	/* read requested channels results */
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
	tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
	tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
	res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
	res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;

	pcap->adc_queue[pcap->adc_head] = NULL;
	pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
	mutex_unlock(&pcap->adc_mutex);

	/* pass the results and release memory */
	req->callback(req->data, res);
	kfree(req);

	/* trigger next conversion (if any) on queue */
	pcap_adc_trigger(pcap);

	return IRQ_HANDLED;
}

int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
						void *callback, void *data)
{
	struct pcap_adc_request *req;

	/* This will be freed after we have a result */
	req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
	if (!req)
		return -ENOMEM;

	req->bank = bank;
	req->flags = flags;
	req->ch[0] = ch[0];
	req->ch[1] = ch[1];
	req->callback = callback;
	req->data = data;

	mutex_lock(&pcap->adc_mutex);
	if (pcap->adc_queue[pcap->adc_tail]) {
		mutex_unlock(&pcap->adc_mutex);
		kfree(req);
		return -EBUSY;
	}
	pcap->adc_queue[pcap->adc_tail] = req;
	pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
	mutex_unlock(&pcap->adc_mutex);

	/* start conversion */
	pcap_adc_trigger(pcap);

	return 0;
}
EXPORT_SYMBOL_GPL(pcap_adc_async);

static void pcap_adc_sync_cb(void *param, u16 res[])
{
	struct pcap_adc_sync_request *req = param;

	req->res[0] = res[0];
	req->res[1] = res[1];
	complete(&req->completion);
}

int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
								u16 res[])
{
	struct pcap_adc_sync_request sync_data;
	int ret;

	init_completion(&sync_data.completion);
	ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
								&sync_data);
	if (ret)
		return ret;
	wait_for_completion(&sync_data.completion);
	res[0] = sync_data.res[0];
	res[1] = sync_data.res[1];

	return 0;
}
EXPORT_SYMBOL_GPL(pcap_adc_sync);

/* subdevs */
static int pcap_remove_subdev(struct device *dev, void *unused)
{
	platform_device_unregister(to_platform_device(dev));
	return 0;
}

static int pcap_add_subdev(struct pcap_chip *pcap,
						struct pcap_subdev *subdev)
{
	struct platform_device *pdev;
	int ret;

	pdev = platform_device_alloc(subdev->name, subdev->id);
	if (!pdev)
		return -ENOMEM;

	pdev->dev.parent = &pcap->spi->dev;
	pdev->dev.platform_data = subdev->platform_data;

	ret = platform_device_add(pdev);
	if (ret)
		platform_device_put(pdev);

	return ret;
}

static int ezx_pcap_remove(struct spi_device *spi)
{
	struct pcap_chip *pcap = spi_get_drvdata(spi);
	int i;

	/* remove all registered subdevs */
	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);

	/* cleanup ADC */
	mutex_lock(&pcap->adc_mutex);
	for (i = 0; i < PCAP_ADC_MAXQ; i++)
		kfree(pcap->adc_queue[i]);
	mutex_unlock(&pcap->adc_mutex);

	/* cleanup irqchip */
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
		irq_set_chip_and_handler(i, NULL, NULL);

	destroy_workqueue(pcap->workqueue);

	return 0;
}

static int ezx_pcap_probe(struct spi_device *spi)
{
	struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
	struct pcap_chip *pcap;
	int i, adc_irq;
	int ret = -ENODEV;

	/* platform data is required */
	if (!pdata)
		goto ret;

	pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
	if (!pcap) {
		ret = -ENOMEM;
		goto ret;
	}

	mutex_init(&pcap->io_mutex);
	mutex_init(&pcap->adc_mutex);
	INIT_WORK(&pcap->isr_work, pcap_isr_work);
	INIT_WORK(&pcap->msr_work, pcap_msr_work);
	spi_set_drvdata(spi, pcap);

	/* setup spi */
	spi->bits_per_word = 32;
	spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
	ret = spi_setup(spi);
	if (ret)
		goto ret;

	pcap->spi = spi;

	/* setup irq */
	pcap->irq_base = pdata->irq_base;
	pcap->workqueue = create_singlethread_workqueue("pcapd");
	if (!pcap->workqueue) {
		ret = -ENOMEM;
		dev_err(&spi->dev, "can't create pcap thread\n");
		goto ret;
	}

	/* redirect interrupts to AP, except adcdone2 */
	if (!(pdata->config & PCAP_SECOND_PORT))
		ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
					(1 << PCAP_IRQ_ADCDONE2));

	/* setup irq chip */
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
		irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
		irq_set_chip_data(i, pcap);
		irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
	}

	/* mask/ack all PCAP interrupts */
	ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
	ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
	pcap->msr = PCAP_MASK_ALL_INTERRUPT;

	irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
	irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
	irq_set_irq_wake(spi->irq, 1);

	/* ADC */
	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
					PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);

	ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
				pcap);
	if (ret)
		goto free_irqchip;

	/* setup subdevs */
	for (i = 0; i < pdata->num_subdevs; i++) {
		ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
		if (ret)
			goto remove_subdevs;
	}

	/* board specific quirks */
	if (pdata->init)
		pdata->init(pcap);

	return 0;

remove_subdevs:
	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
free_irqchip:
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
		irq_set_chip_and_handler(i, NULL, NULL);
/* destroy_workqueue: */
	destroy_workqueue(pcap->workqueue);
ret:
	return ret;
}

static struct spi_driver ezxpcap_driver = {
	.probe	= ezx_pcap_probe,
	.remove = ezx_pcap_remove,
	.driver = {
		.name	= "ezx-pcap",
	},
};

static int __init ezx_pcap_init(void)
{
	return spi_register_driver(&ezxpcap_driver);
}

static void __exit ezx_pcap_exit(void)
{
	spi_unregister_driver(&ezxpcap_driver);
}

subsys_initcall(ezx_pcap_init);
module_exit(ezx_pcap_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
MODULE_ALIAS("spi:ezx-pcap");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
13a09f93 DR	2	/*
	3	* Driver for Motorola PCAP2 as present in EZX phones
	4	*
	5	* Copyright (C) 2006 Harald Welte <laforge@openezx.org>
	6	* Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
13a09f93 DR	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/kernel.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14	#include <linux/mfd/ezx-pcap.h>
	15	#include <linux/spi/spi.h>
b1148fd4	16	#include <linux/gpio.h>
5a0e3ad6	17	#include <linux/slab.h>
13a09f93 DR	18
	19	#define PCAP_ADC_MAXQ 8
	20	struct pcap_adc_request {
	21	u8 bank;
	22	u8 ch[2];
	23	u32 flags;
	24	void (callback)(void , u16[]);
	25	void *data;
	26	};
	27
	28	struct pcap_adc_sync_request {
	29	u16 res[2];
	30	struct completion completion;
	31	};
	32
	33	struct pcap_chip {
	34	struct spi_device *spi;
	35
	36	/* IO */
	37	u32 buf;
	38	struct mutex io_mutex;
	39
	40	/* IRQ */
	41	unsigned int irq_base;
	42	u32 msr;
	43	struct work_struct isr_work;
	44	struct work_struct msr_work;
	45	struct workqueue_struct *workqueue;
	46
	47	/* ADC */
	48	struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
	49	u8 adc_head;
	50	u8 adc_tail;
	51	struct mutex adc_mutex;
	52	};
	53
	54	/* IO */
	55	static int ezx_pcap_putget(struct pcap_chip pcap, u32 data)
	56	{
	57	struct spi_transfer t;
	58	struct spi_message m;
	59	int status;
	60
0309528a	61	memset(&t, 0, sizeof(t));
13a09f93 DR	62	spi_message_init(&m);
	63	t.len = sizeof(u32);
	64	spi_message_add_tail(&t, &m);
	65
	66	pcap->buf = *data;
	67	t.tx_buf = (u8 *) &pcap->buf;
	68	t.rx_buf = (u8 *) &pcap->buf;
	69	status = spi_sync(pcap->spi, &m);
	70
	71	if (status == 0)
	72	*data = pcap->buf;
	73
	74	return status;
	75	}
	76
	77	int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
	78	{
	79	int ret;
	80
	81	mutex_lock(&pcap->io_mutex);
	82	value &= PCAP_REGISTER_VALUE_MASK;
	83	value \|= PCAP_REGISTER_WRITE_OP_BIT
	84	\| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	85	ret = ezx_pcap_putget(pcap, &value);
	86	mutex_unlock(&pcap->io_mutex);
	87
	88	return ret;
	89	}
	90	EXPORT_SYMBOL_GPL(ezx_pcap_write);
	91
	92	int ezx_pcap_read(struct pcap_chip pcap, u8 reg_num, u32 value)
	93	{
	94	int ret;
	95
	96	mutex_lock(&pcap->io_mutex);
	97	*value = PCAP_REGISTER_READ_OP_BIT
	98	\| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	99
	100	ret = ezx_pcap_putget(pcap, value);
	101	mutex_unlock(&pcap->io_mutex);
	102
	103	return ret;
	104	}
	105	EXPORT_SYMBOL_GPL(ezx_pcap_read);
	106
e9a22635 DR	107	int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
	108	{
	109	int ret;
	110	u32 tmp = PCAP_REGISTER_READ_OP_BIT \|
	111	(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	112
	113	mutex_lock(&pcap->io_mutex);
	114	ret = ezx_pcap_putget(pcap, &tmp);
	115	if (ret)
	116	goto out_unlock;
	117
	118	tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
	119	tmp \|= (val & mask) \| PCAP_REGISTER_WRITE_OP_BIT \|
	120	(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	121
	122	ret = ezx_pcap_putget(pcap, &tmp);
	123	out_unlock:
	124	mutex_unlock(&pcap->io_mutex);
	125
	126	return ret;
	127	}
	128	EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
	129
13a09f93	130	/* IRQ */
9f7b07d6	131	int irq_to_pcap(struct pcap_chip *pcap, int irq)
13a09f93	132	{
9f7b07d6	133	return irq - pcap->irq_base;
13a09f93	134	}
9f7b07d6	135	EXPORT_SYMBOL_GPL(irq_to_pcap);
13a09f93 DR	136
	137	int pcap_to_irq(struct pcap_chip *pcap, int irq)
	138	{
	139	return pcap->irq_base + irq;
	140	}
	141	EXPORT_SYMBOL_GPL(pcap_to_irq);
	142
c232f22f	143	static void pcap_mask_irq(struct irq_data *d)
13a09f93	144	{
c232f22f	145	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
13a09f93	146
c232f22f	147	pcap->msr \|= 1 << irq_to_pcap(pcap, d->irq);
13a09f93 DR	148	queue_work(pcap->workqueue, &pcap->msr_work);
	149	}
	150
c232f22f	151	static void pcap_unmask_irq(struct irq_data *d)
13a09f93	152	{
c232f22f	153	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
13a09f93	154
c232f22f	155	pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
13a09f93 DR	156	queue_work(pcap->workqueue, &pcap->msr_work);
	157	}
	158
	159	static struct irq_chip pcap_irq_chip = {
c232f22f	160	.name = "pcap",
73a6839f	161	.irq_disable = pcap_mask_irq,
c232f22f LB	162	.irq_mask = pcap_mask_irq,
c232f22f LB	163	.irq_unmask = pcap_unmask_irq,
13a09f93 DR	164	};
	165
	166	static void pcap_msr_work(struct work_struct *work)
	167	{
	168	struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
	169
	170	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
	171	}
	172
	173	static void pcap_isr_work(struct work_struct *work)
	174	{
	175	struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
334a41ce	176	struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
13a09f93 DR	177	u32 msr, isr, int_sel, service;
	178	int irq;
	179
b1148fd4 DR	180	do {
	181	ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
	182	ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
13a09f93	183
25985edc	184	/* We can't service/ack irqs that are assigned to port 2 */
b1148fd4 DR	185	if (!(pdata->config & PCAP_SECOND_PORT)) {
	186	ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
	187	isr &= ~int_sel;
	188	}
13a09f93	189
b1148fd4 DR	190	ezx_pcap_write(pcap, PCAP_REG_MSR, isr \| msr);
b1148fd4 DR	191	ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
13a09f93	192
b1148fd4 DR	193	local_irq_disable();
	194	service = isr & ~msr;
	195	for (irq = pcap->irq_base; service; service >>= 1, irq++) {
73a6839f TG	196	if (service & 1)
73a6839f TG	197	generic_handle_irq(irq);
13a09f93	198	}
b1148fd4 DR	199	local_irq_enable();
b1148fd4 DR	200	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
59ee93a5	201	} while (gpio_get_value(pdata->gpio));
13a09f93 DR	202	}
13a09f93 DR	203
bd0b9ac4	204	static void pcap_irq_handler(struct irq_desc *desc)
13a09f93	205	{
1e84aa44	206	struct pcap_chip *pcap = irq_desc_get_handler_data(desc);
13a09f93	207
c232f22f	208	desc->irq_data.chip->irq_ack(&desc->irq_data);
13a09f93	209	queue_work(pcap->workqueue, &pcap->isr_work);
13a09f93 DR	210	}
	211
	212	/* ADC */
ecd78cbd DR	213	void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
	214	{
	215	u32 tmp;
	216
	217	mutex_lock(&pcap->adc_mutex);
	218	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	219	tmp &= ~(PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	220	tmp \|= bits & (PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	221	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	222	mutex_unlock(&pcap->adc_mutex);
	223	}
	224	EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
	225
13a09f93 DR	226	static void pcap_disable_adc(struct pcap_chip *pcap)
	227	{
	228	u32 tmp;
	229
	230	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	231	tmp &= ~(PCAP_ADC_ADEN\|PCAP_ADC_BATT_I_ADC\|PCAP_ADC_BATT_I_POLARITY);
	232	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	233	}
	234
	235	static void pcap_adc_trigger(struct pcap_chip *pcap)
	236	{
	237	u32 tmp;
	238	u8 head;
	239
	240	mutex_lock(&pcap->adc_mutex);
	241	head = pcap->adc_head;
	242	if (!pcap->adc_queue[head]) {
	243	/* queue is empty, save power */
	244	pcap_disable_adc(pcap);
	245	mutex_unlock(&pcap->adc_mutex);
	246	return;
	247	}
ecd78cbd DR	248	/* start conversion on requested bank, save TS_M bits */
	249	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	250	tmp &= (PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	251	tmp \|= pcap->adc_queue[head]->flags \| PCAP_ADC_ADEN;
13a09f93 DR	252
	253	if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
	254	tmp \|= PCAP_ADC_AD_SEL1;
	255
	256	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
ecd78cbd	257	mutex_unlock(&pcap->adc_mutex);
13a09f93 DR	258	ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
	259	}
	260
	261	static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
	262	{
	263	struct pcap_chip *pcap = _pcap;
	264	struct pcap_adc_request *req;
	265	u16 res[2];
	266	u32 tmp;
	267
	268	mutex_lock(&pcap->adc_mutex);
	269	req = pcap->adc_queue[pcap->adc_head];
	270
e0084aa9	271	if (WARN(!req, "adc irq without pending request\n")) {
1c90ea2c	272	mutex_unlock(&pcap->adc_mutex);
13a09f93	273	return IRQ_HANDLED;
1c90ea2c	274	}
13a09f93 DR	275
	276	/* read requested channels results */
	277	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	278	tmp &= ~(PCAP_ADC_ADA1_MASK \| PCAP_ADC_ADA2_MASK);
	279	tmp \|= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
	280	tmp \|= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
	281	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	282	ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
	283	res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
	284	res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
	285
	286	pcap->adc_queue[pcap->adc_head] = NULL;
	287	pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
	288	mutex_unlock(&pcap->adc_mutex);
	289
	290	/* pass the results and release memory */
	291	req->callback(req->data, res);
	292	kfree(req);
	293
	294	/* trigger next conversion (if any) on queue */
	295	pcap_adc_trigger(pcap);
	296
	297	return IRQ_HANDLED;
	298	}
	299
	300	int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
	301	void callback, void data)
	302	{
	303	struct pcap_adc_request *req;
	304
	305	/* This will be freed after we have a result */
	306	req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
	307	if (!req)
	308	return -ENOMEM;
	309
	310	req->bank = bank;
	311	req->flags = flags;
	312	req->ch[0] = ch[0];
	313	req->ch[1] = ch[1];
	314	req->callback = callback;
	315	req->data = data;
	316
	317	mutex_lock(&pcap->adc_mutex);
	318	if (pcap->adc_queue[pcap->adc_tail]) {
	319	mutex_unlock(&pcap->adc_mutex);
	320	kfree(req);
	321	return -EBUSY;
	322	}
	323	pcap->adc_queue[pcap->adc_tail] = req;
	324	pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
	325	mutex_unlock(&pcap->adc_mutex);
	326
	327	/* start conversion */
	328	pcap_adc_trigger(pcap);
	329
	330	return 0;
	331	}
	332	EXPORT_SYMBOL_GPL(pcap_adc_async);
	333
	334	static void pcap_adc_sync_cb(void *param, u16 res[])
	335	{
	336	struct pcap_adc_sync_request *req = param;
	337
	338	req->res[0] = res[0];
339	req->res[1] = res[1];
340	complete(&req->completion);
341	}
342
343	int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
344	u16 res[])
345	{
346	struct pcap_adc_sync_request sync_data;
347	int ret;
348
349	init_completion(&sync_data.completion);
350	ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
351	&sync_data);
352	if (ret)
353	return ret;
354	wait_for_completion(&sync_data.completion);
355	res[0] = sync_data.res[0];
356	res[1] = sync_data.res[1];
357
358	return 0;
359	}
360	EXPORT_SYMBOL_GPL(pcap_adc_sync);
361
362	/* subdevs */
363	static int pcap_remove_subdev(struct device dev, void unused)
364	{
365	platform_device_unregister(to_platform_device(dev));
366	return 0;
367	}
368
f791be49	369	static int pcap_add_subdev(struct pcap_chip *pcap,
13a09f93 DR	370	struct pcap_subdev *subdev)
	371	{
	372	struct platform_device *pdev;
09ff21e0	373	int ret;
13a09f93 DR	374
13a09f93 DR	375	pdev = platform_device_alloc(subdev->name, subdev->id);
09ff21e0 AL	376	if (!pdev)
	377	return -ENOMEM;
	378
13a09f93 DR	379	pdev->dev.parent = &pcap->spi->dev;
13a09f93 DR	380	pdev->dev.platform_data = subdev->platform_data;
13a09f93	381
09ff21e0 AL	382	ret = platform_device_add(pdev);
	383	if (ret)
	384	platform_device_put(pdev);
	385
	386	return ret;
13a09f93 DR	387	}
13a09f93 DR	388
4740f73f	389	static int ezx_pcap_remove(struct spi_device *spi)
13a09f93	390	{
7c478b40	391	struct pcap_chip *pcap = spi_get_drvdata(spi);
89720264	392	int i;
13a09f93 DR	393
	394	/* remove all registered subdevs */
	395	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
	396
	397	/* cleanup ADC */
13a09f93 DR	398	mutex_lock(&pcap->adc_mutex);
	399	for (i = 0; i < PCAP_ADC_MAXQ; i++)
	400	kfree(pcap->adc_queue[i]);
	401	mutex_unlock(&pcap->adc_mutex);
	402
	403	/* cleanup irqchip */
	404	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
d5bb1221	405	irq_set_chip_and_handler(i, NULL, NULL);
13a09f93 DR	406
	407	destroy_workqueue(pcap->workqueue);
	408
13a09f93 DR	409	return 0;
	410	}
	411
f791be49	412	static int ezx_pcap_probe(struct spi_device *spi)
13a09f93	413	{
334a41ce	414	struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
13a09f93 DR	415	struct pcap_chip *pcap;
	416	int i, adc_irq;
	417	int ret = -ENODEV;
	418
	419	/* platform data is required */
	420	if (!pdata)
	421	goto ret;
	422
1ba895e0	423	pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
13a09f93 DR	424	if (!pcap) {
	425	ret = -ENOMEM;
	426	goto ret;
	427	}
	428
	429	mutex_init(&pcap->io_mutex);
	430	mutex_init(&pcap->adc_mutex);
	431	INIT_WORK(&pcap->isr_work, pcap_isr_work);
	432	INIT_WORK(&pcap->msr_work, pcap_msr_work);
7c478b40	433	spi_set_drvdata(spi, pcap);
13a09f93 DR	434
	435	/* setup spi */
	436	spi->bits_per_word = 32;
	437	spi->mode = SPI_MODE_0 \| (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
	438	ret = spi_setup(spi);
	439	if (ret)
1ba895e0	440	goto ret;
13a09f93 DR	441
	442	pcap->spi = spi;
	443
	444	/* setup irq */
	445	pcap->irq_base = pdata->irq_base;
	446	pcap->workqueue = create_singlethread_workqueue("pcapd");
	447	if (!pcap->workqueue) {
47dabaee	448	ret = -ENOMEM;
25985edc	449	dev_err(&spi->dev, "can't create pcap thread\n");
1ba895e0	450	goto ret;
13a09f93 DR	451	}
	452
	453	/* redirect interrupts to AP, except adcdone2 */
	454	if (!(pdata->config & PCAP_SECOND_PORT))
	455	ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
	456	(1 << PCAP_IRQ_ADCDONE2));
	457
	458	/* setup irq chip */
	459	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
d5bb1221 TG	460	irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
d5bb1221 TG	461	irq_set_chip_data(i, pcap);
9bd09f34	462	irq_clear_status_flags(i, IRQ_NOREQUEST \| IRQ_NOPROBE);
13a09f93 DR	463	}
	464
	465	/* mask/ack all PCAP interrupts */
	466	ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
	467	ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
	468	pcap->msr = PCAP_MASK_ALL_INTERRUPT;
	469
d5bb1221	470	irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
c89fc9ac	471	irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
d5bb1221	472	irq_set_irq_wake(spi->irq, 1);
13a09f93 DR	473
	474	/* ADC */
	475	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
	476	PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
	477
1ba895e0 JH	478	ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
1ba895e0 JH	479	pcap);
13a09f93 DR	480	if (ret)
	481	goto free_irqchip;
	482
	483	/* setup subdevs */
	484	for (i = 0; i < pdata->num_subdevs; i++) {
	485	ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
	486	if (ret)
	487	goto remove_subdevs;
	488	}
	489
	490	/* board specific quirks */
	491	if (pdata->init)
	492	pdata->init(pcap);
	493
	494	return 0;
	495
	496	remove_subdevs:
	497	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
13a09f93 DR	498	free_irqchip:
13a09f93 DR	499	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
d5bb1221	500	irq_set_chip_and_handler(i, NULL, NULL);
13a09f93 DR	501	/* destroy_workqueue: */
13a09f93 DR	502	destroy_workqueue(pcap->workqueue);
13a09f93 DR	503	ret:
	504	return ret;
	505	}
	506
	507	static struct spi_driver ezxpcap_driver = {
	508	.probe = ezx_pcap_probe,
84449216	509	.remove = ezx_pcap_remove,
13a09f93 DR	510	.driver = {
13a09f93 DR	511	.name = "ezx-pcap",
13a09f93 DR	512	},
	513	};
	514
	515	static int __init ezx_pcap_init(void)
	516	{
	517	return spi_register_driver(&ezxpcap_driver);
	518	}
	519
	520	static void __exit ezx_pcap_exit(void)
	521	{
	522	spi_unregister_driver(&ezxpcap_driver);
	523	}
	524
f078237b	525	subsys_initcall(ezx_pcap_init);
13a09f93 DR	526	module_exit(ezx_pcap_exit);
	527
	528	MODULE_LICENSE("GPL");
	529	MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
	530	MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
e0626e38	531	MODULE_ALIAS("spi:ezx-pcap");