Commit | Line | Data |
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13a09f93 DR |
1 | /* |
2 | * Driver for Motorola PCAP2 as present in EZX phones | |
3 | * | |
4 | * Copyright (C) 2006 Harald Welte <laforge@openezx.org> | |
5 | * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/mfd/ezx-pcap.h> | |
19 | #include <linux/spi/spi.h> | |
b1148fd4 | 20 | #include <linux/gpio.h> |
13a09f93 DR |
21 | |
22 | #define PCAP_ADC_MAXQ 8 | |
23 | struct pcap_adc_request { | |
24 | u8 bank; | |
25 | u8 ch[2]; | |
26 | u32 flags; | |
27 | void (*callback)(void *, u16[]); | |
28 | void *data; | |
29 | }; | |
30 | ||
31 | struct pcap_adc_sync_request { | |
32 | u16 res[2]; | |
33 | struct completion completion; | |
34 | }; | |
35 | ||
36 | struct pcap_chip { | |
37 | struct spi_device *spi; | |
38 | ||
39 | /* IO */ | |
40 | u32 buf; | |
41 | struct mutex io_mutex; | |
42 | ||
43 | /* IRQ */ | |
44 | unsigned int irq_base; | |
45 | u32 msr; | |
46 | struct work_struct isr_work; | |
47 | struct work_struct msr_work; | |
48 | struct workqueue_struct *workqueue; | |
49 | ||
50 | /* ADC */ | |
51 | struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ]; | |
52 | u8 adc_head; | |
53 | u8 adc_tail; | |
54 | struct mutex adc_mutex; | |
55 | }; | |
56 | ||
57 | /* IO */ | |
58 | static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data) | |
59 | { | |
60 | struct spi_transfer t; | |
61 | struct spi_message m; | |
62 | int status; | |
63 | ||
64 | memset(&t, 0, sizeof t); | |
65 | spi_message_init(&m); | |
66 | t.len = sizeof(u32); | |
67 | spi_message_add_tail(&t, &m); | |
68 | ||
69 | pcap->buf = *data; | |
70 | t.tx_buf = (u8 *) &pcap->buf; | |
71 | t.rx_buf = (u8 *) &pcap->buf; | |
72 | status = spi_sync(pcap->spi, &m); | |
73 | ||
74 | if (status == 0) | |
75 | *data = pcap->buf; | |
76 | ||
77 | return status; | |
78 | } | |
79 | ||
80 | int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value) | |
81 | { | |
82 | int ret; | |
83 | ||
84 | mutex_lock(&pcap->io_mutex); | |
85 | value &= PCAP_REGISTER_VALUE_MASK; | |
86 | value |= PCAP_REGISTER_WRITE_OP_BIT | |
87 | | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); | |
88 | ret = ezx_pcap_putget(pcap, &value); | |
89 | mutex_unlock(&pcap->io_mutex); | |
90 | ||
91 | return ret; | |
92 | } | |
93 | EXPORT_SYMBOL_GPL(ezx_pcap_write); | |
94 | ||
95 | int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value) | |
96 | { | |
97 | int ret; | |
98 | ||
99 | mutex_lock(&pcap->io_mutex); | |
100 | *value = PCAP_REGISTER_READ_OP_BIT | |
101 | | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); | |
102 | ||
103 | ret = ezx_pcap_putget(pcap, value); | |
104 | mutex_unlock(&pcap->io_mutex); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | EXPORT_SYMBOL_GPL(ezx_pcap_read); | |
109 | ||
110 | /* IRQ */ | |
9f7b07d6 | 111 | int irq_to_pcap(struct pcap_chip *pcap, int irq) |
13a09f93 | 112 | { |
9f7b07d6 | 113 | return irq - pcap->irq_base; |
13a09f93 | 114 | } |
9f7b07d6 | 115 | EXPORT_SYMBOL_GPL(irq_to_pcap); |
13a09f93 DR |
116 | |
117 | int pcap_to_irq(struct pcap_chip *pcap, int irq) | |
118 | { | |
119 | return pcap->irq_base + irq; | |
120 | } | |
121 | EXPORT_SYMBOL_GPL(pcap_to_irq); | |
122 | ||
123 | static void pcap_mask_irq(unsigned int irq) | |
124 | { | |
125 | struct pcap_chip *pcap = get_irq_chip_data(irq); | |
126 | ||
9f7b07d6 | 127 | pcap->msr |= 1 << irq_to_pcap(pcap, irq); |
13a09f93 DR |
128 | queue_work(pcap->workqueue, &pcap->msr_work); |
129 | } | |
130 | ||
131 | static void pcap_unmask_irq(unsigned int irq) | |
132 | { | |
133 | struct pcap_chip *pcap = get_irq_chip_data(irq); | |
134 | ||
9f7b07d6 | 135 | pcap->msr &= ~(1 << irq_to_pcap(pcap, irq)); |
13a09f93 DR |
136 | queue_work(pcap->workqueue, &pcap->msr_work); |
137 | } | |
138 | ||
139 | static struct irq_chip pcap_irq_chip = { | |
140 | .name = "pcap", | |
141 | .mask = pcap_mask_irq, | |
142 | .unmask = pcap_unmask_irq, | |
143 | }; | |
144 | ||
145 | static void pcap_msr_work(struct work_struct *work) | |
146 | { | |
147 | struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work); | |
148 | ||
149 | ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); | |
150 | } | |
151 | ||
152 | static void pcap_isr_work(struct work_struct *work) | |
153 | { | |
154 | struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work); | |
155 | struct pcap_platform_data *pdata = pcap->spi->dev.platform_data; | |
156 | u32 msr, isr, int_sel, service; | |
157 | int irq; | |
158 | ||
b1148fd4 DR |
159 | do { |
160 | ezx_pcap_read(pcap, PCAP_REG_MSR, &msr); | |
161 | ezx_pcap_read(pcap, PCAP_REG_ISR, &isr); | |
13a09f93 | 162 | |
b1148fd4 DR |
163 | /* We cant service/ack irqs that are assigned to port 2 */ |
164 | if (!(pdata->config & PCAP_SECOND_PORT)) { | |
165 | ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); | |
166 | isr &= ~int_sel; | |
167 | } | |
13a09f93 | 168 | |
b1148fd4 DR |
169 | ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr); |
170 | ezx_pcap_write(pcap, PCAP_REG_ISR, isr); | |
13a09f93 | 171 | |
b1148fd4 DR |
172 | local_irq_disable(); |
173 | service = isr & ~msr; | |
174 | for (irq = pcap->irq_base; service; service >>= 1, irq++) { | |
175 | if (service & 1) { | |
176 | struct irq_desc *desc = irq_to_desc(irq); | |
13a09f93 | 177 | |
b1148fd4 DR |
178 | if (WARN(!desc, KERN_WARNING |
179 | "Invalid PCAP IRQ %d\n", irq)) | |
180 | break; | |
13a09f93 | 181 | |
b1148fd4 DR |
182 | if (desc->status & IRQ_DISABLED) |
183 | note_interrupt(irq, desc, IRQ_NONE); | |
184 | else | |
185 | desc->handle_irq(irq, desc); | |
186 | } | |
13a09f93 | 187 | } |
b1148fd4 DR |
188 | local_irq_enable(); |
189 | ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); | |
190 | } while (gpio_get_value(irq_to_gpio(pcap->spi->irq))); | |
13a09f93 DR |
191 | } |
192 | ||
193 | static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc) | |
194 | { | |
195 | struct pcap_chip *pcap = get_irq_data(irq); | |
196 | ||
197 | desc->chip->ack(irq); | |
198 | queue_work(pcap->workqueue, &pcap->isr_work); | |
199 | return; | |
200 | } | |
201 | ||
202 | /* ADC */ | |
ecd78cbd DR |
203 | void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits) |
204 | { | |
205 | u32 tmp; | |
206 | ||
207 | mutex_lock(&pcap->adc_mutex); | |
208 | ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); | |
209 | tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); | |
210 | tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); | |
211 | ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); | |
212 | mutex_unlock(&pcap->adc_mutex); | |
213 | } | |
214 | EXPORT_SYMBOL_GPL(pcap_set_ts_bits); | |
215 | ||
13a09f93 DR |
216 | static void pcap_disable_adc(struct pcap_chip *pcap) |
217 | { | |
218 | u32 tmp; | |
219 | ||
220 | ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); | |
221 | tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY); | |
222 | ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); | |
223 | } | |
224 | ||
225 | static void pcap_adc_trigger(struct pcap_chip *pcap) | |
226 | { | |
227 | u32 tmp; | |
228 | u8 head; | |
229 | ||
230 | mutex_lock(&pcap->adc_mutex); | |
231 | head = pcap->adc_head; | |
232 | if (!pcap->adc_queue[head]) { | |
233 | /* queue is empty, save power */ | |
234 | pcap_disable_adc(pcap); | |
235 | mutex_unlock(&pcap->adc_mutex); | |
236 | return; | |
237 | } | |
ecd78cbd DR |
238 | /* start conversion on requested bank, save TS_M bits */ |
239 | ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); | |
240 | tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); | |
241 | tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN; | |
13a09f93 DR |
242 | |
243 | if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1) | |
244 | tmp |= PCAP_ADC_AD_SEL1; | |
245 | ||
246 | ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); | |
ecd78cbd | 247 | mutex_unlock(&pcap->adc_mutex); |
13a09f93 DR |
248 | ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC); |
249 | } | |
250 | ||
251 | static irqreturn_t pcap_adc_irq(int irq, void *_pcap) | |
252 | { | |
253 | struct pcap_chip *pcap = _pcap; | |
254 | struct pcap_adc_request *req; | |
255 | u16 res[2]; | |
256 | u32 tmp; | |
257 | ||
258 | mutex_lock(&pcap->adc_mutex); | |
259 | req = pcap->adc_queue[pcap->adc_head]; | |
260 | ||
1c90ea2c DR |
261 | if (WARN(!req, KERN_WARNING "adc irq without pending request\n")) { |
262 | mutex_unlock(&pcap->adc_mutex); | |
13a09f93 | 263 | return IRQ_HANDLED; |
1c90ea2c | 264 | } |
13a09f93 DR |
265 | |
266 | /* read requested channels results */ | |
267 | ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); | |
268 | tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK); | |
269 | tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT); | |
270 | tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT); | |
271 | ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); | |
272 | ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp); | |
273 | res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT; | |
274 | res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT; | |
275 | ||
276 | pcap->adc_queue[pcap->adc_head] = NULL; | |
277 | pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1); | |
278 | mutex_unlock(&pcap->adc_mutex); | |
279 | ||
280 | /* pass the results and release memory */ | |
281 | req->callback(req->data, res); | |
282 | kfree(req); | |
283 | ||
284 | /* trigger next conversion (if any) on queue */ | |
285 | pcap_adc_trigger(pcap); | |
286 | ||
287 | return IRQ_HANDLED; | |
288 | } | |
289 | ||
290 | int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[], | |
291 | void *callback, void *data) | |
292 | { | |
293 | struct pcap_adc_request *req; | |
294 | ||
295 | /* This will be freed after we have a result */ | |
296 | req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL); | |
297 | if (!req) | |
298 | return -ENOMEM; | |
299 | ||
300 | req->bank = bank; | |
301 | req->flags = flags; | |
302 | req->ch[0] = ch[0]; | |
303 | req->ch[1] = ch[1]; | |
304 | req->callback = callback; | |
305 | req->data = data; | |
306 | ||
307 | mutex_lock(&pcap->adc_mutex); | |
308 | if (pcap->adc_queue[pcap->adc_tail]) { | |
309 | mutex_unlock(&pcap->adc_mutex); | |
310 | kfree(req); | |
311 | return -EBUSY; | |
312 | } | |
313 | pcap->adc_queue[pcap->adc_tail] = req; | |
314 | pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1); | |
315 | mutex_unlock(&pcap->adc_mutex); | |
316 | ||
317 | /* start conversion */ | |
318 | pcap_adc_trigger(pcap); | |
319 | ||
320 | return 0; | |
321 | } | |
322 | EXPORT_SYMBOL_GPL(pcap_adc_async); | |
323 | ||
324 | static void pcap_adc_sync_cb(void *param, u16 res[]) | |
325 | { | |
326 | struct pcap_adc_sync_request *req = param; | |
327 | ||
328 | req->res[0] = res[0]; | |
329 | req->res[1] = res[1]; | |
330 | complete(&req->completion); | |
331 | } | |
332 | ||
333 | int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[], | |
334 | u16 res[]) | |
335 | { | |
336 | struct pcap_adc_sync_request sync_data; | |
337 | int ret; | |
338 | ||
339 | init_completion(&sync_data.completion); | |
340 | ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb, | |
341 | &sync_data); | |
342 | if (ret) | |
343 | return ret; | |
344 | wait_for_completion(&sync_data.completion); | |
345 | res[0] = sync_data.res[0]; | |
346 | res[1] = sync_data.res[1]; | |
347 | ||
348 | return 0; | |
349 | } | |
350 | EXPORT_SYMBOL_GPL(pcap_adc_sync); | |
351 | ||
352 | /* subdevs */ | |
353 | static int pcap_remove_subdev(struct device *dev, void *unused) | |
354 | { | |
355 | platform_device_unregister(to_platform_device(dev)); | |
356 | return 0; | |
357 | } | |
358 | ||
359 | static int __devinit pcap_add_subdev(struct pcap_chip *pcap, | |
360 | struct pcap_subdev *subdev) | |
361 | { | |
362 | struct platform_device *pdev; | |
363 | ||
364 | pdev = platform_device_alloc(subdev->name, subdev->id); | |
365 | pdev->dev.parent = &pcap->spi->dev; | |
366 | pdev->dev.platform_data = subdev->platform_data; | |
367 | platform_set_drvdata(pdev, pcap); | |
368 | ||
369 | return platform_device_add(pdev); | |
370 | } | |
371 | ||
372 | static int __devexit ezx_pcap_remove(struct spi_device *spi) | |
373 | { | |
374 | struct pcap_chip *pcap = dev_get_drvdata(&spi->dev); | |
375 | struct pcap_platform_data *pdata = spi->dev.platform_data; | |
376 | int i, adc_irq; | |
377 | ||
378 | /* remove all registered subdevs */ | |
379 | device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); | |
380 | ||
381 | /* cleanup ADC */ | |
382 | adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ? | |
383 | PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE); | |
384 | free_irq(adc_irq, pcap); | |
385 | mutex_lock(&pcap->adc_mutex); | |
386 | for (i = 0; i < PCAP_ADC_MAXQ; i++) | |
387 | kfree(pcap->adc_queue[i]); | |
388 | mutex_unlock(&pcap->adc_mutex); | |
389 | ||
390 | /* cleanup irqchip */ | |
391 | for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) | |
392 | set_irq_chip_and_handler(i, NULL, NULL); | |
393 | ||
394 | destroy_workqueue(pcap->workqueue); | |
395 | ||
396 | kfree(pcap); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int __devinit ezx_pcap_probe(struct spi_device *spi) | |
402 | { | |
403 | struct pcap_platform_data *pdata = spi->dev.platform_data; | |
404 | struct pcap_chip *pcap; | |
405 | int i, adc_irq; | |
406 | int ret = -ENODEV; | |
407 | ||
408 | /* platform data is required */ | |
409 | if (!pdata) | |
410 | goto ret; | |
411 | ||
412 | pcap = kzalloc(sizeof(*pcap), GFP_KERNEL); | |
413 | if (!pcap) { | |
414 | ret = -ENOMEM; | |
415 | goto ret; | |
416 | } | |
417 | ||
418 | mutex_init(&pcap->io_mutex); | |
419 | mutex_init(&pcap->adc_mutex); | |
420 | INIT_WORK(&pcap->isr_work, pcap_isr_work); | |
421 | INIT_WORK(&pcap->msr_work, pcap_msr_work); | |
422 | dev_set_drvdata(&spi->dev, pcap); | |
423 | ||
424 | /* setup spi */ | |
425 | spi->bits_per_word = 32; | |
426 | spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0); | |
427 | ret = spi_setup(spi); | |
428 | if (ret) | |
429 | goto free_pcap; | |
430 | ||
431 | pcap->spi = spi; | |
432 | ||
433 | /* setup irq */ | |
434 | pcap->irq_base = pdata->irq_base; | |
435 | pcap->workqueue = create_singlethread_workqueue("pcapd"); | |
436 | if (!pcap->workqueue) { | |
437 | dev_err(&spi->dev, "cant create pcap thread\n"); | |
438 | goto free_pcap; | |
439 | } | |
440 | ||
441 | /* redirect interrupts to AP, except adcdone2 */ | |
442 | if (!(pdata->config & PCAP_SECOND_PORT)) | |
443 | ezx_pcap_write(pcap, PCAP_REG_INT_SEL, | |
444 | (1 << PCAP_IRQ_ADCDONE2)); | |
445 | ||
446 | /* setup irq chip */ | |
447 | for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) { | |
448 | set_irq_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq); | |
449 | set_irq_chip_data(i, pcap); | |
450 | #ifdef CONFIG_ARM | |
451 | set_irq_flags(i, IRQF_VALID); | |
452 | #else | |
453 | set_irq_noprobe(i); | |
454 | #endif | |
455 | } | |
456 | ||
457 | /* mask/ack all PCAP interrupts */ | |
458 | ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT); | |
459 | ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER); | |
460 | pcap->msr = PCAP_MASK_ALL_INTERRUPT; | |
461 | ||
462 | set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING); | |
463 | set_irq_data(spi->irq, pcap); | |
464 | set_irq_chained_handler(spi->irq, pcap_irq_handler); | |
465 | set_irq_wake(spi->irq, 1); | |
466 | ||
467 | /* ADC */ | |
468 | adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ? | |
469 | PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE); | |
470 | ||
471 | ret = request_irq(adc_irq, pcap_adc_irq, 0, "ADC", pcap); | |
472 | if (ret) | |
473 | goto free_irqchip; | |
474 | ||
475 | /* setup subdevs */ | |
476 | for (i = 0; i < pdata->num_subdevs; i++) { | |
477 | ret = pcap_add_subdev(pcap, &pdata->subdevs[i]); | |
478 | if (ret) | |
479 | goto remove_subdevs; | |
480 | } | |
481 | ||
482 | /* board specific quirks */ | |
483 | if (pdata->init) | |
484 | pdata->init(pcap); | |
485 | ||
486 | return 0; | |
487 | ||
488 | remove_subdevs: | |
489 | device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); | |
490 | /* free_adc: */ | |
491 | free_irq(adc_irq, pcap); | |
492 | free_irqchip: | |
493 | for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) | |
494 | set_irq_chip_and_handler(i, NULL, NULL); | |
495 | /* destroy_workqueue: */ | |
496 | destroy_workqueue(pcap->workqueue); | |
497 | free_pcap: | |
498 | kfree(pcap); | |
499 | ret: | |
500 | return ret; | |
501 | } | |
502 | ||
503 | static struct spi_driver ezxpcap_driver = { | |
504 | .probe = ezx_pcap_probe, | |
505 | .remove = __devexit_p(ezx_pcap_remove), | |
506 | .driver = { | |
507 | .name = "ezx-pcap", | |
508 | .owner = THIS_MODULE, | |
509 | }, | |
510 | }; | |
511 | ||
512 | static int __init ezx_pcap_init(void) | |
513 | { | |
514 | return spi_register_driver(&ezxpcap_driver); | |
515 | } | |
516 | ||
517 | static void __exit ezx_pcap_exit(void) | |
518 | { | |
519 | spi_unregister_driver(&ezxpcap_driver); | |
520 | } | |
521 | ||
522 | module_init(ezx_pcap_init); | |
523 | module_exit(ezx_pcap_exit); | |
524 | ||
525 | MODULE_LICENSE("GPL"); | |
526 | MODULE_AUTHOR("Daniel Ribeiro / Harald Welte"); | |
527 | MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver"); |