[linux-2.6-block.git] / drivers / mfd / ezx-pcap.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Motorola PCAP2 as present in EZX phones
 *
 * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
 * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/ezx-pcap.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#define PCAP_ADC_MAXQ		8
struct pcap_adc_request {
	u8 bank;
	u8 ch[2];
	u32 flags;
	void (*callback)(void *, u16[]);
	void *data;
};

struct pcap_adc_sync_request {
	u16 res[2];
	struct completion completion;
};

struct pcap_chip {
	struct spi_device *spi;

	/* IO */
	u32 buf;
	spinlock_t io_lock;

	/* IRQ */
	unsigned int irq_base;
	u32 msr;
	struct work_struct isr_work;
	struct work_struct msr_work;
	struct workqueue_struct *workqueue;

	/* ADC */
	struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
	u8 adc_head;
	u8 adc_tail;
	spinlock_t adc_lock;
};

/* IO */
static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
{
	struct spi_transfer t;
	struct spi_message m;
	int status;

	memset(&t, 0, sizeof(t));
	spi_message_init(&m);
	t.len = sizeof(u32);
	spi_message_add_tail(&t, &m);

	pcap->buf = *data;
	t.tx_buf = (u8 *) &pcap->buf;
	t.rx_buf = (u8 *) &pcap->buf;
	status = spi_sync(pcap->spi, &m);

	if (status == 0)
		*data = pcap->buf;

	return status;
}

int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pcap->io_lock, flags);
	value &= PCAP_REGISTER_VALUE_MASK;
	value |= PCAP_REGISTER_WRITE_OP_BIT
		| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	ret = ezx_pcap_putget(pcap, &value);
	spin_unlock_irqrestore(&pcap->io_lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_write);

int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pcap->io_lock, flags);
	*value = PCAP_REGISTER_READ_OP_BIT
		| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	ret = ezx_pcap_putget(pcap, value);
	spin_unlock_irqrestore(&pcap->io_lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_read);

int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
{
	unsigned long flags;
	int ret;
	u32 tmp = PCAP_REGISTER_READ_OP_BIT |
		(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	spin_lock_irqsave(&pcap->io_lock, flags);
	ret = ezx_pcap_putget(pcap, &tmp);
	if (ret)
		goto out_unlock;

	tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
	tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
		(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	ret = ezx_pcap_putget(pcap, &tmp);
out_unlock:
	spin_unlock_irqrestore(&pcap->io_lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);

/* IRQ */
int irq_to_pcap(struct pcap_chip *pcap, int irq)
{
	return irq - pcap->irq_base;
}
EXPORT_SYMBOL_GPL(irq_to_pcap);

int pcap_to_irq(struct pcap_chip *pcap, int irq)
{
	return pcap->irq_base + irq;
}
EXPORT_SYMBOL_GPL(pcap_to_irq);

static void pcap_mask_irq(struct irq_data *d)
{
	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);

	pcap->msr |= 1 << irq_to_pcap(pcap, d->irq);
	queue_work(pcap->workqueue, &pcap->msr_work);
}

static void pcap_unmask_irq(struct irq_data *d)
{
	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);

	pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
	queue_work(pcap->workqueue, &pcap->msr_work);
}

static struct irq_chip pcap_irq_chip = {
	.name		= "pcap",
	.irq_disable	= pcap_mask_irq,
	.irq_mask	= pcap_mask_irq,
	.irq_unmask	= pcap_unmask_irq,
};

static void pcap_msr_work(struct work_struct *work)
{
	struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);

	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
}

static void pcap_isr_work(struct work_struct *work)
{
	struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
	struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
	u32 msr, isr, int_sel, service;
	int irq;

	do {
		ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
		ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);

		/* We can't service/ack irqs that are assigned to port 2 */
		if (!(pdata->config & PCAP_SECOND_PORT)) {
			ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
			isr &= ~int_sel;
		}

		ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
		ezx_pcap_write(pcap, PCAP_REG_ISR, isr);

		local_irq_disable();
		service = isr & ~msr;
		for (irq = pcap->irq_base; service; service >>= 1, irq++) {
			if (service & 1)
				generic_handle_irq(irq);
		}
		local_irq_enable();
		ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
	} while (gpio_get_value(pdata->gpio));
}

static void pcap_irq_handler(struct irq_desc *desc)
{
	struct pcap_chip *pcap = irq_desc_get_handler_data(desc);

	desc->irq_data.chip->irq_ack(&desc->irq_data);
	queue_work(pcap->workqueue, &pcap->isr_work);
}

/* ADC */
void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
{
	unsigned long flags;
	u32 tmp;

	spin_lock_irqsave(&pcap->adc_lock, flags);
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	spin_unlock_irqrestore(&pcap->adc_lock, flags);
}
EXPORT_SYMBOL_GPL(pcap_set_ts_bits);

static void pcap_disable_adc(struct pcap_chip *pcap)
{
	u32 tmp;

	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
}

static void pcap_adc_trigger(struct pcap_chip *pcap)
{
	unsigned long flags;
	u32 tmp;
	u8 head;

	spin_lock_irqsave(&pcap->adc_lock, flags);
	head = pcap->adc_head;
	if (!pcap->adc_queue[head]) {
		/* queue is empty, save power */
		pcap_disable_adc(pcap);
		spin_unlock_irqrestore(&pcap->adc_lock, flags);
		return;
	}
	/* start conversion on requested bank, save TS_M bits */
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;

	if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
		tmp |= PCAP_ADC_AD_SEL1;

	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	spin_unlock_irqrestore(&pcap->adc_lock, flags);
	ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
}

static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
{
	struct pcap_chip *pcap = _pcap;
	struct pcap_adc_request *req;
	u16 res[2];
	u32 tmp;

	spin_lock(&pcap->adc_lock);
	req = pcap->adc_queue[pcap->adc_head];

	if (WARN(!req, "adc irq without pending request\n")) {
		spin_unlock(&pcap->adc_lock);
		return IRQ_HANDLED;
	}

	/* read requested channels results */
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
	tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
	tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
	res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
	res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;

	pcap->adc_queue[pcap->adc_head] = NULL;
	pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
	spin_unlock(&pcap->adc_lock);

	/* pass the results and release memory */
	req->callback(req->data, res);
	kfree(req);

	/* trigger next conversion (if any) on queue */
	pcap_adc_trigger(pcap);

	return IRQ_HANDLED;
}

int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
						void *callback, void *data)
{
	struct pcap_adc_request *req;
	unsigned long irq_flags;

	/* This will be freed after we have a result */
	req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
	if (!req)
		return -ENOMEM;

	req->bank = bank;
	req->flags = flags;
	req->ch[0] = ch[0];
	req->ch[1] = ch[1];
	req->callback = callback;
	req->data = data;

	spin_lock_irqsave(&pcap->adc_lock, irq_flags);
	if (pcap->adc_queue[pcap->adc_tail]) {
		spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
		kfree(req);
		return -EBUSY;
	}
	pcap->adc_queue[pcap->adc_tail] = req;
	pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
	spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);

	/* start conversion */
	pcap_adc_trigger(pcap);

	return 0;
}
EXPORT_SYMBOL_GPL(pcap_adc_async);

static void pcap_adc_sync_cb(void *param, u16 res[])
{
	struct pcap_adc_sync_request *req = param;

	req->res[0] = res[0];
	req->res[1] = res[1];
	complete(&req->completion);
}

int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
								u16 res[])
{
	struct pcap_adc_sync_request sync_data;
	int ret;

	init_completion(&sync_data.completion);
	ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
								&sync_data);
	if (ret)
		return ret;
	wait_for_completion(&sync_data.completion);
	res[0] = sync_data.res[0];
	res[1] = sync_data.res[1];

	return 0;
}
EXPORT_SYMBOL_GPL(pcap_adc_sync);

/* subdevs */
static int pcap_remove_subdev(struct device *dev, void *unused)
{
	platform_device_unregister(to_platform_device(dev));
	return 0;
}

static int pcap_add_subdev(struct pcap_chip *pcap,
						struct pcap_subdev *subdev)
{
	struct platform_device *pdev;
	int ret;

	pdev = platform_device_alloc(subdev->name, subdev->id);
	if (!pdev)
		return -ENOMEM;

	pdev->dev.parent = &pcap->spi->dev;
	pdev->dev.platform_data = subdev->platform_data;

	ret = platform_device_add(pdev);
	if (ret)
		platform_device_put(pdev);

	return ret;
}

static int ezx_pcap_remove(struct spi_device *spi)
{
	struct pcap_chip *pcap = spi_get_drvdata(spi);
	unsigned long flags;
	int i;

	/* remove all registered subdevs */
	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);

	/* cleanup ADC */
	spin_lock_irqsave(&pcap->adc_lock, flags);
	for (i = 0; i < PCAP_ADC_MAXQ; i++)
		kfree(pcap->adc_queue[i]);
	spin_unlock_irqrestore(&pcap->adc_lock, flags);

	/* cleanup irqchip */
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
		irq_set_chip_and_handler(i, NULL, NULL);

	destroy_workqueue(pcap->workqueue);

	return 0;
}

static int ezx_pcap_probe(struct spi_device *spi)
{
	struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
	struct pcap_chip *pcap;
	int i, adc_irq;
	int ret = -ENODEV;

	/* platform data is required */
	if (!pdata)
		goto ret;

	pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
	if (!pcap) {
		ret = -ENOMEM;
		goto ret;
	}

	spin_lock_init(&pcap->io_lock);
	spin_lock_init(&pcap->adc_lock);
	INIT_WORK(&pcap->isr_work, pcap_isr_work);
	INIT_WORK(&pcap->msr_work, pcap_msr_work);
	spi_set_drvdata(spi, pcap);

	/* setup spi */
	spi->bits_per_word = 32;
	spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
	ret = spi_setup(spi);
	if (ret)
		goto ret;

	pcap->spi = spi;

	/* setup irq */
	pcap->irq_base = pdata->irq_base;
	pcap->workqueue = create_singlethread_workqueue("pcapd");
	if (!pcap->workqueue) {
		ret = -ENOMEM;
		dev_err(&spi->dev, "can't create pcap thread\n");
		goto ret;
	}

	/* redirect interrupts to AP, except adcdone2 */
	if (!(pdata->config & PCAP_SECOND_PORT))
		ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
					(1 << PCAP_IRQ_ADCDONE2));

	/* setup irq chip */
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
		irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
		irq_set_chip_data(i, pcap);
		irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
	}

	/* mask/ack all PCAP interrupts */
	ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
	ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
	pcap->msr = PCAP_MASK_ALL_INTERRUPT;

	irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
	irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
	irq_set_irq_wake(spi->irq, 1);

	/* ADC */
	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
					PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);

	ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
				pcap);
	if (ret)
		goto free_irqchip;

	/* setup subdevs */
	for (i = 0; i < pdata->num_subdevs; i++) {
		ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
		if (ret)
			goto remove_subdevs;
	}

	/* board specific quirks */
	if (pdata->init)
		pdata->init(pcap);

	return 0;

remove_subdevs:
	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
free_irqchip:
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
		irq_set_chip_and_handler(i, NULL, NULL);
/* destroy_workqueue: */
	destroy_workqueue(pcap->workqueue);
ret:
	return ret;
}

static struct spi_driver ezxpcap_driver = {
	.probe	= ezx_pcap_probe,
	.remove = ezx_pcap_remove,
	.driver = {
		.name	= "ezx-pcap",
	},
};

static int __init ezx_pcap_init(void)
{
	return spi_register_driver(&ezxpcap_driver);
}

static void __exit ezx_pcap_exit(void)
{
	spi_unregister_driver(&ezxpcap_driver);
}

subsys_initcall(ezx_pcap_init);
module_exit(ezx_pcap_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
MODULE_ALIAS("spi:ezx-pcap");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
13a09f93 DR	2	/*
	3	* Driver for Motorola PCAP2 as present in EZX phones
	4	*
	5	* Copyright (C) 2006 Harald Welte <laforge@openezx.org>
	6	* Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
13a09f93 DR	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/kernel.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14	#include <linux/mfd/ezx-pcap.h>
	15	#include <linux/spi/spi.h>
b1148fd4	16	#include <linux/gpio.h>
5a0e3ad6	17	#include <linux/slab.h>
13a09f93 DR	18
	19	#define PCAP_ADC_MAXQ 8
	20	struct pcap_adc_request {
	21	u8 bank;
	22	u8 ch[2];
	23	u32 flags;
	24	void (callback)(void , u16[]);
	25	void *data;
	26	};
	27
	28	struct pcap_adc_sync_request {
	29	u16 res[2];
	30	struct completion completion;
	31	};
	32
	33	struct pcap_chip {
	34	struct spi_device *spi;
	35
	36	/* IO */
	37	u32 buf;
b65dc4f6	38	spinlock_t io_lock;
13a09f93 DR	39
	40	/* IRQ */
	41	unsigned int irq_base;
	42	u32 msr;
	43	struct work_struct isr_work;
	44	struct work_struct msr_work;
	45	struct workqueue_struct *workqueue;
	46
	47	/* ADC */
	48	struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
	49	u8 adc_head;
	50	u8 adc_tail;
b65dc4f6	51	spinlock_t adc_lock;
13a09f93 DR	52	};
	53
	54	/* IO */
	55	static int ezx_pcap_putget(struct pcap_chip pcap, u32 data)
	56	{
	57	struct spi_transfer t;
	58	struct spi_message m;
	59	int status;
	60
0309528a	61	memset(&t, 0, sizeof(t));
13a09f93 DR	62	spi_message_init(&m);
	63	t.len = sizeof(u32);
	64	spi_message_add_tail(&t, &m);
	65
	66	pcap->buf = *data;
	67	t.tx_buf = (u8 *) &pcap->buf;
	68	t.rx_buf = (u8 *) &pcap->buf;
	69	status = spi_sync(pcap->spi, &m);
	70
	71	if (status == 0)
	72	*data = pcap->buf;
	73
	74	return status;
	75	}
	76
	77	int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
	78	{
b65dc4f6	79	unsigned long flags;
13a09f93 DR	80	int ret;
13a09f93 DR	81
b65dc4f6	82	spin_lock_irqsave(&pcap->io_lock, flags);
13a09f93 DR	83	value &= PCAP_REGISTER_VALUE_MASK;
	84	value \|= PCAP_REGISTER_WRITE_OP_BIT
	85	\| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	86	ret = ezx_pcap_putget(pcap, &value);
b65dc4f6	87	spin_unlock_irqrestore(&pcap->io_lock, flags);
13a09f93 DR	88
	89	return ret;
	90	}
	91	EXPORT_SYMBOL_GPL(ezx_pcap_write);
	92
	93	int ezx_pcap_read(struct pcap_chip pcap, u8 reg_num, u32 value)
	94	{
b65dc4f6	95	unsigned long flags;
13a09f93 DR	96	int ret;
13a09f93 DR	97
b65dc4f6	98	spin_lock_irqsave(&pcap->io_lock, flags);
13a09f93 DR	99	*value = PCAP_REGISTER_READ_OP_BIT
	100	\| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	101
	102	ret = ezx_pcap_putget(pcap, value);
b65dc4f6	103	spin_unlock_irqrestore(&pcap->io_lock, flags);
13a09f93 DR	104
	105	return ret;
	106	}
	107	EXPORT_SYMBOL_GPL(ezx_pcap_read);
	108
e9a22635 DR	109	int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
e9a22635 DR	110	{
b65dc4f6	111	unsigned long flags;
e9a22635 DR	112	int ret;
	113	u32 tmp = PCAP_REGISTER_READ_OP_BIT \|
	114	(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	115
b65dc4f6	116	spin_lock_irqsave(&pcap->io_lock, flags);
e9a22635 DR	117	ret = ezx_pcap_putget(pcap, &tmp);
	118	if (ret)
	119	goto out_unlock;
	120
	121	tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
	122	tmp \|= (val & mask) \| PCAP_REGISTER_WRITE_OP_BIT \|
	123	(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	124
	125	ret = ezx_pcap_putget(pcap, &tmp);
	126	out_unlock:
b65dc4f6	127	spin_unlock_irqrestore(&pcap->io_lock, flags);
e9a22635 DR	128
	129	return ret;
	130	}
	131	EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
	132
13a09f93	133	/* IRQ */
9f7b07d6	134	int irq_to_pcap(struct pcap_chip *pcap, int irq)
13a09f93	135	{
9f7b07d6	136	return irq - pcap->irq_base;
13a09f93	137	}
9f7b07d6	138	EXPORT_SYMBOL_GPL(irq_to_pcap);
13a09f93 DR	139
	140	int pcap_to_irq(struct pcap_chip *pcap, int irq)
	141	{
	142	return pcap->irq_base + irq;
	143	}
	144	EXPORT_SYMBOL_GPL(pcap_to_irq);
	145
c232f22f	146	static void pcap_mask_irq(struct irq_data *d)
13a09f93	147	{
c232f22f	148	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
13a09f93	149
c232f22f	150	pcap->msr \|= 1 << irq_to_pcap(pcap, d->irq);
13a09f93 DR	151	queue_work(pcap->workqueue, &pcap->msr_work);
	152	}
	153
c232f22f	154	static void pcap_unmask_irq(struct irq_data *d)
13a09f93	155	{
c232f22f	156	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
13a09f93	157
c232f22f	158	pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
13a09f93 DR	159	queue_work(pcap->workqueue, &pcap->msr_work);
	160	}
	161
	162	static struct irq_chip pcap_irq_chip = {
c232f22f	163	.name = "pcap",
73a6839f	164	.irq_disable = pcap_mask_irq,
c232f22f LB	165	.irq_mask = pcap_mask_irq,
c232f22f LB	166	.irq_unmask = pcap_unmask_irq,
13a09f93 DR	167	};
	168
	169	static void pcap_msr_work(struct work_struct *work)
	170	{
	171	struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
	172
	173	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
	174	}
	175
	176	static void pcap_isr_work(struct work_struct *work)
	177	{
	178	struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
334a41ce	179	struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
13a09f93 DR	180	u32 msr, isr, int_sel, service;
	181	int irq;
	182
b1148fd4 DR	183	do {
	184	ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
	185	ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
13a09f93	186
25985edc	187	/* We can't service/ack irqs that are assigned to port 2 */
b1148fd4 DR	188	if (!(pdata->config & PCAP_SECOND_PORT)) {
	189	ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
	190	isr &= ~int_sel;
	191	}
13a09f93	192
b1148fd4 DR	193	ezx_pcap_write(pcap, PCAP_REG_MSR, isr \| msr);
b1148fd4 DR	194	ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
13a09f93	195
b1148fd4 DR	196	local_irq_disable();
	197	service = isr & ~msr;
	198	for (irq = pcap->irq_base; service; service >>= 1, irq++) {
73a6839f TG	199	if (service & 1)
73a6839f TG	200	generic_handle_irq(irq);
13a09f93	201	}
b1148fd4 DR	202	local_irq_enable();
b1148fd4 DR	203	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
59ee93a5	204	} while (gpio_get_value(pdata->gpio));
13a09f93 DR	205	}
13a09f93 DR	206
bd0b9ac4	207	static void pcap_irq_handler(struct irq_desc *desc)
13a09f93	208	{
1e84aa44	209	struct pcap_chip *pcap = irq_desc_get_handler_data(desc);
13a09f93	210
c232f22f	211	desc->irq_data.chip->irq_ack(&desc->irq_data);
13a09f93	212	queue_work(pcap->workqueue, &pcap->isr_work);
13a09f93 DR	213	}
	214
	215	/* ADC */
ecd78cbd DR	216	void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
ecd78cbd DR	217	{
b65dc4f6	218	unsigned long flags;
ecd78cbd DR	219	u32 tmp;
ecd78cbd DR	220
b65dc4f6	221	spin_lock_irqsave(&pcap->adc_lock, flags);
ecd78cbd DR	222	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	223	tmp &= ~(PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	224	tmp \|= bits & (PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	225	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
b65dc4f6	226	spin_unlock_irqrestore(&pcap->adc_lock, flags);
ecd78cbd DR	227	}
	228	EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
	229
13a09f93 DR	230	static void pcap_disable_adc(struct pcap_chip *pcap)
	231	{
	232	u32 tmp;
	233
	234	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	235	tmp &= ~(PCAP_ADC_ADEN\|PCAP_ADC_BATT_I_ADC\|PCAP_ADC_BATT_I_POLARITY);
	236	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	237	}
	238
	239	static void pcap_adc_trigger(struct pcap_chip *pcap)
	240	{
b65dc4f6	241	unsigned long flags;
13a09f93 DR	242	u32 tmp;
	243	u8 head;
	244
b65dc4f6	245	spin_lock_irqsave(&pcap->adc_lock, flags);
13a09f93 DR	246	head = pcap->adc_head;
	247	if (!pcap->adc_queue[head]) {
	248	/* queue is empty, save power */
	249	pcap_disable_adc(pcap);
b65dc4f6	250	spin_unlock_irqrestore(&pcap->adc_lock, flags);
13a09f93 DR	251	return;
13a09f93 DR	252	}
ecd78cbd DR	253	/* start conversion on requested bank, save TS_M bits */
	254	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	255	tmp &= (PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	256	tmp \|= pcap->adc_queue[head]->flags \| PCAP_ADC_ADEN;
13a09f93 DR	257
	258	if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
	259	tmp \|= PCAP_ADC_AD_SEL1;
	260
	261	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
b65dc4f6	262	spin_unlock_irqrestore(&pcap->adc_lock, flags);
13a09f93 DR	263	ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
	264	}
	265
	266	static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
	267	{
	268	struct pcap_chip *pcap = _pcap;
	269	struct pcap_adc_request *req;
	270	u16 res[2];
	271	u32 tmp;
	272
b65dc4f6	273	spin_lock(&pcap->adc_lock);
13a09f93 DR	274	req = pcap->adc_queue[pcap->adc_head];
13a09f93 DR	275
e0084aa9	276	if (WARN(!req, "adc irq without pending request\n")) {
b65dc4f6	277	spin_unlock(&pcap->adc_lock);
13a09f93	278	return IRQ_HANDLED;
1c90ea2c	279	}
13a09f93 DR	280
	281	/* read requested channels results */
	282	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	283	tmp &= ~(PCAP_ADC_ADA1_MASK \| PCAP_ADC_ADA2_MASK);
	284	tmp \|= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
	285	tmp \|= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
	286	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	287	ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
	288	res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
	289	res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
	290
	291	pcap->adc_queue[pcap->adc_head] = NULL;
	292	pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
b65dc4f6	293	spin_unlock(&pcap->adc_lock);
13a09f93 DR	294
	295	/* pass the results and release memory */
	296	req->callback(req->data, res);
	297	kfree(req);
	298
	299	/* trigger next conversion (if any) on queue */
	300	pcap_adc_trigger(pcap);
	301
	302	return IRQ_HANDLED;
	303	}
	304
	305	int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
	306	void callback, void data)
	307	{
	308	struct pcap_adc_request *req;
b65dc4f6	309	unsigned long irq_flags;
13a09f93 DR	310
	311	/* This will be freed after we have a result */
	312	req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
	313	if (!req)
	314	return -ENOMEM;
	315
	316	req->bank = bank;
	317	req->flags = flags;
	318	req->ch[0] = ch[0];
	319	req->ch[1] = ch[1];
	320	req->callback = callback;
	321	req->data = data;
	322
b65dc4f6	323	spin_lock_irqsave(&pcap->adc_lock, irq_flags);
13a09f93	324	if (pcap->adc_queue[pcap->adc_tail]) {
b65dc4f6	325	spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
13a09f93 DR	326	kfree(req);
	327	return -EBUSY;
	328	}
	329	pcap->adc_queue[pcap->adc_tail] = req;
	330	pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
b65dc4f6	331	spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
13a09f93 DR	332
	333	/* start conversion */
	334	pcap_adc_trigger(pcap);
	335
	336	return 0;
	337	}
	338	EXPORT_SYMBOL_GPL(pcap_adc_async);
	339
	340	static void pcap_adc_sync_cb(void *param, u16 res[])
	341	{
	342	struct pcap_adc_sync_request *req = param;
	343
	344	req->res[0] = res[0];
	345	req->res[1] = res[1];
	346	complete(&req->completion);
	347	}
	348
	349	int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
	350	u16 res[])
	351	{
	352	struct pcap_adc_sync_request sync_data;
	353	int ret;
	354
	355	init_completion(&sync_data.completion);
	356	ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
	357	&sync_data);
	358	if (ret)
	359	return ret;
	360	wait_for_completion(&sync_data.completion);
	361	res[0] = sync_data.res[0];
	362	res[1] = sync_data.res[1];
	363
	364	return 0;
	365	}
	366	EXPORT_SYMBOL_GPL(pcap_adc_sync);
	367
	368	/* subdevs */
	369	static int pcap_remove_subdev(struct device dev, void unused)
	370	{
	371	platform_device_unregister(to_platform_device(dev));
	372	return 0;
	373	}
	374
f791be49	375	static int pcap_add_subdev(struct pcap_chip *pcap,
13a09f93 DR	376	struct pcap_subdev *subdev)
	377	{
	378	struct platform_device *pdev;
09ff21e0	379	int ret;
13a09f93 DR	380
13a09f93 DR	381	pdev = platform_device_alloc(subdev->name, subdev->id);
09ff21e0 AL	382	if (!pdev)
	383	return -ENOMEM;
	384
13a09f93 DR	385	pdev->dev.parent = &pcap->spi->dev;
13a09f93 DR	386	pdev->dev.platform_data = subdev->platform_data;
13a09f93	387
09ff21e0 AL	388	ret = platform_device_add(pdev);
	389	if (ret)
	390	platform_device_put(pdev);
	391
	392	return ret;
13a09f93 DR	393	}
13a09f93 DR	394
4740f73f	395	static int ezx_pcap_remove(struct spi_device *spi)
13a09f93	396	{
7c478b40	397	struct pcap_chip *pcap = spi_get_drvdata(spi);
b65dc4f6	398	unsigned long flags;
89720264	399	int i;
13a09f93 DR	400
	401	/* remove all registered subdevs */
	402	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
	403
	404	/* cleanup ADC */
b65dc4f6	405	spin_lock_irqsave(&pcap->adc_lock, flags);
13a09f93 DR	406	for (i = 0; i < PCAP_ADC_MAXQ; i++)
13a09f93 DR	407	kfree(pcap->adc_queue[i]);
b65dc4f6	408	spin_unlock_irqrestore(&pcap->adc_lock, flags);
13a09f93 DR	409
	410	/* cleanup irqchip */
	411	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
d5bb1221	412	irq_set_chip_and_handler(i, NULL, NULL);
13a09f93 DR	413
	414	destroy_workqueue(pcap->workqueue);
	415
13a09f93 DR	416	return 0;
	417	}
	418
f791be49	419	static int ezx_pcap_probe(struct spi_device *spi)
13a09f93	420	{
334a41ce	421	struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
13a09f93 DR	422	struct pcap_chip *pcap;
	423	int i, adc_irq;
	424	int ret = -ENODEV;
	425
	426	/* platform data is required */
	427	if (!pdata)
	428	goto ret;
	429
1ba895e0	430	pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
13a09f93 DR	431	if (!pcap) {
	432	ret = -ENOMEM;
	433	goto ret;
	434	}
	435
b65dc4f6 FH	436	spin_lock_init(&pcap->io_lock);
b65dc4f6 FH	437	spin_lock_init(&pcap->adc_lock);
13a09f93 DR	438	INIT_WORK(&pcap->isr_work, pcap_isr_work);
13a09f93 DR	439	INIT_WORK(&pcap->msr_work, pcap_msr_work);
7c478b40	440	spi_set_drvdata(spi, pcap);
13a09f93 DR	441
	442	/* setup spi */
	443	spi->bits_per_word = 32;
	444	spi->mode = SPI_MODE_0 \| (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
	445	ret = spi_setup(spi);
	446	if (ret)
1ba895e0	447	goto ret;
13a09f93 DR	448
	449	pcap->spi = spi;
	450
	451	/* setup irq */
	452	pcap->irq_base = pdata->irq_base;
	453	pcap->workqueue = create_singlethread_workqueue("pcapd");
	454	if (!pcap->workqueue) {
47dabaee	455	ret = -ENOMEM;
25985edc	456	dev_err(&spi->dev, "can't create pcap thread\n");
1ba895e0	457	goto ret;
13a09f93 DR	458	}
	459
	460	/* redirect interrupts to AP, except adcdone2 */
	461	if (!(pdata->config & PCAP_SECOND_PORT))
	462	ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
	463	(1 << PCAP_IRQ_ADCDONE2));
	464
	465	/* setup irq chip */
	466	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
d5bb1221 TG	467	irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
d5bb1221 TG	468	irq_set_chip_data(i, pcap);
9bd09f34	469	irq_clear_status_flags(i, IRQ_NOREQUEST \| IRQ_NOPROBE);
13a09f93 DR	470	}
	471
	472	/* mask/ack all PCAP interrupts */
	473	ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
	474	ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
	475	pcap->msr = PCAP_MASK_ALL_INTERRUPT;
	476
d5bb1221	477	irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
c89fc9ac	478	irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
d5bb1221	479	irq_set_irq_wake(spi->irq, 1);
13a09f93 DR	480
	481	/* ADC */
	482	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
	483	PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
	484
1ba895e0 JH	485	ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
1ba895e0 JH	486	pcap);
13a09f93 DR	487	if (ret)
	488	goto free_irqchip;
	489
	490	/* setup subdevs */
	491	for (i = 0; i < pdata->num_subdevs; i++) {
	492	ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
	493	if (ret)
	494	goto remove_subdevs;
	495	}
	496
	497	/* board specific quirks */
	498	if (pdata->init)
	499	pdata->init(pcap);
	500
	501	return 0;
	502
	503	remove_subdevs:
	504	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
13a09f93 DR	505	free_irqchip:
13a09f93 DR	506	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
d5bb1221	507	irq_set_chip_and_handler(i, NULL, NULL);
13a09f93 DR	508	/* destroy_workqueue: */
13a09f93 DR	509	destroy_workqueue(pcap->workqueue);
13a09f93 DR	510	ret:
	511	return ret;
	512	}
	513
	514	static struct spi_driver ezxpcap_driver = {
	515	.probe = ezx_pcap_probe,
84449216	516	.remove = ezx_pcap_remove,
13a09f93 DR	517	.driver = {
13a09f93 DR	518	.name = "ezx-pcap",
13a09f93 DR	519	},
	520	};
	521
	522	static int __init ezx_pcap_init(void)
	523	{
	524	return spi_register_driver(&ezxpcap_driver);
	525	}
	526
	527	static void __exit ezx_pcap_exit(void)
	528	{
	529	spi_unregister_driver(&ezxpcap_driver);
	530	}
	531
f078237b	532	subsys_initcall(ezx_pcap_init);
13a09f93 DR	533	module_exit(ezx_pcap_exit);
	534
	535	MODULE_LICENSE("GPL");
	536	MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
	537	MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
e0626e38	538	MODULE_ALIAS("spi:ezx-pcap");