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e3726fcf | 1 | /* |
e0befb23 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
e3726fcf LW |
4 | * |
5 | * License Terms: GNU General Public License v2 | |
e0befb23 MP |
6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | |
e3726fcf LW |
8 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
9 | * | |
e0befb23 MP |
10 | * U8500 PRCM Unit interface driver |
11 | * | |
e3726fcf | 12 | */ |
e3726fcf | 13 | #include <linux/module.h> |
3df57bcf MN |
14 | #include <linux/kernel.h> |
15 | #include <linux/delay.h> | |
e3726fcf LW |
16 | #include <linux/errno.h> |
17 | #include <linux/err.h> | |
3df57bcf | 18 | #include <linux/spinlock.h> |
e3726fcf | 19 | #include <linux/io.h> |
3df57bcf | 20 | #include <linux/slab.h> |
e3726fcf LW |
21 | #include <linux/mutex.h> |
22 | #include <linux/completion.h> | |
3df57bcf | 23 | #include <linux/irq.h> |
e3726fcf LW |
24 | #include <linux/jiffies.h> |
25 | #include <linux/bitops.h> | |
3df57bcf MN |
26 | #include <linux/fs.h> |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
29 | #include <linux/mfd/core.h> | |
73180f85 | 30 | #include <linux/mfd/dbx500-prcmu.h> |
3a8e39c9 | 31 | #include <linux/mfd/abx500/ab8500.h> |
1032fbfd BJ |
32 | #include <linux/regulator/db8500-prcmu.h> |
33 | #include <linux/regulator/machine.h> | |
c280f45f | 34 | #include <linux/cpufreq.h> |
cc9a0f68 | 35 | #include <asm/hardware/gic.h> |
3df57bcf MN |
36 | #include <mach/hardware.h> |
37 | #include <mach/irqs.h> | |
38 | #include <mach/db8500-regs.h> | |
39 | #include <mach/id.h> | |
73180f85 | 40 | #include "dbx500-prcmu-regs.h" |
3df57bcf MN |
41 | |
42 | /* Offset for the firmware version within the TCPM */ | |
43 | #define PRCMU_FW_VERSION_OFFSET 0xA4 | |
44 | ||
3df57bcf MN |
45 | /* Index of different voltages to be used when accessing AVSData */ |
46 | #define PRCM_AVS_BASE 0x2FC | |
47 | #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) | |
48 | #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) | |
49 | #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) | |
50 | #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) | |
51 | #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) | |
52 | #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) | |
53 | #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) | |
54 | #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) | |
55 | #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) | |
56 | #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) | |
57 | #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) | |
58 | #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) | |
59 | #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) | |
60 | ||
61 | #define PRCM_AVS_VOLTAGE 0 | |
62 | #define PRCM_AVS_VOLTAGE_MASK 0x3f | |
63 | #define PRCM_AVS_ISSLOWSTARTUP 6 | |
64 | #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) | |
65 | #define PRCM_AVS_ISMODEENABLE 7 | |
66 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) | |
67 | ||
68 | #define PRCM_BOOT_STATUS 0xFFF | |
69 | #define PRCM_ROMCODE_A2P 0xFFE | |
70 | #define PRCM_ROMCODE_P2A 0xFFD | |
71 | #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ | |
72 | ||
73 | #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ | |
74 | ||
75 | #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ | |
76 | #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) | |
77 | #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) | |
78 | #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) | |
79 | #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) | |
80 | #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) | |
81 | #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) | |
82 | #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) | |
83 | ||
84 | /* Req Mailboxes */ | |
85 | #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ | |
86 | #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ | |
87 | #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ | |
88 | #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ | |
89 | #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ | |
90 | #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ | |
91 | ||
92 | /* Ack Mailboxes */ | |
93 | #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ | |
94 | #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ | |
95 | #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ | |
96 | #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ | |
97 | #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ | |
98 | #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ | |
99 | ||
100 | /* Mailbox 0 headers */ | |
101 | #define MB0H_POWER_STATE_TRANS 0 | |
102 | #define MB0H_CONFIG_WAKEUPS_EXE 1 | |
103 | #define MB0H_READ_WAKEUP_ACK 3 | |
104 | #define MB0H_CONFIG_WAKEUPS_SLEEP 4 | |
105 | ||
106 | #define MB0H_WAKEUP_EXE 2 | |
107 | #define MB0H_WAKEUP_SLEEP 5 | |
108 | ||
109 | /* Mailbox 0 REQs */ | |
110 | #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) | |
111 | #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) | |
112 | #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) | |
113 | #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) | |
114 | #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) | |
115 | #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) | |
116 | ||
117 | /* Mailbox 0 ACKs */ | |
118 | #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) | |
119 | #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) | |
120 | #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) | |
121 | #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) | |
122 | #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) | |
123 | #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) | |
124 | #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 | |
125 | ||
126 | /* Mailbox 1 headers */ | |
127 | #define MB1H_ARM_APE_OPP 0x0 | |
128 | #define MB1H_RESET_MODEM 0x2 | |
129 | #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 | |
130 | #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 | |
131 | #define MB1H_RELEASE_USB_WAKEUP 0x5 | |
a592c2e2 | 132 | #define MB1H_PLL_ON_OFF 0x6 |
3df57bcf MN |
133 | |
134 | /* Mailbox 1 Requests */ | |
135 | #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) | |
136 | #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) | |
a592c2e2 | 137 | #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) |
6b6fae2b MN |
138 | #define PLL_SOC0_OFF 0x1 |
139 | #define PLL_SOC0_ON 0x2 | |
a592c2e2 MN |
140 | #define PLL_SOC1_OFF 0x4 |
141 | #define PLL_SOC1_ON 0x8 | |
3df57bcf MN |
142 | |
143 | /* Mailbox 1 ACKs */ | |
144 | #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) | |
145 | #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) | |
146 | #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) | |
147 | #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) | |
148 | ||
149 | /* Mailbox 2 headers */ | |
150 | #define MB2H_DPS 0x0 | |
151 | #define MB2H_AUTO_PWR 0x1 | |
152 | ||
153 | /* Mailbox 2 REQs */ | |
154 | #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) | |
155 | #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) | |
156 | #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) | |
157 | #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) | |
158 | #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) | |
159 | #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) | |
160 | #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) | |
161 | #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) | |
162 | #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) | |
163 | #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) | |
164 | ||
165 | /* Mailbox 2 ACKs */ | |
166 | #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) | |
167 | #define HWACC_PWR_ST_OK 0xFE | |
168 | ||
169 | /* Mailbox 3 headers */ | |
170 | #define MB3H_ANC 0x0 | |
171 | #define MB3H_SIDETONE 0x1 | |
172 | #define MB3H_SYSCLK 0xE | |
173 | ||
174 | /* Mailbox 3 Requests */ | |
175 | #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) | |
176 | #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) | |
177 | #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) | |
178 | #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) | |
179 | #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) | |
180 | #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) | |
181 | #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) | |
182 | ||
183 | /* Mailbox 4 headers */ | |
184 | #define MB4H_DDR_INIT 0x0 | |
185 | #define MB4H_MEM_ST 0x1 | |
186 | #define MB4H_HOTDOG 0x12 | |
187 | #define MB4H_HOTMON 0x13 | |
188 | #define MB4H_HOT_PERIOD 0x14 | |
a592c2e2 MN |
189 | #define MB4H_A9WDOG_CONF 0x16 |
190 | #define MB4H_A9WDOG_EN 0x17 | |
191 | #define MB4H_A9WDOG_DIS 0x18 | |
192 | #define MB4H_A9WDOG_LOAD 0x19 | |
193 | #define MB4H_A9WDOG_KICK 0x20 | |
3df57bcf MN |
194 | |
195 | /* Mailbox 4 Requests */ | |
196 | #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) | |
197 | #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) | |
198 | #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) | |
199 | #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) | |
200 | #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) | |
201 | #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) | |
202 | #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) | |
203 | #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) | |
204 | #define HOTMON_CONFIG_LOW BIT(0) | |
205 | #define HOTMON_CONFIG_HIGH BIT(1) | |
a592c2e2 MN |
206 | #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) |
207 | #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) | |
208 | #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) | |
209 | #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) | |
210 | #define A9WDOG_AUTO_OFF_EN BIT(7) | |
211 | #define A9WDOG_AUTO_OFF_DIS 0 | |
212 | #define A9WDOG_ID_MASK 0xf | |
3df57bcf MN |
213 | |
214 | /* Mailbox 5 Requests */ | |
215 | #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) | |
216 | #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) | |
217 | #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) | |
218 | #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) | |
219 | #define PRCMU_I2C_WRITE(slave) \ | |
220 | (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) | |
221 | #define PRCMU_I2C_READ(slave) \ | |
222 | (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) | |
223 | #define PRCMU_I2C_STOP_EN BIT(3) | |
224 | ||
225 | /* Mailbox 5 ACKs */ | |
226 | #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) | |
227 | #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) | |
228 | #define I2C_WR_OK 0x1 | |
229 | #define I2C_RD_OK 0x2 | |
230 | ||
231 | #define NUM_MB 8 | |
232 | #define MBOX_BIT BIT | |
233 | #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) | |
234 | ||
235 | /* | |
236 | * Wakeups/IRQs | |
237 | */ | |
238 | ||
239 | #define WAKEUP_BIT_RTC BIT(0) | |
240 | #define WAKEUP_BIT_RTT0 BIT(1) | |
241 | #define WAKEUP_BIT_RTT1 BIT(2) | |
242 | #define WAKEUP_BIT_HSI0 BIT(3) | |
243 | #define WAKEUP_BIT_HSI1 BIT(4) | |
244 | #define WAKEUP_BIT_CA_WAKE BIT(5) | |
245 | #define WAKEUP_BIT_USB BIT(6) | |
246 | #define WAKEUP_BIT_ABB BIT(7) | |
247 | #define WAKEUP_BIT_ABB_FIFO BIT(8) | |
248 | #define WAKEUP_BIT_SYSCLK_OK BIT(9) | |
249 | #define WAKEUP_BIT_CA_SLEEP BIT(10) | |
250 | #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) | |
251 | #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) | |
252 | #define WAKEUP_BIT_ANC_OK BIT(13) | |
253 | #define WAKEUP_BIT_SW_ERROR BIT(14) | |
254 | #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) | |
255 | #define WAKEUP_BIT_ARM BIT(17) | |
256 | #define WAKEUP_BIT_HOTMON_LOW BIT(18) | |
257 | #define WAKEUP_BIT_HOTMON_HIGH BIT(19) | |
258 | #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) | |
259 | #define WAKEUP_BIT_GPIO0 BIT(23) | |
260 | #define WAKEUP_BIT_GPIO1 BIT(24) | |
261 | #define WAKEUP_BIT_GPIO2 BIT(25) | |
262 | #define WAKEUP_BIT_GPIO3 BIT(26) | |
263 | #define WAKEUP_BIT_GPIO4 BIT(27) | |
264 | #define WAKEUP_BIT_GPIO5 BIT(28) | |
265 | #define WAKEUP_BIT_GPIO6 BIT(29) | |
266 | #define WAKEUP_BIT_GPIO7 BIT(30) | |
267 | #define WAKEUP_BIT_GPIO8 BIT(31) | |
268 | ||
b58d12fe MN |
269 | static struct { |
270 | bool valid; | |
271 | struct prcmu_fw_version version; | |
272 | } fw_info; | |
273 | ||
f3f1f0a1 LJ |
274 | static struct irq_domain *db8500_irq_domain; |
275 | ||
3df57bcf MN |
276 | /* |
277 | * This vector maps irq numbers to the bits in the bit field used in | |
278 | * communication with the PRCMU firmware. | |
279 | * | |
280 | * The reason for having this is to keep the irq numbers contiguous even though | |
281 | * the bits in the bit field are not. (The bits also have a tendency to move | |
282 | * around, to further complicate matters.) | |
283 | */ | |
284 | #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) | |
285 | #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) | |
286 | static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { | |
287 | IRQ_ENTRY(RTC), | |
288 | IRQ_ENTRY(RTT0), | |
289 | IRQ_ENTRY(RTT1), | |
290 | IRQ_ENTRY(HSI0), | |
291 | IRQ_ENTRY(HSI1), | |
292 | IRQ_ENTRY(CA_WAKE), | |
293 | IRQ_ENTRY(USB), | |
294 | IRQ_ENTRY(ABB), | |
295 | IRQ_ENTRY(ABB_FIFO), | |
296 | IRQ_ENTRY(CA_SLEEP), | |
297 | IRQ_ENTRY(ARM), | |
298 | IRQ_ENTRY(HOTMON_LOW), | |
299 | IRQ_ENTRY(HOTMON_HIGH), | |
300 | IRQ_ENTRY(MODEM_SW_RESET_REQ), | |
301 | IRQ_ENTRY(GPIO0), | |
302 | IRQ_ENTRY(GPIO1), | |
303 | IRQ_ENTRY(GPIO2), | |
304 | IRQ_ENTRY(GPIO3), | |
305 | IRQ_ENTRY(GPIO4), | |
306 | IRQ_ENTRY(GPIO5), | |
307 | IRQ_ENTRY(GPIO6), | |
308 | IRQ_ENTRY(GPIO7), | |
309 | IRQ_ENTRY(GPIO8) | |
310 | }; | |
311 | ||
312 | #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) | |
313 | #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) | |
314 | static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { | |
315 | WAKEUP_ENTRY(RTC), | |
316 | WAKEUP_ENTRY(RTT0), | |
317 | WAKEUP_ENTRY(RTT1), | |
318 | WAKEUP_ENTRY(HSI0), | |
319 | WAKEUP_ENTRY(HSI1), | |
320 | WAKEUP_ENTRY(USB), | |
321 | WAKEUP_ENTRY(ABB), | |
322 | WAKEUP_ENTRY(ABB_FIFO), | |
323 | WAKEUP_ENTRY(ARM) | |
324 | }; | |
325 | ||
326 | /* | |
327 | * mb0_transfer - state needed for mailbox 0 communication. | |
328 | * @lock: The transaction lock. | |
329 | * @dbb_events_lock: A lock used to handle concurrent access to (parts of) | |
330 | * the request data. | |
331 | * @mask_work: Work structure used for (un)masking wakeup interrupts. | |
332 | * @req: Request data that need to persist between requests. | |
333 | */ | |
334 | static struct { | |
335 | spinlock_t lock; | |
336 | spinlock_t dbb_irqs_lock; | |
337 | struct work_struct mask_work; | |
338 | struct mutex ac_wake_lock; | |
339 | struct completion ac_wake_work; | |
340 | struct { | |
341 | u32 dbb_irqs; | |
342 | u32 dbb_wakeups; | |
343 | u32 abb_events; | |
344 | } req; | |
345 | } mb0_transfer; | |
346 | ||
347 | /* | |
348 | * mb1_transfer - state needed for mailbox 1 communication. | |
349 | * @lock: The transaction lock. | |
350 | * @work: The transaction completion structure. | |
4d64d2e3 | 351 | * @ape_opp: The current APE OPP. |
3df57bcf MN |
352 | * @ack: Reply ("acknowledge") data. |
353 | */ | |
354 | static struct { | |
355 | struct mutex lock; | |
356 | struct completion work; | |
4d64d2e3 | 357 | u8 ape_opp; |
3df57bcf MN |
358 | struct { |
359 | u8 header; | |
360 | u8 arm_opp; | |
361 | u8 ape_opp; | |
362 | u8 ape_voltage_status; | |
363 | } ack; | |
364 | } mb1_transfer; | |
365 | ||
366 | /* | |
367 | * mb2_transfer - state needed for mailbox 2 communication. | |
368 | * @lock: The transaction lock. | |
369 | * @work: The transaction completion structure. | |
370 | * @auto_pm_lock: The autonomous power management configuration lock. | |
371 | * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. | |
372 | * @req: Request data that need to persist between requests. | |
373 | * @ack: Reply ("acknowledge") data. | |
374 | */ | |
375 | static struct { | |
376 | struct mutex lock; | |
377 | struct completion work; | |
378 | spinlock_t auto_pm_lock; | |
379 | bool auto_pm_enabled; | |
380 | struct { | |
381 | u8 status; | |
382 | } ack; | |
383 | } mb2_transfer; | |
384 | ||
385 | /* | |
386 | * mb3_transfer - state needed for mailbox 3 communication. | |
387 | * @lock: The request lock. | |
388 | * @sysclk_lock: A lock used to handle concurrent sysclk requests. | |
389 | * @sysclk_work: Work structure used for sysclk requests. | |
390 | */ | |
391 | static struct { | |
392 | spinlock_t lock; | |
393 | struct mutex sysclk_lock; | |
394 | struct completion sysclk_work; | |
395 | } mb3_transfer; | |
396 | ||
397 | /* | |
398 | * mb4_transfer - state needed for mailbox 4 communication. | |
399 | * @lock: The transaction lock. | |
400 | * @work: The transaction completion structure. | |
401 | */ | |
402 | static struct { | |
403 | struct mutex lock; | |
404 | struct completion work; | |
405 | } mb4_transfer; | |
406 | ||
407 | /* | |
408 | * mb5_transfer - state needed for mailbox 5 communication. | |
409 | * @lock: The transaction lock. | |
410 | * @work: The transaction completion structure. | |
411 | * @ack: Reply ("acknowledge") data. | |
412 | */ | |
413 | static struct { | |
414 | struct mutex lock; | |
415 | struct completion work; | |
416 | struct { | |
417 | u8 status; | |
418 | u8 value; | |
419 | } ack; | |
420 | } mb5_transfer; | |
421 | ||
422 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); | |
423 | ||
20aee5b6 MJ |
424 | /* Functions definition */ |
425 | static void compute_armss_rate(void); | |
426 | ||
3df57bcf | 427 | /* Spinlocks */ |
b4a6dbd5 | 428 | static DEFINE_SPINLOCK(prcmu_lock); |
3df57bcf | 429 | static DEFINE_SPINLOCK(clkout_lock); |
3df57bcf MN |
430 | |
431 | /* Global var to runtime determine TCDM base for v2 or v1 */ | |
432 | static __iomem void *tcdm_base; | |
433 | ||
434 | struct clk_mgt { | |
6b6fae2b | 435 | void __iomem *reg; |
3df57bcf | 436 | u32 pllsw; |
6b6fae2b MN |
437 | int branch; |
438 | bool clk38div; | |
439 | }; | |
440 | ||
441 | enum { | |
442 | PLL_RAW, | |
443 | PLL_FIX, | |
444 | PLL_DIV | |
3df57bcf MN |
445 | }; |
446 | ||
447 | static DEFINE_SPINLOCK(clk_mgt_lock); | |
448 | ||
6b6fae2b MN |
449 | #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ |
450 | { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} | |
3df57bcf | 451 | struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { |
6b6fae2b MN |
452 | CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), |
453 | CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), | |
454 | CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), | |
455 | CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), | |
456 | CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), | |
457 | CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), | |
458 | CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), | |
459 | CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), | |
460 | CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), | |
461 | CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), | |
462 | CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), | |
463 | CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), | |
464 | CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), | |
465 | CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), | |
466 | CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), | |
467 | CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), | |
468 | CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), | |
469 | CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), | |
470 | CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), | |
471 | CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), | |
472 | CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), | |
473 | CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), | |
474 | CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), | |
475 | CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), | |
476 | CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), | |
477 | CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), | |
478 | CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), | |
479 | CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), | |
480 | CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), | |
481 | }; | |
482 | ||
483 | struct dsiclk { | |
484 | u32 divsel_mask; | |
485 | u32 divsel_shift; | |
486 | u32 divsel; | |
487 | }; | |
488 | ||
489 | static struct dsiclk dsiclk[2] = { | |
490 | { | |
491 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, | |
492 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, | |
493 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, | |
494 | }, | |
495 | { | |
496 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, | |
497 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, | |
498 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, | |
499 | } | |
500 | }; | |
501 | ||
502 | struct dsiescclk { | |
503 | u32 en; | |
504 | u32 div_mask; | |
505 | u32 div_shift; | |
506 | }; | |
507 | ||
508 | static struct dsiescclk dsiescclk[3] = { | |
509 | { | |
510 | .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, | |
511 | .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, | |
512 | .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, | |
513 | }, | |
514 | { | |
515 | .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, | |
516 | .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, | |
517 | .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, | |
518 | }, | |
519 | { | |
520 | .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, | |
521 | .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, | |
522 | .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, | |
523 | } | |
3df57bcf MN |
524 | }; |
525 | ||
20aee5b6 | 526 | |
3df57bcf MN |
527 | /* |
528 | * Used by MCDE to setup all necessary PRCMU registers | |
529 | */ | |
530 | #define PRCMU_RESET_DSIPLL 0x00004000 | |
531 | #define PRCMU_UNCLAMP_DSIPLL 0x00400800 | |
532 | ||
533 | #define PRCMU_CLK_PLL_DIV_SHIFT 0 | |
534 | #define PRCMU_CLK_PLL_SW_SHIFT 5 | |
535 | #define PRCMU_CLK_38 (1 << 9) | |
536 | #define PRCMU_CLK_38_SRC (1 << 10) | |
537 | #define PRCMU_CLK_38_DIV (1 << 11) | |
538 | ||
539 | /* PLLDIV=12, PLLSW=4 (PLLDDR) */ | |
540 | #define PRCMU_DSI_CLOCK_SETTING 0x0000008C | |
541 | ||
3df57bcf MN |
542 | /* DPI 50000000 Hz */ |
543 | #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ | |
544 | (16 << PRCMU_CLK_PLL_DIV_SHIFT)) | |
545 | #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 | |
546 | ||
547 | /* D=101, N=1, R=4, SELDIV2=0 */ | |
548 | #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 | |
549 | ||
3df57bcf MN |
550 | #define PRCMU_ENABLE_PLLDSI 0x00000001 |
551 | #define PRCMU_DISABLE_PLLDSI 0x00000000 | |
552 | #define PRCMU_RELEASE_RESET_DSS 0x0000400C | |
553 | #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 | |
554 | /* ESC clk, div0=1, div1=1, div2=3 */ | |
555 | #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 | |
556 | #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 | |
557 | #define PRCMU_DSI_RESET_SW 0x00000007 | |
558 | ||
559 | #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 | |
560 | ||
73180f85 | 561 | int db8500_prcmu_enable_dsipll(void) |
3df57bcf MN |
562 | { |
563 | int i; | |
3df57bcf MN |
564 | |
565 | /* Clear DSIPLL_RESETN */ | |
c553b3ca | 566 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); |
3df57bcf | 567 | /* Unclamp DSIPLL in/out */ |
c553b3ca | 568 | writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); |
3df57bcf | 569 | |
3df57bcf | 570 | /* Set DSI PLL FREQ */ |
c72fe851 | 571 | writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); |
c553b3ca | 572 | writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); |
3df57bcf | 573 | /* Enable Escape clocks */ |
c553b3ca | 574 | writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
575 | |
576 | /* Start DSI PLL */ | |
c553b3ca | 577 | writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 578 | /* Reset DSI PLL */ |
c553b3ca | 579 | writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); |
3df57bcf | 580 | for (i = 0; i < 10; i++) { |
c553b3ca | 581 | if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) |
3df57bcf MN |
582 | == PRCMU_PLLDSI_LOCKP_LOCKED) |
583 | break; | |
584 | udelay(100); | |
585 | } | |
586 | /* Set DSIPLL_RESETN */ | |
c553b3ca | 587 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); |
3df57bcf MN |
588 | return 0; |
589 | } | |
590 | ||
73180f85 | 591 | int db8500_prcmu_disable_dsipll(void) |
3df57bcf MN |
592 | { |
593 | /* Disable dsi pll */ | |
c553b3ca | 594 | writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 595 | /* Disable escapeclock */ |
c553b3ca | 596 | writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
597 | return 0; |
598 | } | |
599 | ||
73180f85 | 600 | int db8500_prcmu_set_display_clocks(void) |
3df57bcf MN |
601 | { |
602 | unsigned long flags; | |
3df57bcf MN |
603 | |
604 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
605 | ||
606 | /* Grab the HW semaphore. */ | |
c553b3ca | 607 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
608 | cpu_relax(); |
609 | ||
c72fe851 | 610 | writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); |
c553b3ca MN |
611 | writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); |
612 | writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); | |
3df57bcf MN |
613 | |
614 | /* Release the HW semaphore. */ | |
c553b3ca | 615 | writel(0, PRCM_SEM); |
3df57bcf MN |
616 | |
617 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
b4a6dbd5 MN |
622 | u32 db8500_prcmu_read(unsigned int reg) |
623 | { | |
624 | return readl(_PRCMU_BASE + reg); | |
625 | } | |
626 | ||
627 | void db8500_prcmu_write(unsigned int reg, u32 value) | |
3df57bcf | 628 | { |
3df57bcf MN |
629 | unsigned long flags; |
630 | ||
b4a6dbd5 MN |
631 | spin_lock_irqsave(&prcmu_lock, flags); |
632 | writel(value, (_PRCMU_BASE + reg)); | |
633 | spin_unlock_irqrestore(&prcmu_lock, flags); | |
3df57bcf MN |
634 | } |
635 | ||
b4a6dbd5 | 636 | void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) |
3df57bcf | 637 | { |
b4a6dbd5 | 638 | u32 val; |
3df57bcf MN |
639 | unsigned long flags; |
640 | ||
b4a6dbd5 MN |
641 | spin_lock_irqsave(&prcmu_lock, flags); |
642 | val = readl(_PRCMU_BASE + reg); | |
643 | val = ((val & ~mask) | (value & mask)); | |
644 | writel(val, (_PRCMU_BASE + reg)); | |
645 | spin_unlock_irqrestore(&prcmu_lock, flags); | |
3df57bcf MN |
646 | } |
647 | ||
b58d12fe MN |
648 | struct prcmu_fw_version *prcmu_get_fw_version(void) |
649 | { | |
650 | return fw_info.valid ? &fw_info.version : NULL; | |
651 | } | |
652 | ||
3df57bcf MN |
653 | bool prcmu_has_arm_maxopp(void) |
654 | { | |
655 | return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & | |
656 | PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; | |
657 | } | |
658 | ||
3df57bcf MN |
659 | /** |
660 | * prcmu_get_boot_status - PRCMU boot status checking | |
661 | * Returns: the current PRCMU boot status | |
662 | */ | |
663 | int prcmu_get_boot_status(void) | |
664 | { | |
665 | return readb(tcdm_base + PRCM_BOOT_STATUS); | |
666 | } | |
667 | ||
668 | /** | |
669 | * prcmu_set_rc_a2p - This function is used to run few power state sequences | |
670 | * @val: Value to be set, i.e. transition requested | |
671 | * Returns: 0 on success, -EINVAL on invalid argument | |
672 | * | |
673 | * This function is used to run the following power state sequences - | |
674 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
675 | */ | |
676 | int prcmu_set_rc_a2p(enum romcode_write val) | |
677 | { | |
678 | if (val < RDY_2_DS || val > RDY_2_XP70_RST) | |
679 | return -EINVAL; | |
680 | writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); | |
681 | return 0; | |
682 | } | |
683 | ||
684 | /** | |
685 | * prcmu_get_rc_p2a - This function is used to get power state sequences | |
686 | * Returns: the power transition that has last happened | |
687 | * | |
688 | * This function can return the following transitions- | |
689 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
690 | */ | |
691 | enum romcode_read prcmu_get_rc_p2a(void) | |
692 | { | |
693 | return readb(tcdm_base + PRCM_ROMCODE_P2A); | |
694 | } | |
695 | ||
696 | /** | |
697 | * prcmu_get_current_mode - Return the current XP70 power mode | |
698 | * Returns: Returns the current AP(ARM) power mode: init, | |
699 | * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset | |
700 | */ | |
701 | enum ap_pwrst prcmu_get_xp70_current_state(void) | |
702 | { | |
703 | return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); | |
704 | } | |
705 | ||
706 | /** | |
707 | * prcmu_config_clkout - Configure one of the programmable clock outputs. | |
708 | * @clkout: The CLKOUT number (0 or 1). | |
709 | * @source: The clock to be used (one of the PRCMU_CLKSRC_*). | |
710 | * @div: The divider to be applied. | |
711 | * | |
712 | * Configures one of the programmable clock outputs (CLKOUTs). | |
713 | * @div should be in the range [1,63] to request a configuration, or 0 to | |
714 | * inform that the configuration is no longer requested. | |
715 | */ | |
716 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div) | |
717 | { | |
718 | static int requests[2]; | |
719 | int r = 0; | |
720 | unsigned long flags; | |
721 | u32 val; | |
722 | u32 bits; | |
723 | u32 mask; | |
724 | u32 div_mask; | |
725 | ||
726 | BUG_ON(clkout > 1); | |
727 | BUG_ON(div > 63); | |
728 | BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); | |
729 | ||
730 | if (!div && !requests[clkout]) | |
731 | return -EINVAL; | |
732 | ||
733 | switch (clkout) { | |
734 | case 0: | |
735 | div_mask = PRCM_CLKOCR_CLKODIV0_MASK; | |
736 | mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); | |
737 | bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | | |
738 | (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); | |
739 | break; | |
740 | case 1: | |
741 | div_mask = PRCM_CLKOCR_CLKODIV1_MASK; | |
742 | mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | | |
743 | PRCM_CLKOCR_CLK1TYPE); | |
744 | bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | | |
745 | (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); | |
746 | break; | |
747 | } | |
748 | bits &= mask; | |
749 | ||
750 | spin_lock_irqsave(&clkout_lock, flags); | |
751 | ||
c553b3ca | 752 | val = readl(PRCM_CLKOCR); |
3df57bcf MN |
753 | if (val & div_mask) { |
754 | if (div) { | |
755 | if ((val & mask) != bits) { | |
756 | r = -EBUSY; | |
757 | goto unlock_and_return; | |
758 | } | |
759 | } else { | |
760 | if ((val & mask & ~div_mask) != bits) { | |
761 | r = -EINVAL; | |
762 | goto unlock_and_return; | |
763 | } | |
764 | } | |
765 | } | |
c553b3ca | 766 | writel((bits | (val & ~mask)), PRCM_CLKOCR); |
3df57bcf MN |
767 | requests[clkout] += (div ? 1 : -1); |
768 | ||
769 | unlock_and_return: | |
770 | spin_unlock_irqrestore(&clkout_lock, flags); | |
771 | ||
772 | return r; | |
773 | } | |
774 | ||
73180f85 | 775 | int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) |
3df57bcf MN |
776 | { |
777 | unsigned long flags; | |
778 | ||
779 | BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); | |
780 | ||
781 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
782 | ||
c553b3ca | 783 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
784 | cpu_relax(); |
785 | ||
786 | writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
787 | writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); | |
788 | writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); | |
789 | writeb((keep_ulp_clk ? 1 : 0), | |
790 | (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); | |
791 | writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); | |
c553b3ca | 792 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
793 | |
794 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
4d64d2e3 MN |
799 | u8 db8500_prcmu_get_power_state_result(void) |
800 | { | |
801 | return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); | |
802 | } | |
803 | ||
485540dc DL |
804 | /* This function decouple the gic from the prcmu */ |
805 | int db8500_prcmu_gic_decouple(void) | |
806 | { | |
801448e0 | 807 | u32 val = readl(PRCM_A9_MASK_REQ); |
485540dc DL |
808 | |
809 | /* Set bit 0 register value to 1 */ | |
801448e0 DL |
810 | writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, |
811 | PRCM_A9_MASK_REQ); | |
485540dc DL |
812 | |
813 | /* Make sure the register is updated */ | |
801448e0 | 814 | readl(PRCM_A9_MASK_REQ); |
485540dc DL |
815 | |
816 | /* Wait a few cycles for the gic mask completion */ | |
801448e0 | 817 | udelay(1); |
485540dc DL |
818 | |
819 | return 0; | |
820 | } | |
821 | ||
822 | /* This function recouple the gic with the prcmu */ | |
823 | int db8500_prcmu_gic_recouple(void) | |
824 | { | |
801448e0 | 825 | u32 val = readl(PRCM_A9_MASK_REQ); |
485540dc DL |
826 | |
827 | /* Set bit 0 register value to 0 */ | |
801448e0 | 828 | writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); |
485540dc DL |
829 | |
830 | return 0; | |
831 | } | |
832 | ||
cc9a0f68 DL |
833 | #define PRCMU_GIC_NUMBER_REGS 5 |
834 | ||
835 | /* | |
836 | * This function checks if there are pending irq on the gic. It only | |
837 | * makes sense if the gic has been decoupled before with the | |
838 | * db8500_prcmu_gic_decouple function. Disabling an interrupt only | |
839 | * disables the forwarding of the interrupt to any CPU interface. It | |
840 | * does not prevent the interrupt from changing state, for example | |
841 | * becoming pending, or active and pending if it is already | |
842 | * active. Hence, we have to check the interrupt is pending *and* is | |
843 | * active. | |
844 | */ | |
845 | bool db8500_prcmu_gic_pending_irq(void) | |
846 | { | |
847 | u32 pr; /* Pending register */ | |
848 | u32 er; /* Enable register */ | |
849 | void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); | |
850 | int i; | |
851 | ||
852 | /* 5 registers. STI & PPI not skipped */ | |
853 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { | |
854 | ||
855 | pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); | |
856 | er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
857 | ||
858 | if (pr & er) | |
859 | return true; /* There is a pending interrupt */ | |
860 | } | |
861 | ||
862 | return false; | |
863 | } | |
864 | ||
9ab492e1 DL |
865 | /* |
866 | * This function checks if there are pending interrupt on the | |
867 | * prcmu which has been delegated to monitor the irqs with the | |
868 | * db8500_prcmu_copy_gic_settings function. | |
869 | */ | |
870 | bool db8500_prcmu_pending_irq(void) | |
871 | { | |
872 | u32 it, im; | |
873 | int i; | |
874 | ||
875 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { | |
876 | it = readl(PRCM_ARMITVAL31TO0 + i * 4); | |
877 | im = readl(PRCM_ARMITMSK31TO0 + i * 4); | |
878 | if (it & im) | |
879 | return true; /* There is a pending interrupt */ | |
880 | } | |
881 | ||
882 | return false; | |
883 | } | |
884 | ||
34fe6f10 DL |
885 | /* |
886 | * This function checks if the specified cpu is in in WFI. It's usage | |
887 | * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple | |
888 | * function. Of course passing smp_processor_id() to this function will | |
889 | * always return false... | |
890 | */ | |
891 | bool db8500_prcmu_is_cpu_in_wfi(int cpu) | |
892 | { | |
893 | return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : | |
894 | PRCM_ARM_WFI_STANDBY_WFI0; | |
895 | } | |
896 | ||
9f60d33e DL |
897 | /* |
898 | * This function copies the gic SPI settings to the prcmu in order to | |
899 | * monitor them and abort/finish the retention/off sequence or state. | |
900 | */ | |
901 | int db8500_prcmu_copy_gic_settings(void) | |
902 | { | |
903 | u32 er; /* Enable register */ | |
904 | void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); | |
905 | int i; | |
906 | ||
907 | /* We skip the STI and PPI */ | |
908 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { | |
909 | er = readl_relaxed(dist_base + | |
910 | GIC_DIST_ENABLE_SET + (i + 1) * 4); | |
911 | writel(er, PRCM_ARMITMSK31TO0 + i * 4); | |
912 | } | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
3df57bcf MN |
917 | /* This function should only be called while mb0_transfer.lock is held. */ |
918 | static void config_wakeups(void) | |
919 | { | |
920 | const u8 header[2] = { | |
921 | MB0H_CONFIG_WAKEUPS_EXE, | |
922 | MB0H_CONFIG_WAKEUPS_SLEEP | |
923 | }; | |
924 | static u32 last_dbb_events; | |
925 | static u32 last_abb_events; | |
926 | u32 dbb_events; | |
927 | u32 abb_events; | |
928 | unsigned int i; | |
929 | ||
930 | dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; | |
931 | dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); | |
932 | ||
933 | abb_events = mb0_transfer.req.abb_events; | |
934 | ||
935 | if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) | |
936 | return; | |
937 | ||
938 | for (i = 0; i < 2; i++) { | |
c553b3ca | 939 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
940 | cpu_relax(); |
941 | writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); | |
942 | writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); | |
943 | writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 944 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
945 | } |
946 | last_dbb_events = dbb_events; | |
947 | last_abb_events = abb_events; | |
948 | } | |
949 | ||
73180f85 | 950 | void db8500_prcmu_enable_wakeups(u32 wakeups) |
3df57bcf MN |
951 | { |
952 | unsigned long flags; | |
953 | u32 bits; | |
954 | int i; | |
955 | ||
956 | BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); | |
957 | ||
958 | for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { | |
959 | if (wakeups & BIT(i)) | |
960 | bits |= prcmu_wakeup_bit[i]; | |
961 | } | |
962 | ||
963 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
964 | ||
965 | mb0_transfer.req.dbb_wakeups = bits; | |
966 | config_wakeups(); | |
967 | ||
968 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
969 | } | |
970 | ||
73180f85 | 971 | void db8500_prcmu_config_abb_event_readout(u32 abb_events) |
3df57bcf MN |
972 | { |
973 | unsigned long flags; | |
974 | ||
975 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
976 | ||
977 | mb0_transfer.req.abb_events = abb_events; | |
978 | config_wakeups(); | |
979 | ||
980 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
981 | } | |
982 | ||
73180f85 | 983 | void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) |
3df57bcf MN |
984 | { |
985 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
986 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); | |
987 | else | |
988 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); | |
989 | } | |
990 | ||
991 | /** | |
73180f85 | 992 | * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP |
3df57bcf MN |
993 | * @opp: The new ARM operating point to which transition is to be made |
994 | * Returns: 0 on success, non-zero on failure | |
995 | * | |
996 | * This function sets the the operating point of the ARM. | |
997 | */ | |
73180f85 | 998 | int db8500_prcmu_set_arm_opp(u8 opp) |
3df57bcf MN |
999 | { |
1000 | int r; | |
1001 | ||
1002 | if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) | |
1003 | return -EINVAL; | |
1004 | ||
1005 | r = 0; | |
1006 | ||
1007 | mutex_lock(&mb1_transfer.lock); | |
1008 | ||
c553b3ca | 1009 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1010 | cpu_relax(); |
1011 | ||
1012 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1013 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
1014 | writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
1015 | ||
c553b3ca | 1016 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1017 | wait_for_completion(&mb1_transfer.work); |
1018 | ||
1019 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
1020 | (mb1_transfer.ack.arm_opp != opp)) | |
1021 | r = -EIO; | |
1022 | ||
20aee5b6 | 1023 | compute_armss_rate(); |
3df57bcf MN |
1024 | mutex_unlock(&mb1_transfer.lock); |
1025 | ||
1026 | return r; | |
1027 | } | |
1028 | ||
1029 | /** | |
73180f85 | 1030 | * db8500_prcmu_get_arm_opp - get the current ARM OPP |
3df57bcf MN |
1031 | * |
1032 | * Returns: the current ARM OPP | |
1033 | */ | |
73180f85 | 1034 | int db8500_prcmu_get_arm_opp(void) |
3df57bcf MN |
1035 | { |
1036 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
1037 | } | |
1038 | ||
1039 | /** | |
0508901c | 1040 | * db8500_prcmu_get_ddr_opp - get the current DDR OPP |
3df57bcf MN |
1041 | * |
1042 | * Returns: the current DDR OPP | |
1043 | */ | |
0508901c | 1044 | int db8500_prcmu_get_ddr_opp(void) |
3df57bcf | 1045 | { |
c553b3ca | 1046 | return readb(PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
1047 | } |
1048 | ||
1049 | /** | |
0508901c | 1050 | * db8500_set_ddr_opp - set the appropriate DDR OPP |
3df57bcf MN |
1051 | * @opp: The new DDR operating point to which transition is to be made |
1052 | * Returns: 0 on success, non-zero on failure | |
1053 | * | |
1054 | * This function sets the operating point of the DDR. | |
1055 | */ | |
0508901c | 1056 | int db8500_prcmu_set_ddr_opp(u8 opp) |
3df57bcf MN |
1057 | { |
1058 | if (opp < DDR_100_OPP || opp > DDR_25_OPP) | |
1059 | return -EINVAL; | |
1060 | /* Changing the DDR OPP can hang the hardware pre-v21 */ | |
1061 | if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) | |
c553b3ca | 1062 | writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
1063 | |
1064 | return 0; | |
1065 | } | |
6b6fae2b | 1066 | |
4d64d2e3 MN |
1067 | /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ |
1068 | static void request_even_slower_clocks(bool enable) | |
1069 | { | |
1070 | void __iomem *clock_reg[] = { | |
1071 | PRCM_ACLK_MGT, | |
1072 | PRCM_DMACLK_MGT | |
1073 | }; | |
1074 | unsigned long flags; | |
1075 | unsigned int i; | |
1076 | ||
1077 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1078 | ||
1079 | /* Grab the HW semaphore. */ | |
1080 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) | |
1081 | cpu_relax(); | |
1082 | ||
1083 | for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { | |
1084 | u32 val; | |
1085 | u32 div; | |
1086 | ||
1087 | val = readl(clock_reg[i]); | |
1088 | div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); | |
1089 | if (enable) { | |
1090 | if ((div <= 1) || (div > 15)) { | |
1091 | pr_err("prcmu: Bad clock divider %d in %s\n", | |
1092 | div, __func__); | |
1093 | goto unlock_and_return; | |
1094 | } | |
1095 | div <<= 1; | |
1096 | } else { | |
1097 | if (div <= 2) | |
1098 | goto unlock_and_return; | |
1099 | div >>= 1; | |
1100 | } | |
1101 | val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | | |
1102 | (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); | |
1103 | writel(val, clock_reg[i]); | |
1104 | } | |
1105 | ||
1106 | unlock_and_return: | |
1107 | /* Release the HW semaphore. */ | |
1108 | writel(0, PRCM_SEM); | |
1109 | ||
1110 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1111 | } | |
1112 | ||
3df57bcf | 1113 | /** |
0508901c | 1114 | * db8500_set_ape_opp - set the appropriate APE OPP |
3df57bcf MN |
1115 | * @opp: The new APE operating point to which transition is to be made |
1116 | * Returns: 0 on success, non-zero on failure | |
1117 | * | |
1118 | * This function sets the operating point of the APE. | |
1119 | */ | |
0508901c | 1120 | int db8500_prcmu_set_ape_opp(u8 opp) |
3df57bcf MN |
1121 | { |
1122 | int r = 0; | |
1123 | ||
4d64d2e3 MN |
1124 | if (opp == mb1_transfer.ape_opp) |
1125 | return 0; | |
1126 | ||
3df57bcf MN |
1127 | mutex_lock(&mb1_transfer.lock); |
1128 | ||
4d64d2e3 MN |
1129 | if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) |
1130 | request_even_slower_clocks(false); | |
1131 | ||
1132 | if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) | |
1133 | goto skip_message; | |
1134 | ||
c553b3ca | 1135 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1136 | cpu_relax(); |
1137 | ||
1138 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1139 | writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
4d64d2e3 MN |
1140 | writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), |
1141 | (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
3df57bcf | 1142 | |
c553b3ca | 1143 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1144 | wait_for_completion(&mb1_transfer.work); |
1145 | ||
1146 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
1147 | (mb1_transfer.ack.ape_opp != opp)) | |
1148 | r = -EIO; | |
1149 | ||
4d64d2e3 MN |
1150 | skip_message: |
1151 | if ((!r && (opp == APE_50_PARTLY_25_OPP)) || | |
1152 | (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) | |
1153 | request_even_slower_clocks(true); | |
1154 | if (!r) | |
1155 | mb1_transfer.ape_opp = opp; | |
1156 | ||
3df57bcf MN |
1157 | mutex_unlock(&mb1_transfer.lock); |
1158 | ||
1159 | return r; | |
1160 | } | |
1161 | ||
1162 | /** | |
0508901c | 1163 | * db8500_prcmu_get_ape_opp - get the current APE OPP |
3df57bcf MN |
1164 | * |
1165 | * Returns: the current APE OPP | |
1166 | */ | |
0508901c | 1167 | int db8500_prcmu_get_ape_opp(void) |
3df57bcf MN |
1168 | { |
1169 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); | |
1170 | } | |
1171 | ||
1172 | /** | |
686f871b | 1173 | * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage |
3df57bcf MN |
1174 | * @enable: true to request the higher voltage, false to drop a request. |
1175 | * | |
1176 | * Calls to this function to enable and disable requests must be balanced. | |
1177 | */ | |
686f871b | 1178 | int db8500_prcmu_request_ape_opp_100_voltage(bool enable) |
3df57bcf MN |
1179 | { |
1180 | int r = 0; | |
1181 | u8 header; | |
1182 | static unsigned int requests; | |
1183 | ||
1184 | mutex_lock(&mb1_transfer.lock); | |
1185 | ||
1186 | if (enable) { | |
1187 | if (0 != requests++) | |
1188 | goto unlock_and_return; | |
1189 | header = MB1H_REQUEST_APE_OPP_100_VOLT; | |
1190 | } else { | |
1191 | if (requests == 0) { | |
1192 | r = -EIO; | |
1193 | goto unlock_and_return; | |
1194 | } else if (1 != requests--) { | |
1195 | goto unlock_and_return; | |
1196 | } | |
1197 | header = MB1H_RELEASE_APE_OPP_100_VOLT; | |
1198 | } | |
1199 | ||
c553b3ca | 1200 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1201 | cpu_relax(); |
1202 | ||
1203 | writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1204 | ||
c553b3ca | 1205 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1206 | wait_for_completion(&mb1_transfer.work); |
1207 | ||
1208 | if ((mb1_transfer.ack.header != header) || | |
1209 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1210 | r = -EIO; | |
1211 | ||
1212 | unlock_and_return: | |
1213 | mutex_unlock(&mb1_transfer.lock); | |
1214 | ||
1215 | return r; | |
1216 | } | |
1217 | ||
1218 | /** | |
1219 | * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup | |
1220 | * | |
1221 | * This function releases the power state requirements of a USB wakeup. | |
1222 | */ | |
1223 | int prcmu_release_usb_wakeup_state(void) | |
1224 | { | |
1225 | int r = 0; | |
1226 | ||
1227 | mutex_lock(&mb1_transfer.lock); | |
1228 | ||
c553b3ca | 1229 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1230 | cpu_relax(); |
1231 | ||
1232 | writeb(MB1H_RELEASE_USB_WAKEUP, | |
1233 | (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1234 | ||
c553b3ca | 1235 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1236 | wait_for_completion(&mb1_transfer.work); |
1237 | ||
1238 | if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || | |
1239 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1240 | r = -EIO; | |
1241 | ||
1242 | mutex_unlock(&mb1_transfer.lock); | |
1243 | ||
1244 | return r; | |
1245 | } | |
1246 | ||
0837bb72 MN |
1247 | static int request_pll(u8 clock, bool enable) |
1248 | { | |
1249 | int r = 0; | |
1250 | ||
6b6fae2b MN |
1251 | if (clock == PRCMU_PLLSOC0) |
1252 | clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); | |
1253 | else if (clock == PRCMU_PLLSOC1) | |
0837bb72 MN |
1254 | clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); |
1255 | else | |
1256 | return -EINVAL; | |
1257 | ||
1258 | mutex_lock(&mb1_transfer.lock); | |
1259 | ||
1260 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) | |
1261 | cpu_relax(); | |
1262 | ||
1263 | writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1264 | writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); | |
1265 | ||
1266 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); | |
1267 | wait_for_completion(&mb1_transfer.work); | |
1268 | ||
1269 | if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) | |
1270 | r = -EIO; | |
1271 | ||
1272 | mutex_unlock(&mb1_transfer.lock); | |
1273 | ||
1274 | return r; | |
1275 | } | |
1276 | ||
3df57bcf | 1277 | /** |
73180f85 | 1278 | * db8500_prcmu_set_epod - set the state of a EPOD (power domain) |
3df57bcf MN |
1279 | * @epod_id: The EPOD to set |
1280 | * @epod_state: The new EPOD state | |
1281 | * | |
1282 | * This function sets the state of a EPOD (power domain). It may not be called | |
1283 | * from interrupt context. | |
1284 | */ | |
73180f85 | 1285 | int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) |
3df57bcf MN |
1286 | { |
1287 | int r = 0; | |
1288 | bool ram_retention = false; | |
1289 | int i; | |
1290 | ||
1291 | /* check argument */ | |
1292 | BUG_ON(epod_id >= NUM_EPOD_ID); | |
1293 | ||
1294 | /* set flag if retention is possible */ | |
1295 | switch (epod_id) { | |
1296 | case EPOD_ID_SVAMMDSP: | |
1297 | case EPOD_ID_SIAMMDSP: | |
1298 | case EPOD_ID_ESRAM12: | |
1299 | case EPOD_ID_ESRAM34: | |
1300 | ram_retention = true; | |
1301 | break; | |
1302 | } | |
1303 | ||
1304 | /* check argument */ | |
1305 | BUG_ON(epod_state > EPOD_STATE_ON); | |
1306 | BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); | |
1307 | ||
1308 | /* get lock */ | |
1309 | mutex_lock(&mb2_transfer.lock); | |
1310 | ||
1311 | /* wait for mailbox */ | |
c553b3ca | 1312 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) |
3df57bcf MN |
1313 | cpu_relax(); |
1314 | ||
1315 | /* fill in mailbox */ | |
1316 | for (i = 0; i < NUM_EPOD_ID; i++) | |
1317 | writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); | |
1318 | writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); | |
1319 | ||
1320 | writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); | |
1321 | ||
c553b3ca | 1322 | writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1323 | |
1324 | /* | |
1325 | * The current firmware version does not handle errors correctly, | |
1326 | * and we cannot recover if there is an error. | |
1327 | * This is expected to change when the firmware is updated. | |
1328 | */ | |
1329 | if (!wait_for_completion_timeout(&mb2_transfer.work, | |
1330 | msecs_to_jiffies(20000))) { | |
1331 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1332 | __func__); | |
1333 | r = -EIO; | |
1334 | goto unlock_and_return; | |
1335 | } | |
1336 | ||
1337 | if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) | |
1338 | r = -EIO; | |
1339 | ||
1340 | unlock_and_return: | |
1341 | mutex_unlock(&mb2_transfer.lock); | |
1342 | return r; | |
1343 | } | |
1344 | ||
1345 | /** | |
1346 | * prcmu_configure_auto_pm - Configure autonomous power management. | |
1347 | * @sleep: Configuration for ApSleep. | |
1348 | * @idle: Configuration for ApIdle. | |
1349 | */ | |
1350 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, | |
1351 | struct prcmu_auto_pm_config *idle) | |
1352 | { | |
1353 | u32 sleep_cfg; | |
1354 | u32 idle_cfg; | |
1355 | unsigned long flags; | |
e3726fcf | 1356 | |
3df57bcf | 1357 | BUG_ON((sleep == NULL) || (idle == NULL)); |
650c2a21 | 1358 | |
3df57bcf MN |
1359 | sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); |
1360 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); | |
1361 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); | |
1362 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); | |
1363 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); | |
1364 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); | |
e3726fcf | 1365 | |
3df57bcf MN |
1366 | idle_cfg = (idle->sva_auto_pm_enable & 0xF); |
1367 | idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); | |
1368 | idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); | |
1369 | idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); | |
1370 | idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); | |
1371 | idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); | |
e3726fcf | 1372 | |
3df57bcf | 1373 | spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); |
e0befb23 | 1374 | |
3df57bcf MN |
1375 | /* |
1376 | * The autonomous power management configuration is done through | |
1377 | * fields in mailbox 2, but these fields are only used as shared | |
1378 | * variables - i.e. there is no need to send a message. | |
1379 | */ | |
1380 | writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); | |
1381 | writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); | |
e0befb23 | 1382 | |
3df57bcf MN |
1383 | mb2_transfer.auto_pm_enabled = |
1384 | ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1385 | (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1386 | (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1387 | (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); | |
e0befb23 | 1388 | |
3df57bcf MN |
1389 | spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); |
1390 | } | |
1391 | EXPORT_SYMBOL(prcmu_configure_auto_pm); | |
e3726fcf | 1392 | |
3df57bcf MN |
1393 | bool prcmu_is_auto_pm_enabled(void) |
1394 | { | |
1395 | return mb2_transfer.auto_pm_enabled; | |
1396 | } | |
e0befb23 | 1397 | |
3df57bcf MN |
1398 | static int request_sysclk(bool enable) |
1399 | { | |
1400 | int r; | |
1401 | unsigned long flags; | |
e3726fcf | 1402 | |
3df57bcf | 1403 | r = 0; |
e3726fcf | 1404 | |
3df57bcf | 1405 | mutex_lock(&mb3_transfer.sysclk_lock); |
e0befb23 | 1406 | |
3df57bcf | 1407 | spin_lock_irqsave(&mb3_transfer.lock, flags); |
e0befb23 | 1408 | |
c553b3ca | 1409 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) |
3df57bcf | 1410 | cpu_relax(); |
e0befb23 | 1411 | |
3df57bcf | 1412 | writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); |
e3726fcf | 1413 | |
3df57bcf | 1414 | writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); |
c553b3ca | 1415 | writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); |
e3726fcf | 1416 | |
3df57bcf MN |
1417 | spin_unlock_irqrestore(&mb3_transfer.lock, flags); |
1418 | ||
1419 | /* | |
1420 | * The firmware only sends an ACK if we want to enable the | |
1421 | * SysClk, and it succeeds. | |
1422 | */ | |
1423 | if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, | |
1424 | msecs_to_jiffies(20000))) { | |
1425 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1426 | __func__); | |
1427 | r = -EIO; | |
1428 | } | |
1429 | ||
1430 | mutex_unlock(&mb3_transfer.sysclk_lock); | |
1431 | ||
1432 | return r; | |
1433 | } | |
1434 | ||
1435 | static int request_timclk(bool enable) | |
1436 | { | |
1437 | u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); | |
1438 | ||
1439 | if (!enable) | |
1440 | val |= PRCM_TCR_STOP_TIMERS; | |
c553b3ca | 1441 | writel(val, PRCM_TCR); |
3df57bcf MN |
1442 | |
1443 | return 0; | |
1444 | } | |
1445 | ||
6b6fae2b | 1446 | static int request_clock(u8 clock, bool enable) |
3df57bcf MN |
1447 | { |
1448 | u32 val; | |
1449 | unsigned long flags; | |
1450 | ||
1451 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1452 | ||
1453 | /* Grab the HW semaphore. */ | |
c553b3ca | 1454 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
1455 | cpu_relax(); |
1456 | ||
6b6fae2b | 1457 | val = readl(clk_mgt[clock].reg); |
3df57bcf MN |
1458 | if (enable) { |
1459 | val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); | |
1460 | } else { | |
1461 | clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1462 | val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1463 | } | |
6b6fae2b | 1464 | writel(val, clk_mgt[clock].reg); |
3df57bcf MN |
1465 | |
1466 | /* Release the HW semaphore. */ | |
c553b3ca | 1467 | writel(0, PRCM_SEM); |
3df57bcf MN |
1468 | |
1469 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
0837bb72 MN |
1474 | static int request_sga_clock(u8 clock, bool enable) |
1475 | { | |
1476 | u32 val; | |
1477 | int ret; | |
1478 | ||
1479 | if (enable) { | |
1480 | val = readl(PRCM_CGATING_BYPASS); | |
1481 | writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1482 | } | |
1483 | ||
6b6fae2b | 1484 | ret = request_clock(clock, enable); |
0837bb72 MN |
1485 | |
1486 | if (!ret && !enable) { | |
1487 | val = readl(PRCM_CGATING_BYPASS); | |
1488 | writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1489 | } | |
1490 | ||
1491 | return ret; | |
1492 | } | |
1493 | ||
6b6fae2b MN |
1494 | static inline bool plldsi_locked(void) |
1495 | { | |
1496 | return (readl(PRCM_PLLDSI_LOCKP) & | |
1497 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | | |
1498 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == | |
1499 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | | |
1500 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); | |
1501 | } | |
1502 | ||
1503 | static int request_plldsi(bool enable) | |
1504 | { | |
1505 | int r = 0; | |
1506 | u32 val; | |
1507 | ||
1508 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | | |
1509 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? | |
1510 | PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); | |
1511 | ||
1512 | val = readl(PRCM_PLLDSI_ENABLE); | |
1513 | if (enable) | |
1514 | val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1515 | else | |
1516 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1517 | writel(val, PRCM_PLLDSI_ENABLE); | |
1518 | ||
1519 | if (enable) { | |
1520 | unsigned int i; | |
1521 | bool locked = plldsi_locked(); | |
1522 | ||
1523 | for (i = 10; !locked && (i > 0); --i) { | |
1524 | udelay(100); | |
1525 | locked = plldsi_locked(); | |
1526 | } | |
1527 | if (locked) { | |
1528 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, | |
1529 | PRCM_APE_RESETN_SET); | |
1530 | } else { | |
1531 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | | |
1532 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), | |
1533 | PRCM_MMIP_LS_CLAMP_SET); | |
1534 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1535 | writel(val, PRCM_PLLDSI_ENABLE); | |
1536 | r = -EAGAIN; | |
1537 | } | |
1538 | } else { | |
1539 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); | |
1540 | } | |
1541 | return r; | |
1542 | } | |
1543 | ||
1544 | static int request_dsiclk(u8 n, bool enable) | |
1545 | { | |
1546 | u32 val; | |
1547 | ||
1548 | val = readl(PRCM_DSI_PLLOUT_SEL); | |
1549 | val &= ~dsiclk[n].divsel_mask; | |
1550 | val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << | |
1551 | dsiclk[n].divsel_shift); | |
1552 | writel(val, PRCM_DSI_PLLOUT_SEL); | |
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | static int request_dsiescclk(u8 n, bool enable) | |
1557 | { | |
1558 | u32 val; | |
1559 | ||
1560 | val = readl(PRCM_DSITVCLK_DIV); | |
1561 | enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); | |
1562 | writel(val, PRCM_DSITVCLK_DIV); | |
1563 | return 0; | |
1564 | } | |
1565 | ||
3df57bcf | 1566 | /** |
73180f85 | 1567 | * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. |
3df57bcf MN |
1568 | * @clock: The clock for which the request is made. |
1569 | * @enable: Whether the clock should be enabled (true) or disabled (false). | |
1570 | * | |
1571 | * This function should only be used by the clock implementation. | |
1572 | * Do not use it from any other place! | |
1573 | */ | |
73180f85 | 1574 | int db8500_prcmu_request_clock(u8 clock, bool enable) |
3df57bcf | 1575 | { |
6b6fae2b | 1576 | if (clock == PRCMU_SGACLK) |
0837bb72 | 1577 | return request_sga_clock(clock, enable); |
6b6fae2b MN |
1578 | else if (clock < PRCMU_NUM_REG_CLOCKS) |
1579 | return request_clock(clock, enable); | |
1580 | else if (clock == PRCMU_TIMCLK) | |
3df57bcf | 1581 | return request_timclk(enable); |
6b6fae2b MN |
1582 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
1583 | return request_dsiclk((clock - PRCMU_DSI0CLK), enable); | |
1584 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1585 | return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); | |
1586 | else if (clock == PRCMU_PLLDSI) | |
1587 | return request_plldsi(enable); | |
1588 | else if (clock == PRCMU_SYSCLK) | |
3df57bcf | 1589 | return request_sysclk(enable); |
6b6fae2b | 1590 | else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) |
0837bb72 | 1591 | return request_pll(clock, enable); |
6b6fae2b MN |
1592 | else |
1593 | return -EINVAL; | |
1594 | } | |
1595 | ||
1596 | static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, | |
1597 | int branch) | |
1598 | { | |
1599 | u64 rate; | |
1600 | u32 val; | |
1601 | u32 d; | |
1602 | u32 div = 1; | |
1603 | ||
1604 | val = readl(reg); | |
1605 | ||
1606 | rate = src_rate; | |
1607 | rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); | |
1608 | ||
1609 | d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); | |
1610 | if (d > 1) | |
1611 | div *= d; | |
1612 | ||
1613 | d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); | |
1614 | if (d > 1) | |
1615 | div *= d; | |
1616 | ||
1617 | if (val & PRCM_PLL_FREQ_SELDIV2) | |
1618 | div *= 2; | |
1619 | ||
1620 | if ((branch == PLL_FIX) || ((branch == PLL_DIV) && | |
1621 | (val & PRCM_PLL_FREQ_DIV2EN) && | |
1622 | ((reg == PRCM_PLLSOC0_FREQ) || | |
20aee5b6 | 1623 | (reg == PRCM_PLLARM_FREQ) || |
6b6fae2b MN |
1624 | (reg == PRCM_PLLDDR_FREQ)))) |
1625 | div *= 2; | |
1626 | ||
1627 | (void)do_div(rate, div); | |
1628 | ||
1629 | return (unsigned long)rate; | |
1630 | } | |
1631 | ||
1632 | #define ROOT_CLOCK_RATE 38400000 | |
1633 | ||
1634 | static unsigned long clock_rate(u8 clock) | |
1635 | { | |
1636 | u32 val; | |
1637 | u32 pllsw; | |
1638 | unsigned long rate = ROOT_CLOCK_RATE; | |
1639 | ||
1640 | val = readl(clk_mgt[clock].reg); | |
1641 | ||
1642 | if (val & PRCM_CLK_MGT_CLK38) { | |
1643 | if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) | |
1644 | rate /= 2; | |
1645 | return rate; | |
1646 | } | |
1647 | ||
1648 | val |= clk_mgt[clock].pllsw; | |
1649 | pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1650 | ||
1651 | if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) | |
1652 | rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); | |
1653 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) | |
1654 | rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); | |
1655 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) | |
1656 | rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); | |
1657 | else | |
1658 | return 0; | |
1659 | ||
1660 | if ((clock == PRCMU_SGACLK) && | |
1661 | (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { | |
1662 | u64 r = (rate * 10); | |
1663 | ||
1664 | (void)do_div(r, 25); | |
1665 | return (unsigned long)r; | |
1666 | } | |
1667 | val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1668 | if (val) | |
1669 | return rate / val; | |
1670 | else | |
1671 | return 0; | |
1672 | } | |
20aee5b6 MJ |
1673 | static unsigned long latest_armss_rate; |
1674 | static unsigned long armss_rate(void) | |
1675 | { | |
1676 | return latest_armss_rate; | |
1677 | } | |
1678 | ||
1679 | static void compute_armss_rate(void) | |
1680 | { | |
1681 | u32 r; | |
1682 | unsigned long rate; | |
1683 | ||
1684 | r = readl(PRCM_ARM_CHGCLKREQ); | |
1685 | ||
1686 | if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { | |
1687 | /* External ARMCLKFIX clock */ | |
1688 | ||
1689 | rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); | |
1690 | ||
1691 | /* Check PRCM_ARM_CHGCLKREQ divider */ | |
1692 | if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) | |
1693 | rate /= 2; | |
1694 | ||
1695 | /* Check PRCM_ARMCLKFIX_MGT divider */ | |
1696 | r = readl(PRCM_ARMCLKFIX_MGT); | |
1697 | r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1698 | rate /= r; | |
1699 | ||
1700 | } else {/* ARM PLL */ | |
1701 | rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); | |
1702 | } | |
1703 | ||
1704 | latest_armss_rate = rate; | |
1705 | } | |
6b6fae2b MN |
1706 | |
1707 | static unsigned long dsiclk_rate(u8 n) | |
1708 | { | |
1709 | u32 divsel; | |
1710 | u32 div = 1; | |
1711 | ||
1712 | divsel = readl(PRCM_DSI_PLLOUT_SEL); | |
1713 | divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); | |
1714 | ||
1715 | if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) | |
1716 | divsel = dsiclk[n].divsel; | |
1717 | ||
1718 | switch (divsel) { | |
1719 | case PRCM_DSI_PLLOUT_SEL_PHI_4: | |
1720 | div *= 2; | |
1721 | case PRCM_DSI_PLLOUT_SEL_PHI_2: | |
1722 | div *= 2; | |
1723 | case PRCM_DSI_PLLOUT_SEL_PHI: | |
1724 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1725 | PLL_RAW) / div; | |
e62ccf3a | 1726 | default: |
6b6fae2b | 1727 | return 0; |
e62ccf3a | 1728 | } |
6b6fae2b MN |
1729 | } |
1730 | ||
1731 | static unsigned long dsiescclk_rate(u8 n) | |
1732 | { | |
1733 | u32 div; | |
1734 | ||
1735 | div = readl(PRCM_DSITVCLK_DIV); | |
1736 | div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); | |
1737 | return clock_rate(PRCMU_TVCLK) / max((u32)1, div); | |
1738 | } | |
1739 | ||
1740 | unsigned long prcmu_clock_rate(u8 clock) | |
1741 | { | |
e62ccf3a | 1742 | if (clock < PRCMU_NUM_REG_CLOCKS) |
6b6fae2b MN |
1743 | return clock_rate(clock); |
1744 | else if (clock == PRCMU_TIMCLK) | |
1745 | return ROOT_CLOCK_RATE / 16; | |
1746 | else if (clock == PRCMU_SYSCLK) | |
1747 | return ROOT_CLOCK_RATE; | |
1748 | else if (clock == PRCMU_PLLSOC0) | |
1749 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1750 | else if (clock == PRCMU_PLLSOC1) | |
1751 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
20aee5b6 MJ |
1752 | else if (clock == PRCMU_ARMSS) |
1753 | return armss_rate(); | |
6b6fae2b MN |
1754 | else if (clock == PRCMU_PLLDDR) |
1755 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1756 | else if (clock == PRCMU_PLLDSI) | |
1757 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1758 | PLL_RAW); | |
1759 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1760 | return dsiclk_rate(clock - PRCMU_DSI0CLK); | |
1761 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1762 | return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); | |
1763 | else | |
1764 | return 0; | |
1765 | } | |
1766 | ||
1767 | static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) | |
1768 | { | |
1769 | if (clk_mgt_val & PRCM_CLK_MGT_CLK38) | |
1770 | return ROOT_CLOCK_RATE; | |
1771 | clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; | |
1772 | if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) | |
1773 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); | |
1774 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) | |
1775 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); | |
1776 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) | |
1777 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); | |
1778 | else | |
1779 | return 0; | |
1780 | } | |
1781 | ||
1782 | static u32 clock_divider(unsigned long src_rate, unsigned long rate) | |
1783 | { | |
1784 | u32 div; | |
1785 | ||
1786 | div = (src_rate / rate); | |
1787 | if (div == 0) | |
1788 | return 1; | |
1789 | if (rate < (src_rate / div)) | |
1790 | div++; | |
1791 | return div; | |
1792 | } | |
1793 | ||
1794 | static long round_clock_rate(u8 clock, unsigned long rate) | |
1795 | { | |
1796 | u32 val; | |
1797 | u32 div; | |
1798 | unsigned long src_rate; | |
1799 | long rounded_rate; | |
1800 | ||
1801 | val = readl(clk_mgt[clock].reg); | |
1802 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), | |
1803 | clk_mgt[clock].branch); | |
1804 | div = clock_divider(src_rate, rate); | |
1805 | if (val & PRCM_CLK_MGT_CLK38) { | |
1806 | if (clk_mgt[clock].clk38div) { | |
1807 | if (div > 2) | |
1808 | div = 2; | |
1809 | } else { | |
1810 | div = 1; | |
1811 | } | |
1812 | } else if ((clock == PRCMU_SGACLK) && (div == 3)) { | |
1813 | u64 r = (src_rate * 10); | |
1814 | ||
1815 | (void)do_div(r, 25); | |
1816 | if (r <= rate) | |
1817 | return (unsigned long)r; | |
1818 | } | |
1819 | rounded_rate = (src_rate / min(div, (u32)31)); | |
1820 | ||
1821 | return rounded_rate; | |
1822 | } | |
1823 | ||
1824 | #define MIN_PLL_VCO_RATE 600000000ULL | |
1825 | #define MAX_PLL_VCO_RATE 1680640000ULL | |
1826 | ||
1827 | static long round_plldsi_rate(unsigned long rate) | |
1828 | { | |
1829 | long rounded_rate = 0; | |
1830 | unsigned long src_rate; | |
1831 | unsigned long rem; | |
1832 | u32 r; | |
1833 | ||
1834 | src_rate = clock_rate(PRCMU_HDMICLK); | |
1835 | rem = rate; | |
1836 | ||
1837 | for (r = 7; (rem > 0) && (r > 0); r--) { | |
1838 | u64 d; | |
1839 | ||
1840 | d = (r * rate); | |
1841 | (void)do_div(d, src_rate); | |
1842 | if (d < 6) | |
1843 | d = 6; | |
1844 | else if (d > 255) | |
1845 | d = 255; | |
1846 | d *= src_rate; | |
1847 | if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || | |
1848 | ((r * MAX_PLL_VCO_RATE) < (2 * d))) | |
1849 | continue; | |
1850 | (void)do_div(d, r); | |
1851 | if (rate < d) { | |
1852 | if (rounded_rate == 0) | |
1853 | rounded_rate = (long)d; | |
1854 | break; | |
1855 | } | |
1856 | if ((rate - d) < rem) { | |
1857 | rem = (rate - d); | |
1858 | rounded_rate = (long)d; | |
1859 | } | |
1860 | } | |
1861 | return rounded_rate; | |
1862 | } | |
1863 | ||
1864 | static long round_dsiclk_rate(unsigned long rate) | |
1865 | { | |
1866 | u32 div; | |
1867 | unsigned long src_rate; | |
1868 | long rounded_rate; | |
1869 | ||
1870 | src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1871 | PLL_RAW); | |
1872 | div = clock_divider(src_rate, rate); | |
1873 | rounded_rate = (src_rate / ((div > 2) ? 4 : div)); | |
1874 | ||
1875 | return rounded_rate; | |
1876 | } | |
1877 | ||
1878 | static long round_dsiescclk_rate(unsigned long rate) | |
1879 | { | |
1880 | u32 div; | |
1881 | unsigned long src_rate; | |
1882 | long rounded_rate; | |
1883 | ||
1884 | src_rate = clock_rate(PRCMU_TVCLK); | |
1885 | div = clock_divider(src_rate, rate); | |
1886 | rounded_rate = (src_rate / min(div, (u32)255)); | |
1887 | ||
1888 | return rounded_rate; | |
1889 | } | |
1890 | ||
1891 | long prcmu_round_clock_rate(u8 clock, unsigned long rate) | |
1892 | { | |
1893 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
1894 | return round_clock_rate(clock, rate); | |
1895 | else if (clock == PRCMU_PLLDSI) | |
1896 | return round_plldsi_rate(rate); | |
1897 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1898 | return round_dsiclk_rate(rate); | |
1899 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1900 | return round_dsiescclk_rate(rate); | |
1901 | else | |
1902 | return (long)prcmu_clock_rate(clock); | |
1903 | } | |
1904 | ||
1905 | static void set_clock_rate(u8 clock, unsigned long rate) | |
1906 | { | |
1907 | u32 val; | |
1908 | u32 div; | |
1909 | unsigned long src_rate; | |
1910 | unsigned long flags; | |
1911 | ||
1912 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1913 | ||
1914 | /* Grab the HW semaphore. */ | |
1915 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) | |
1916 | cpu_relax(); | |
1917 | ||
1918 | val = readl(clk_mgt[clock].reg); | |
1919 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), | |
1920 | clk_mgt[clock].branch); | |
1921 | div = clock_divider(src_rate, rate); | |
1922 | if (val & PRCM_CLK_MGT_CLK38) { | |
1923 | if (clk_mgt[clock].clk38div) { | |
1924 | if (div > 1) | |
1925 | val |= PRCM_CLK_MGT_CLK38DIV; | |
1926 | else | |
1927 | val &= ~PRCM_CLK_MGT_CLK38DIV; | |
1928 | } | |
1929 | } else if (clock == PRCMU_SGACLK) { | |
1930 | val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | | |
1931 | PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); | |
1932 | if (div == 3) { | |
1933 | u64 r = (src_rate * 10); | |
1934 | ||
1935 | (void)do_div(r, 25); | |
1936 | if (r <= rate) { | |
1937 | val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; | |
1938 | div = 0; | |
1939 | } | |
1940 | } | |
1941 | val |= min(div, (u32)31); | |
1942 | } else { | |
1943 | val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1944 | val |= min(div, (u32)31); | |
1945 | } | |
1946 | writel(val, clk_mgt[clock].reg); | |
1947 | ||
1948 | /* Release the HW semaphore. */ | |
1949 | writel(0, PRCM_SEM); | |
1950 | ||
1951 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1952 | } | |
1953 | ||
1954 | static int set_plldsi_rate(unsigned long rate) | |
1955 | { | |
1956 | unsigned long src_rate; | |
1957 | unsigned long rem; | |
1958 | u32 pll_freq = 0; | |
1959 | u32 r; | |
1960 | ||
1961 | src_rate = clock_rate(PRCMU_HDMICLK); | |
1962 | rem = rate; | |
1963 | ||
1964 | for (r = 7; (rem > 0) && (r > 0); r--) { | |
1965 | u64 d; | |
1966 | u64 hwrate; | |
1967 | ||
1968 | d = (r * rate); | |
1969 | (void)do_div(d, src_rate); | |
1970 | if (d < 6) | |
1971 | d = 6; | |
1972 | else if (d > 255) | |
1973 | d = 255; | |
1974 | hwrate = (d * src_rate); | |
1975 | if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || | |
1976 | ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) | |
1977 | continue; | |
1978 | (void)do_div(hwrate, r); | |
1979 | if (rate < hwrate) { | |
1980 | if (pll_freq == 0) | |
1981 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | | |
1982 | (r << PRCM_PLL_FREQ_R_SHIFT)); | |
1983 | break; | |
1984 | } | |
1985 | if ((rate - hwrate) < rem) { | |
1986 | rem = (rate - hwrate); | |
1987 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | | |
1988 | (r << PRCM_PLL_FREQ_R_SHIFT)); | |
1989 | } | |
1990 | } | |
1991 | if (pll_freq == 0) | |
1992 | return -EINVAL; | |
1993 | ||
1994 | pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); | |
1995 | writel(pll_freq, PRCM_PLLDSI_FREQ); | |
1996 | ||
1997 | return 0; | |
1998 | } | |
1999 | ||
2000 | static void set_dsiclk_rate(u8 n, unsigned long rate) | |
2001 | { | |
2002 | u32 val; | |
2003 | u32 div; | |
2004 | ||
2005 | div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, | |
2006 | clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); | |
2007 | ||
2008 | dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : | |
2009 | (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : | |
2010 | /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; | |
2011 | ||
2012 | val = readl(PRCM_DSI_PLLOUT_SEL); | |
2013 | val &= ~dsiclk[n].divsel_mask; | |
2014 | val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); | |
2015 | writel(val, PRCM_DSI_PLLOUT_SEL); | |
2016 | } | |
2017 | ||
2018 | static void set_dsiescclk_rate(u8 n, unsigned long rate) | |
2019 | { | |
2020 | u32 val; | |
2021 | u32 div; | |
2022 | ||
2023 | div = clock_divider(clock_rate(PRCMU_TVCLK), rate); | |
2024 | val = readl(PRCM_DSITVCLK_DIV); | |
2025 | val &= ~dsiescclk[n].div_mask; | |
2026 | val |= (min(div, (u32)255) << dsiescclk[n].div_shift); | |
2027 | writel(val, PRCM_DSITVCLK_DIV); | |
2028 | } | |
2029 | ||
2030 | int prcmu_set_clock_rate(u8 clock, unsigned long rate) | |
2031 | { | |
2032 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
2033 | set_clock_rate(clock, rate); | |
2034 | else if (clock == PRCMU_PLLDSI) | |
2035 | return set_plldsi_rate(rate); | |
2036 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
2037 | set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); | |
2038 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
2039 | set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); | |
2040 | return 0; | |
3df57bcf MN |
2041 | } |
2042 | ||
73180f85 | 2043 | int db8500_prcmu_config_esram0_deep_sleep(u8 state) |
3df57bcf MN |
2044 | { |
2045 | if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || | |
2046 | (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) | |
2047 | return -EINVAL; | |
2048 | ||
2049 | mutex_lock(&mb4_transfer.lock); | |
2050 | ||
c553b3ca | 2051 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2052 | cpu_relax(); |
2053 | ||
2054 | writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2055 | writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), | |
2056 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); | |
2057 | writeb(DDR_PWR_STATE_ON, | |
2058 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); | |
2059 | writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); | |
2060 | ||
c553b3ca | 2061 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2062 | wait_for_completion(&mb4_transfer.work); |
2063 | ||
2064 | mutex_unlock(&mb4_transfer.lock); | |
2065 | ||
2066 | return 0; | |
2067 | } | |
2068 | ||
0508901c | 2069 | int db8500_prcmu_config_hotdog(u8 threshold) |
3df57bcf MN |
2070 | { |
2071 | mutex_lock(&mb4_transfer.lock); | |
2072 | ||
c553b3ca | 2073 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2074 | cpu_relax(); |
2075 | ||
2076 | writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); | |
2077 | writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2078 | ||
c553b3ca | 2079 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2080 | wait_for_completion(&mb4_transfer.work); |
2081 | ||
2082 | mutex_unlock(&mb4_transfer.lock); | |
2083 | ||
2084 | return 0; | |
2085 | } | |
2086 | ||
0508901c | 2087 | int db8500_prcmu_config_hotmon(u8 low, u8 high) |
3df57bcf MN |
2088 | { |
2089 | mutex_lock(&mb4_transfer.lock); | |
2090 | ||
c553b3ca | 2091 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2092 | cpu_relax(); |
2093 | ||
2094 | writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); | |
2095 | writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); | |
2096 | writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), | |
2097 | (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); | |
2098 | writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2099 | ||
c553b3ca | 2100 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2101 | wait_for_completion(&mb4_transfer.work); |
2102 | ||
2103 | mutex_unlock(&mb4_transfer.lock); | |
2104 | ||
2105 | return 0; | |
2106 | } | |
2107 | ||
2108 | static int config_hot_period(u16 val) | |
2109 | { | |
2110 | mutex_lock(&mb4_transfer.lock); | |
2111 | ||
c553b3ca | 2112 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2113 | cpu_relax(); |
2114 | ||
2115 | writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); | |
2116 | writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2117 | ||
c553b3ca | 2118 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2119 | wait_for_completion(&mb4_transfer.work); |
2120 | ||
2121 | mutex_unlock(&mb4_transfer.lock); | |
2122 | ||
2123 | return 0; | |
2124 | } | |
2125 | ||
0508901c | 2126 | int db8500_prcmu_start_temp_sense(u16 cycles32k) |
3df57bcf MN |
2127 | { |
2128 | if (cycles32k == 0xFFFF) | |
2129 | return -EINVAL; | |
2130 | ||
2131 | return config_hot_period(cycles32k); | |
2132 | } | |
2133 | ||
0508901c | 2134 | int db8500_prcmu_stop_temp_sense(void) |
3df57bcf MN |
2135 | { |
2136 | return config_hot_period(0xFFFF); | |
2137 | } | |
2138 | ||
84165b80 JA |
2139 | static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) |
2140 | { | |
2141 | ||
2142 | mutex_lock(&mb4_transfer.lock); | |
2143 | ||
2144 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) | |
2145 | cpu_relax(); | |
2146 | ||
2147 | writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); | |
2148 | writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); | |
2149 | writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); | |
2150 | writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); | |
2151 | ||
2152 | writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2153 | ||
2154 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); | |
2155 | wait_for_completion(&mb4_transfer.work); | |
2156 | ||
2157 | mutex_unlock(&mb4_transfer.lock); | |
2158 | ||
2159 | return 0; | |
2160 | ||
2161 | } | |
2162 | ||
0508901c | 2163 | int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) |
84165b80 JA |
2164 | { |
2165 | BUG_ON(num == 0 || num > 0xf); | |
2166 | return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, | |
2167 | sleep_auto_off ? A9WDOG_AUTO_OFF_EN : | |
2168 | A9WDOG_AUTO_OFF_DIS); | |
2169 | } | |
2170 | ||
0508901c | 2171 | int db8500_prcmu_enable_a9wdog(u8 id) |
84165b80 JA |
2172 | { |
2173 | return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); | |
2174 | } | |
2175 | ||
0508901c | 2176 | int db8500_prcmu_disable_a9wdog(u8 id) |
84165b80 JA |
2177 | { |
2178 | return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); | |
2179 | } | |
2180 | ||
0508901c | 2181 | int db8500_prcmu_kick_a9wdog(u8 id) |
84165b80 JA |
2182 | { |
2183 | return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); | |
2184 | } | |
2185 | ||
2186 | /* | |
2187 | * timeout is 28 bit, in ms. | |
2188 | */ | |
0508901c | 2189 | int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) |
84165b80 | 2190 | { |
84165b80 JA |
2191 | return prcmu_a9wdog(MB4H_A9WDOG_LOAD, |
2192 | (id & A9WDOG_ID_MASK) | | |
2193 | /* | |
2194 | * Put the lowest 28 bits of timeout at | |
2195 | * offset 4. Four first bits are used for id. | |
2196 | */ | |
2197 | (u8)((timeout << 4) & 0xf0), | |
2198 | (u8)((timeout >> 4) & 0xff), | |
2199 | (u8)((timeout >> 12) & 0xff), | |
2200 | (u8)((timeout >> 20) & 0xff)); | |
2201 | } | |
2202 | ||
e3726fcf LW |
2203 | /** |
2204 | * prcmu_abb_read() - Read register value(s) from the ABB. | |
2205 | * @slave: The I2C slave address. | |
2206 | * @reg: The (start) register address. | |
2207 | * @value: The read out value(s). | |
2208 | * @size: The number of registers to read. | |
2209 | * | |
2210 | * Reads register value(s) from the ABB. | |
2211 | * @size has to be 1 for the current firmware version. | |
2212 | */ | |
2213 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
2214 | { | |
2215 | int r; | |
2216 | ||
2217 | if (size != 1) | |
2218 | return -EINVAL; | |
2219 | ||
3df57bcf | 2220 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 2221 | |
c553b3ca | 2222 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
2223 | cpu_relax(); |
2224 | ||
3c3e4898 | 2225 | writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
3df57bcf MN |
2226 | writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2227 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
2228 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
2229 | writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
2230 | ||
c553b3ca | 2231 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 2232 | |
e3726fcf | 2233 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
2234 | msecs_to_jiffies(20000))) { |
2235 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
2236 | __func__); | |
e3726fcf | 2237 | r = -EIO; |
3df57bcf MN |
2238 | } else { |
2239 | r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); | |
e3726fcf | 2240 | } |
3df57bcf | 2241 | |
e3726fcf LW |
2242 | if (!r) |
2243 | *value = mb5_transfer.ack.value; | |
2244 | ||
e3726fcf | 2245 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 2246 | |
e3726fcf LW |
2247 | return r; |
2248 | } | |
e3726fcf LW |
2249 | |
2250 | /** | |
3c3e4898 | 2251 | * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. |
e3726fcf LW |
2252 | * @slave: The I2C slave address. |
2253 | * @reg: The (start) register address. | |
2254 | * @value: The value(s) to write. | |
3c3e4898 | 2255 | * @mask: The mask(s) to use. |
e3726fcf LW |
2256 | * @size: The number of registers to write. |
2257 | * | |
3c3e4898 MN |
2258 | * Writes masked register value(s) to the ABB. |
2259 | * For each @value, only the bits set to 1 in the corresponding @mask | |
2260 | * will be written. The other bits are not changed. | |
e3726fcf LW |
2261 | * @size has to be 1 for the current firmware version. |
2262 | */ | |
3c3e4898 | 2263 | int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) |
e3726fcf LW |
2264 | { |
2265 | int r; | |
2266 | ||
2267 | if (size != 1) | |
2268 | return -EINVAL; | |
2269 | ||
3df57bcf | 2270 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 2271 | |
c553b3ca | 2272 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
2273 | cpu_relax(); |
2274 | ||
3c3e4898 | 2275 | writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
3df57bcf MN |
2276 | writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2277 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
2278 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
2279 | writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
2280 | ||
c553b3ca | 2281 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 2282 | |
e3726fcf | 2283 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
2284 | msecs_to_jiffies(20000))) { |
2285 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
2286 | __func__); | |
e3726fcf | 2287 | r = -EIO; |
3df57bcf MN |
2288 | } else { |
2289 | r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); | |
e3726fcf | 2290 | } |
e3726fcf | 2291 | |
e3726fcf | 2292 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 2293 | |
e3726fcf LW |
2294 | return r; |
2295 | } | |
e3726fcf | 2296 | |
3c3e4898 MN |
2297 | /** |
2298 | * prcmu_abb_write() - Write register value(s) to the ABB. | |
2299 | * @slave: The I2C slave address. | |
2300 | * @reg: The (start) register address. | |
2301 | * @value: The value(s) to write. | |
2302 | * @size: The number of registers to write. | |
2303 | * | |
2304 | * Writes register value(s) to the ABB. | |
2305 | * @size has to be 1 for the current firmware version. | |
2306 | */ | |
2307 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
2308 | { | |
2309 | u8 mask = ~0; | |
2310 | ||
2311 | return prcmu_abb_write_masked(slave, reg, value, &mask, size); | |
2312 | } | |
2313 | ||
3df57bcf MN |
2314 | /** |
2315 | * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem | |
2316 | */ | |
5261e101 | 2317 | int prcmu_ac_wake_req(void) |
e0befb23 | 2318 | { |
3df57bcf | 2319 | u32 val; |
5261e101 | 2320 | int ret = 0; |
e0befb23 | 2321 | |
3df57bcf | 2322 | mutex_lock(&mb0_transfer.ac_wake_lock); |
e0befb23 | 2323 | |
c553b3ca | 2324 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2325 | if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) |
2326 | goto unlock_and_return; | |
e0befb23 | 2327 | |
3df57bcf | 2328 | atomic_set(&ac_wake_req_state, 1); |
e0befb23 | 2329 | |
5261e101 AM |
2330 | /* |
2331 | * Force Modem Wake-up before hostaccess_req ping-pong. | |
2332 | * It prevents Modem to enter in Sleep while acking the hostaccess | |
2333 | * request. The 31us delay has been calculated by HWI. | |
2334 | */ | |
2335 | val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; | |
2336 | writel(val, PRCM_HOSTACCESS_REQ); | |
2337 | ||
2338 | udelay(31); | |
2339 | ||
2340 | val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; | |
2341 | writel(val, PRCM_HOSTACCESS_REQ); | |
e0befb23 | 2342 | |
3df57bcf | 2343 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
d6e3002e | 2344 | msecs_to_jiffies(5000))) { |
5261e101 AM |
2345 | #if defined(CONFIG_DBX500_PRCMU_DEBUG) |
2346 | db8500_prcmu_debug_dump(__func__, true, true); | |
2347 | #endif | |
57265bc1 | 2348 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
d6e3002e | 2349 | __func__); |
5261e101 | 2350 | ret = -EFAULT; |
3df57bcf | 2351 | } |
e0befb23 | 2352 | |
3df57bcf MN |
2353 | unlock_and_return: |
2354 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
5261e101 | 2355 | return ret; |
e0befb23 MP |
2356 | } |
2357 | ||
2358 | /** | |
3df57bcf | 2359 | * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem |
e0befb23 | 2360 | */ |
3df57bcf | 2361 | void prcmu_ac_sleep_req() |
e0befb23 | 2362 | { |
3df57bcf MN |
2363 | u32 val; |
2364 | ||
2365 | mutex_lock(&mb0_transfer.ac_wake_lock); | |
2366 | ||
c553b3ca | 2367 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2368 | if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) |
2369 | goto unlock_and_return; | |
2370 | ||
2371 | writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), | |
c553b3ca | 2372 | PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2373 | |
2374 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, | |
d6e3002e | 2375 | msecs_to_jiffies(5000))) { |
57265bc1 | 2376 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
3df57bcf MN |
2377 | __func__); |
2378 | } | |
2379 | ||
2380 | atomic_set(&ac_wake_req_state, 0); | |
2381 | ||
2382 | unlock_and_return: | |
2383 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 | 2384 | } |
e0befb23 | 2385 | |
73180f85 | 2386 | bool db8500_prcmu_is_ac_wake_requested(void) |
e0befb23 | 2387 | { |
3df57bcf | 2388 | return (atomic_read(&ac_wake_req_state) != 0); |
e0befb23 | 2389 | } |
e0befb23 MP |
2390 | |
2391 | /** | |
73180f85 | 2392 | * db8500_prcmu_system_reset - System reset |
e0befb23 | 2393 | * |
73180f85 | 2394 | * Saves the reset reason code and then sets the APE_SOFTRST register which |
3df57bcf | 2395 | * fires interrupt to fw |
e0befb23 | 2396 | */ |
73180f85 | 2397 | void db8500_prcmu_system_reset(u16 reset_code) |
e0befb23 | 2398 | { |
3df57bcf | 2399 | writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); |
c553b3ca | 2400 | writel(1, PRCM_APE_SOFTRST); |
e0befb23 | 2401 | } |
e0befb23 | 2402 | |
597045de SR |
2403 | /** |
2404 | * db8500_prcmu_get_reset_code - Retrieve SW reset reason code | |
2405 | * | |
2406 | * Retrieves the reset reason code stored by prcmu_system_reset() before | |
2407 | * last restart. | |
2408 | */ | |
2409 | u16 db8500_prcmu_get_reset_code(void) | |
2410 | { | |
2411 | return readw(tcdm_base + PRCM_SW_RST_REASON); | |
2412 | } | |
2413 | ||
e0befb23 | 2414 | /** |
0508901c | 2415 | * db8500_prcmu_reset_modem - ask the PRCMU to reset modem |
e0befb23 | 2416 | */ |
0508901c | 2417 | void db8500_prcmu_modem_reset(void) |
e0befb23 | 2418 | { |
3df57bcf MN |
2419 | mutex_lock(&mb1_transfer.lock); |
2420 | ||
c553b3ca | 2421 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
2422 | cpu_relax(); |
2423 | ||
2424 | writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
c553b3ca | 2425 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2426 | wait_for_completion(&mb1_transfer.work); |
2427 | ||
2428 | /* | |
2429 | * No need to check return from PRCMU as modem should go in reset state | |
2430 | * This state is already managed by upper layer | |
2431 | */ | |
2432 | ||
2433 | mutex_unlock(&mb1_transfer.lock); | |
e0befb23 | 2434 | } |
e0befb23 | 2435 | |
3df57bcf | 2436 | static void ack_dbb_wakeup(void) |
e0befb23 | 2437 | { |
3df57bcf MN |
2438 | unsigned long flags; |
2439 | ||
2440 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2441 | ||
c553b3ca | 2442 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
2443 | cpu_relax(); |
2444 | ||
2445 | writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 2446 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2447 | |
2448 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
e0befb23 | 2449 | } |
e0befb23 | 2450 | |
3df57bcf | 2451 | static inline void print_unknown_header_warning(u8 n, u8 header) |
e0befb23 | 2452 | { |
3df57bcf MN |
2453 | pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", |
2454 | header, n); | |
e0befb23 MP |
2455 | } |
2456 | ||
3df57bcf | 2457 | static bool read_mailbox_0(void) |
e3726fcf | 2458 | { |
3df57bcf MN |
2459 | bool r; |
2460 | u32 ev; | |
2461 | unsigned int n; | |
2462 | u8 header; | |
2463 | ||
2464 | header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); | |
2465 | switch (header) { | |
2466 | case MB0H_WAKEUP_EXE: | |
2467 | case MB0H_WAKEUP_SLEEP: | |
2468 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
2469 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); | |
2470 | else | |
2471 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); | |
2472 | ||
2473 | if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) | |
2474 | complete(&mb0_transfer.ac_wake_work); | |
2475 | if (ev & WAKEUP_BIT_SYSCLK_OK) | |
2476 | complete(&mb3_transfer.sysclk_work); | |
2477 | ||
2478 | ev &= mb0_transfer.req.dbb_irqs; | |
2479 | ||
2480 | for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { | |
2481 | if (ev & prcmu_irq_bit[n]) | |
2482 | generic_handle_irq(IRQ_PRCMU_BASE + n); | |
2483 | } | |
2484 | r = true; | |
2485 | break; | |
2486 | default: | |
2487 | print_unknown_header_warning(0, header); | |
2488 | r = false; | |
2489 | break; | |
2490 | } | |
c553b3ca | 2491 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); |
3df57bcf | 2492 | return r; |
e3726fcf LW |
2493 | } |
2494 | ||
3df57bcf | 2495 | static bool read_mailbox_1(void) |
e3726fcf | 2496 | { |
3df57bcf MN |
2497 | mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); |
2498 | mb1_transfer.ack.arm_opp = readb(tcdm_base + | |
2499 | PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
2500 | mb1_transfer.ack.ape_opp = readb(tcdm_base + | |
2501 | PRCM_ACK_MB1_CURRENT_APE_OPP); | |
2502 | mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + | |
2503 | PRCM_ACK_MB1_APE_VOLTAGE_STATUS); | |
c553b3ca | 2504 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); |
e0befb23 | 2505 | complete(&mb1_transfer.work); |
3df57bcf | 2506 | return false; |
e3726fcf LW |
2507 | } |
2508 | ||
3df57bcf | 2509 | static bool read_mailbox_2(void) |
e3726fcf | 2510 | { |
3df57bcf | 2511 | mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); |
c553b3ca | 2512 | writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2513 | complete(&mb2_transfer.work); |
2514 | return false; | |
e3726fcf LW |
2515 | } |
2516 | ||
3df57bcf | 2517 | static bool read_mailbox_3(void) |
e3726fcf | 2518 | { |
c553b3ca | 2519 | writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); |
3df57bcf | 2520 | return false; |
e3726fcf LW |
2521 | } |
2522 | ||
3df57bcf | 2523 | static bool read_mailbox_4(void) |
e3726fcf | 2524 | { |
3df57bcf MN |
2525 | u8 header; |
2526 | bool do_complete = true; | |
2527 | ||
2528 | header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); | |
2529 | switch (header) { | |
2530 | case MB4H_MEM_ST: | |
2531 | case MB4H_HOTDOG: | |
2532 | case MB4H_HOTMON: | |
2533 | case MB4H_HOT_PERIOD: | |
a592c2e2 MN |
2534 | case MB4H_A9WDOG_CONF: |
2535 | case MB4H_A9WDOG_EN: | |
2536 | case MB4H_A9WDOG_DIS: | |
2537 | case MB4H_A9WDOG_LOAD: | |
2538 | case MB4H_A9WDOG_KICK: | |
3df57bcf MN |
2539 | break; |
2540 | default: | |
2541 | print_unknown_header_warning(4, header); | |
2542 | do_complete = false; | |
2543 | break; | |
2544 | } | |
2545 | ||
c553b3ca | 2546 | writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2547 | |
2548 | if (do_complete) | |
2549 | complete(&mb4_transfer.work); | |
2550 | ||
2551 | return false; | |
e3726fcf LW |
2552 | } |
2553 | ||
3df57bcf | 2554 | static bool read_mailbox_5(void) |
e3726fcf | 2555 | { |
3df57bcf MN |
2556 | mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); |
2557 | mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); | |
c553b3ca | 2558 | writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); |
e3726fcf | 2559 | complete(&mb5_transfer.work); |
3df57bcf | 2560 | return false; |
e3726fcf LW |
2561 | } |
2562 | ||
3df57bcf | 2563 | static bool read_mailbox_6(void) |
e3726fcf | 2564 | { |
c553b3ca | 2565 | writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); |
3df57bcf | 2566 | return false; |
e3726fcf LW |
2567 | } |
2568 | ||
3df57bcf | 2569 | static bool read_mailbox_7(void) |
e3726fcf | 2570 | { |
c553b3ca | 2571 | writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); |
3df57bcf | 2572 | return false; |
e3726fcf LW |
2573 | } |
2574 | ||
3df57bcf | 2575 | static bool (* const read_mailbox[NUM_MB])(void) = { |
e3726fcf LW |
2576 | read_mailbox_0, |
2577 | read_mailbox_1, | |
2578 | read_mailbox_2, | |
2579 | read_mailbox_3, | |
2580 | read_mailbox_4, | |
2581 | read_mailbox_5, | |
2582 | read_mailbox_6, | |
2583 | read_mailbox_7 | |
2584 | }; | |
2585 | ||
2586 | static irqreturn_t prcmu_irq_handler(int irq, void *data) | |
2587 | { | |
2588 | u32 bits; | |
2589 | u8 n; | |
3df57bcf | 2590 | irqreturn_t r; |
e3726fcf | 2591 | |
c553b3ca | 2592 | bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); |
e3726fcf LW |
2593 | if (unlikely(!bits)) |
2594 | return IRQ_NONE; | |
2595 | ||
3df57bcf | 2596 | r = IRQ_HANDLED; |
e3726fcf LW |
2597 | for (n = 0; bits; n++) { |
2598 | if (bits & MBOX_BIT(n)) { | |
2599 | bits -= MBOX_BIT(n); | |
3df57bcf MN |
2600 | if (read_mailbox[n]()) |
2601 | r = IRQ_WAKE_THREAD; | |
e3726fcf LW |
2602 | } |
2603 | } | |
3df57bcf MN |
2604 | return r; |
2605 | } | |
2606 | ||
2607 | static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) | |
2608 | { | |
2609 | ack_dbb_wakeup(); | |
e3726fcf LW |
2610 | return IRQ_HANDLED; |
2611 | } | |
2612 | ||
3df57bcf MN |
2613 | static void prcmu_mask_work(struct work_struct *work) |
2614 | { | |
2615 | unsigned long flags; | |
2616 | ||
2617 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2618 | ||
2619 | config_wakeups(); | |
2620 | ||
2621 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
2622 | } | |
2623 | ||
2624 | static void prcmu_irq_mask(struct irq_data *d) | |
2625 | { | |
2626 | unsigned long flags; | |
2627 | ||
2628 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2629 | ||
f3f1f0a1 | 2630 | mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; |
3df57bcf MN |
2631 | |
2632 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2633 | ||
2634 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2635 | schedule_work(&mb0_transfer.mask_work); | |
2636 | } | |
2637 | ||
2638 | static void prcmu_irq_unmask(struct irq_data *d) | |
2639 | { | |
2640 | unsigned long flags; | |
2641 | ||
2642 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2643 | ||
f3f1f0a1 | 2644 | mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; |
3df57bcf MN |
2645 | |
2646 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2647 | ||
2648 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2649 | schedule_work(&mb0_transfer.mask_work); | |
2650 | } | |
2651 | ||
2652 | static void noop(struct irq_data *d) | |
2653 | { | |
2654 | } | |
2655 | ||
2656 | static struct irq_chip prcmu_irq_chip = { | |
2657 | .name = "prcmu", | |
2658 | .irq_disable = prcmu_irq_mask, | |
2659 | .irq_ack = noop, | |
2660 | .irq_mask = prcmu_irq_mask, | |
2661 | .irq_unmask = prcmu_irq_unmask, | |
2662 | }; | |
2663 | ||
b58d12fe MN |
2664 | static char *fw_project_name(u8 project) |
2665 | { | |
2666 | switch (project) { | |
2667 | case PRCMU_FW_PROJECT_U8500: | |
2668 | return "U8500"; | |
2669 | case PRCMU_FW_PROJECT_U8500_C2: | |
2670 | return "U8500 C2"; | |
2671 | case PRCMU_FW_PROJECT_U9500: | |
2672 | return "U9500"; | |
2673 | case PRCMU_FW_PROJECT_U9500_C2: | |
2674 | return "U9500 C2"; | |
5f96a1a6 BJ |
2675 | case PRCMU_FW_PROJECT_U8520: |
2676 | return "U8520"; | |
1927ddf6 BJ |
2677 | case PRCMU_FW_PROJECT_U8420: |
2678 | return "U8420"; | |
b58d12fe MN |
2679 | default: |
2680 | return "Unknown"; | |
2681 | } | |
2682 | } | |
2683 | ||
f3f1f0a1 LJ |
2684 | static int db8500_irq_map(struct irq_domain *d, unsigned int virq, |
2685 | irq_hw_number_t hwirq) | |
2686 | { | |
2687 | irq_set_chip_and_handler(virq, &prcmu_irq_chip, | |
2688 | handle_simple_irq); | |
2689 | set_irq_flags(virq, IRQF_VALID); | |
2690 | ||
2691 | return 0; | |
2692 | } | |
2693 | ||
2694 | static struct irq_domain_ops db8500_irq_ops = { | |
2695 | .map = db8500_irq_map, | |
2696 | .xlate = irq_domain_xlate_twocell, | |
2697 | }; | |
2698 | ||
2699 | static int db8500_irq_init(struct device_node *np) | |
2700 | { | |
2701 | db8500_irq_domain = irq_domain_add_legacy( | |
2702 | np, NUM_PRCMU_WAKEUPS, IRQ_PRCMU_BASE, | |
2703 | 0, &db8500_irq_ops, NULL); | |
2704 | ||
2705 | if (!db8500_irq_domain) { | |
2706 | pr_err("Failed to create irqdomain\n"); | |
2707 | return -ENOSYS; | |
2708 | } | |
2709 | ||
2710 | return 0; | |
2711 | } | |
2712 | ||
73180f85 | 2713 | void __init db8500_prcmu_early_init(void) |
fcbd458e | 2714 | { |
3e2762c8 | 2715 | if (cpu_is_u8500v2()) { |
3df57bcf MN |
2716 | void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); |
2717 | ||
2718 | if (tcpm_base != NULL) { | |
3e2762c8 | 2719 | u32 version; |
3df57bcf | 2720 | version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); |
b58d12fe MN |
2721 | fw_info.version.project = version & 0xFF; |
2722 | fw_info.version.api_version = (version >> 8) & 0xFF; | |
2723 | fw_info.version.func_version = (version >> 16) & 0xFF; | |
2724 | fw_info.version.errata = (version >> 24) & 0xFF; | |
2725 | fw_info.valid = true; | |
2726 | pr_info("PRCMU firmware: %s, version %d.%d.%d\n", | |
2727 | fw_project_name(fw_info.version.project), | |
3df57bcf MN |
2728 | (version >> 8) & 0xFF, (version >> 16) & 0xFF, |
2729 | (version >> 24) & 0xFF); | |
2730 | iounmap(tcpm_base); | |
2731 | } | |
2732 | ||
fcbd458e MW |
2733 | tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); |
2734 | } else { | |
2735 | pr_err("prcmu: Unsupported chip version\n"); | |
2736 | BUG(); | |
2737 | } | |
e0befb23 | 2738 | |
3df57bcf MN |
2739 | spin_lock_init(&mb0_transfer.lock); |
2740 | spin_lock_init(&mb0_transfer.dbb_irqs_lock); | |
2741 | mutex_init(&mb0_transfer.ac_wake_lock); | |
2742 | init_completion(&mb0_transfer.ac_wake_work); | |
e0befb23 MP |
2743 | mutex_init(&mb1_transfer.lock); |
2744 | init_completion(&mb1_transfer.work); | |
4d64d2e3 | 2745 | mb1_transfer.ape_opp = APE_NO_CHANGE; |
3df57bcf MN |
2746 | mutex_init(&mb2_transfer.lock); |
2747 | init_completion(&mb2_transfer.work); | |
2748 | spin_lock_init(&mb2_transfer.auto_pm_lock); | |
2749 | spin_lock_init(&mb3_transfer.lock); | |
2750 | mutex_init(&mb3_transfer.sysclk_lock); | |
2751 | init_completion(&mb3_transfer.sysclk_work); | |
2752 | mutex_init(&mb4_transfer.lock); | |
2753 | init_completion(&mb4_transfer.work); | |
e3726fcf LW |
2754 | mutex_init(&mb5_transfer.lock); |
2755 | init_completion(&mb5_transfer.work); | |
2756 | ||
3df57bcf MN |
2757 | INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); |
2758 | ||
20aee5b6 | 2759 | compute_armss_rate(); |
3df57bcf MN |
2760 | } |
2761 | ||
0508901c | 2762 | static void __init init_prcm_registers(void) |
d65e12d7 MN |
2763 | { |
2764 | u32 val; | |
2765 | ||
2766 | val = readl(PRCM_A9PL_FORCE_CLKEN); | |
2767 | val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | | |
2768 | PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); | |
2769 | writel(val, (PRCM_A9PL_FORCE_CLKEN)); | |
2770 | } | |
2771 | ||
1032fbfd BJ |
2772 | /* |
2773 | * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC | |
2774 | */ | |
2775 | static struct regulator_consumer_supply db8500_vape_consumers[] = { | |
2776 | REGULATOR_SUPPLY("v-ape", NULL), | |
2777 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), | |
2778 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), | |
2779 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), | |
2780 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), | |
ae840635 | 2781 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), |
1032fbfd BJ |
2782 | /* "v-mmc" changed to "vcore" in the mainline kernel */ |
2783 | REGULATOR_SUPPLY("vcore", "sdi0"), | |
2784 | REGULATOR_SUPPLY("vcore", "sdi1"), | |
2785 | REGULATOR_SUPPLY("vcore", "sdi2"), | |
2786 | REGULATOR_SUPPLY("vcore", "sdi3"), | |
2787 | REGULATOR_SUPPLY("vcore", "sdi4"), | |
2788 | REGULATOR_SUPPLY("v-dma", "dma40.0"), | |
2789 | REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), | |
2790 | /* "v-uart" changed to "vcore" in the mainline kernel */ | |
2791 | REGULATOR_SUPPLY("vcore", "uart0"), | |
2792 | REGULATOR_SUPPLY("vcore", "uart1"), | |
2793 | REGULATOR_SUPPLY("vcore", "uart2"), | |
2794 | REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), | |
992b133a | 2795 | REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), |
bc367481 | 2796 | REGULATOR_SUPPLY("vddvario", "smsc911x.0"), |
1032fbfd BJ |
2797 | }; |
2798 | ||
2799 | static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { | |
1032fbfd BJ |
2800 | REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), |
2801 | /* AV8100 regulator */ | |
2802 | REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), | |
2803 | }; | |
2804 | ||
2805 | static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { | |
992b133a | 2806 | REGULATOR_SUPPLY("vsupply", "b2r2_bus"), |
624e87c2 BJ |
2807 | REGULATOR_SUPPLY("vsupply", "mcde"), |
2808 | }; | |
2809 | ||
2810 | /* SVA MMDSP regulator switch */ | |
2811 | static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { | |
2812 | REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), | |
2813 | }; | |
2814 | ||
2815 | /* SVA pipe regulator switch */ | |
2816 | static struct regulator_consumer_supply db8500_svapipe_consumers[] = { | |
2817 | REGULATOR_SUPPLY("sva-pipe", "cm_control"), | |
2818 | }; | |
2819 | ||
2820 | /* SIA MMDSP regulator switch */ | |
2821 | static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { | |
2822 | REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), | |
2823 | }; | |
2824 | ||
2825 | /* SIA pipe regulator switch */ | |
2826 | static struct regulator_consumer_supply db8500_siapipe_consumers[] = { | |
2827 | REGULATOR_SUPPLY("sia-pipe", "cm_control"), | |
2828 | }; | |
2829 | ||
2830 | static struct regulator_consumer_supply db8500_sga_consumers[] = { | |
2831 | REGULATOR_SUPPLY("v-mali", NULL), | |
2832 | }; | |
2833 | ||
2834 | /* ESRAM1 and 2 regulator switch */ | |
2835 | static struct regulator_consumer_supply db8500_esram12_consumers[] = { | |
2836 | REGULATOR_SUPPLY("esram12", "cm_control"), | |
2837 | }; | |
2838 | ||
2839 | /* ESRAM3 and 4 regulator switch */ | |
2840 | static struct regulator_consumer_supply db8500_esram34_consumers[] = { | |
2841 | REGULATOR_SUPPLY("v-esram34", "mcde"), | |
2842 | REGULATOR_SUPPLY("esram34", "cm_control"), | |
992b133a | 2843 | REGULATOR_SUPPLY("lcla_esram", "dma40.0"), |
1032fbfd BJ |
2844 | }; |
2845 | ||
2846 | static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { | |
2847 | [DB8500_REGULATOR_VAPE] = { | |
2848 | .constraints = { | |
2849 | .name = "db8500-vape", | |
2850 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1e45860f | 2851 | .always_on = true, |
1032fbfd BJ |
2852 | }, |
2853 | .consumer_supplies = db8500_vape_consumers, | |
2854 | .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), | |
2855 | }, | |
2856 | [DB8500_REGULATOR_VARM] = { | |
2857 | .constraints = { | |
2858 | .name = "db8500-varm", | |
2859 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2860 | }, | |
2861 | }, | |
2862 | [DB8500_REGULATOR_VMODEM] = { | |
2863 | .constraints = { | |
2864 | .name = "db8500-vmodem", | |
2865 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2866 | }, | |
2867 | }, | |
2868 | [DB8500_REGULATOR_VPLL] = { | |
2869 | .constraints = { | |
2870 | .name = "db8500-vpll", | |
2871 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2872 | }, | |
2873 | }, | |
2874 | [DB8500_REGULATOR_VSMPS1] = { | |
2875 | .constraints = { | |
2876 | .name = "db8500-vsmps1", | |
2877 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2878 | }, | |
2879 | }, | |
2880 | [DB8500_REGULATOR_VSMPS2] = { | |
2881 | .constraints = { | |
2882 | .name = "db8500-vsmps2", | |
2883 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2884 | }, | |
2885 | .consumer_supplies = db8500_vsmps2_consumers, | |
2886 | .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), | |
2887 | }, | |
2888 | [DB8500_REGULATOR_VSMPS3] = { | |
2889 | .constraints = { | |
2890 | .name = "db8500-vsmps3", | |
2891 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2892 | }, | |
2893 | }, | |
2894 | [DB8500_REGULATOR_VRF1] = { | |
2895 | .constraints = { | |
2896 | .name = "db8500-vrf1", | |
2897 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2898 | }, | |
2899 | }, | |
2900 | [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { | |
992b133a | 2901 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2902 | .constraints = { |
2903 | .name = "db8500-sva-mmdsp", | |
2904 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2905 | }, | |
624e87c2 BJ |
2906 | .consumer_supplies = db8500_svammdsp_consumers, |
2907 | .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), | |
1032fbfd BJ |
2908 | }, |
2909 | [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { | |
2910 | .constraints = { | |
2911 | /* "ret" means "retention" */ | |
2912 | .name = "db8500-sva-mmdsp-ret", | |
2913 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2914 | }, | |
2915 | }, | |
2916 | [DB8500_REGULATOR_SWITCH_SVAPIPE] = { | |
992b133a | 2917 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2918 | .constraints = { |
2919 | .name = "db8500-sva-pipe", | |
2920 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2921 | }, | |
624e87c2 BJ |
2922 | .consumer_supplies = db8500_svapipe_consumers, |
2923 | .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), | |
1032fbfd BJ |
2924 | }, |
2925 | [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { | |
992b133a | 2926 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2927 | .constraints = { |
2928 | .name = "db8500-sia-mmdsp", | |
2929 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2930 | }, | |
624e87c2 BJ |
2931 | .consumer_supplies = db8500_siammdsp_consumers, |
2932 | .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), | |
1032fbfd BJ |
2933 | }, |
2934 | [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { | |
2935 | .constraints = { | |
2936 | .name = "db8500-sia-mmdsp-ret", | |
2937 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2938 | }, | |
2939 | }, | |
2940 | [DB8500_REGULATOR_SWITCH_SIAPIPE] = { | |
992b133a | 2941 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2942 | .constraints = { |
2943 | .name = "db8500-sia-pipe", | |
2944 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2945 | }, | |
624e87c2 BJ |
2946 | .consumer_supplies = db8500_siapipe_consumers, |
2947 | .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), | |
1032fbfd BJ |
2948 | }, |
2949 | [DB8500_REGULATOR_SWITCH_SGA] = { | |
2950 | .supply_regulator = "db8500-vape", | |
2951 | .constraints = { | |
2952 | .name = "db8500-sga", | |
2953 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2954 | }, | |
624e87c2 BJ |
2955 | .consumer_supplies = db8500_sga_consumers, |
2956 | .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), | |
2957 | ||
1032fbfd BJ |
2958 | }, |
2959 | [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { | |
2960 | .supply_regulator = "db8500-vape", | |
2961 | .constraints = { | |
2962 | .name = "db8500-b2r2-mcde", | |
2963 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2964 | }, | |
2965 | .consumer_supplies = db8500_b2r2_mcde_consumers, | |
2966 | .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), | |
2967 | }, | |
2968 | [DB8500_REGULATOR_SWITCH_ESRAM12] = { | |
992b133a BJ |
2969 | /* |
2970 | * esram12 is set in retention and supplied by Vsafe when Vape is off, | |
2971 | * no need to hold Vape | |
2972 | */ | |
1032fbfd BJ |
2973 | .constraints = { |
2974 | .name = "db8500-esram12", | |
2975 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2976 | }, | |
624e87c2 BJ |
2977 | .consumer_supplies = db8500_esram12_consumers, |
2978 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), | |
1032fbfd BJ |
2979 | }, |
2980 | [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { | |
2981 | .constraints = { | |
2982 | .name = "db8500-esram12-ret", | |
2983 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2984 | }, | |
2985 | }, | |
2986 | [DB8500_REGULATOR_SWITCH_ESRAM34] = { | |
992b133a BJ |
2987 | /* |
2988 | * esram34 is set in retention and supplied by Vsafe when Vape is off, | |
2989 | * no need to hold Vape | |
2990 | */ | |
1032fbfd BJ |
2991 | .constraints = { |
2992 | .name = "db8500-esram34", | |
2993 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2994 | }, | |
624e87c2 BJ |
2995 | .consumer_supplies = db8500_esram34_consumers, |
2996 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), | |
1032fbfd BJ |
2997 | }, |
2998 | [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { | |
2999 | .constraints = { | |
3000 | .name = "db8500-esram34-ret", | |
3001 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
3002 | }, | |
3003 | }, | |
3004 | }; | |
3005 | ||
c280f45f UH |
3006 | /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ |
3007 | static struct cpufreq_frequency_table db8500_cpufreq_table[] = { | |
3008 | { .frequency = 200000, .index = ARM_EXTCLK,}, | |
3009 | { .frequency = 400000, .index = ARM_50_OPP,}, | |
3010 | { .frequency = 800000, .index = ARM_100_OPP,}, | |
3011 | { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ | |
3012 | { .frequency = CPUFREQ_TABLE_END,}, | |
3013 | }; | |
3014 | ||
6d11d135 LJ |
3015 | static struct resource ab8500_resources[] = { |
3016 | [0] = { | |
3017 | .start = IRQ_DB8500_AB8500, | |
3018 | .end = IRQ_DB8500_AB8500, | |
3019 | .flags = IORESOURCE_IRQ | |
3020 | } | |
3021 | }; | |
3022 | ||
3df57bcf MN |
3023 | static struct mfd_cell db8500_prcmu_devs[] = { |
3024 | { | |
3025 | .name = "db8500-prcmu-regulators", | |
5d90322b | 3026 | .of_compatible = "stericsson,db8500-prcmu-regulator", |
1ed7891f MW |
3027 | .platform_data = &db8500_regulators, |
3028 | .pdata_size = sizeof(db8500_regulators), | |
3df57bcf MN |
3029 | }, |
3030 | { | |
3031 | .name = "cpufreq-u8500", | |
5d90322b | 3032 | .of_compatible = "stericsson,cpufreq-u8500", |
c280f45f UH |
3033 | .platform_data = &db8500_cpufreq_table, |
3034 | .pdata_size = sizeof(db8500_cpufreq_table), | |
3df57bcf | 3035 | }, |
6d11d135 LJ |
3036 | { |
3037 | .name = "ab8500-core", | |
3038 | .of_compatible = "stericsson,ab8500", | |
3039 | .num_resources = ARRAY_SIZE(ab8500_resources), | |
3040 | .resources = ab8500_resources, | |
3041 | .id = AB8500_VERSION_AB8500, | |
3042 | }, | |
3df57bcf MN |
3043 | }; |
3044 | ||
c280f45f UH |
3045 | static void db8500_prcmu_update_cpufreq(void) |
3046 | { | |
3047 | if (prcmu_has_arm_maxopp()) { | |
3048 | db8500_cpufreq_table[3].frequency = 1000000; | |
3049 | db8500_cpufreq_table[3].index = ARM_MAX_OPP; | |
3050 | } | |
3051 | } | |
3052 | ||
3df57bcf MN |
3053 | /** |
3054 | * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic | |
3055 | * | |
3056 | */ | |
9fc63f67 | 3057 | static int __devinit db8500_prcmu_probe(struct platform_device *pdev) |
3df57bcf | 3058 | { |
3a8e39c9 | 3059 | struct ab8500_platform_data *ab8500_platdata = pdev->dev.platform_data; |
ca7edd16 | 3060 | struct device_node *np = pdev->dev.of_node; |
3a8e39c9 | 3061 | int irq = 0, err = 0, i; |
3df57bcf MN |
3062 | |
3063 | if (ux500_is_svp()) | |
3064 | return -ENODEV; | |
3065 | ||
0508901c | 3066 | init_prcm_registers(); |
d65e12d7 | 3067 | |
e3726fcf | 3068 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
c553b3ca | 3069 | writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); |
3df57bcf | 3070 | |
ca7edd16 LJ |
3071 | if (np) |
3072 | irq = platform_get_irq(pdev, 0); | |
3073 | ||
3074 | if (!np || irq <= 0) | |
3075 | irq = IRQ_DB8500_PRCMU1; | |
3076 | ||
3077 | err = request_threaded_irq(irq, prcmu_irq_handler, | |
3078 | prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); | |
3df57bcf MN |
3079 | if (err < 0) { |
3080 | pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); | |
3081 | err = -EBUSY; | |
3082 | goto no_irq_return; | |
3083 | } | |
3084 | ||
f3f1f0a1 LJ |
3085 | db8500_irq_init(np); |
3086 | ||
3a8e39c9 LJ |
3087 | for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) { |
3088 | if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) { | |
3089 | db8500_prcmu_devs[i].platform_data = ab8500_platdata; | |
3c1534c7 | 3090 | db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data); |
3a8e39c9 LJ |
3091 | } |
3092 | } | |
3093 | ||
3df57bcf MN |
3094 | if (cpu_is_u8500v20_or_later()) |
3095 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); | |
3096 | ||
c280f45f UH |
3097 | db8500_prcmu_update_cpufreq(); |
3098 | ||
5d90322b | 3099 | err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, |
0848c94f | 3100 | ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL); |
5d90322b LJ |
3101 | if (err) { |
3102 | pr_err("prcmu: Failed to add subdevices\n"); | |
3103 | return err; | |
ca7edd16 | 3104 | } |
e3726fcf | 3105 | |
ca7edd16 | 3106 | pr_info("DB8500 PRCMU initialized\n"); |
3df57bcf MN |
3107 | |
3108 | no_irq_return: | |
3109 | return err; | |
3110 | } | |
3c144762 LJ |
3111 | static const struct of_device_id db8500_prcmu_match[] = { |
3112 | { .compatible = "stericsson,db8500-prcmu"}, | |
3113 | { }, | |
3114 | }; | |
3df57bcf MN |
3115 | |
3116 | static struct platform_driver db8500_prcmu_driver = { | |
3117 | .driver = { | |
3118 | .name = "db8500-prcmu", | |
3119 | .owner = THIS_MODULE, | |
3c144762 | 3120 | .of_match_table = db8500_prcmu_match, |
3df57bcf | 3121 | }, |
9fc63f67 | 3122 | .probe = db8500_prcmu_probe, |
3df57bcf MN |
3123 | }; |
3124 | ||
3125 | static int __init db8500_prcmu_init(void) | |
3126 | { | |
9fc63f67 | 3127 | return platform_driver_register(&db8500_prcmu_driver); |
e3726fcf LW |
3128 | } |
3129 | ||
a661aca4 | 3130 | core_initcall(db8500_prcmu_init); |
3df57bcf MN |
3131 | |
3132 | MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); | |
3133 | MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); | |
3134 | MODULE_LICENSE("GPL v2"); |