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e3726fcf | 1 | /* |
e0befb23 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
e3726fcf LW |
4 | * |
5 | * License Terms: GNU General Public License v2 | |
e0befb23 MP |
6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | |
e3726fcf LW |
8 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
9 | * | |
e0befb23 MP |
10 | * U8500 PRCM Unit interface driver |
11 | * | |
e3726fcf | 12 | */ |
e3726fcf | 13 | #include <linux/module.h> |
3df57bcf MN |
14 | #include <linux/kernel.h> |
15 | #include <linux/delay.h> | |
e3726fcf LW |
16 | #include <linux/errno.h> |
17 | #include <linux/err.h> | |
3df57bcf | 18 | #include <linux/spinlock.h> |
e3726fcf | 19 | #include <linux/io.h> |
3df57bcf | 20 | #include <linux/slab.h> |
e3726fcf LW |
21 | #include <linux/mutex.h> |
22 | #include <linux/completion.h> | |
3df57bcf | 23 | #include <linux/irq.h> |
e3726fcf LW |
24 | #include <linux/jiffies.h> |
25 | #include <linux/bitops.h> | |
3df57bcf MN |
26 | #include <linux/fs.h> |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
29 | #include <linux/mfd/core.h> | |
73180f85 | 30 | #include <linux/mfd/dbx500-prcmu.h> |
1032fbfd BJ |
31 | #include <linux/regulator/db8500-prcmu.h> |
32 | #include <linux/regulator/machine.h> | |
3df57bcf MN |
33 | #include <mach/hardware.h> |
34 | #include <mach/irqs.h> | |
35 | #include <mach/db8500-regs.h> | |
36 | #include <mach/id.h> | |
73180f85 | 37 | #include "dbx500-prcmu-regs.h" |
3df57bcf MN |
38 | |
39 | /* Offset for the firmware version within the TCPM */ | |
40 | #define PRCMU_FW_VERSION_OFFSET 0xA4 | |
41 | ||
42 | /* PRCMU project numbers, defined by PRCMU FW */ | |
43 | #define PRCMU_PROJECT_ID_8500V1_0 1 | |
44 | #define PRCMU_PROJECT_ID_8500V2_0 2 | |
45 | #define PRCMU_PROJECT_ID_8400V2_0 3 | |
46 | ||
47 | /* Index of different voltages to be used when accessing AVSData */ | |
48 | #define PRCM_AVS_BASE 0x2FC | |
49 | #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) | |
50 | #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) | |
51 | #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) | |
52 | #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) | |
53 | #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) | |
54 | #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) | |
55 | #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) | |
56 | #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) | |
57 | #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) | |
58 | #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) | |
59 | #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) | |
60 | #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) | |
61 | #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) | |
62 | ||
63 | #define PRCM_AVS_VOLTAGE 0 | |
64 | #define PRCM_AVS_VOLTAGE_MASK 0x3f | |
65 | #define PRCM_AVS_ISSLOWSTARTUP 6 | |
66 | #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) | |
67 | #define PRCM_AVS_ISMODEENABLE 7 | |
68 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) | |
69 | ||
70 | #define PRCM_BOOT_STATUS 0xFFF | |
71 | #define PRCM_ROMCODE_A2P 0xFFE | |
72 | #define PRCM_ROMCODE_P2A 0xFFD | |
73 | #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ | |
74 | ||
75 | #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ | |
76 | ||
77 | #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ | |
78 | #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) | |
79 | #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) | |
80 | #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) | |
81 | #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) | |
82 | #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) | |
83 | #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) | |
84 | #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) | |
85 | ||
86 | /* Req Mailboxes */ | |
87 | #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ | |
88 | #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ | |
89 | #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ | |
90 | #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ | |
91 | #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ | |
92 | #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ | |
93 | ||
94 | /* Ack Mailboxes */ | |
95 | #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ | |
96 | #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ | |
97 | #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ | |
98 | #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ | |
99 | #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ | |
100 | #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ | |
101 | ||
102 | /* Mailbox 0 headers */ | |
103 | #define MB0H_POWER_STATE_TRANS 0 | |
104 | #define MB0H_CONFIG_WAKEUPS_EXE 1 | |
105 | #define MB0H_READ_WAKEUP_ACK 3 | |
106 | #define MB0H_CONFIG_WAKEUPS_SLEEP 4 | |
107 | ||
108 | #define MB0H_WAKEUP_EXE 2 | |
109 | #define MB0H_WAKEUP_SLEEP 5 | |
110 | ||
111 | /* Mailbox 0 REQs */ | |
112 | #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) | |
113 | #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) | |
114 | #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) | |
115 | #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) | |
116 | #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) | |
117 | #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) | |
118 | ||
119 | /* Mailbox 0 ACKs */ | |
120 | #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) | |
121 | #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) | |
122 | #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) | |
123 | #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) | |
124 | #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) | |
125 | #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) | |
126 | #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 | |
127 | ||
128 | /* Mailbox 1 headers */ | |
129 | #define MB1H_ARM_APE_OPP 0x0 | |
130 | #define MB1H_RESET_MODEM 0x2 | |
131 | #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 | |
132 | #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 | |
133 | #define MB1H_RELEASE_USB_WAKEUP 0x5 | |
a592c2e2 | 134 | #define MB1H_PLL_ON_OFF 0x6 |
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135 | |
136 | /* Mailbox 1 Requests */ | |
137 | #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) | |
138 | #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) | |
a592c2e2 MN |
139 | #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) |
140 | #define PLL_SOC1_OFF 0x4 | |
141 | #define PLL_SOC1_ON 0x8 | |
3df57bcf MN |
142 | |
143 | /* Mailbox 1 ACKs */ | |
144 | #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) | |
145 | #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) | |
146 | #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) | |
147 | #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) | |
148 | ||
149 | /* Mailbox 2 headers */ | |
150 | #define MB2H_DPS 0x0 | |
151 | #define MB2H_AUTO_PWR 0x1 | |
152 | ||
153 | /* Mailbox 2 REQs */ | |
154 | #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) | |
155 | #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) | |
156 | #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) | |
157 | #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) | |
158 | #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) | |
159 | #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) | |
160 | #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) | |
161 | #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) | |
162 | #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) | |
163 | #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) | |
164 | ||
165 | /* Mailbox 2 ACKs */ | |
166 | #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) | |
167 | #define HWACC_PWR_ST_OK 0xFE | |
168 | ||
169 | /* Mailbox 3 headers */ | |
170 | #define MB3H_ANC 0x0 | |
171 | #define MB3H_SIDETONE 0x1 | |
172 | #define MB3H_SYSCLK 0xE | |
173 | ||
174 | /* Mailbox 3 Requests */ | |
175 | #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) | |
176 | #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) | |
177 | #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) | |
178 | #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) | |
179 | #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) | |
180 | #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) | |
181 | #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) | |
182 | ||
183 | /* Mailbox 4 headers */ | |
184 | #define MB4H_DDR_INIT 0x0 | |
185 | #define MB4H_MEM_ST 0x1 | |
186 | #define MB4H_HOTDOG 0x12 | |
187 | #define MB4H_HOTMON 0x13 | |
188 | #define MB4H_HOT_PERIOD 0x14 | |
a592c2e2 MN |
189 | #define MB4H_A9WDOG_CONF 0x16 |
190 | #define MB4H_A9WDOG_EN 0x17 | |
191 | #define MB4H_A9WDOG_DIS 0x18 | |
192 | #define MB4H_A9WDOG_LOAD 0x19 | |
193 | #define MB4H_A9WDOG_KICK 0x20 | |
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194 | |
195 | /* Mailbox 4 Requests */ | |
196 | #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) | |
197 | #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) | |
198 | #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) | |
199 | #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) | |
200 | #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) | |
201 | #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) | |
202 | #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) | |
203 | #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) | |
204 | #define HOTMON_CONFIG_LOW BIT(0) | |
205 | #define HOTMON_CONFIG_HIGH BIT(1) | |
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206 | #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) |
207 | #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) | |
208 | #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) | |
209 | #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) | |
210 | #define A9WDOG_AUTO_OFF_EN BIT(7) | |
211 | #define A9WDOG_AUTO_OFF_DIS 0 | |
212 | #define A9WDOG_ID_MASK 0xf | |
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213 | |
214 | /* Mailbox 5 Requests */ | |
215 | #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) | |
216 | #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) | |
217 | #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) | |
218 | #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) | |
219 | #define PRCMU_I2C_WRITE(slave) \ | |
220 | (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) | |
221 | #define PRCMU_I2C_READ(slave) \ | |
222 | (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) | |
223 | #define PRCMU_I2C_STOP_EN BIT(3) | |
224 | ||
225 | /* Mailbox 5 ACKs */ | |
226 | #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) | |
227 | #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) | |
228 | #define I2C_WR_OK 0x1 | |
229 | #define I2C_RD_OK 0x2 | |
230 | ||
231 | #define NUM_MB 8 | |
232 | #define MBOX_BIT BIT | |
233 | #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) | |
234 | ||
235 | /* | |
236 | * Wakeups/IRQs | |
237 | */ | |
238 | ||
239 | #define WAKEUP_BIT_RTC BIT(0) | |
240 | #define WAKEUP_BIT_RTT0 BIT(1) | |
241 | #define WAKEUP_BIT_RTT1 BIT(2) | |
242 | #define WAKEUP_BIT_HSI0 BIT(3) | |
243 | #define WAKEUP_BIT_HSI1 BIT(4) | |
244 | #define WAKEUP_BIT_CA_WAKE BIT(5) | |
245 | #define WAKEUP_BIT_USB BIT(6) | |
246 | #define WAKEUP_BIT_ABB BIT(7) | |
247 | #define WAKEUP_BIT_ABB_FIFO BIT(8) | |
248 | #define WAKEUP_BIT_SYSCLK_OK BIT(9) | |
249 | #define WAKEUP_BIT_CA_SLEEP BIT(10) | |
250 | #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) | |
251 | #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) | |
252 | #define WAKEUP_BIT_ANC_OK BIT(13) | |
253 | #define WAKEUP_BIT_SW_ERROR BIT(14) | |
254 | #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) | |
255 | #define WAKEUP_BIT_ARM BIT(17) | |
256 | #define WAKEUP_BIT_HOTMON_LOW BIT(18) | |
257 | #define WAKEUP_BIT_HOTMON_HIGH BIT(19) | |
258 | #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) | |
259 | #define WAKEUP_BIT_GPIO0 BIT(23) | |
260 | #define WAKEUP_BIT_GPIO1 BIT(24) | |
261 | #define WAKEUP_BIT_GPIO2 BIT(25) | |
262 | #define WAKEUP_BIT_GPIO3 BIT(26) | |
263 | #define WAKEUP_BIT_GPIO4 BIT(27) | |
264 | #define WAKEUP_BIT_GPIO5 BIT(28) | |
265 | #define WAKEUP_BIT_GPIO6 BIT(29) | |
266 | #define WAKEUP_BIT_GPIO7 BIT(30) | |
267 | #define WAKEUP_BIT_GPIO8 BIT(31) | |
268 | ||
269 | /* | |
270 | * This vector maps irq numbers to the bits in the bit field used in | |
271 | * communication with the PRCMU firmware. | |
272 | * | |
273 | * The reason for having this is to keep the irq numbers contiguous even though | |
274 | * the bits in the bit field are not. (The bits also have a tendency to move | |
275 | * around, to further complicate matters.) | |
276 | */ | |
277 | #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) | |
278 | #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) | |
279 | static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { | |
280 | IRQ_ENTRY(RTC), | |
281 | IRQ_ENTRY(RTT0), | |
282 | IRQ_ENTRY(RTT1), | |
283 | IRQ_ENTRY(HSI0), | |
284 | IRQ_ENTRY(HSI1), | |
285 | IRQ_ENTRY(CA_WAKE), | |
286 | IRQ_ENTRY(USB), | |
287 | IRQ_ENTRY(ABB), | |
288 | IRQ_ENTRY(ABB_FIFO), | |
289 | IRQ_ENTRY(CA_SLEEP), | |
290 | IRQ_ENTRY(ARM), | |
291 | IRQ_ENTRY(HOTMON_LOW), | |
292 | IRQ_ENTRY(HOTMON_HIGH), | |
293 | IRQ_ENTRY(MODEM_SW_RESET_REQ), | |
294 | IRQ_ENTRY(GPIO0), | |
295 | IRQ_ENTRY(GPIO1), | |
296 | IRQ_ENTRY(GPIO2), | |
297 | IRQ_ENTRY(GPIO3), | |
298 | IRQ_ENTRY(GPIO4), | |
299 | IRQ_ENTRY(GPIO5), | |
300 | IRQ_ENTRY(GPIO6), | |
301 | IRQ_ENTRY(GPIO7), | |
302 | IRQ_ENTRY(GPIO8) | |
303 | }; | |
304 | ||
305 | #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) | |
306 | #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) | |
307 | static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { | |
308 | WAKEUP_ENTRY(RTC), | |
309 | WAKEUP_ENTRY(RTT0), | |
310 | WAKEUP_ENTRY(RTT1), | |
311 | WAKEUP_ENTRY(HSI0), | |
312 | WAKEUP_ENTRY(HSI1), | |
313 | WAKEUP_ENTRY(USB), | |
314 | WAKEUP_ENTRY(ABB), | |
315 | WAKEUP_ENTRY(ABB_FIFO), | |
316 | WAKEUP_ENTRY(ARM) | |
317 | }; | |
318 | ||
319 | /* | |
320 | * mb0_transfer - state needed for mailbox 0 communication. | |
321 | * @lock: The transaction lock. | |
322 | * @dbb_events_lock: A lock used to handle concurrent access to (parts of) | |
323 | * the request data. | |
324 | * @mask_work: Work structure used for (un)masking wakeup interrupts. | |
325 | * @req: Request data that need to persist between requests. | |
326 | */ | |
327 | static struct { | |
328 | spinlock_t lock; | |
329 | spinlock_t dbb_irqs_lock; | |
330 | struct work_struct mask_work; | |
331 | struct mutex ac_wake_lock; | |
332 | struct completion ac_wake_work; | |
333 | struct { | |
334 | u32 dbb_irqs; | |
335 | u32 dbb_wakeups; | |
336 | u32 abb_events; | |
337 | } req; | |
338 | } mb0_transfer; | |
339 | ||
340 | /* | |
341 | * mb1_transfer - state needed for mailbox 1 communication. | |
342 | * @lock: The transaction lock. | |
343 | * @work: The transaction completion structure. | |
344 | * @ack: Reply ("acknowledge") data. | |
345 | */ | |
346 | static struct { | |
347 | struct mutex lock; | |
348 | struct completion work; | |
349 | struct { | |
350 | u8 header; | |
351 | u8 arm_opp; | |
352 | u8 ape_opp; | |
353 | u8 ape_voltage_status; | |
354 | } ack; | |
355 | } mb1_transfer; | |
356 | ||
357 | /* | |
358 | * mb2_transfer - state needed for mailbox 2 communication. | |
359 | * @lock: The transaction lock. | |
360 | * @work: The transaction completion structure. | |
361 | * @auto_pm_lock: The autonomous power management configuration lock. | |
362 | * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. | |
363 | * @req: Request data that need to persist between requests. | |
364 | * @ack: Reply ("acknowledge") data. | |
365 | */ | |
366 | static struct { | |
367 | struct mutex lock; | |
368 | struct completion work; | |
369 | spinlock_t auto_pm_lock; | |
370 | bool auto_pm_enabled; | |
371 | struct { | |
372 | u8 status; | |
373 | } ack; | |
374 | } mb2_transfer; | |
375 | ||
376 | /* | |
377 | * mb3_transfer - state needed for mailbox 3 communication. | |
378 | * @lock: The request lock. | |
379 | * @sysclk_lock: A lock used to handle concurrent sysclk requests. | |
380 | * @sysclk_work: Work structure used for sysclk requests. | |
381 | */ | |
382 | static struct { | |
383 | spinlock_t lock; | |
384 | struct mutex sysclk_lock; | |
385 | struct completion sysclk_work; | |
386 | } mb3_transfer; | |
387 | ||
388 | /* | |
389 | * mb4_transfer - state needed for mailbox 4 communication. | |
390 | * @lock: The transaction lock. | |
391 | * @work: The transaction completion structure. | |
392 | */ | |
393 | static struct { | |
394 | struct mutex lock; | |
395 | struct completion work; | |
396 | } mb4_transfer; | |
397 | ||
398 | /* | |
399 | * mb5_transfer - state needed for mailbox 5 communication. | |
400 | * @lock: The transaction lock. | |
401 | * @work: The transaction completion structure. | |
402 | * @ack: Reply ("acknowledge") data. | |
403 | */ | |
404 | static struct { | |
405 | struct mutex lock; | |
406 | struct completion work; | |
407 | struct { | |
408 | u8 status; | |
409 | u8 value; | |
410 | } ack; | |
411 | } mb5_transfer; | |
412 | ||
413 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); | |
414 | ||
415 | /* Spinlocks */ | |
416 | static DEFINE_SPINLOCK(clkout_lock); | |
417 | static DEFINE_SPINLOCK(gpiocr_lock); | |
418 | ||
419 | /* Global var to runtime determine TCDM base for v2 or v1 */ | |
420 | static __iomem void *tcdm_base; | |
421 | ||
422 | struct clk_mgt { | |
423 | unsigned int offset; | |
424 | u32 pllsw; | |
425 | }; | |
426 | ||
427 | static DEFINE_SPINLOCK(clk_mgt_lock); | |
428 | ||
c553b3ca | 429 | #define CLK_MGT_ENTRY(_name)[PRCMU_##_name] = { (PRCM_##_name##_MGT_OFF), 0 } |
3df57bcf MN |
430 | struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { |
431 | CLK_MGT_ENTRY(SGACLK), | |
432 | CLK_MGT_ENTRY(UARTCLK), | |
433 | CLK_MGT_ENTRY(MSP02CLK), | |
434 | CLK_MGT_ENTRY(MSP1CLK), | |
435 | CLK_MGT_ENTRY(I2CCLK), | |
436 | CLK_MGT_ENTRY(SDMMCCLK), | |
437 | CLK_MGT_ENTRY(SLIMCLK), | |
438 | CLK_MGT_ENTRY(PER1CLK), | |
439 | CLK_MGT_ENTRY(PER2CLK), | |
440 | CLK_MGT_ENTRY(PER3CLK), | |
441 | CLK_MGT_ENTRY(PER5CLK), | |
442 | CLK_MGT_ENTRY(PER6CLK), | |
443 | CLK_MGT_ENTRY(PER7CLK), | |
444 | CLK_MGT_ENTRY(LCDCLK), | |
445 | CLK_MGT_ENTRY(BMLCLK), | |
446 | CLK_MGT_ENTRY(HSITXCLK), | |
447 | CLK_MGT_ENTRY(HSIRXCLK), | |
448 | CLK_MGT_ENTRY(HDMICLK), | |
449 | CLK_MGT_ENTRY(APEATCLK), | |
450 | CLK_MGT_ENTRY(APETRACECLK), | |
451 | CLK_MGT_ENTRY(MCDECLK), | |
452 | CLK_MGT_ENTRY(IPI2CCLK), | |
453 | CLK_MGT_ENTRY(DSIALTCLK), | |
454 | CLK_MGT_ENTRY(DMACLK), | |
455 | CLK_MGT_ENTRY(B2R2CLK), | |
456 | CLK_MGT_ENTRY(TVCLK), | |
457 | CLK_MGT_ENTRY(SSPCLK), | |
458 | CLK_MGT_ENTRY(RNGCLK), | |
459 | CLK_MGT_ENTRY(UICCCLK), | |
460 | }; | |
461 | ||
0837bb72 MN |
462 | static struct regulator *hwacc_regulator[NUM_HW_ACC]; |
463 | static struct regulator *hwacc_ret_regulator[NUM_HW_ACC]; | |
464 | ||
465 | static bool hwacc_enabled[NUM_HW_ACC]; | |
466 | static bool hwacc_ret_enabled[NUM_HW_ACC]; | |
467 | ||
468 | static const char *hwacc_regulator_name[NUM_HW_ACC] = { | |
469 | [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp", | |
470 | [HW_ACC_SVAPIPE] = "hwacc-sva-pipe", | |
471 | [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp", | |
472 | [HW_ACC_SIAPIPE] = "hwacc-sia-pipe", | |
473 | [HW_ACC_SGA] = "hwacc-sga", | |
474 | [HW_ACC_B2R2] = "hwacc-b2r2", | |
475 | [HW_ACC_MCDE] = "hwacc-mcde", | |
476 | [HW_ACC_ESRAM1] = "hwacc-esram1", | |
477 | [HW_ACC_ESRAM2] = "hwacc-esram2", | |
478 | [HW_ACC_ESRAM3] = "hwacc-esram3", | |
479 | [HW_ACC_ESRAM4] = "hwacc-esram4", | |
480 | }; | |
481 | ||
482 | static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { | |
483 | [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp-ret", | |
484 | [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp-ret", | |
485 | [HW_ACC_ESRAM1] = "hwacc-esram1-ret", | |
486 | [HW_ACC_ESRAM2] = "hwacc-esram2-ret", | |
487 | [HW_ACC_ESRAM3] = "hwacc-esram3-ret", | |
488 | [HW_ACC_ESRAM4] = "hwacc-esram4-ret", | |
489 | }; | |
490 | ||
3df57bcf MN |
491 | /* |
492 | * Used by MCDE to setup all necessary PRCMU registers | |
493 | */ | |
494 | #define PRCMU_RESET_DSIPLL 0x00004000 | |
495 | #define PRCMU_UNCLAMP_DSIPLL 0x00400800 | |
496 | ||
497 | #define PRCMU_CLK_PLL_DIV_SHIFT 0 | |
498 | #define PRCMU_CLK_PLL_SW_SHIFT 5 | |
499 | #define PRCMU_CLK_38 (1 << 9) | |
500 | #define PRCMU_CLK_38_SRC (1 << 10) | |
501 | #define PRCMU_CLK_38_DIV (1 << 11) | |
502 | ||
503 | /* PLLDIV=12, PLLSW=4 (PLLDDR) */ | |
504 | #define PRCMU_DSI_CLOCK_SETTING 0x0000008C | |
505 | ||
3df57bcf MN |
506 | /* DPI 50000000 Hz */ |
507 | #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ | |
508 | (16 << PRCMU_CLK_PLL_DIV_SHIFT)) | |
509 | #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 | |
510 | ||
511 | /* D=101, N=1, R=4, SELDIV2=0 */ | |
512 | #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 | |
513 | ||
3df57bcf MN |
514 | #define PRCMU_ENABLE_PLLDSI 0x00000001 |
515 | #define PRCMU_DISABLE_PLLDSI 0x00000000 | |
516 | #define PRCMU_RELEASE_RESET_DSS 0x0000400C | |
517 | #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 | |
518 | /* ESC clk, div0=1, div1=1, div2=3 */ | |
519 | #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 | |
520 | #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 | |
521 | #define PRCMU_DSI_RESET_SW 0x00000007 | |
522 | ||
523 | #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 | |
524 | ||
525 | static struct { | |
526 | u8 project_number; | |
527 | u8 api_version; | |
528 | u8 func_version; | |
529 | u8 errata; | |
530 | } prcmu_version; | |
531 | ||
532 | ||
73180f85 | 533 | int db8500_prcmu_enable_dsipll(void) |
3df57bcf MN |
534 | { |
535 | int i; | |
3df57bcf MN |
536 | |
537 | /* Clear DSIPLL_RESETN */ | |
c553b3ca | 538 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); |
3df57bcf | 539 | /* Unclamp DSIPLL in/out */ |
c553b3ca | 540 | writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); |
3df57bcf | 541 | |
3df57bcf | 542 | /* Set DSI PLL FREQ */ |
c72fe851 | 543 | writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); |
c553b3ca | 544 | writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); |
3df57bcf | 545 | /* Enable Escape clocks */ |
c553b3ca | 546 | writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
547 | |
548 | /* Start DSI PLL */ | |
c553b3ca | 549 | writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 550 | /* Reset DSI PLL */ |
c553b3ca | 551 | writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); |
3df57bcf | 552 | for (i = 0; i < 10; i++) { |
c553b3ca | 553 | if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) |
3df57bcf MN |
554 | == PRCMU_PLLDSI_LOCKP_LOCKED) |
555 | break; | |
556 | udelay(100); | |
557 | } | |
558 | /* Set DSIPLL_RESETN */ | |
c553b3ca | 559 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); |
3df57bcf MN |
560 | return 0; |
561 | } | |
562 | ||
73180f85 | 563 | int db8500_prcmu_disable_dsipll(void) |
3df57bcf MN |
564 | { |
565 | /* Disable dsi pll */ | |
c553b3ca | 566 | writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 567 | /* Disable escapeclock */ |
c553b3ca | 568 | writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
569 | return 0; |
570 | } | |
571 | ||
73180f85 | 572 | int db8500_prcmu_set_display_clocks(void) |
3df57bcf MN |
573 | { |
574 | unsigned long flags; | |
3df57bcf MN |
575 | |
576 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
577 | ||
578 | /* Grab the HW semaphore. */ | |
c553b3ca | 579 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
580 | cpu_relax(); |
581 | ||
c72fe851 | 582 | writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); |
c553b3ca MN |
583 | writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); |
584 | writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); | |
3df57bcf MN |
585 | |
586 | /* Release the HW semaphore. */ | |
c553b3ca | 587 | writel(0, PRCM_SEM); |
3df57bcf MN |
588 | |
589 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | /** | |
595 | * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. | |
596 | */ | |
597 | void prcmu_enable_spi2(void) | |
598 | { | |
599 | u32 reg; | |
600 | unsigned long flags; | |
601 | ||
602 | spin_lock_irqsave(&gpiocr_lock, flags); | |
c553b3ca MN |
603 | reg = readl(PRCM_GPIOCR); |
604 | writel(reg | PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); | |
3df57bcf MN |
605 | spin_unlock_irqrestore(&gpiocr_lock, flags); |
606 | } | |
607 | ||
608 | /** | |
609 | * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. | |
610 | */ | |
611 | void prcmu_disable_spi2(void) | |
612 | { | |
613 | u32 reg; | |
614 | unsigned long flags; | |
615 | ||
616 | spin_lock_irqsave(&gpiocr_lock, flags); | |
c553b3ca MN |
617 | reg = readl(PRCM_GPIOCR); |
618 | writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); | |
3df57bcf MN |
619 | spin_unlock_irqrestore(&gpiocr_lock, flags); |
620 | } | |
621 | ||
622 | bool prcmu_has_arm_maxopp(void) | |
623 | { | |
624 | return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & | |
625 | PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; | |
626 | } | |
627 | ||
3df57bcf MN |
628 | /** |
629 | * prcmu_get_boot_status - PRCMU boot status checking | |
630 | * Returns: the current PRCMU boot status | |
631 | */ | |
632 | int prcmu_get_boot_status(void) | |
633 | { | |
634 | return readb(tcdm_base + PRCM_BOOT_STATUS); | |
635 | } | |
636 | ||
637 | /** | |
638 | * prcmu_set_rc_a2p - This function is used to run few power state sequences | |
639 | * @val: Value to be set, i.e. transition requested | |
640 | * Returns: 0 on success, -EINVAL on invalid argument | |
641 | * | |
642 | * This function is used to run the following power state sequences - | |
643 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
644 | */ | |
645 | int prcmu_set_rc_a2p(enum romcode_write val) | |
646 | { | |
647 | if (val < RDY_2_DS || val > RDY_2_XP70_RST) | |
648 | return -EINVAL; | |
649 | writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); | |
650 | return 0; | |
651 | } | |
652 | ||
653 | /** | |
654 | * prcmu_get_rc_p2a - This function is used to get power state sequences | |
655 | * Returns: the power transition that has last happened | |
656 | * | |
657 | * This function can return the following transitions- | |
658 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
659 | */ | |
660 | enum romcode_read prcmu_get_rc_p2a(void) | |
661 | { | |
662 | return readb(tcdm_base + PRCM_ROMCODE_P2A); | |
663 | } | |
664 | ||
665 | /** | |
666 | * prcmu_get_current_mode - Return the current XP70 power mode | |
667 | * Returns: Returns the current AP(ARM) power mode: init, | |
668 | * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset | |
669 | */ | |
670 | enum ap_pwrst prcmu_get_xp70_current_state(void) | |
671 | { | |
672 | return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); | |
673 | } | |
674 | ||
675 | /** | |
676 | * prcmu_config_clkout - Configure one of the programmable clock outputs. | |
677 | * @clkout: The CLKOUT number (0 or 1). | |
678 | * @source: The clock to be used (one of the PRCMU_CLKSRC_*). | |
679 | * @div: The divider to be applied. | |
680 | * | |
681 | * Configures one of the programmable clock outputs (CLKOUTs). | |
682 | * @div should be in the range [1,63] to request a configuration, or 0 to | |
683 | * inform that the configuration is no longer requested. | |
684 | */ | |
685 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div) | |
686 | { | |
687 | static int requests[2]; | |
688 | int r = 0; | |
689 | unsigned long flags; | |
690 | u32 val; | |
691 | u32 bits; | |
692 | u32 mask; | |
693 | u32 div_mask; | |
694 | ||
695 | BUG_ON(clkout > 1); | |
696 | BUG_ON(div > 63); | |
697 | BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); | |
698 | ||
699 | if (!div && !requests[clkout]) | |
700 | return -EINVAL; | |
701 | ||
702 | switch (clkout) { | |
703 | case 0: | |
704 | div_mask = PRCM_CLKOCR_CLKODIV0_MASK; | |
705 | mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); | |
706 | bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | | |
707 | (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); | |
708 | break; | |
709 | case 1: | |
710 | div_mask = PRCM_CLKOCR_CLKODIV1_MASK; | |
711 | mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | | |
712 | PRCM_CLKOCR_CLK1TYPE); | |
713 | bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | | |
714 | (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); | |
715 | break; | |
716 | } | |
717 | bits &= mask; | |
718 | ||
719 | spin_lock_irqsave(&clkout_lock, flags); | |
720 | ||
c553b3ca | 721 | val = readl(PRCM_CLKOCR); |
3df57bcf MN |
722 | if (val & div_mask) { |
723 | if (div) { | |
724 | if ((val & mask) != bits) { | |
725 | r = -EBUSY; | |
726 | goto unlock_and_return; | |
727 | } | |
728 | } else { | |
729 | if ((val & mask & ~div_mask) != bits) { | |
730 | r = -EINVAL; | |
731 | goto unlock_and_return; | |
732 | } | |
733 | } | |
734 | } | |
c553b3ca | 735 | writel((bits | (val & ~mask)), PRCM_CLKOCR); |
3df57bcf MN |
736 | requests[clkout] += (div ? 1 : -1); |
737 | ||
738 | unlock_and_return: | |
739 | spin_unlock_irqrestore(&clkout_lock, flags); | |
740 | ||
741 | return r; | |
742 | } | |
743 | ||
73180f85 | 744 | int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) |
3df57bcf MN |
745 | { |
746 | unsigned long flags; | |
747 | ||
748 | BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); | |
749 | ||
750 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
751 | ||
c553b3ca | 752 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
753 | cpu_relax(); |
754 | ||
755 | writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
756 | writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); | |
757 | writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); | |
758 | writeb((keep_ulp_clk ? 1 : 0), | |
759 | (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); | |
760 | writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); | |
c553b3ca | 761 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
762 | |
763 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | /* This function should only be called while mb0_transfer.lock is held. */ | |
769 | static void config_wakeups(void) | |
770 | { | |
771 | const u8 header[2] = { | |
772 | MB0H_CONFIG_WAKEUPS_EXE, | |
773 | MB0H_CONFIG_WAKEUPS_SLEEP | |
774 | }; | |
775 | static u32 last_dbb_events; | |
776 | static u32 last_abb_events; | |
777 | u32 dbb_events; | |
778 | u32 abb_events; | |
779 | unsigned int i; | |
780 | ||
781 | dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; | |
782 | dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); | |
783 | ||
784 | abb_events = mb0_transfer.req.abb_events; | |
785 | ||
786 | if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) | |
787 | return; | |
788 | ||
789 | for (i = 0; i < 2; i++) { | |
c553b3ca | 790 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
791 | cpu_relax(); |
792 | writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); | |
793 | writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); | |
794 | writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 795 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
796 | } |
797 | last_dbb_events = dbb_events; | |
798 | last_abb_events = abb_events; | |
799 | } | |
800 | ||
73180f85 | 801 | void db8500_prcmu_enable_wakeups(u32 wakeups) |
3df57bcf MN |
802 | { |
803 | unsigned long flags; | |
804 | u32 bits; | |
805 | int i; | |
806 | ||
807 | BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); | |
808 | ||
809 | for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { | |
810 | if (wakeups & BIT(i)) | |
811 | bits |= prcmu_wakeup_bit[i]; | |
812 | } | |
813 | ||
814 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
815 | ||
816 | mb0_transfer.req.dbb_wakeups = bits; | |
817 | config_wakeups(); | |
818 | ||
819 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
820 | } | |
821 | ||
73180f85 | 822 | void db8500_prcmu_config_abb_event_readout(u32 abb_events) |
3df57bcf MN |
823 | { |
824 | unsigned long flags; | |
825 | ||
826 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
827 | ||
828 | mb0_transfer.req.abb_events = abb_events; | |
829 | config_wakeups(); | |
830 | ||
831 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
832 | } | |
833 | ||
73180f85 | 834 | void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) |
3df57bcf MN |
835 | { |
836 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
837 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); | |
838 | else | |
839 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); | |
840 | } | |
841 | ||
842 | /** | |
73180f85 | 843 | * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP |
3df57bcf MN |
844 | * @opp: The new ARM operating point to which transition is to be made |
845 | * Returns: 0 on success, non-zero on failure | |
846 | * | |
847 | * This function sets the the operating point of the ARM. | |
848 | */ | |
73180f85 | 849 | int db8500_prcmu_set_arm_opp(u8 opp) |
3df57bcf MN |
850 | { |
851 | int r; | |
852 | ||
853 | if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) | |
854 | return -EINVAL; | |
855 | ||
856 | r = 0; | |
857 | ||
858 | mutex_lock(&mb1_transfer.lock); | |
859 | ||
c553b3ca | 860 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
861 | cpu_relax(); |
862 | ||
863 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
864 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
865 | writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
866 | ||
c553b3ca | 867 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
868 | wait_for_completion(&mb1_transfer.work); |
869 | ||
870 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
871 | (mb1_transfer.ack.arm_opp != opp)) | |
872 | r = -EIO; | |
873 | ||
874 | mutex_unlock(&mb1_transfer.lock); | |
875 | ||
876 | return r; | |
877 | } | |
878 | ||
879 | /** | |
73180f85 | 880 | * db8500_prcmu_get_arm_opp - get the current ARM OPP |
3df57bcf MN |
881 | * |
882 | * Returns: the current ARM OPP | |
883 | */ | |
73180f85 | 884 | int db8500_prcmu_get_arm_opp(void) |
3df57bcf MN |
885 | { |
886 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
887 | } | |
888 | ||
889 | /** | |
890 | * prcmu_get_ddr_opp - get the current DDR OPP | |
891 | * | |
892 | * Returns: the current DDR OPP | |
893 | */ | |
894 | int prcmu_get_ddr_opp(void) | |
895 | { | |
c553b3ca | 896 | return readb(PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
897 | } |
898 | ||
899 | /** | |
900 | * set_ddr_opp - set the appropriate DDR OPP | |
901 | * @opp: The new DDR operating point to which transition is to be made | |
902 | * Returns: 0 on success, non-zero on failure | |
903 | * | |
904 | * This function sets the operating point of the DDR. | |
905 | */ | |
906 | int prcmu_set_ddr_opp(u8 opp) | |
907 | { | |
908 | if (opp < DDR_100_OPP || opp > DDR_25_OPP) | |
909 | return -EINVAL; | |
910 | /* Changing the DDR OPP can hang the hardware pre-v21 */ | |
911 | if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) | |
c553b3ca | 912 | writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
913 | |
914 | return 0; | |
915 | } | |
916 | /** | |
917 | * set_ape_opp - set the appropriate APE OPP | |
918 | * @opp: The new APE operating point to which transition is to be made | |
919 | * Returns: 0 on success, non-zero on failure | |
920 | * | |
921 | * This function sets the operating point of the APE. | |
922 | */ | |
923 | int prcmu_set_ape_opp(u8 opp) | |
924 | { | |
925 | int r = 0; | |
926 | ||
927 | mutex_lock(&mb1_transfer.lock); | |
928 | ||
c553b3ca | 929 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
930 | cpu_relax(); |
931 | ||
932 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
933 | writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
934 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
935 | ||
c553b3ca | 936 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
937 | wait_for_completion(&mb1_transfer.work); |
938 | ||
939 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
940 | (mb1_transfer.ack.ape_opp != opp)) | |
941 | r = -EIO; | |
942 | ||
943 | mutex_unlock(&mb1_transfer.lock); | |
944 | ||
945 | return r; | |
946 | } | |
947 | ||
948 | /** | |
949 | * prcmu_get_ape_opp - get the current APE OPP | |
950 | * | |
951 | * Returns: the current APE OPP | |
952 | */ | |
953 | int prcmu_get_ape_opp(void) | |
954 | { | |
955 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); | |
956 | } | |
957 | ||
958 | /** | |
959 | * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage | |
960 | * @enable: true to request the higher voltage, false to drop a request. | |
961 | * | |
962 | * Calls to this function to enable and disable requests must be balanced. | |
963 | */ | |
964 | int prcmu_request_ape_opp_100_voltage(bool enable) | |
965 | { | |
966 | int r = 0; | |
967 | u8 header; | |
968 | static unsigned int requests; | |
969 | ||
970 | mutex_lock(&mb1_transfer.lock); | |
971 | ||
972 | if (enable) { | |
973 | if (0 != requests++) | |
974 | goto unlock_and_return; | |
975 | header = MB1H_REQUEST_APE_OPP_100_VOLT; | |
976 | } else { | |
977 | if (requests == 0) { | |
978 | r = -EIO; | |
979 | goto unlock_and_return; | |
980 | } else if (1 != requests--) { | |
981 | goto unlock_and_return; | |
982 | } | |
983 | header = MB1H_RELEASE_APE_OPP_100_VOLT; | |
984 | } | |
985 | ||
c553b3ca | 986 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
987 | cpu_relax(); |
988 | ||
989 | writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
990 | ||
c553b3ca | 991 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
992 | wait_for_completion(&mb1_transfer.work); |
993 | ||
994 | if ((mb1_transfer.ack.header != header) || | |
995 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
996 | r = -EIO; | |
997 | ||
998 | unlock_and_return: | |
999 | mutex_unlock(&mb1_transfer.lock); | |
1000 | ||
1001 | return r; | |
1002 | } | |
1003 | ||
1004 | /** | |
1005 | * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup | |
1006 | * | |
1007 | * This function releases the power state requirements of a USB wakeup. | |
1008 | */ | |
1009 | int prcmu_release_usb_wakeup_state(void) | |
1010 | { | |
1011 | int r = 0; | |
1012 | ||
1013 | mutex_lock(&mb1_transfer.lock); | |
1014 | ||
c553b3ca | 1015 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1016 | cpu_relax(); |
1017 | ||
1018 | writeb(MB1H_RELEASE_USB_WAKEUP, | |
1019 | (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1020 | ||
c553b3ca | 1021 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1022 | wait_for_completion(&mb1_transfer.work); |
1023 | ||
1024 | if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || | |
1025 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1026 | r = -EIO; | |
1027 | ||
1028 | mutex_unlock(&mb1_transfer.lock); | |
1029 | ||
1030 | return r; | |
1031 | } | |
1032 | ||
0837bb72 MN |
1033 | static int request_pll(u8 clock, bool enable) |
1034 | { | |
1035 | int r = 0; | |
1036 | ||
1037 | if (clock == PRCMU_PLLSOC1) | |
1038 | clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); | |
1039 | else | |
1040 | return -EINVAL; | |
1041 | ||
1042 | mutex_lock(&mb1_transfer.lock); | |
1043 | ||
1044 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) | |
1045 | cpu_relax(); | |
1046 | ||
1047 | writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1048 | writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); | |
1049 | ||
1050 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); | |
1051 | wait_for_completion(&mb1_transfer.work); | |
1052 | ||
1053 | if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) | |
1054 | r = -EIO; | |
1055 | ||
1056 | mutex_unlock(&mb1_transfer.lock); | |
1057 | ||
1058 | return r; | |
1059 | } | |
1060 | ||
0b9199e3 BJ |
1061 | /** |
1062 | * prcmu_set_hwacc - set the power state of a h/w accelerator | |
1063 | * @hwacc_dev: The hardware accelerator (enum hw_acc_dev). | |
1064 | * @state: The new power state (enum hw_acc_state). | |
1065 | * | |
1066 | * This function sets the power state of a hardware accelerator. | |
1067 | * This function should not be called from interrupt context. | |
1068 | * | |
1069 | * NOTE! Deprecated, to be removed when all users switched over to use the | |
1070 | * regulator framework API. | |
1071 | */ | |
1072 | int prcmu_set_hwacc(u16 hwacc_dev, u8 state) | |
1073 | { | |
1074 | int r = 0; | |
1075 | bool ram_retention = false; | |
1076 | bool enable, enable_ret; | |
1077 | ||
1078 | /* check argument */ | |
1079 | BUG_ON(hwacc_dev >= NUM_HW_ACC); | |
1080 | ||
1081 | /* get state of switches */ | |
1082 | enable = hwacc_enabled[hwacc_dev]; | |
1083 | enable_ret = hwacc_ret_enabled[hwacc_dev]; | |
1084 | ||
1085 | /* set flag if retention is possible */ | |
1086 | switch (hwacc_dev) { | |
1087 | case HW_ACC_SVAMMDSP: | |
1088 | case HW_ACC_SIAMMDSP: | |
1089 | case HW_ACC_ESRAM1: | |
1090 | case HW_ACC_ESRAM2: | |
1091 | case HW_ACC_ESRAM3: | |
1092 | case HW_ACC_ESRAM4: | |
1093 | ram_retention = true; | |
1094 | break; | |
1095 | } | |
1096 | ||
1097 | /* check argument */ | |
1098 | BUG_ON(state > HW_ON); | |
1099 | BUG_ON(state == HW_OFF_RAMRET && !ram_retention); | |
1100 | ||
1101 | /* modify enable flags */ | |
1102 | switch (state) { | |
1103 | case HW_OFF: | |
1104 | enable_ret = false; | |
1105 | enable = false; | |
1106 | break; | |
1107 | case HW_ON: | |
1108 | enable = true; | |
1109 | break; | |
1110 | case HW_OFF_RAMRET: | |
1111 | enable_ret = true; | |
1112 | enable = false; | |
1113 | break; | |
1114 | } | |
1115 | ||
1116 | /* get regulator (lazy) */ | |
1117 | if (hwacc_regulator[hwacc_dev] == NULL) { | |
1118 | hwacc_regulator[hwacc_dev] = regulator_get(NULL, | |
1119 | hwacc_regulator_name[hwacc_dev]); | |
1120 | if (IS_ERR(hwacc_regulator[hwacc_dev])) { | |
1121 | pr_err("prcmu: failed to get supply %s\n", | |
1122 | hwacc_regulator_name[hwacc_dev]); | |
1123 | r = PTR_ERR(hwacc_regulator[hwacc_dev]); | |
1124 | goto out; | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | if (ram_retention) { | |
1129 | if (hwacc_ret_regulator[hwacc_dev] == NULL) { | |
1130 | hwacc_ret_regulator[hwacc_dev] = regulator_get(NULL, | |
1131 | hwacc_ret_regulator_name[hwacc_dev]); | |
1132 | if (IS_ERR(hwacc_ret_regulator[hwacc_dev])) { | |
1133 | pr_err("prcmu: failed to get supply %s\n", | |
1134 | hwacc_ret_regulator_name[hwacc_dev]); | |
1135 | r = PTR_ERR(hwacc_ret_regulator[hwacc_dev]); | |
1136 | goto out; | |
1137 | } | |
1138 | } | |
1139 | } | |
1140 | ||
1141 | /* set regulators */ | |
1142 | if (ram_retention) { | |
1143 | if (enable_ret && !hwacc_ret_enabled[hwacc_dev]) { | |
1144 | r = regulator_enable(hwacc_ret_regulator[hwacc_dev]); | |
1145 | if (r < 0) { | |
1146 | pr_err("prcmu_set_hwacc: ret enable failed\n"); | |
1147 | goto out; | |
1148 | } | |
1149 | hwacc_ret_enabled[hwacc_dev] = true; | |
1150 | } | |
1151 | } | |
1152 | ||
1153 | if (enable && !hwacc_enabled[hwacc_dev]) { | |
1154 | r = regulator_enable(hwacc_regulator[hwacc_dev]); | |
1155 | if (r < 0) { | |
1156 | pr_err("prcmu_set_hwacc: enable failed\n"); | |
1157 | goto out; | |
1158 | } | |
1159 | hwacc_enabled[hwacc_dev] = true; | |
1160 | } | |
1161 | ||
1162 | if (!enable && hwacc_enabled[hwacc_dev]) { | |
1163 | r = regulator_disable(hwacc_regulator[hwacc_dev]); | |
1164 | if (r < 0) { | |
1165 | pr_err("prcmu_set_hwacc: disable failed\n"); | |
1166 | goto out; | |
1167 | } | |
1168 | hwacc_enabled[hwacc_dev] = false; | |
1169 | } | |
1170 | ||
1171 | if (ram_retention) { | |
1172 | if (!enable_ret && hwacc_ret_enabled[hwacc_dev]) { | |
1173 | r = regulator_disable(hwacc_ret_regulator[hwacc_dev]); | |
1174 | if (r < 0) { | |
1175 | pr_err("prcmu_set_hwacc: ret disable failed\n"); | |
1176 | goto out; | |
1177 | } | |
1178 | hwacc_ret_enabled[hwacc_dev] = false; | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | out: | |
1183 | return r; | |
1184 | } | |
1185 | EXPORT_SYMBOL(prcmu_set_hwacc); | |
1186 | ||
3df57bcf | 1187 | /** |
73180f85 | 1188 | * db8500_prcmu_set_epod - set the state of a EPOD (power domain) |
3df57bcf MN |
1189 | * @epod_id: The EPOD to set |
1190 | * @epod_state: The new EPOD state | |
1191 | * | |
1192 | * This function sets the state of a EPOD (power domain). It may not be called | |
1193 | * from interrupt context. | |
1194 | */ | |
73180f85 | 1195 | int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) |
3df57bcf MN |
1196 | { |
1197 | int r = 0; | |
1198 | bool ram_retention = false; | |
1199 | int i; | |
1200 | ||
1201 | /* check argument */ | |
1202 | BUG_ON(epod_id >= NUM_EPOD_ID); | |
1203 | ||
1204 | /* set flag if retention is possible */ | |
1205 | switch (epod_id) { | |
1206 | case EPOD_ID_SVAMMDSP: | |
1207 | case EPOD_ID_SIAMMDSP: | |
1208 | case EPOD_ID_ESRAM12: | |
1209 | case EPOD_ID_ESRAM34: | |
1210 | ram_retention = true; | |
1211 | break; | |
1212 | } | |
1213 | ||
1214 | /* check argument */ | |
1215 | BUG_ON(epod_state > EPOD_STATE_ON); | |
1216 | BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); | |
1217 | ||
1218 | /* get lock */ | |
1219 | mutex_lock(&mb2_transfer.lock); | |
1220 | ||
1221 | /* wait for mailbox */ | |
c553b3ca | 1222 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) |
3df57bcf MN |
1223 | cpu_relax(); |
1224 | ||
1225 | /* fill in mailbox */ | |
1226 | for (i = 0; i < NUM_EPOD_ID; i++) | |
1227 | writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); | |
1228 | writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); | |
1229 | ||
1230 | writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); | |
1231 | ||
c553b3ca | 1232 | writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1233 | |
1234 | /* | |
1235 | * The current firmware version does not handle errors correctly, | |
1236 | * and we cannot recover if there is an error. | |
1237 | * This is expected to change when the firmware is updated. | |
1238 | */ | |
1239 | if (!wait_for_completion_timeout(&mb2_transfer.work, | |
1240 | msecs_to_jiffies(20000))) { | |
1241 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1242 | __func__); | |
1243 | r = -EIO; | |
1244 | goto unlock_and_return; | |
1245 | } | |
1246 | ||
1247 | if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) | |
1248 | r = -EIO; | |
1249 | ||
1250 | unlock_and_return: | |
1251 | mutex_unlock(&mb2_transfer.lock); | |
1252 | return r; | |
1253 | } | |
1254 | ||
1255 | /** | |
1256 | * prcmu_configure_auto_pm - Configure autonomous power management. | |
1257 | * @sleep: Configuration for ApSleep. | |
1258 | * @idle: Configuration for ApIdle. | |
1259 | */ | |
1260 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, | |
1261 | struct prcmu_auto_pm_config *idle) | |
1262 | { | |
1263 | u32 sleep_cfg; | |
1264 | u32 idle_cfg; | |
1265 | unsigned long flags; | |
e3726fcf | 1266 | |
3df57bcf | 1267 | BUG_ON((sleep == NULL) || (idle == NULL)); |
650c2a21 | 1268 | |
3df57bcf MN |
1269 | sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); |
1270 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); | |
1271 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); | |
1272 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); | |
1273 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); | |
1274 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); | |
e3726fcf | 1275 | |
3df57bcf MN |
1276 | idle_cfg = (idle->sva_auto_pm_enable & 0xF); |
1277 | idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); | |
1278 | idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); | |
1279 | idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); | |
1280 | idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); | |
1281 | idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); | |
e3726fcf | 1282 | |
3df57bcf | 1283 | spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); |
e0befb23 | 1284 | |
3df57bcf MN |
1285 | /* |
1286 | * The autonomous power management configuration is done through | |
1287 | * fields in mailbox 2, but these fields are only used as shared | |
1288 | * variables - i.e. there is no need to send a message. | |
1289 | */ | |
1290 | writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); | |
1291 | writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); | |
e0befb23 | 1292 | |
3df57bcf MN |
1293 | mb2_transfer.auto_pm_enabled = |
1294 | ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1295 | (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1296 | (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1297 | (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); | |
e0befb23 | 1298 | |
3df57bcf MN |
1299 | spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); |
1300 | } | |
1301 | EXPORT_SYMBOL(prcmu_configure_auto_pm); | |
e3726fcf | 1302 | |
3df57bcf MN |
1303 | bool prcmu_is_auto_pm_enabled(void) |
1304 | { | |
1305 | return mb2_transfer.auto_pm_enabled; | |
1306 | } | |
e0befb23 | 1307 | |
3df57bcf MN |
1308 | static int request_sysclk(bool enable) |
1309 | { | |
1310 | int r; | |
1311 | unsigned long flags; | |
e3726fcf | 1312 | |
3df57bcf | 1313 | r = 0; |
e3726fcf | 1314 | |
3df57bcf | 1315 | mutex_lock(&mb3_transfer.sysclk_lock); |
e0befb23 | 1316 | |
3df57bcf | 1317 | spin_lock_irqsave(&mb3_transfer.lock, flags); |
e0befb23 | 1318 | |
c553b3ca | 1319 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) |
3df57bcf | 1320 | cpu_relax(); |
e0befb23 | 1321 | |
3df57bcf | 1322 | writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); |
e3726fcf | 1323 | |
3df57bcf | 1324 | writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); |
c553b3ca | 1325 | writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); |
e3726fcf | 1326 | |
3df57bcf MN |
1327 | spin_unlock_irqrestore(&mb3_transfer.lock, flags); |
1328 | ||
1329 | /* | |
1330 | * The firmware only sends an ACK if we want to enable the | |
1331 | * SysClk, and it succeeds. | |
1332 | */ | |
1333 | if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, | |
1334 | msecs_to_jiffies(20000))) { | |
1335 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1336 | __func__); | |
1337 | r = -EIO; | |
1338 | } | |
1339 | ||
1340 | mutex_unlock(&mb3_transfer.sysclk_lock); | |
1341 | ||
1342 | return r; | |
1343 | } | |
1344 | ||
1345 | static int request_timclk(bool enable) | |
1346 | { | |
1347 | u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); | |
1348 | ||
1349 | if (!enable) | |
1350 | val |= PRCM_TCR_STOP_TIMERS; | |
c553b3ca | 1351 | writel(val, PRCM_TCR); |
3df57bcf MN |
1352 | |
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | static int request_reg_clock(u8 clock, bool enable) | |
1357 | { | |
1358 | u32 val; | |
1359 | unsigned long flags; | |
1360 | ||
1361 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1362 | ||
1363 | /* Grab the HW semaphore. */ | |
c553b3ca | 1364 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
1365 | cpu_relax(); |
1366 | ||
1367 | val = readl(_PRCMU_BASE + clk_mgt[clock].offset); | |
1368 | if (enable) { | |
1369 | val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); | |
1370 | } else { | |
1371 | clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1372 | val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1373 | } | |
1374 | writel(val, (_PRCMU_BASE + clk_mgt[clock].offset)); | |
1375 | ||
1376 | /* Release the HW semaphore. */ | |
c553b3ca | 1377 | writel(0, PRCM_SEM); |
3df57bcf MN |
1378 | |
1379 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
0837bb72 MN |
1384 | static int request_sga_clock(u8 clock, bool enable) |
1385 | { | |
1386 | u32 val; | |
1387 | int ret; | |
1388 | ||
1389 | if (enable) { | |
1390 | val = readl(PRCM_CGATING_BYPASS); | |
1391 | writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1392 | } | |
1393 | ||
1394 | ret = request_reg_clock(clock, enable); | |
1395 | ||
1396 | if (!ret && !enable) { | |
1397 | val = readl(PRCM_CGATING_BYPASS); | |
1398 | writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1399 | } | |
1400 | ||
1401 | return ret; | |
1402 | } | |
1403 | ||
3df57bcf | 1404 | /** |
73180f85 | 1405 | * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. |
3df57bcf MN |
1406 | * @clock: The clock for which the request is made. |
1407 | * @enable: Whether the clock should be enabled (true) or disabled (false). | |
1408 | * | |
1409 | * This function should only be used by the clock implementation. | |
1410 | * Do not use it from any other place! | |
1411 | */ | |
73180f85 | 1412 | int db8500_prcmu_request_clock(u8 clock, bool enable) |
3df57bcf | 1413 | { |
e62ccf3a LW |
1414 | switch(clock) { |
1415 | case PRCMU_SGACLK: | |
0837bb72 | 1416 | return request_sga_clock(clock, enable); |
e62ccf3a | 1417 | case PRCMU_TIMCLK: |
3df57bcf | 1418 | return request_timclk(enable); |
e62ccf3a | 1419 | case PRCMU_SYSCLK: |
3df57bcf | 1420 | return request_sysclk(enable); |
e62ccf3a | 1421 | case PRCMU_PLLSOC1: |
0837bb72 | 1422 | return request_pll(clock, enable); |
e62ccf3a LW |
1423 | default: |
1424 | break; | |
1425 | } | |
1426 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
1427 | return request_reg_clock(clock, enable); | |
1428 | return -EINVAL; | |
3df57bcf MN |
1429 | } |
1430 | ||
73180f85 | 1431 | int db8500_prcmu_config_esram0_deep_sleep(u8 state) |
3df57bcf MN |
1432 | { |
1433 | if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || | |
1434 | (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) | |
1435 | return -EINVAL; | |
1436 | ||
1437 | mutex_lock(&mb4_transfer.lock); | |
1438 | ||
c553b3ca | 1439 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1440 | cpu_relax(); |
1441 | ||
1442 | writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1443 | writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), | |
1444 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); | |
1445 | writeb(DDR_PWR_STATE_ON, | |
1446 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); | |
1447 | writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); | |
1448 | ||
c553b3ca | 1449 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1450 | wait_for_completion(&mb4_transfer.work); |
1451 | ||
1452 | mutex_unlock(&mb4_transfer.lock); | |
1453 | ||
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | int prcmu_config_hotdog(u8 threshold) | |
1458 | { | |
1459 | mutex_lock(&mb4_transfer.lock); | |
1460 | ||
c553b3ca | 1461 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1462 | cpu_relax(); |
1463 | ||
1464 | writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); | |
1465 | writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1466 | ||
c553b3ca | 1467 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1468 | wait_for_completion(&mb4_transfer.work); |
1469 | ||
1470 | mutex_unlock(&mb4_transfer.lock); | |
1471 | ||
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | int prcmu_config_hotmon(u8 low, u8 high) | |
1476 | { | |
1477 | mutex_lock(&mb4_transfer.lock); | |
1478 | ||
c553b3ca | 1479 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1480 | cpu_relax(); |
1481 | ||
1482 | writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); | |
1483 | writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); | |
1484 | writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), | |
1485 | (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); | |
1486 | writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1487 | ||
c553b3ca | 1488 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1489 | wait_for_completion(&mb4_transfer.work); |
1490 | ||
1491 | mutex_unlock(&mb4_transfer.lock); | |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
1496 | static int config_hot_period(u16 val) | |
1497 | { | |
1498 | mutex_lock(&mb4_transfer.lock); | |
1499 | ||
c553b3ca | 1500 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1501 | cpu_relax(); |
1502 | ||
1503 | writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); | |
1504 | writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1505 | ||
c553b3ca | 1506 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1507 | wait_for_completion(&mb4_transfer.work); |
1508 | ||
1509 | mutex_unlock(&mb4_transfer.lock); | |
1510 | ||
1511 | return 0; | |
1512 | } | |
1513 | ||
1514 | int prcmu_start_temp_sense(u16 cycles32k) | |
1515 | { | |
1516 | if (cycles32k == 0xFFFF) | |
1517 | return -EINVAL; | |
1518 | ||
1519 | return config_hot_period(cycles32k); | |
1520 | } | |
1521 | ||
1522 | int prcmu_stop_temp_sense(void) | |
1523 | { | |
1524 | return config_hot_period(0xFFFF); | |
1525 | } | |
1526 | ||
84165b80 JA |
1527 | static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) |
1528 | { | |
1529 | ||
1530 | mutex_lock(&mb4_transfer.lock); | |
1531 | ||
1532 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) | |
1533 | cpu_relax(); | |
1534 | ||
1535 | writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); | |
1536 | writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); | |
1537 | writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); | |
1538 | writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); | |
1539 | ||
1540 | writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1541 | ||
1542 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); | |
1543 | wait_for_completion(&mb4_transfer.work); | |
1544 | ||
1545 | mutex_unlock(&mb4_transfer.lock); | |
1546 | ||
1547 | return 0; | |
1548 | ||
1549 | } | |
1550 | ||
1551 | int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) | |
1552 | { | |
1553 | BUG_ON(num == 0 || num > 0xf); | |
1554 | return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, | |
1555 | sleep_auto_off ? A9WDOG_AUTO_OFF_EN : | |
1556 | A9WDOG_AUTO_OFF_DIS); | |
1557 | } | |
1558 | ||
1559 | int prcmu_enable_a9wdog(u8 id) | |
1560 | { | |
1561 | return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); | |
1562 | } | |
1563 | ||
1564 | int prcmu_disable_a9wdog(u8 id) | |
1565 | { | |
1566 | return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); | |
1567 | } | |
1568 | ||
1569 | int prcmu_kick_a9wdog(u8 id) | |
1570 | { | |
1571 | return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); | |
1572 | } | |
1573 | ||
1574 | /* | |
1575 | * timeout is 28 bit, in ms. | |
1576 | */ | |
1577 | #define MAX_WATCHDOG_TIMEOUT 131000 | |
1578 | int prcmu_load_a9wdog(u8 id, u32 timeout) | |
1579 | { | |
1580 | if (timeout > MAX_WATCHDOG_TIMEOUT) | |
1581 | /* | |
1582 | * Due to calculation bug in prcmu fw, timeouts | |
1583 | * can't be bigger than 131 seconds. | |
1584 | */ | |
1585 | return -EINVAL; | |
1586 | ||
1587 | return prcmu_a9wdog(MB4H_A9WDOG_LOAD, | |
1588 | (id & A9WDOG_ID_MASK) | | |
1589 | /* | |
1590 | * Put the lowest 28 bits of timeout at | |
1591 | * offset 4. Four first bits are used for id. | |
1592 | */ | |
1593 | (u8)((timeout << 4) & 0xf0), | |
1594 | (u8)((timeout >> 4) & 0xff), | |
1595 | (u8)((timeout >> 12) & 0xff), | |
1596 | (u8)((timeout >> 20) & 0xff)); | |
1597 | } | |
1598 | ||
3df57bcf MN |
1599 | /** |
1600 | * prcmu_set_clock_divider() - Configure the clock divider. | |
1601 | * @clock: The clock for which the request is made. | |
1602 | * @divider: The clock divider. (< 32) | |
1603 | * | |
1604 | * This function should only be used by the clock implementation. | |
1605 | * Do not use it from any other place! | |
1606 | */ | |
1607 | int prcmu_set_clock_divider(u8 clock, u8 divider) | |
1608 | { | |
1609 | u32 val; | |
1610 | unsigned long flags; | |
1611 | ||
1612 | if ((clock >= PRCMU_NUM_REG_CLOCKS) || (divider < 1) || (31 < divider)) | |
1613 | return -EINVAL; | |
1614 | ||
1615 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1616 | ||
1617 | /* Grab the HW semaphore. */ | |
c553b3ca | 1618 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
1619 | cpu_relax(); |
1620 | ||
1621 | val = readl(_PRCMU_BASE + clk_mgt[clock].offset); | |
1622 | val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK); | |
1623 | val |= (u32)divider; | |
1624 | writel(val, (_PRCMU_BASE + clk_mgt[clock].offset)); | |
1625 | ||
1626 | /* Release the HW semaphore. */ | |
c553b3ca | 1627 | writel(0, PRCM_SEM); |
3df57bcf MN |
1628 | |
1629 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1630 | ||
1631 | return 0; | |
1632 | } | |
e3726fcf LW |
1633 | |
1634 | /** | |
1635 | * prcmu_abb_read() - Read register value(s) from the ABB. | |
1636 | * @slave: The I2C slave address. | |
1637 | * @reg: The (start) register address. | |
1638 | * @value: The read out value(s). | |
1639 | * @size: The number of registers to read. | |
1640 | * | |
1641 | * Reads register value(s) from the ABB. | |
1642 | * @size has to be 1 for the current firmware version. | |
1643 | */ | |
1644 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
1645 | { | |
1646 | int r; | |
1647 | ||
1648 | if (size != 1) | |
1649 | return -EINVAL; | |
1650 | ||
3df57bcf | 1651 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 1652 | |
c553b3ca | 1653 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
1654 | cpu_relax(); |
1655 | ||
3df57bcf MN |
1656 | writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
1657 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
1658 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
1659 | writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
1660 | ||
c553b3ca | 1661 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 1662 | |
e3726fcf | 1663 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
1664 | msecs_to_jiffies(20000))) { |
1665 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1666 | __func__); | |
e3726fcf | 1667 | r = -EIO; |
3df57bcf MN |
1668 | } else { |
1669 | r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); | |
e3726fcf | 1670 | } |
3df57bcf | 1671 | |
e3726fcf LW |
1672 | if (!r) |
1673 | *value = mb5_transfer.ack.value; | |
1674 | ||
e3726fcf | 1675 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 1676 | |
e3726fcf LW |
1677 | return r; |
1678 | } | |
e3726fcf LW |
1679 | |
1680 | /** | |
1681 | * prcmu_abb_write() - Write register value(s) to the ABB. | |
1682 | * @slave: The I2C slave address. | |
1683 | * @reg: The (start) register address. | |
1684 | * @value: The value(s) to write. | |
1685 | * @size: The number of registers to write. | |
1686 | * | |
1687 | * Reads register value(s) from the ABB. | |
1688 | * @size has to be 1 for the current firmware version. | |
1689 | */ | |
1690 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
1691 | { | |
1692 | int r; | |
1693 | ||
1694 | if (size != 1) | |
1695 | return -EINVAL; | |
1696 | ||
3df57bcf | 1697 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 1698 | |
c553b3ca | 1699 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
1700 | cpu_relax(); |
1701 | ||
3df57bcf MN |
1702 | writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
1703 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
1704 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
1705 | writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
1706 | ||
c553b3ca | 1707 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 1708 | |
e3726fcf | 1709 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
1710 | msecs_to_jiffies(20000))) { |
1711 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1712 | __func__); | |
e3726fcf | 1713 | r = -EIO; |
3df57bcf MN |
1714 | } else { |
1715 | r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); | |
e3726fcf | 1716 | } |
e3726fcf | 1717 | |
e3726fcf | 1718 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 1719 | |
e3726fcf LW |
1720 | return r; |
1721 | } | |
e3726fcf | 1722 | |
3df57bcf MN |
1723 | /** |
1724 | * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem | |
1725 | */ | |
1726 | void prcmu_ac_wake_req(void) | |
e0befb23 | 1727 | { |
3df57bcf | 1728 | u32 val; |
d6e3002e | 1729 | u32 status; |
e0befb23 | 1730 | |
3df57bcf | 1731 | mutex_lock(&mb0_transfer.ac_wake_lock); |
e0befb23 | 1732 | |
c553b3ca | 1733 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
1734 | if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) |
1735 | goto unlock_and_return; | |
e0befb23 | 1736 | |
3df57bcf | 1737 | atomic_set(&ac_wake_req_state, 1); |
e0befb23 | 1738 | |
d6e3002e | 1739 | retry: |
c553b3ca | 1740 | writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); |
e0befb23 | 1741 | |
3df57bcf | 1742 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
d6e3002e | 1743 | msecs_to_jiffies(5000))) { |
57265bc1 | 1744 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
d6e3002e MN |
1745 | __func__); |
1746 | goto unlock_and_return; | |
1747 | } | |
1748 | ||
1749 | /* | |
1750 | * The modem can generate an AC_WAKE_ACK, and then still go to sleep. | |
1751 | * As a workaround, we wait, and then check that the modem is indeed | |
1752 | * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS | |
1753 | * register, which may not be the whole truth). | |
1754 | */ | |
1755 | udelay(400); | |
1756 | status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2)); | |
1757 | if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE | | |
1758 | PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) { | |
1759 | pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n", | |
1760 | __func__, status); | |
1761 | udelay(1200); | |
1762 | writel(val, PRCM_HOSTACCESS_REQ); | |
1763 | if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work, | |
1764 | msecs_to_jiffies(5000))) | |
1765 | goto retry; | |
57265bc1 | 1766 | pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n", |
3df57bcf MN |
1767 | __func__); |
1768 | } | |
e0befb23 | 1769 | |
3df57bcf MN |
1770 | unlock_and_return: |
1771 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 MP |
1772 | } |
1773 | ||
1774 | /** | |
3df57bcf | 1775 | * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem |
e0befb23 | 1776 | */ |
3df57bcf | 1777 | void prcmu_ac_sleep_req() |
e0befb23 | 1778 | { |
3df57bcf MN |
1779 | u32 val; |
1780 | ||
1781 | mutex_lock(&mb0_transfer.ac_wake_lock); | |
1782 | ||
c553b3ca | 1783 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
1784 | if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) |
1785 | goto unlock_and_return; | |
1786 | ||
1787 | writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), | |
c553b3ca | 1788 | PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
1789 | |
1790 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, | |
d6e3002e | 1791 | msecs_to_jiffies(5000))) { |
57265bc1 | 1792 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
3df57bcf MN |
1793 | __func__); |
1794 | } | |
1795 | ||
1796 | atomic_set(&ac_wake_req_state, 0); | |
1797 | ||
1798 | unlock_and_return: | |
1799 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 | 1800 | } |
e0befb23 | 1801 | |
73180f85 | 1802 | bool db8500_prcmu_is_ac_wake_requested(void) |
e0befb23 | 1803 | { |
3df57bcf | 1804 | return (atomic_read(&ac_wake_req_state) != 0); |
e0befb23 | 1805 | } |
e0befb23 MP |
1806 | |
1807 | /** | |
73180f85 | 1808 | * db8500_prcmu_system_reset - System reset |
e0befb23 | 1809 | * |
73180f85 | 1810 | * Saves the reset reason code and then sets the APE_SOFTRST register which |
3df57bcf | 1811 | * fires interrupt to fw |
e0befb23 | 1812 | */ |
73180f85 | 1813 | void db8500_prcmu_system_reset(u16 reset_code) |
e0befb23 | 1814 | { |
3df57bcf | 1815 | writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); |
c553b3ca | 1816 | writel(1, PRCM_APE_SOFTRST); |
e0befb23 | 1817 | } |
e0befb23 | 1818 | |
597045de SR |
1819 | /** |
1820 | * db8500_prcmu_get_reset_code - Retrieve SW reset reason code | |
1821 | * | |
1822 | * Retrieves the reset reason code stored by prcmu_system_reset() before | |
1823 | * last restart. | |
1824 | */ | |
1825 | u16 db8500_prcmu_get_reset_code(void) | |
1826 | { | |
1827 | return readw(tcdm_base + PRCM_SW_RST_REASON); | |
1828 | } | |
1829 | ||
e0befb23 | 1830 | /** |
3df57bcf | 1831 | * prcmu_reset_modem - ask the PRCMU to reset modem |
e0befb23 | 1832 | */ |
3df57bcf | 1833 | void prcmu_modem_reset(void) |
e0befb23 | 1834 | { |
3df57bcf MN |
1835 | mutex_lock(&mb1_transfer.lock); |
1836 | ||
c553b3ca | 1837 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1838 | cpu_relax(); |
1839 | ||
1840 | writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
c553b3ca | 1841 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1842 | wait_for_completion(&mb1_transfer.work); |
1843 | ||
1844 | /* | |
1845 | * No need to check return from PRCMU as modem should go in reset state | |
1846 | * This state is already managed by upper layer | |
1847 | */ | |
1848 | ||
1849 | mutex_unlock(&mb1_transfer.lock); | |
e0befb23 | 1850 | } |
e0befb23 | 1851 | |
3df57bcf | 1852 | static void ack_dbb_wakeup(void) |
e0befb23 | 1853 | { |
3df57bcf MN |
1854 | unsigned long flags; |
1855 | ||
1856 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
1857 | ||
c553b3ca | 1858 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
1859 | cpu_relax(); |
1860 | ||
1861 | writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 1862 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1863 | |
1864 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
e0befb23 | 1865 | } |
e0befb23 | 1866 | |
3df57bcf | 1867 | static inline void print_unknown_header_warning(u8 n, u8 header) |
e0befb23 | 1868 | { |
3df57bcf MN |
1869 | pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", |
1870 | header, n); | |
e0befb23 MP |
1871 | } |
1872 | ||
3df57bcf | 1873 | static bool read_mailbox_0(void) |
e3726fcf | 1874 | { |
3df57bcf MN |
1875 | bool r; |
1876 | u32 ev; | |
1877 | unsigned int n; | |
1878 | u8 header; | |
1879 | ||
1880 | header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); | |
1881 | switch (header) { | |
1882 | case MB0H_WAKEUP_EXE: | |
1883 | case MB0H_WAKEUP_SLEEP: | |
1884 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
1885 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); | |
1886 | else | |
1887 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); | |
1888 | ||
1889 | if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) | |
1890 | complete(&mb0_transfer.ac_wake_work); | |
1891 | if (ev & WAKEUP_BIT_SYSCLK_OK) | |
1892 | complete(&mb3_transfer.sysclk_work); | |
1893 | ||
1894 | ev &= mb0_transfer.req.dbb_irqs; | |
1895 | ||
1896 | for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { | |
1897 | if (ev & prcmu_irq_bit[n]) | |
1898 | generic_handle_irq(IRQ_PRCMU_BASE + n); | |
1899 | } | |
1900 | r = true; | |
1901 | break; | |
1902 | default: | |
1903 | print_unknown_header_warning(0, header); | |
1904 | r = false; | |
1905 | break; | |
1906 | } | |
c553b3ca | 1907 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); |
3df57bcf | 1908 | return r; |
e3726fcf LW |
1909 | } |
1910 | ||
3df57bcf | 1911 | static bool read_mailbox_1(void) |
e3726fcf | 1912 | { |
3df57bcf MN |
1913 | mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); |
1914 | mb1_transfer.ack.arm_opp = readb(tcdm_base + | |
1915 | PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
1916 | mb1_transfer.ack.ape_opp = readb(tcdm_base + | |
1917 | PRCM_ACK_MB1_CURRENT_APE_OPP); | |
1918 | mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + | |
1919 | PRCM_ACK_MB1_APE_VOLTAGE_STATUS); | |
c553b3ca | 1920 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); |
e0befb23 | 1921 | complete(&mb1_transfer.work); |
3df57bcf | 1922 | return false; |
e3726fcf LW |
1923 | } |
1924 | ||
3df57bcf | 1925 | static bool read_mailbox_2(void) |
e3726fcf | 1926 | { |
3df57bcf | 1927 | mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); |
c553b3ca | 1928 | writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
1929 | complete(&mb2_transfer.work); |
1930 | return false; | |
e3726fcf LW |
1931 | } |
1932 | ||
3df57bcf | 1933 | static bool read_mailbox_3(void) |
e3726fcf | 1934 | { |
c553b3ca | 1935 | writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); |
3df57bcf | 1936 | return false; |
e3726fcf LW |
1937 | } |
1938 | ||
3df57bcf | 1939 | static bool read_mailbox_4(void) |
e3726fcf | 1940 | { |
3df57bcf MN |
1941 | u8 header; |
1942 | bool do_complete = true; | |
1943 | ||
1944 | header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); | |
1945 | switch (header) { | |
1946 | case MB4H_MEM_ST: | |
1947 | case MB4H_HOTDOG: | |
1948 | case MB4H_HOTMON: | |
1949 | case MB4H_HOT_PERIOD: | |
a592c2e2 MN |
1950 | case MB4H_A9WDOG_CONF: |
1951 | case MB4H_A9WDOG_EN: | |
1952 | case MB4H_A9WDOG_DIS: | |
1953 | case MB4H_A9WDOG_LOAD: | |
1954 | case MB4H_A9WDOG_KICK: | |
3df57bcf MN |
1955 | break; |
1956 | default: | |
1957 | print_unknown_header_warning(4, header); | |
1958 | do_complete = false; | |
1959 | break; | |
1960 | } | |
1961 | ||
c553b3ca | 1962 | writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
1963 | |
1964 | if (do_complete) | |
1965 | complete(&mb4_transfer.work); | |
1966 | ||
1967 | return false; | |
e3726fcf LW |
1968 | } |
1969 | ||
3df57bcf | 1970 | static bool read_mailbox_5(void) |
e3726fcf | 1971 | { |
3df57bcf MN |
1972 | mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); |
1973 | mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); | |
c553b3ca | 1974 | writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); |
e3726fcf | 1975 | complete(&mb5_transfer.work); |
3df57bcf | 1976 | return false; |
e3726fcf LW |
1977 | } |
1978 | ||
3df57bcf | 1979 | static bool read_mailbox_6(void) |
e3726fcf | 1980 | { |
c553b3ca | 1981 | writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); |
3df57bcf | 1982 | return false; |
e3726fcf LW |
1983 | } |
1984 | ||
3df57bcf | 1985 | static bool read_mailbox_7(void) |
e3726fcf | 1986 | { |
c553b3ca | 1987 | writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); |
3df57bcf | 1988 | return false; |
e3726fcf LW |
1989 | } |
1990 | ||
3df57bcf | 1991 | static bool (* const read_mailbox[NUM_MB])(void) = { |
e3726fcf LW |
1992 | read_mailbox_0, |
1993 | read_mailbox_1, | |
1994 | read_mailbox_2, | |
1995 | read_mailbox_3, | |
1996 | read_mailbox_4, | |
1997 | read_mailbox_5, | |
1998 | read_mailbox_6, | |
1999 | read_mailbox_7 | |
2000 | }; | |
2001 | ||
2002 | static irqreturn_t prcmu_irq_handler(int irq, void *data) | |
2003 | { | |
2004 | u32 bits; | |
2005 | u8 n; | |
3df57bcf | 2006 | irqreturn_t r; |
e3726fcf | 2007 | |
c553b3ca | 2008 | bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); |
e3726fcf LW |
2009 | if (unlikely(!bits)) |
2010 | return IRQ_NONE; | |
2011 | ||
3df57bcf | 2012 | r = IRQ_HANDLED; |
e3726fcf LW |
2013 | for (n = 0; bits; n++) { |
2014 | if (bits & MBOX_BIT(n)) { | |
2015 | bits -= MBOX_BIT(n); | |
3df57bcf MN |
2016 | if (read_mailbox[n]()) |
2017 | r = IRQ_WAKE_THREAD; | |
e3726fcf LW |
2018 | } |
2019 | } | |
3df57bcf MN |
2020 | return r; |
2021 | } | |
2022 | ||
2023 | static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) | |
2024 | { | |
2025 | ack_dbb_wakeup(); | |
e3726fcf LW |
2026 | return IRQ_HANDLED; |
2027 | } | |
2028 | ||
3df57bcf MN |
2029 | static void prcmu_mask_work(struct work_struct *work) |
2030 | { | |
2031 | unsigned long flags; | |
2032 | ||
2033 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2034 | ||
2035 | config_wakeups(); | |
2036 | ||
2037 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
2038 | } | |
2039 | ||
2040 | static void prcmu_irq_mask(struct irq_data *d) | |
2041 | { | |
2042 | unsigned long flags; | |
2043 | ||
2044 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2045 | ||
2046 | mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; | |
2047 | ||
2048 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2049 | ||
2050 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2051 | schedule_work(&mb0_transfer.mask_work); | |
2052 | } | |
2053 | ||
2054 | static void prcmu_irq_unmask(struct irq_data *d) | |
2055 | { | |
2056 | unsigned long flags; | |
2057 | ||
2058 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2059 | ||
2060 | mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; | |
2061 | ||
2062 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2063 | ||
2064 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2065 | schedule_work(&mb0_transfer.mask_work); | |
2066 | } | |
2067 | ||
2068 | static void noop(struct irq_data *d) | |
2069 | { | |
2070 | } | |
2071 | ||
2072 | static struct irq_chip prcmu_irq_chip = { | |
2073 | .name = "prcmu", | |
2074 | .irq_disable = prcmu_irq_mask, | |
2075 | .irq_ack = noop, | |
2076 | .irq_mask = prcmu_irq_mask, | |
2077 | .irq_unmask = prcmu_irq_unmask, | |
2078 | }; | |
2079 | ||
73180f85 | 2080 | void __init db8500_prcmu_early_init(void) |
fcbd458e | 2081 | { |
3df57bcf | 2082 | unsigned int i; |
3e2762c8 | 2083 | if (cpu_is_u8500v2()) { |
3df57bcf MN |
2084 | void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); |
2085 | ||
2086 | if (tcpm_base != NULL) { | |
3e2762c8 | 2087 | u32 version; |
3df57bcf MN |
2088 | version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); |
2089 | prcmu_version.project_number = version & 0xFF; | |
2090 | prcmu_version.api_version = (version >> 8) & 0xFF; | |
2091 | prcmu_version.func_version = (version >> 16) & 0xFF; | |
2092 | prcmu_version.errata = (version >> 24) & 0xFF; | |
2093 | pr_info("PRCMU firmware version %d.%d.%d\n", | |
2094 | (version >> 8) & 0xFF, (version >> 16) & 0xFF, | |
2095 | (version >> 24) & 0xFF); | |
2096 | iounmap(tcpm_base); | |
2097 | } | |
2098 | ||
fcbd458e MW |
2099 | tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); |
2100 | } else { | |
2101 | pr_err("prcmu: Unsupported chip version\n"); | |
2102 | BUG(); | |
2103 | } | |
e0befb23 | 2104 | |
3df57bcf MN |
2105 | spin_lock_init(&mb0_transfer.lock); |
2106 | spin_lock_init(&mb0_transfer.dbb_irqs_lock); | |
2107 | mutex_init(&mb0_transfer.ac_wake_lock); | |
2108 | init_completion(&mb0_transfer.ac_wake_work); | |
e0befb23 MP |
2109 | mutex_init(&mb1_transfer.lock); |
2110 | init_completion(&mb1_transfer.work); | |
3df57bcf MN |
2111 | mutex_init(&mb2_transfer.lock); |
2112 | init_completion(&mb2_transfer.work); | |
2113 | spin_lock_init(&mb2_transfer.auto_pm_lock); | |
2114 | spin_lock_init(&mb3_transfer.lock); | |
2115 | mutex_init(&mb3_transfer.sysclk_lock); | |
2116 | init_completion(&mb3_transfer.sysclk_work); | |
2117 | mutex_init(&mb4_transfer.lock); | |
2118 | init_completion(&mb4_transfer.work); | |
e3726fcf LW |
2119 | mutex_init(&mb5_transfer.lock); |
2120 | init_completion(&mb5_transfer.work); | |
2121 | ||
3df57bcf MN |
2122 | INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); |
2123 | ||
2124 | /* Initalize irqs. */ | |
2125 | for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) { | |
2126 | unsigned int irq; | |
2127 | ||
2128 | irq = IRQ_PRCMU_BASE + i; | |
2129 | irq_set_chip_and_handler(irq, &prcmu_irq_chip, | |
2130 | handle_simple_irq); | |
2131 | set_irq_flags(irq, IRQF_VALID); | |
2132 | } | |
2133 | } | |
2134 | ||
1934dae2 | 2135 | static void __init db8500_prcmu_init_clkforce(void) |
d65e12d7 MN |
2136 | { |
2137 | u32 val; | |
2138 | ||
2139 | val = readl(PRCM_A9PL_FORCE_CLKEN); | |
2140 | val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | | |
2141 | PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); | |
2142 | writel(val, (PRCM_A9PL_FORCE_CLKEN)); | |
2143 | } | |
2144 | ||
1032fbfd BJ |
2145 | /* |
2146 | * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC | |
2147 | */ | |
2148 | static struct regulator_consumer_supply db8500_vape_consumers[] = { | |
2149 | REGULATOR_SUPPLY("v-ape", NULL), | |
2150 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), | |
2151 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), | |
2152 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), | |
2153 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), | |
2154 | /* "v-mmc" changed to "vcore" in the mainline kernel */ | |
2155 | REGULATOR_SUPPLY("vcore", "sdi0"), | |
2156 | REGULATOR_SUPPLY("vcore", "sdi1"), | |
2157 | REGULATOR_SUPPLY("vcore", "sdi2"), | |
2158 | REGULATOR_SUPPLY("vcore", "sdi3"), | |
2159 | REGULATOR_SUPPLY("vcore", "sdi4"), | |
2160 | REGULATOR_SUPPLY("v-dma", "dma40.0"), | |
2161 | REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), | |
2162 | /* "v-uart" changed to "vcore" in the mainline kernel */ | |
2163 | REGULATOR_SUPPLY("vcore", "uart0"), | |
2164 | REGULATOR_SUPPLY("vcore", "uart1"), | |
2165 | REGULATOR_SUPPLY("vcore", "uart2"), | |
2166 | REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), | |
2167 | }; | |
2168 | ||
2169 | static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { | |
2170 | /* CG2900 and CW1200 power to off-chip peripherals */ | |
2171 | REGULATOR_SUPPLY("gbf_1v8", "cg2900-uart.0"), | |
2172 | REGULATOR_SUPPLY("wlan_1v8", "cw1200.0"), | |
2173 | REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), | |
2174 | /* AV8100 regulator */ | |
2175 | REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), | |
2176 | }; | |
2177 | ||
2178 | static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { | |
2179 | REGULATOR_SUPPLY("vsupply", "b2r2.0"), | |
624e87c2 BJ |
2180 | REGULATOR_SUPPLY("vsupply", "mcde"), |
2181 | }; | |
2182 | ||
2183 | /* SVA MMDSP regulator switch */ | |
2184 | static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { | |
2185 | REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), | |
2186 | }; | |
2187 | ||
2188 | /* SVA pipe regulator switch */ | |
2189 | static struct regulator_consumer_supply db8500_svapipe_consumers[] = { | |
2190 | REGULATOR_SUPPLY("sva-pipe", "cm_control"), | |
2191 | }; | |
2192 | ||
2193 | /* SIA MMDSP regulator switch */ | |
2194 | static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { | |
2195 | REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), | |
2196 | }; | |
2197 | ||
2198 | /* SIA pipe regulator switch */ | |
2199 | static struct regulator_consumer_supply db8500_siapipe_consumers[] = { | |
2200 | REGULATOR_SUPPLY("sia-pipe", "cm_control"), | |
2201 | }; | |
2202 | ||
2203 | static struct regulator_consumer_supply db8500_sga_consumers[] = { | |
2204 | REGULATOR_SUPPLY("v-mali", NULL), | |
2205 | }; | |
2206 | ||
2207 | /* ESRAM1 and 2 regulator switch */ | |
2208 | static struct regulator_consumer_supply db8500_esram12_consumers[] = { | |
2209 | REGULATOR_SUPPLY("esram12", "cm_control"), | |
2210 | }; | |
2211 | ||
2212 | /* ESRAM3 and 4 regulator switch */ | |
2213 | static struct regulator_consumer_supply db8500_esram34_consumers[] = { | |
2214 | REGULATOR_SUPPLY("v-esram34", "mcde"), | |
2215 | REGULATOR_SUPPLY("esram34", "cm_control"), | |
1032fbfd BJ |
2216 | }; |
2217 | ||
2218 | static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { | |
2219 | [DB8500_REGULATOR_VAPE] = { | |
2220 | .constraints = { | |
2221 | .name = "db8500-vape", | |
2222 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2223 | }, | |
2224 | .consumer_supplies = db8500_vape_consumers, | |
2225 | .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), | |
2226 | }, | |
2227 | [DB8500_REGULATOR_VARM] = { | |
2228 | .constraints = { | |
2229 | .name = "db8500-varm", | |
2230 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2231 | }, | |
2232 | }, | |
2233 | [DB8500_REGULATOR_VMODEM] = { | |
2234 | .constraints = { | |
2235 | .name = "db8500-vmodem", | |
2236 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2237 | }, | |
2238 | }, | |
2239 | [DB8500_REGULATOR_VPLL] = { | |
2240 | .constraints = { | |
2241 | .name = "db8500-vpll", | |
2242 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2243 | }, | |
2244 | }, | |
2245 | [DB8500_REGULATOR_VSMPS1] = { | |
2246 | .constraints = { | |
2247 | .name = "db8500-vsmps1", | |
2248 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2249 | }, | |
2250 | }, | |
2251 | [DB8500_REGULATOR_VSMPS2] = { | |
2252 | .constraints = { | |
2253 | .name = "db8500-vsmps2", | |
2254 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2255 | }, | |
2256 | .consumer_supplies = db8500_vsmps2_consumers, | |
2257 | .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), | |
2258 | }, | |
2259 | [DB8500_REGULATOR_VSMPS3] = { | |
2260 | .constraints = { | |
2261 | .name = "db8500-vsmps3", | |
2262 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2263 | }, | |
2264 | }, | |
2265 | [DB8500_REGULATOR_VRF1] = { | |
2266 | .constraints = { | |
2267 | .name = "db8500-vrf1", | |
2268 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2269 | }, | |
2270 | }, | |
2271 | [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { | |
2272 | .supply_regulator = "db8500-vape", | |
2273 | .constraints = { | |
2274 | .name = "db8500-sva-mmdsp", | |
2275 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2276 | }, | |
624e87c2 BJ |
2277 | .consumer_supplies = db8500_svammdsp_consumers, |
2278 | .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), | |
1032fbfd BJ |
2279 | }, |
2280 | [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { | |
2281 | .constraints = { | |
2282 | /* "ret" means "retention" */ | |
2283 | .name = "db8500-sva-mmdsp-ret", | |
2284 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2285 | }, | |
2286 | }, | |
2287 | [DB8500_REGULATOR_SWITCH_SVAPIPE] = { | |
2288 | .supply_regulator = "db8500-vape", | |
2289 | .constraints = { | |
2290 | .name = "db8500-sva-pipe", | |
2291 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2292 | }, | |
624e87c2 BJ |
2293 | .consumer_supplies = db8500_svapipe_consumers, |
2294 | .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), | |
1032fbfd BJ |
2295 | }, |
2296 | [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { | |
2297 | .supply_regulator = "db8500-vape", | |
2298 | .constraints = { | |
2299 | .name = "db8500-sia-mmdsp", | |
2300 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2301 | }, | |
624e87c2 BJ |
2302 | .consumer_supplies = db8500_siammdsp_consumers, |
2303 | .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), | |
1032fbfd BJ |
2304 | }, |
2305 | [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { | |
2306 | .constraints = { | |
2307 | .name = "db8500-sia-mmdsp-ret", | |
2308 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2309 | }, | |
2310 | }, | |
2311 | [DB8500_REGULATOR_SWITCH_SIAPIPE] = { | |
2312 | .supply_regulator = "db8500-vape", | |
2313 | .constraints = { | |
2314 | .name = "db8500-sia-pipe", | |
2315 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2316 | }, | |
624e87c2 BJ |
2317 | .consumer_supplies = db8500_siapipe_consumers, |
2318 | .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), | |
1032fbfd BJ |
2319 | }, |
2320 | [DB8500_REGULATOR_SWITCH_SGA] = { | |
2321 | .supply_regulator = "db8500-vape", | |
2322 | .constraints = { | |
2323 | .name = "db8500-sga", | |
2324 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2325 | }, | |
624e87c2 BJ |
2326 | .consumer_supplies = db8500_sga_consumers, |
2327 | .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), | |
2328 | ||
1032fbfd BJ |
2329 | }, |
2330 | [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { | |
2331 | .supply_regulator = "db8500-vape", | |
2332 | .constraints = { | |
2333 | .name = "db8500-b2r2-mcde", | |
2334 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2335 | }, | |
2336 | .consumer_supplies = db8500_b2r2_mcde_consumers, | |
2337 | .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), | |
2338 | }, | |
2339 | [DB8500_REGULATOR_SWITCH_ESRAM12] = { | |
2340 | .supply_regulator = "db8500-vape", | |
2341 | .constraints = { | |
2342 | .name = "db8500-esram12", | |
2343 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2344 | }, | |
624e87c2 BJ |
2345 | .consumer_supplies = db8500_esram12_consumers, |
2346 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), | |
1032fbfd BJ |
2347 | }, |
2348 | [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { | |
2349 | .constraints = { | |
2350 | .name = "db8500-esram12-ret", | |
2351 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2352 | }, | |
2353 | }, | |
2354 | [DB8500_REGULATOR_SWITCH_ESRAM34] = { | |
2355 | .supply_regulator = "db8500-vape", | |
2356 | .constraints = { | |
2357 | .name = "db8500-esram34", | |
2358 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2359 | }, | |
624e87c2 BJ |
2360 | .consumer_supplies = db8500_esram34_consumers, |
2361 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), | |
1032fbfd BJ |
2362 | }, |
2363 | [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { | |
2364 | .constraints = { | |
2365 | .name = "db8500-esram34-ret", | |
2366 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2367 | }, | |
2368 | }, | |
2369 | }; | |
2370 | ||
3df57bcf MN |
2371 | static struct mfd_cell db8500_prcmu_devs[] = { |
2372 | { | |
2373 | .name = "db8500-prcmu-regulators", | |
1ed7891f MW |
2374 | .platform_data = &db8500_regulators, |
2375 | .pdata_size = sizeof(db8500_regulators), | |
3df57bcf MN |
2376 | }, |
2377 | { | |
2378 | .name = "cpufreq-u8500", | |
2379 | }, | |
2380 | }; | |
2381 | ||
2382 | /** | |
2383 | * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic | |
2384 | * | |
2385 | */ | |
2386 | static int __init db8500_prcmu_probe(struct platform_device *pdev) | |
2387 | { | |
2388 | int err = 0; | |
2389 | ||
2390 | if (ux500_is_svp()) | |
2391 | return -ENODEV; | |
2392 | ||
1934dae2 | 2393 | db8500_prcmu_init_clkforce(); |
d65e12d7 | 2394 | |
e3726fcf | 2395 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
c553b3ca | 2396 | writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2397 | |
2398 | err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, | |
2399 | prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); | |
2400 | if (err < 0) { | |
2401 | pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); | |
2402 | err = -EBUSY; | |
2403 | goto no_irq_return; | |
2404 | } | |
2405 | ||
2406 | if (cpu_is_u8500v20_or_later()) | |
2407 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); | |
2408 | ||
2409 | err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, | |
2410 | ARRAY_SIZE(db8500_prcmu_devs), NULL, | |
2411 | 0); | |
e3726fcf | 2412 | |
3df57bcf MN |
2413 | if (err) |
2414 | pr_err("prcmu: Failed to add subdevices\n"); | |
2415 | else | |
2416 | pr_info("DB8500 PRCMU initialized\n"); | |
2417 | ||
2418 | no_irq_return: | |
2419 | return err; | |
2420 | } | |
2421 | ||
2422 | static struct platform_driver db8500_prcmu_driver = { | |
2423 | .driver = { | |
2424 | .name = "db8500-prcmu", | |
2425 | .owner = THIS_MODULE, | |
2426 | }, | |
2427 | }; | |
2428 | ||
2429 | static int __init db8500_prcmu_init(void) | |
2430 | { | |
2431 | return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe); | |
e3726fcf LW |
2432 | } |
2433 | ||
3df57bcf MN |
2434 | arch_initcall(db8500_prcmu_init); |
2435 | ||
2436 | MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); | |
2437 | MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); | |
2438 | MODULE_LICENSE("GPL v2"); |