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e3726fcf | 1 | /* |
e0befb23 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
e3726fcf LW |
4 | * |
5 | * License Terms: GNU General Public License v2 | |
e0befb23 MP |
6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | |
e3726fcf LW |
8 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
9 | * | |
e0befb23 MP |
10 | * U8500 PRCM Unit interface driver |
11 | * | |
e3726fcf | 12 | */ |
e3726fcf | 13 | #include <linux/module.h> |
3df57bcf MN |
14 | #include <linux/kernel.h> |
15 | #include <linux/delay.h> | |
e3726fcf LW |
16 | #include <linux/errno.h> |
17 | #include <linux/err.h> | |
3df57bcf | 18 | #include <linux/spinlock.h> |
e3726fcf | 19 | #include <linux/io.h> |
3df57bcf | 20 | #include <linux/slab.h> |
e3726fcf LW |
21 | #include <linux/mutex.h> |
22 | #include <linux/completion.h> | |
3df57bcf | 23 | #include <linux/irq.h> |
e3726fcf LW |
24 | #include <linux/jiffies.h> |
25 | #include <linux/bitops.h> | |
3df57bcf MN |
26 | #include <linux/fs.h> |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
29 | #include <linux/mfd/core.h> | |
650c2a21 | 30 | #include <linux/mfd/db8500-prcmu.h> |
1032fbfd BJ |
31 | #include <linux/regulator/db8500-prcmu.h> |
32 | #include <linux/regulator/machine.h> | |
3df57bcf MN |
33 | #include <mach/hardware.h> |
34 | #include <mach/irqs.h> | |
35 | #include <mach/db8500-regs.h> | |
36 | #include <mach/id.h> | |
37 | #include "db8500-prcmu-regs.h" | |
38 | ||
39 | /* Offset for the firmware version within the TCPM */ | |
40 | #define PRCMU_FW_VERSION_OFFSET 0xA4 | |
41 | ||
42 | /* PRCMU project numbers, defined by PRCMU FW */ | |
43 | #define PRCMU_PROJECT_ID_8500V1_0 1 | |
44 | #define PRCMU_PROJECT_ID_8500V2_0 2 | |
45 | #define PRCMU_PROJECT_ID_8400V2_0 3 | |
46 | ||
47 | /* Index of different voltages to be used when accessing AVSData */ | |
48 | #define PRCM_AVS_BASE 0x2FC | |
49 | #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) | |
50 | #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) | |
51 | #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) | |
52 | #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) | |
53 | #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) | |
54 | #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) | |
55 | #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) | |
56 | #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) | |
57 | #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) | |
58 | #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) | |
59 | #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) | |
60 | #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) | |
61 | #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) | |
62 | ||
63 | #define PRCM_AVS_VOLTAGE 0 | |
64 | #define PRCM_AVS_VOLTAGE_MASK 0x3f | |
65 | #define PRCM_AVS_ISSLOWSTARTUP 6 | |
66 | #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) | |
67 | #define PRCM_AVS_ISMODEENABLE 7 | |
68 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) | |
69 | ||
70 | #define PRCM_BOOT_STATUS 0xFFF | |
71 | #define PRCM_ROMCODE_A2P 0xFFE | |
72 | #define PRCM_ROMCODE_P2A 0xFFD | |
73 | #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ | |
74 | ||
75 | #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ | |
76 | ||
77 | #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ | |
78 | #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) | |
79 | #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) | |
80 | #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) | |
81 | #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) | |
82 | #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) | |
83 | #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) | |
84 | #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) | |
85 | ||
86 | /* Req Mailboxes */ | |
87 | #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ | |
88 | #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ | |
89 | #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ | |
90 | #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ | |
91 | #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ | |
92 | #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ | |
93 | ||
94 | /* Ack Mailboxes */ | |
95 | #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ | |
96 | #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ | |
97 | #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ | |
98 | #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ | |
99 | #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ | |
100 | #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ | |
101 | ||
102 | /* Mailbox 0 headers */ | |
103 | #define MB0H_POWER_STATE_TRANS 0 | |
104 | #define MB0H_CONFIG_WAKEUPS_EXE 1 | |
105 | #define MB0H_READ_WAKEUP_ACK 3 | |
106 | #define MB0H_CONFIG_WAKEUPS_SLEEP 4 | |
107 | ||
108 | #define MB0H_WAKEUP_EXE 2 | |
109 | #define MB0H_WAKEUP_SLEEP 5 | |
110 | ||
111 | /* Mailbox 0 REQs */ | |
112 | #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) | |
113 | #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) | |
114 | #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) | |
115 | #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) | |
116 | #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) | |
117 | #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) | |
118 | ||
119 | /* Mailbox 0 ACKs */ | |
120 | #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) | |
121 | #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) | |
122 | #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) | |
123 | #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) | |
124 | #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) | |
125 | #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) | |
126 | #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 | |
127 | ||
128 | /* Mailbox 1 headers */ | |
129 | #define MB1H_ARM_APE_OPP 0x0 | |
130 | #define MB1H_RESET_MODEM 0x2 | |
131 | #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 | |
132 | #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 | |
133 | #define MB1H_RELEASE_USB_WAKEUP 0x5 | |
a592c2e2 | 134 | #define MB1H_PLL_ON_OFF 0x6 |
3df57bcf MN |
135 | |
136 | /* Mailbox 1 Requests */ | |
137 | #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) | |
138 | #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) | |
a592c2e2 MN |
139 | #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) |
140 | #define PLL_SOC1_OFF 0x4 | |
141 | #define PLL_SOC1_ON 0x8 | |
3df57bcf MN |
142 | |
143 | /* Mailbox 1 ACKs */ | |
144 | #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) | |
145 | #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) | |
146 | #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) | |
147 | #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) | |
148 | ||
149 | /* Mailbox 2 headers */ | |
150 | #define MB2H_DPS 0x0 | |
151 | #define MB2H_AUTO_PWR 0x1 | |
152 | ||
153 | /* Mailbox 2 REQs */ | |
154 | #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) | |
155 | #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) | |
156 | #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) | |
157 | #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) | |
158 | #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) | |
159 | #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) | |
160 | #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) | |
161 | #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) | |
162 | #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) | |
163 | #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) | |
164 | ||
165 | /* Mailbox 2 ACKs */ | |
166 | #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) | |
167 | #define HWACC_PWR_ST_OK 0xFE | |
168 | ||
169 | /* Mailbox 3 headers */ | |
170 | #define MB3H_ANC 0x0 | |
171 | #define MB3H_SIDETONE 0x1 | |
172 | #define MB3H_SYSCLK 0xE | |
173 | ||
174 | /* Mailbox 3 Requests */ | |
175 | #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) | |
176 | #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) | |
177 | #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) | |
178 | #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) | |
179 | #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) | |
180 | #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) | |
181 | #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) | |
182 | ||
183 | /* Mailbox 4 headers */ | |
184 | #define MB4H_DDR_INIT 0x0 | |
185 | #define MB4H_MEM_ST 0x1 | |
186 | #define MB4H_HOTDOG 0x12 | |
187 | #define MB4H_HOTMON 0x13 | |
188 | #define MB4H_HOT_PERIOD 0x14 | |
a592c2e2 MN |
189 | #define MB4H_A9WDOG_CONF 0x16 |
190 | #define MB4H_A9WDOG_EN 0x17 | |
191 | #define MB4H_A9WDOG_DIS 0x18 | |
192 | #define MB4H_A9WDOG_LOAD 0x19 | |
193 | #define MB4H_A9WDOG_KICK 0x20 | |
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194 | |
195 | /* Mailbox 4 Requests */ | |
196 | #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) | |
197 | #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) | |
198 | #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) | |
199 | #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) | |
200 | #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) | |
201 | #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) | |
202 | #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) | |
203 | #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) | |
204 | #define HOTMON_CONFIG_LOW BIT(0) | |
205 | #define HOTMON_CONFIG_HIGH BIT(1) | |
a592c2e2 MN |
206 | #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) |
207 | #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) | |
208 | #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) | |
209 | #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) | |
210 | #define A9WDOG_AUTO_OFF_EN BIT(7) | |
211 | #define A9WDOG_AUTO_OFF_DIS 0 | |
212 | #define A9WDOG_ID_MASK 0xf | |
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213 | |
214 | /* Mailbox 5 Requests */ | |
215 | #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) | |
216 | #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) | |
217 | #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) | |
218 | #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) | |
219 | #define PRCMU_I2C_WRITE(slave) \ | |
220 | (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) | |
221 | #define PRCMU_I2C_READ(slave) \ | |
222 | (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) | |
223 | #define PRCMU_I2C_STOP_EN BIT(3) | |
224 | ||
225 | /* Mailbox 5 ACKs */ | |
226 | #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) | |
227 | #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) | |
228 | #define I2C_WR_OK 0x1 | |
229 | #define I2C_RD_OK 0x2 | |
230 | ||
231 | #define NUM_MB 8 | |
232 | #define MBOX_BIT BIT | |
233 | #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) | |
234 | ||
235 | /* | |
236 | * Wakeups/IRQs | |
237 | */ | |
238 | ||
239 | #define WAKEUP_BIT_RTC BIT(0) | |
240 | #define WAKEUP_BIT_RTT0 BIT(1) | |
241 | #define WAKEUP_BIT_RTT1 BIT(2) | |
242 | #define WAKEUP_BIT_HSI0 BIT(3) | |
243 | #define WAKEUP_BIT_HSI1 BIT(4) | |
244 | #define WAKEUP_BIT_CA_WAKE BIT(5) | |
245 | #define WAKEUP_BIT_USB BIT(6) | |
246 | #define WAKEUP_BIT_ABB BIT(7) | |
247 | #define WAKEUP_BIT_ABB_FIFO BIT(8) | |
248 | #define WAKEUP_BIT_SYSCLK_OK BIT(9) | |
249 | #define WAKEUP_BIT_CA_SLEEP BIT(10) | |
250 | #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) | |
251 | #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) | |
252 | #define WAKEUP_BIT_ANC_OK BIT(13) | |
253 | #define WAKEUP_BIT_SW_ERROR BIT(14) | |
254 | #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) | |
255 | #define WAKEUP_BIT_ARM BIT(17) | |
256 | #define WAKEUP_BIT_HOTMON_LOW BIT(18) | |
257 | #define WAKEUP_BIT_HOTMON_HIGH BIT(19) | |
258 | #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) | |
259 | #define WAKEUP_BIT_GPIO0 BIT(23) | |
260 | #define WAKEUP_BIT_GPIO1 BIT(24) | |
261 | #define WAKEUP_BIT_GPIO2 BIT(25) | |
262 | #define WAKEUP_BIT_GPIO3 BIT(26) | |
263 | #define WAKEUP_BIT_GPIO4 BIT(27) | |
264 | #define WAKEUP_BIT_GPIO5 BIT(28) | |
265 | #define WAKEUP_BIT_GPIO6 BIT(29) | |
266 | #define WAKEUP_BIT_GPIO7 BIT(30) | |
267 | #define WAKEUP_BIT_GPIO8 BIT(31) | |
268 | ||
269 | /* | |
270 | * This vector maps irq numbers to the bits in the bit field used in | |
271 | * communication with the PRCMU firmware. | |
272 | * | |
273 | * The reason for having this is to keep the irq numbers contiguous even though | |
274 | * the bits in the bit field are not. (The bits also have a tendency to move | |
275 | * around, to further complicate matters.) | |
276 | */ | |
277 | #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) | |
278 | #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) | |
279 | static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { | |
280 | IRQ_ENTRY(RTC), | |
281 | IRQ_ENTRY(RTT0), | |
282 | IRQ_ENTRY(RTT1), | |
283 | IRQ_ENTRY(HSI0), | |
284 | IRQ_ENTRY(HSI1), | |
285 | IRQ_ENTRY(CA_WAKE), | |
286 | IRQ_ENTRY(USB), | |
287 | IRQ_ENTRY(ABB), | |
288 | IRQ_ENTRY(ABB_FIFO), | |
289 | IRQ_ENTRY(CA_SLEEP), | |
290 | IRQ_ENTRY(ARM), | |
291 | IRQ_ENTRY(HOTMON_LOW), | |
292 | IRQ_ENTRY(HOTMON_HIGH), | |
293 | IRQ_ENTRY(MODEM_SW_RESET_REQ), | |
294 | IRQ_ENTRY(GPIO0), | |
295 | IRQ_ENTRY(GPIO1), | |
296 | IRQ_ENTRY(GPIO2), | |
297 | IRQ_ENTRY(GPIO3), | |
298 | IRQ_ENTRY(GPIO4), | |
299 | IRQ_ENTRY(GPIO5), | |
300 | IRQ_ENTRY(GPIO6), | |
301 | IRQ_ENTRY(GPIO7), | |
302 | IRQ_ENTRY(GPIO8) | |
303 | }; | |
304 | ||
305 | #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) | |
306 | #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) | |
307 | static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { | |
308 | WAKEUP_ENTRY(RTC), | |
309 | WAKEUP_ENTRY(RTT0), | |
310 | WAKEUP_ENTRY(RTT1), | |
311 | WAKEUP_ENTRY(HSI0), | |
312 | WAKEUP_ENTRY(HSI1), | |
313 | WAKEUP_ENTRY(USB), | |
314 | WAKEUP_ENTRY(ABB), | |
315 | WAKEUP_ENTRY(ABB_FIFO), | |
316 | WAKEUP_ENTRY(ARM) | |
317 | }; | |
318 | ||
319 | /* | |
320 | * mb0_transfer - state needed for mailbox 0 communication. | |
321 | * @lock: The transaction lock. | |
322 | * @dbb_events_lock: A lock used to handle concurrent access to (parts of) | |
323 | * the request data. | |
324 | * @mask_work: Work structure used for (un)masking wakeup interrupts. | |
325 | * @req: Request data that need to persist between requests. | |
326 | */ | |
327 | static struct { | |
328 | spinlock_t lock; | |
329 | spinlock_t dbb_irqs_lock; | |
330 | struct work_struct mask_work; | |
331 | struct mutex ac_wake_lock; | |
332 | struct completion ac_wake_work; | |
333 | struct { | |
334 | u32 dbb_irqs; | |
335 | u32 dbb_wakeups; | |
336 | u32 abb_events; | |
337 | } req; | |
338 | } mb0_transfer; | |
339 | ||
340 | /* | |
341 | * mb1_transfer - state needed for mailbox 1 communication. | |
342 | * @lock: The transaction lock. | |
343 | * @work: The transaction completion structure. | |
344 | * @ack: Reply ("acknowledge") data. | |
345 | */ | |
346 | static struct { | |
347 | struct mutex lock; | |
348 | struct completion work; | |
349 | struct { | |
350 | u8 header; | |
351 | u8 arm_opp; | |
352 | u8 ape_opp; | |
353 | u8 ape_voltage_status; | |
354 | } ack; | |
355 | } mb1_transfer; | |
356 | ||
357 | /* | |
358 | * mb2_transfer - state needed for mailbox 2 communication. | |
359 | * @lock: The transaction lock. | |
360 | * @work: The transaction completion structure. | |
361 | * @auto_pm_lock: The autonomous power management configuration lock. | |
362 | * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. | |
363 | * @req: Request data that need to persist between requests. | |
364 | * @ack: Reply ("acknowledge") data. | |
365 | */ | |
366 | static struct { | |
367 | struct mutex lock; | |
368 | struct completion work; | |
369 | spinlock_t auto_pm_lock; | |
370 | bool auto_pm_enabled; | |
371 | struct { | |
372 | u8 status; | |
373 | } ack; | |
374 | } mb2_transfer; | |
375 | ||
376 | /* | |
377 | * mb3_transfer - state needed for mailbox 3 communication. | |
378 | * @lock: The request lock. | |
379 | * @sysclk_lock: A lock used to handle concurrent sysclk requests. | |
380 | * @sysclk_work: Work structure used for sysclk requests. | |
381 | */ | |
382 | static struct { | |
383 | spinlock_t lock; | |
384 | struct mutex sysclk_lock; | |
385 | struct completion sysclk_work; | |
386 | } mb3_transfer; | |
387 | ||
388 | /* | |
389 | * mb4_transfer - state needed for mailbox 4 communication. | |
390 | * @lock: The transaction lock. | |
391 | * @work: The transaction completion structure. | |
392 | */ | |
393 | static struct { | |
394 | struct mutex lock; | |
395 | struct completion work; | |
396 | } mb4_transfer; | |
397 | ||
398 | /* | |
399 | * mb5_transfer - state needed for mailbox 5 communication. | |
400 | * @lock: The transaction lock. | |
401 | * @work: The transaction completion structure. | |
402 | * @ack: Reply ("acknowledge") data. | |
403 | */ | |
404 | static struct { | |
405 | struct mutex lock; | |
406 | struct completion work; | |
407 | struct { | |
408 | u8 status; | |
409 | u8 value; | |
410 | } ack; | |
411 | } mb5_transfer; | |
412 | ||
413 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); | |
414 | ||
415 | /* Spinlocks */ | |
416 | static DEFINE_SPINLOCK(clkout_lock); | |
417 | static DEFINE_SPINLOCK(gpiocr_lock); | |
418 | ||
419 | /* Global var to runtime determine TCDM base for v2 or v1 */ | |
420 | static __iomem void *tcdm_base; | |
421 | ||
422 | struct clk_mgt { | |
423 | unsigned int offset; | |
424 | u32 pllsw; | |
425 | }; | |
426 | ||
427 | static DEFINE_SPINLOCK(clk_mgt_lock); | |
428 | ||
c553b3ca | 429 | #define CLK_MGT_ENTRY(_name)[PRCMU_##_name] = { (PRCM_##_name##_MGT_OFF), 0 } |
3df57bcf MN |
430 | struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { |
431 | CLK_MGT_ENTRY(SGACLK), | |
432 | CLK_MGT_ENTRY(UARTCLK), | |
433 | CLK_MGT_ENTRY(MSP02CLK), | |
434 | CLK_MGT_ENTRY(MSP1CLK), | |
435 | CLK_MGT_ENTRY(I2CCLK), | |
436 | CLK_MGT_ENTRY(SDMMCCLK), | |
437 | CLK_MGT_ENTRY(SLIMCLK), | |
438 | CLK_MGT_ENTRY(PER1CLK), | |
439 | CLK_MGT_ENTRY(PER2CLK), | |
440 | CLK_MGT_ENTRY(PER3CLK), | |
441 | CLK_MGT_ENTRY(PER5CLK), | |
442 | CLK_MGT_ENTRY(PER6CLK), | |
443 | CLK_MGT_ENTRY(PER7CLK), | |
444 | CLK_MGT_ENTRY(LCDCLK), | |
445 | CLK_MGT_ENTRY(BMLCLK), | |
446 | CLK_MGT_ENTRY(HSITXCLK), | |
447 | CLK_MGT_ENTRY(HSIRXCLK), | |
448 | CLK_MGT_ENTRY(HDMICLK), | |
449 | CLK_MGT_ENTRY(APEATCLK), | |
450 | CLK_MGT_ENTRY(APETRACECLK), | |
451 | CLK_MGT_ENTRY(MCDECLK), | |
452 | CLK_MGT_ENTRY(IPI2CCLK), | |
453 | CLK_MGT_ENTRY(DSIALTCLK), | |
454 | CLK_MGT_ENTRY(DMACLK), | |
455 | CLK_MGT_ENTRY(B2R2CLK), | |
456 | CLK_MGT_ENTRY(TVCLK), | |
457 | CLK_MGT_ENTRY(SSPCLK), | |
458 | CLK_MGT_ENTRY(RNGCLK), | |
459 | CLK_MGT_ENTRY(UICCCLK), | |
460 | }; | |
461 | ||
462 | /* | |
463 | * Used by MCDE to setup all necessary PRCMU registers | |
464 | */ | |
465 | #define PRCMU_RESET_DSIPLL 0x00004000 | |
466 | #define PRCMU_UNCLAMP_DSIPLL 0x00400800 | |
467 | ||
468 | #define PRCMU_CLK_PLL_DIV_SHIFT 0 | |
469 | #define PRCMU_CLK_PLL_SW_SHIFT 5 | |
470 | #define PRCMU_CLK_38 (1 << 9) | |
471 | #define PRCMU_CLK_38_SRC (1 << 10) | |
472 | #define PRCMU_CLK_38_DIV (1 << 11) | |
473 | ||
474 | /* PLLDIV=12, PLLSW=4 (PLLDDR) */ | |
475 | #define PRCMU_DSI_CLOCK_SETTING 0x0000008C | |
476 | ||
477 | /* PLLDIV=8, PLLSW=4 (PLLDDR) */ | |
478 | #define PRCMU_DSI_CLOCK_SETTING_U8400 0x00000088 | |
479 | ||
480 | /* DPI 50000000 Hz */ | |
481 | #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ | |
482 | (16 << PRCMU_CLK_PLL_DIV_SHIFT)) | |
483 | #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 | |
484 | ||
485 | /* D=101, N=1, R=4, SELDIV2=0 */ | |
486 | #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 | |
487 | ||
488 | /* D=70, N=1, R=3, SELDIV2=0 */ | |
489 | #define PRCMU_PLLDSI_FREQ_SETTING_U8400 0x00030146 | |
490 | ||
491 | #define PRCMU_ENABLE_PLLDSI 0x00000001 | |
492 | #define PRCMU_DISABLE_PLLDSI 0x00000000 | |
493 | #define PRCMU_RELEASE_RESET_DSS 0x0000400C | |
494 | #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 | |
495 | /* ESC clk, div0=1, div1=1, div2=3 */ | |
496 | #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 | |
497 | #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 | |
498 | #define PRCMU_DSI_RESET_SW 0x00000007 | |
499 | ||
500 | #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 | |
501 | ||
502 | static struct { | |
503 | u8 project_number; | |
504 | u8 api_version; | |
505 | u8 func_version; | |
506 | u8 errata; | |
507 | } prcmu_version; | |
508 | ||
509 | ||
510 | int prcmu_enable_dsipll(void) | |
511 | { | |
512 | int i; | |
513 | unsigned int plldsifreq; | |
514 | ||
515 | /* Clear DSIPLL_RESETN */ | |
c553b3ca | 516 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); |
3df57bcf | 517 | /* Unclamp DSIPLL in/out */ |
c553b3ca | 518 | writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); |
3df57bcf MN |
519 | |
520 | if (prcmu_is_u8400()) | |
521 | plldsifreq = PRCMU_PLLDSI_FREQ_SETTING_U8400; | |
522 | else | |
523 | plldsifreq = PRCMU_PLLDSI_FREQ_SETTING; | |
524 | /* Set DSI PLL FREQ */ | |
c553b3ca MN |
525 | writel(plldsifreq, PRCM_PLLDSI_FREQ); |
526 | writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); | |
3df57bcf | 527 | /* Enable Escape clocks */ |
c553b3ca | 528 | writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
529 | |
530 | /* Start DSI PLL */ | |
c553b3ca | 531 | writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 532 | /* Reset DSI PLL */ |
c553b3ca | 533 | writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); |
3df57bcf | 534 | for (i = 0; i < 10; i++) { |
c553b3ca | 535 | if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) |
3df57bcf MN |
536 | == PRCMU_PLLDSI_LOCKP_LOCKED) |
537 | break; | |
538 | udelay(100); | |
539 | } | |
540 | /* Set DSIPLL_RESETN */ | |
c553b3ca | 541 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); |
3df57bcf MN |
542 | return 0; |
543 | } | |
544 | ||
545 | int prcmu_disable_dsipll(void) | |
546 | { | |
547 | /* Disable dsi pll */ | |
c553b3ca | 548 | writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 549 | /* Disable escapeclock */ |
c553b3ca | 550 | writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
551 | return 0; |
552 | } | |
553 | ||
554 | int prcmu_set_display_clocks(void) | |
555 | { | |
556 | unsigned long flags; | |
557 | unsigned int dsiclk; | |
558 | ||
559 | if (prcmu_is_u8400()) | |
560 | dsiclk = PRCMU_DSI_CLOCK_SETTING_U8400; | |
561 | else | |
562 | dsiclk = PRCMU_DSI_CLOCK_SETTING; | |
563 | ||
564 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
565 | ||
566 | /* Grab the HW semaphore. */ | |
c553b3ca | 567 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
568 | cpu_relax(); |
569 | ||
c553b3ca MN |
570 | writel(dsiclk, PRCM_HDMICLK_MGT); |
571 | writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); | |
572 | writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); | |
3df57bcf MN |
573 | |
574 | /* Release the HW semaphore. */ | |
c553b3ca | 575 | writel(0, PRCM_SEM); |
3df57bcf MN |
576 | |
577 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
582 | /** | |
583 | * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. | |
584 | */ | |
585 | void prcmu_enable_spi2(void) | |
586 | { | |
587 | u32 reg; | |
588 | unsigned long flags; | |
589 | ||
590 | spin_lock_irqsave(&gpiocr_lock, flags); | |
c553b3ca MN |
591 | reg = readl(PRCM_GPIOCR); |
592 | writel(reg | PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); | |
3df57bcf MN |
593 | spin_unlock_irqrestore(&gpiocr_lock, flags); |
594 | } | |
595 | ||
596 | /** | |
597 | * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. | |
598 | */ | |
599 | void prcmu_disable_spi2(void) | |
600 | { | |
601 | u32 reg; | |
602 | unsigned long flags; | |
603 | ||
604 | spin_lock_irqsave(&gpiocr_lock, flags); | |
c553b3ca MN |
605 | reg = readl(PRCM_GPIOCR); |
606 | writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); | |
3df57bcf MN |
607 | spin_unlock_irqrestore(&gpiocr_lock, flags); |
608 | } | |
609 | ||
610 | bool prcmu_has_arm_maxopp(void) | |
611 | { | |
612 | return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & | |
613 | PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; | |
614 | } | |
615 | ||
616 | bool prcmu_is_u8400(void) | |
617 | { | |
618 | return prcmu_version.project_number == PRCMU_PROJECT_ID_8400V2_0; | |
619 | } | |
620 | ||
621 | /** | |
622 | * prcmu_get_boot_status - PRCMU boot status checking | |
623 | * Returns: the current PRCMU boot status | |
624 | */ | |
625 | int prcmu_get_boot_status(void) | |
626 | { | |
627 | return readb(tcdm_base + PRCM_BOOT_STATUS); | |
628 | } | |
629 | ||
630 | /** | |
631 | * prcmu_set_rc_a2p - This function is used to run few power state sequences | |
632 | * @val: Value to be set, i.e. transition requested | |
633 | * Returns: 0 on success, -EINVAL on invalid argument | |
634 | * | |
635 | * This function is used to run the following power state sequences - | |
636 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
637 | */ | |
638 | int prcmu_set_rc_a2p(enum romcode_write val) | |
639 | { | |
640 | if (val < RDY_2_DS || val > RDY_2_XP70_RST) | |
641 | return -EINVAL; | |
642 | writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); | |
643 | return 0; | |
644 | } | |
645 | ||
646 | /** | |
647 | * prcmu_get_rc_p2a - This function is used to get power state sequences | |
648 | * Returns: the power transition that has last happened | |
649 | * | |
650 | * This function can return the following transitions- | |
651 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
652 | */ | |
653 | enum romcode_read prcmu_get_rc_p2a(void) | |
654 | { | |
655 | return readb(tcdm_base + PRCM_ROMCODE_P2A); | |
656 | } | |
657 | ||
658 | /** | |
659 | * prcmu_get_current_mode - Return the current XP70 power mode | |
660 | * Returns: Returns the current AP(ARM) power mode: init, | |
661 | * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset | |
662 | */ | |
663 | enum ap_pwrst prcmu_get_xp70_current_state(void) | |
664 | { | |
665 | return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); | |
666 | } | |
667 | ||
668 | /** | |
669 | * prcmu_config_clkout - Configure one of the programmable clock outputs. | |
670 | * @clkout: The CLKOUT number (0 or 1). | |
671 | * @source: The clock to be used (one of the PRCMU_CLKSRC_*). | |
672 | * @div: The divider to be applied. | |
673 | * | |
674 | * Configures one of the programmable clock outputs (CLKOUTs). | |
675 | * @div should be in the range [1,63] to request a configuration, or 0 to | |
676 | * inform that the configuration is no longer requested. | |
677 | */ | |
678 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div) | |
679 | { | |
680 | static int requests[2]; | |
681 | int r = 0; | |
682 | unsigned long flags; | |
683 | u32 val; | |
684 | u32 bits; | |
685 | u32 mask; | |
686 | u32 div_mask; | |
687 | ||
688 | BUG_ON(clkout > 1); | |
689 | BUG_ON(div > 63); | |
690 | BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); | |
691 | ||
692 | if (!div && !requests[clkout]) | |
693 | return -EINVAL; | |
694 | ||
695 | switch (clkout) { | |
696 | case 0: | |
697 | div_mask = PRCM_CLKOCR_CLKODIV0_MASK; | |
698 | mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); | |
699 | bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | | |
700 | (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); | |
701 | break; | |
702 | case 1: | |
703 | div_mask = PRCM_CLKOCR_CLKODIV1_MASK; | |
704 | mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | | |
705 | PRCM_CLKOCR_CLK1TYPE); | |
706 | bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | | |
707 | (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); | |
708 | break; | |
709 | } | |
710 | bits &= mask; | |
711 | ||
712 | spin_lock_irqsave(&clkout_lock, flags); | |
713 | ||
c553b3ca | 714 | val = readl(PRCM_CLKOCR); |
3df57bcf MN |
715 | if (val & div_mask) { |
716 | if (div) { | |
717 | if ((val & mask) != bits) { | |
718 | r = -EBUSY; | |
719 | goto unlock_and_return; | |
720 | } | |
721 | } else { | |
722 | if ((val & mask & ~div_mask) != bits) { | |
723 | r = -EINVAL; | |
724 | goto unlock_and_return; | |
725 | } | |
726 | } | |
727 | } | |
c553b3ca | 728 | writel((bits | (val & ~mask)), PRCM_CLKOCR); |
3df57bcf MN |
729 | requests[clkout] += (div ? 1 : -1); |
730 | ||
731 | unlock_and_return: | |
732 | spin_unlock_irqrestore(&clkout_lock, flags); | |
733 | ||
734 | return r; | |
735 | } | |
736 | ||
737 | int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) | |
738 | { | |
739 | unsigned long flags; | |
740 | ||
741 | BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); | |
742 | ||
743 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
744 | ||
c553b3ca | 745 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
746 | cpu_relax(); |
747 | ||
748 | writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
749 | writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); | |
750 | writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); | |
751 | writeb((keep_ulp_clk ? 1 : 0), | |
752 | (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); | |
753 | writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); | |
c553b3ca | 754 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
755 | |
756 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | /* This function should only be called while mb0_transfer.lock is held. */ | |
762 | static void config_wakeups(void) | |
763 | { | |
764 | const u8 header[2] = { | |
765 | MB0H_CONFIG_WAKEUPS_EXE, | |
766 | MB0H_CONFIG_WAKEUPS_SLEEP | |
767 | }; | |
768 | static u32 last_dbb_events; | |
769 | static u32 last_abb_events; | |
770 | u32 dbb_events; | |
771 | u32 abb_events; | |
772 | unsigned int i; | |
773 | ||
774 | dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; | |
775 | dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); | |
776 | ||
777 | abb_events = mb0_transfer.req.abb_events; | |
778 | ||
779 | if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) | |
780 | return; | |
781 | ||
782 | for (i = 0; i < 2; i++) { | |
c553b3ca | 783 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
784 | cpu_relax(); |
785 | writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); | |
786 | writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); | |
787 | writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 788 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
789 | } |
790 | last_dbb_events = dbb_events; | |
791 | last_abb_events = abb_events; | |
792 | } | |
793 | ||
794 | void prcmu_enable_wakeups(u32 wakeups) | |
795 | { | |
796 | unsigned long flags; | |
797 | u32 bits; | |
798 | int i; | |
799 | ||
800 | BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); | |
801 | ||
802 | for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { | |
803 | if (wakeups & BIT(i)) | |
804 | bits |= prcmu_wakeup_bit[i]; | |
805 | } | |
806 | ||
807 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
808 | ||
809 | mb0_transfer.req.dbb_wakeups = bits; | |
810 | config_wakeups(); | |
811 | ||
812 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
813 | } | |
814 | ||
815 | void prcmu_config_abb_event_readout(u32 abb_events) | |
816 | { | |
817 | unsigned long flags; | |
818 | ||
819 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
820 | ||
821 | mb0_transfer.req.abb_events = abb_events; | |
822 | config_wakeups(); | |
823 | ||
824 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
825 | } | |
826 | ||
827 | void prcmu_get_abb_event_buffer(void __iomem **buf) | |
828 | { | |
829 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
830 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); | |
831 | else | |
832 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); | |
833 | } | |
834 | ||
835 | /** | |
836 | * prcmu_set_arm_opp - set the appropriate ARM OPP | |
837 | * @opp: The new ARM operating point to which transition is to be made | |
838 | * Returns: 0 on success, non-zero on failure | |
839 | * | |
840 | * This function sets the the operating point of the ARM. | |
841 | */ | |
842 | int prcmu_set_arm_opp(u8 opp) | |
843 | { | |
844 | int r; | |
845 | ||
846 | if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) | |
847 | return -EINVAL; | |
848 | ||
849 | r = 0; | |
850 | ||
851 | mutex_lock(&mb1_transfer.lock); | |
852 | ||
c553b3ca | 853 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
854 | cpu_relax(); |
855 | ||
856 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
857 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
858 | writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
859 | ||
c553b3ca | 860 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
861 | wait_for_completion(&mb1_transfer.work); |
862 | ||
863 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
864 | (mb1_transfer.ack.arm_opp != opp)) | |
865 | r = -EIO; | |
866 | ||
867 | mutex_unlock(&mb1_transfer.lock); | |
868 | ||
869 | return r; | |
870 | } | |
871 | ||
872 | /** | |
873 | * prcmu_get_arm_opp - get the current ARM OPP | |
874 | * | |
875 | * Returns: the current ARM OPP | |
876 | */ | |
877 | int prcmu_get_arm_opp(void) | |
878 | { | |
879 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
880 | } | |
881 | ||
882 | /** | |
883 | * prcmu_get_ddr_opp - get the current DDR OPP | |
884 | * | |
885 | * Returns: the current DDR OPP | |
886 | */ | |
887 | int prcmu_get_ddr_opp(void) | |
888 | { | |
c553b3ca | 889 | return readb(PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
890 | } |
891 | ||
892 | /** | |
893 | * set_ddr_opp - set the appropriate DDR OPP | |
894 | * @opp: The new DDR operating point to which transition is to be made | |
895 | * Returns: 0 on success, non-zero on failure | |
896 | * | |
897 | * This function sets the operating point of the DDR. | |
898 | */ | |
899 | int prcmu_set_ddr_opp(u8 opp) | |
900 | { | |
901 | if (opp < DDR_100_OPP || opp > DDR_25_OPP) | |
902 | return -EINVAL; | |
903 | /* Changing the DDR OPP can hang the hardware pre-v21 */ | |
904 | if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) | |
c553b3ca | 905 | writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
906 | |
907 | return 0; | |
908 | } | |
909 | /** | |
910 | * set_ape_opp - set the appropriate APE OPP | |
911 | * @opp: The new APE operating point to which transition is to be made | |
912 | * Returns: 0 on success, non-zero on failure | |
913 | * | |
914 | * This function sets the operating point of the APE. | |
915 | */ | |
916 | int prcmu_set_ape_opp(u8 opp) | |
917 | { | |
918 | int r = 0; | |
919 | ||
920 | mutex_lock(&mb1_transfer.lock); | |
921 | ||
c553b3ca | 922 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
923 | cpu_relax(); |
924 | ||
925 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
926 | writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
927 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
928 | ||
c553b3ca | 929 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
930 | wait_for_completion(&mb1_transfer.work); |
931 | ||
932 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
933 | (mb1_transfer.ack.ape_opp != opp)) | |
934 | r = -EIO; | |
935 | ||
936 | mutex_unlock(&mb1_transfer.lock); | |
937 | ||
938 | return r; | |
939 | } | |
940 | ||
941 | /** | |
942 | * prcmu_get_ape_opp - get the current APE OPP | |
943 | * | |
944 | * Returns: the current APE OPP | |
945 | */ | |
946 | int prcmu_get_ape_opp(void) | |
947 | { | |
948 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); | |
949 | } | |
950 | ||
951 | /** | |
952 | * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage | |
953 | * @enable: true to request the higher voltage, false to drop a request. | |
954 | * | |
955 | * Calls to this function to enable and disable requests must be balanced. | |
956 | */ | |
957 | int prcmu_request_ape_opp_100_voltage(bool enable) | |
958 | { | |
959 | int r = 0; | |
960 | u8 header; | |
961 | static unsigned int requests; | |
962 | ||
963 | mutex_lock(&mb1_transfer.lock); | |
964 | ||
965 | if (enable) { | |
966 | if (0 != requests++) | |
967 | goto unlock_and_return; | |
968 | header = MB1H_REQUEST_APE_OPP_100_VOLT; | |
969 | } else { | |
970 | if (requests == 0) { | |
971 | r = -EIO; | |
972 | goto unlock_and_return; | |
973 | } else if (1 != requests--) { | |
974 | goto unlock_and_return; | |
975 | } | |
976 | header = MB1H_RELEASE_APE_OPP_100_VOLT; | |
977 | } | |
978 | ||
c553b3ca | 979 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
980 | cpu_relax(); |
981 | ||
982 | writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
983 | ||
c553b3ca | 984 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
985 | wait_for_completion(&mb1_transfer.work); |
986 | ||
987 | if ((mb1_transfer.ack.header != header) || | |
988 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
989 | r = -EIO; | |
990 | ||
991 | unlock_and_return: | |
992 | mutex_unlock(&mb1_transfer.lock); | |
993 | ||
994 | return r; | |
995 | } | |
996 | ||
997 | /** | |
998 | * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup | |
999 | * | |
1000 | * This function releases the power state requirements of a USB wakeup. | |
1001 | */ | |
1002 | int prcmu_release_usb_wakeup_state(void) | |
1003 | { | |
1004 | int r = 0; | |
1005 | ||
1006 | mutex_lock(&mb1_transfer.lock); | |
1007 | ||
c553b3ca | 1008 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1009 | cpu_relax(); |
1010 | ||
1011 | writeb(MB1H_RELEASE_USB_WAKEUP, | |
1012 | (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1013 | ||
c553b3ca | 1014 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1015 | wait_for_completion(&mb1_transfer.work); |
1016 | ||
1017 | if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || | |
1018 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1019 | r = -EIO; | |
1020 | ||
1021 | mutex_unlock(&mb1_transfer.lock); | |
1022 | ||
1023 | return r; | |
1024 | } | |
1025 | ||
1026 | /** | |
1027 | * prcmu_set_epod - set the state of a EPOD (power domain) | |
1028 | * @epod_id: The EPOD to set | |
1029 | * @epod_state: The new EPOD state | |
1030 | * | |
1031 | * This function sets the state of a EPOD (power domain). It may not be called | |
1032 | * from interrupt context. | |
1033 | */ | |
1034 | int prcmu_set_epod(u16 epod_id, u8 epod_state) | |
1035 | { | |
1036 | int r = 0; | |
1037 | bool ram_retention = false; | |
1038 | int i; | |
1039 | ||
1040 | /* check argument */ | |
1041 | BUG_ON(epod_id >= NUM_EPOD_ID); | |
1042 | ||
1043 | /* set flag if retention is possible */ | |
1044 | switch (epod_id) { | |
1045 | case EPOD_ID_SVAMMDSP: | |
1046 | case EPOD_ID_SIAMMDSP: | |
1047 | case EPOD_ID_ESRAM12: | |
1048 | case EPOD_ID_ESRAM34: | |
1049 | ram_retention = true; | |
1050 | break; | |
1051 | } | |
1052 | ||
1053 | /* check argument */ | |
1054 | BUG_ON(epod_state > EPOD_STATE_ON); | |
1055 | BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); | |
1056 | ||
1057 | /* get lock */ | |
1058 | mutex_lock(&mb2_transfer.lock); | |
1059 | ||
1060 | /* wait for mailbox */ | |
c553b3ca | 1061 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) |
3df57bcf MN |
1062 | cpu_relax(); |
1063 | ||
1064 | /* fill in mailbox */ | |
1065 | for (i = 0; i < NUM_EPOD_ID; i++) | |
1066 | writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); | |
1067 | writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); | |
1068 | ||
1069 | writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); | |
1070 | ||
c553b3ca | 1071 | writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1072 | |
1073 | /* | |
1074 | * The current firmware version does not handle errors correctly, | |
1075 | * and we cannot recover if there is an error. | |
1076 | * This is expected to change when the firmware is updated. | |
1077 | */ | |
1078 | if (!wait_for_completion_timeout(&mb2_transfer.work, | |
1079 | msecs_to_jiffies(20000))) { | |
1080 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1081 | __func__); | |
1082 | r = -EIO; | |
1083 | goto unlock_and_return; | |
1084 | } | |
1085 | ||
1086 | if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) | |
1087 | r = -EIO; | |
1088 | ||
1089 | unlock_and_return: | |
1090 | mutex_unlock(&mb2_transfer.lock); | |
1091 | return r; | |
1092 | } | |
1093 | ||
1094 | /** | |
1095 | * prcmu_configure_auto_pm - Configure autonomous power management. | |
1096 | * @sleep: Configuration for ApSleep. | |
1097 | * @idle: Configuration for ApIdle. | |
1098 | */ | |
1099 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, | |
1100 | struct prcmu_auto_pm_config *idle) | |
1101 | { | |
1102 | u32 sleep_cfg; | |
1103 | u32 idle_cfg; | |
1104 | unsigned long flags; | |
e3726fcf | 1105 | |
3df57bcf | 1106 | BUG_ON((sleep == NULL) || (idle == NULL)); |
650c2a21 | 1107 | |
3df57bcf MN |
1108 | sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); |
1109 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); | |
1110 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); | |
1111 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); | |
1112 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); | |
1113 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); | |
e3726fcf | 1114 | |
3df57bcf MN |
1115 | idle_cfg = (idle->sva_auto_pm_enable & 0xF); |
1116 | idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); | |
1117 | idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); | |
1118 | idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); | |
1119 | idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); | |
1120 | idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); | |
e3726fcf | 1121 | |
3df57bcf | 1122 | spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); |
e0befb23 | 1123 | |
3df57bcf MN |
1124 | /* |
1125 | * The autonomous power management configuration is done through | |
1126 | * fields in mailbox 2, but these fields are only used as shared | |
1127 | * variables - i.e. there is no need to send a message. | |
1128 | */ | |
1129 | writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); | |
1130 | writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); | |
e0befb23 | 1131 | |
3df57bcf MN |
1132 | mb2_transfer.auto_pm_enabled = |
1133 | ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1134 | (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1135 | (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1136 | (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); | |
e0befb23 | 1137 | |
3df57bcf MN |
1138 | spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); |
1139 | } | |
1140 | EXPORT_SYMBOL(prcmu_configure_auto_pm); | |
e3726fcf | 1141 | |
3df57bcf MN |
1142 | bool prcmu_is_auto_pm_enabled(void) |
1143 | { | |
1144 | return mb2_transfer.auto_pm_enabled; | |
1145 | } | |
e0befb23 | 1146 | |
3df57bcf MN |
1147 | static int request_sysclk(bool enable) |
1148 | { | |
1149 | int r; | |
1150 | unsigned long flags; | |
e3726fcf | 1151 | |
3df57bcf | 1152 | r = 0; |
e3726fcf | 1153 | |
3df57bcf | 1154 | mutex_lock(&mb3_transfer.sysclk_lock); |
e0befb23 | 1155 | |
3df57bcf | 1156 | spin_lock_irqsave(&mb3_transfer.lock, flags); |
e0befb23 | 1157 | |
c553b3ca | 1158 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) |
3df57bcf | 1159 | cpu_relax(); |
e0befb23 | 1160 | |
3df57bcf | 1161 | writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); |
e3726fcf | 1162 | |
3df57bcf | 1163 | writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); |
c553b3ca | 1164 | writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); |
e3726fcf | 1165 | |
3df57bcf MN |
1166 | spin_unlock_irqrestore(&mb3_transfer.lock, flags); |
1167 | ||
1168 | /* | |
1169 | * The firmware only sends an ACK if we want to enable the | |
1170 | * SysClk, and it succeeds. | |
1171 | */ | |
1172 | if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, | |
1173 | msecs_to_jiffies(20000))) { | |
1174 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1175 | __func__); | |
1176 | r = -EIO; | |
1177 | } | |
1178 | ||
1179 | mutex_unlock(&mb3_transfer.sysclk_lock); | |
1180 | ||
1181 | return r; | |
1182 | } | |
1183 | ||
1184 | static int request_timclk(bool enable) | |
1185 | { | |
1186 | u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); | |
1187 | ||
1188 | if (!enable) | |
1189 | val |= PRCM_TCR_STOP_TIMERS; | |
c553b3ca | 1190 | writel(val, PRCM_TCR); |
3df57bcf MN |
1191 | |
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | static int request_reg_clock(u8 clock, bool enable) | |
1196 | { | |
1197 | u32 val; | |
1198 | unsigned long flags; | |
1199 | ||
1200 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1201 | ||
1202 | /* Grab the HW semaphore. */ | |
c553b3ca | 1203 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
1204 | cpu_relax(); |
1205 | ||
1206 | val = readl(_PRCMU_BASE + clk_mgt[clock].offset); | |
1207 | if (enable) { | |
1208 | val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); | |
1209 | } else { | |
1210 | clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1211 | val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1212 | } | |
1213 | writel(val, (_PRCMU_BASE + clk_mgt[clock].offset)); | |
1214 | ||
1215 | /* Release the HW semaphore. */ | |
c553b3ca | 1216 | writel(0, PRCM_SEM); |
3df57bcf MN |
1217 | |
1218 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
1223 | /** | |
1224 | * prcmu_request_clock() - Request for a clock to be enabled or disabled. | |
1225 | * @clock: The clock for which the request is made. | |
1226 | * @enable: Whether the clock should be enabled (true) or disabled (false). | |
1227 | * | |
1228 | * This function should only be used by the clock implementation. | |
1229 | * Do not use it from any other place! | |
1230 | */ | |
1231 | int prcmu_request_clock(u8 clock, bool enable) | |
1232 | { | |
1233 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
1234 | return request_reg_clock(clock, enable); | |
1235 | else if (clock == PRCMU_TIMCLK) | |
1236 | return request_timclk(enable); | |
1237 | else if (clock == PRCMU_SYSCLK) | |
1238 | return request_sysclk(enable); | |
1239 | else | |
1240 | return -EINVAL; | |
1241 | } | |
1242 | ||
1243 | int prcmu_config_esram0_deep_sleep(u8 state) | |
1244 | { | |
1245 | if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || | |
1246 | (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) | |
1247 | return -EINVAL; | |
1248 | ||
1249 | mutex_lock(&mb4_transfer.lock); | |
1250 | ||
c553b3ca | 1251 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1252 | cpu_relax(); |
1253 | ||
1254 | writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1255 | writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), | |
1256 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); | |
1257 | writeb(DDR_PWR_STATE_ON, | |
1258 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); | |
1259 | writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); | |
1260 | ||
c553b3ca | 1261 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1262 | wait_for_completion(&mb4_transfer.work); |
1263 | ||
1264 | mutex_unlock(&mb4_transfer.lock); | |
1265 | ||
1266 | return 0; | |
1267 | } | |
1268 | ||
1269 | int prcmu_config_hotdog(u8 threshold) | |
1270 | { | |
1271 | mutex_lock(&mb4_transfer.lock); | |
1272 | ||
c553b3ca | 1273 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1274 | cpu_relax(); |
1275 | ||
1276 | writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); | |
1277 | writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1278 | ||
c553b3ca | 1279 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1280 | wait_for_completion(&mb4_transfer.work); |
1281 | ||
1282 | mutex_unlock(&mb4_transfer.lock); | |
1283 | ||
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | int prcmu_config_hotmon(u8 low, u8 high) | |
1288 | { | |
1289 | mutex_lock(&mb4_transfer.lock); | |
1290 | ||
c553b3ca | 1291 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1292 | cpu_relax(); |
1293 | ||
1294 | writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); | |
1295 | writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); | |
1296 | writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), | |
1297 | (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); | |
1298 | writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1299 | ||
c553b3ca | 1300 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1301 | wait_for_completion(&mb4_transfer.work); |
1302 | ||
1303 | mutex_unlock(&mb4_transfer.lock); | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
1308 | static int config_hot_period(u16 val) | |
1309 | { | |
1310 | mutex_lock(&mb4_transfer.lock); | |
1311 | ||
c553b3ca | 1312 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1313 | cpu_relax(); |
1314 | ||
1315 | writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); | |
1316 | writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1317 | ||
c553b3ca | 1318 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1319 | wait_for_completion(&mb4_transfer.work); |
1320 | ||
1321 | mutex_unlock(&mb4_transfer.lock); | |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
1326 | int prcmu_start_temp_sense(u16 cycles32k) | |
1327 | { | |
1328 | if (cycles32k == 0xFFFF) | |
1329 | return -EINVAL; | |
1330 | ||
1331 | return config_hot_period(cycles32k); | |
1332 | } | |
1333 | ||
1334 | int prcmu_stop_temp_sense(void) | |
1335 | { | |
1336 | return config_hot_period(0xFFFF); | |
1337 | } | |
1338 | ||
1339 | /** | |
1340 | * prcmu_set_clock_divider() - Configure the clock divider. | |
1341 | * @clock: The clock for which the request is made. | |
1342 | * @divider: The clock divider. (< 32) | |
1343 | * | |
1344 | * This function should only be used by the clock implementation. | |
1345 | * Do not use it from any other place! | |
1346 | */ | |
1347 | int prcmu_set_clock_divider(u8 clock, u8 divider) | |
1348 | { | |
1349 | u32 val; | |
1350 | unsigned long flags; | |
1351 | ||
1352 | if ((clock >= PRCMU_NUM_REG_CLOCKS) || (divider < 1) || (31 < divider)) | |
1353 | return -EINVAL; | |
1354 | ||
1355 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1356 | ||
1357 | /* Grab the HW semaphore. */ | |
c553b3ca | 1358 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
1359 | cpu_relax(); |
1360 | ||
1361 | val = readl(_PRCMU_BASE + clk_mgt[clock].offset); | |
1362 | val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK); | |
1363 | val |= (u32)divider; | |
1364 | writel(val, (_PRCMU_BASE + clk_mgt[clock].offset)); | |
1365 | ||
1366 | /* Release the HW semaphore. */ | |
c553b3ca | 1367 | writel(0, PRCM_SEM); |
3df57bcf MN |
1368 | |
1369 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1370 | ||
1371 | return 0; | |
1372 | } | |
e3726fcf LW |
1373 | |
1374 | /** | |
1375 | * prcmu_abb_read() - Read register value(s) from the ABB. | |
1376 | * @slave: The I2C slave address. | |
1377 | * @reg: The (start) register address. | |
1378 | * @value: The read out value(s). | |
1379 | * @size: The number of registers to read. | |
1380 | * | |
1381 | * Reads register value(s) from the ABB. | |
1382 | * @size has to be 1 for the current firmware version. | |
1383 | */ | |
1384 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
1385 | { | |
1386 | int r; | |
1387 | ||
1388 | if (size != 1) | |
1389 | return -EINVAL; | |
1390 | ||
3df57bcf | 1391 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 1392 | |
c553b3ca | 1393 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
1394 | cpu_relax(); |
1395 | ||
3df57bcf MN |
1396 | writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
1397 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
1398 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
1399 | writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
1400 | ||
c553b3ca | 1401 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 1402 | |
e3726fcf | 1403 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
1404 | msecs_to_jiffies(20000))) { |
1405 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1406 | __func__); | |
e3726fcf | 1407 | r = -EIO; |
3df57bcf MN |
1408 | } else { |
1409 | r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); | |
e3726fcf | 1410 | } |
3df57bcf | 1411 | |
e3726fcf LW |
1412 | if (!r) |
1413 | *value = mb5_transfer.ack.value; | |
1414 | ||
e3726fcf | 1415 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 1416 | |
e3726fcf LW |
1417 | return r; |
1418 | } | |
e3726fcf LW |
1419 | |
1420 | /** | |
1421 | * prcmu_abb_write() - Write register value(s) to the ABB. | |
1422 | * @slave: The I2C slave address. | |
1423 | * @reg: The (start) register address. | |
1424 | * @value: The value(s) to write. | |
1425 | * @size: The number of registers to write. | |
1426 | * | |
1427 | * Reads register value(s) from the ABB. | |
1428 | * @size has to be 1 for the current firmware version. | |
1429 | */ | |
1430 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
1431 | { | |
1432 | int r; | |
1433 | ||
1434 | if (size != 1) | |
1435 | return -EINVAL; | |
1436 | ||
3df57bcf | 1437 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 1438 | |
c553b3ca | 1439 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
1440 | cpu_relax(); |
1441 | ||
3df57bcf MN |
1442 | writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
1443 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
1444 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
1445 | writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
1446 | ||
c553b3ca | 1447 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 1448 | |
e3726fcf | 1449 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
1450 | msecs_to_jiffies(20000))) { |
1451 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1452 | __func__); | |
e3726fcf | 1453 | r = -EIO; |
3df57bcf MN |
1454 | } else { |
1455 | r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); | |
e3726fcf | 1456 | } |
e3726fcf | 1457 | |
e3726fcf | 1458 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 1459 | |
e3726fcf LW |
1460 | return r; |
1461 | } | |
e3726fcf | 1462 | |
3df57bcf MN |
1463 | /** |
1464 | * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem | |
1465 | */ | |
1466 | void prcmu_ac_wake_req(void) | |
e0befb23 | 1467 | { |
3df57bcf | 1468 | u32 val; |
e0befb23 | 1469 | |
3df57bcf | 1470 | mutex_lock(&mb0_transfer.ac_wake_lock); |
e0befb23 | 1471 | |
c553b3ca | 1472 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
1473 | if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) |
1474 | goto unlock_and_return; | |
e0befb23 | 1475 | |
3df57bcf | 1476 | atomic_set(&ac_wake_req_state, 1); |
e0befb23 | 1477 | |
c553b3ca | 1478 | writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); |
e0befb23 | 1479 | |
3df57bcf MN |
1480 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
1481 | msecs_to_jiffies(20000))) { | |
1482 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1483 | __func__); | |
1484 | } | |
e0befb23 | 1485 | |
3df57bcf MN |
1486 | unlock_and_return: |
1487 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 MP |
1488 | } |
1489 | ||
1490 | /** | |
3df57bcf | 1491 | * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem |
e0befb23 | 1492 | */ |
3df57bcf | 1493 | void prcmu_ac_sleep_req() |
e0befb23 | 1494 | { |
3df57bcf MN |
1495 | u32 val; |
1496 | ||
1497 | mutex_lock(&mb0_transfer.ac_wake_lock); | |
1498 | ||
c553b3ca | 1499 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
1500 | if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) |
1501 | goto unlock_and_return; | |
1502 | ||
1503 | writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), | |
c553b3ca | 1504 | PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
1505 | |
1506 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, | |
1507 | msecs_to_jiffies(20000))) { | |
1508 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1509 | __func__); | |
1510 | } | |
1511 | ||
1512 | atomic_set(&ac_wake_req_state, 0); | |
1513 | ||
1514 | unlock_and_return: | |
1515 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 | 1516 | } |
e0befb23 | 1517 | |
3df57bcf | 1518 | bool prcmu_is_ac_wake_requested(void) |
e0befb23 | 1519 | { |
3df57bcf | 1520 | return (atomic_read(&ac_wake_req_state) != 0); |
e0befb23 | 1521 | } |
e0befb23 MP |
1522 | |
1523 | /** | |
3df57bcf | 1524 | * prcmu_system_reset - System reset |
e0befb23 | 1525 | * |
3df57bcf MN |
1526 | * Saves the reset reason code and then sets the APE_SOFRST register which |
1527 | * fires interrupt to fw | |
e0befb23 | 1528 | */ |
3df57bcf | 1529 | void prcmu_system_reset(u16 reset_code) |
e0befb23 | 1530 | { |
3df57bcf | 1531 | writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); |
c553b3ca | 1532 | writel(1, PRCM_APE_SOFTRST); |
e0befb23 | 1533 | } |
e0befb23 MP |
1534 | |
1535 | /** | |
3df57bcf | 1536 | * prcmu_reset_modem - ask the PRCMU to reset modem |
e0befb23 | 1537 | */ |
3df57bcf | 1538 | void prcmu_modem_reset(void) |
e0befb23 | 1539 | { |
3df57bcf MN |
1540 | mutex_lock(&mb1_transfer.lock); |
1541 | ||
c553b3ca | 1542 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1543 | cpu_relax(); |
1544 | ||
1545 | writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
c553b3ca | 1546 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1547 | wait_for_completion(&mb1_transfer.work); |
1548 | ||
1549 | /* | |
1550 | * No need to check return from PRCMU as modem should go in reset state | |
1551 | * This state is already managed by upper layer | |
1552 | */ | |
1553 | ||
1554 | mutex_unlock(&mb1_transfer.lock); | |
e0befb23 | 1555 | } |
e0befb23 | 1556 | |
3df57bcf | 1557 | static void ack_dbb_wakeup(void) |
e0befb23 | 1558 | { |
3df57bcf MN |
1559 | unsigned long flags; |
1560 | ||
1561 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
1562 | ||
c553b3ca | 1563 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
1564 | cpu_relax(); |
1565 | ||
1566 | writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 1567 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1568 | |
1569 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
e0befb23 | 1570 | } |
e0befb23 | 1571 | |
3df57bcf | 1572 | static inline void print_unknown_header_warning(u8 n, u8 header) |
e0befb23 | 1573 | { |
3df57bcf MN |
1574 | pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", |
1575 | header, n); | |
e0befb23 MP |
1576 | } |
1577 | ||
3df57bcf | 1578 | static bool read_mailbox_0(void) |
e3726fcf | 1579 | { |
3df57bcf MN |
1580 | bool r; |
1581 | u32 ev; | |
1582 | unsigned int n; | |
1583 | u8 header; | |
1584 | ||
1585 | header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); | |
1586 | switch (header) { | |
1587 | case MB0H_WAKEUP_EXE: | |
1588 | case MB0H_WAKEUP_SLEEP: | |
1589 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
1590 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); | |
1591 | else | |
1592 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); | |
1593 | ||
1594 | if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) | |
1595 | complete(&mb0_transfer.ac_wake_work); | |
1596 | if (ev & WAKEUP_BIT_SYSCLK_OK) | |
1597 | complete(&mb3_transfer.sysclk_work); | |
1598 | ||
1599 | ev &= mb0_transfer.req.dbb_irqs; | |
1600 | ||
1601 | for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { | |
1602 | if (ev & prcmu_irq_bit[n]) | |
1603 | generic_handle_irq(IRQ_PRCMU_BASE + n); | |
1604 | } | |
1605 | r = true; | |
1606 | break; | |
1607 | default: | |
1608 | print_unknown_header_warning(0, header); | |
1609 | r = false; | |
1610 | break; | |
1611 | } | |
c553b3ca | 1612 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); |
3df57bcf | 1613 | return r; |
e3726fcf LW |
1614 | } |
1615 | ||
3df57bcf | 1616 | static bool read_mailbox_1(void) |
e3726fcf | 1617 | { |
3df57bcf MN |
1618 | mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); |
1619 | mb1_transfer.ack.arm_opp = readb(tcdm_base + | |
1620 | PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
1621 | mb1_transfer.ack.ape_opp = readb(tcdm_base + | |
1622 | PRCM_ACK_MB1_CURRENT_APE_OPP); | |
1623 | mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + | |
1624 | PRCM_ACK_MB1_APE_VOLTAGE_STATUS); | |
c553b3ca | 1625 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); |
e0befb23 | 1626 | complete(&mb1_transfer.work); |
3df57bcf | 1627 | return false; |
e3726fcf LW |
1628 | } |
1629 | ||
3df57bcf | 1630 | static bool read_mailbox_2(void) |
e3726fcf | 1631 | { |
3df57bcf | 1632 | mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); |
c553b3ca | 1633 | writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
1634 | complete(&mb2_transfer.work); |
1635 | return false; | |
e3726fcf LW |
1636 | } |
1637 | ||
3df57bcf | 1638 | static bool read_mailbox_3(void) |
e3726fcf | 1639 | { |
c553b3ca | 1640 | writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); |
3df57bcf | 1641 | return false; |
e3726fcf LW |
1642 | } |
1643 | ||
3df57bcf | 1644 | static bool read_mailbox_4(void) |
e3726fcf | 1645 | { |
3df57bcf MN |
1646 | u8 header; |
1647 | bool do_complete = true; | |
1648 | ||
1649 | header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); | |
1650 | switch (header) { | |
1651 | case MB4H_MEM_ST: | |
1652 | case MB4H_HOTDOG: | |
1653 | case MB4H_HOTMON: | |
1654 | case MB4H_HOT_PERIOD: | |
a592c2e2 MN |
1655 | case MB4H_A9WDOG_CONF: |
1656 | case MB4H_A9WDOG_EN: | |
1657 | case MB4H_A9WDOG_DIS: | |
1658 | case MB4H_A9WDOG_LOAD: | |
1659 | case MB4H_A9WDOG_KICK: | |
3df57bcf MN |
1660 | break; |
1661 | default: | |
1662 | print_unknown_header_warning(4, header); | |
1663 | do_complete = false; | |
1664 | break; | |
1665 | } | |
1666 | ||
c553b3ca | 1667 | writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
1668 | |
1669 | if (do_complete) | |
1670 | complete(&mb4_transfer.work); | |
1671 | ||
1672 | return false; | |
e3726fcf LW |
1673 | } |
1674 | ||
3df57bcf | 1675 | static bool read_mailbox_5(void) |
e3726fcf | 1676 | { |
3df57bcf MN |
1677 | mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); |
1678 | mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); | |
c553b3ca | 1679 | writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); |
e3726fcf | 1680 | complete(&mb5_transfer.work); |
3df57bcf | 1681 | return false; |
e3726fcf LW |
1682 | } |
1683 | ||
3df57bcf | 1684 | static bool read_mailbox_6(void) |
e3726fcf | 1685 | { |
c553b3ca | 1686 | writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); |
3df57bcf | 1687 | return false; |
e3726fcf LW |
1688 | } |
1689 | ||
3df57bcf | 1690 | static bool read_mailbox_7(void) |
e3726fcf | 1691 | { |
c553b3ca | 1692 | writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); |
3df57bcf | 1693 | return false; |
e3726fcf LW |
1694 | } |
1695 | ||
3df57bcf | 1696 | static bool (* const read_mailbox[NUM_MB])(void) = { |
e3726fcf LW |
1697 | read_mailbox_0, |
1698 | read_mailbox_1, | |
1699 | read_mailbox_2, | |
1700 | read_mailbox_3, | |
1701 | read_mailbox_4, | |
1702 | read_mailbox_5, | |
1703 | read_mailbox_6, | |
1704 | read_mailbox_7 | |
1705 | }; | |
1706 | ||
1707 | static irqreturn_t prcmu_irq_handler(int irq, void *data) | |
1708 | { | |
1709 | u32 bits; | |
1710 | u8 n; | |
3df57bcf | 1711 | irqreturn_t r; |
e3726fcf | 1712 | |
c553b3ca | 1713 | bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); |
e3726fcf LW |
1714 | if (unlikely(!bits)) |
1715 | return IRQ_NONE; | |
1716 | ||
3df57bcf | 1717 | r = IRQ_HANDLED; |
e3726fcf LW |
1718 | for (n = 0; bits; n++) { |
1719 | if (bits & MBOX_BIT(n)) { | |
1720 | bits -= MBOX_BIT(n); | |
3df57bcf MN |
1721 | if (read_mailbox[n]()) |
1722 | r = IRQ_WAKE_THREAD; | |
e3726fcf LW |
1723 | } |
1724 | } | |
3df57bcf MN |
1725 | return r; |
1726 | } | |
1727 | ||
1728 | static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) | |
1729 | { | |
1730 | ack_dbb_wakeup(); | |
e3726fcf LW |
1731 | return IRQ_HANDLED; |
1732 | } | |
1733 | ||
3df57bcf MN |
1734 | static void prcmu_mask_work(struct work_struct *work) |
1735 | { | |
1736 | unsigned long flags; | |
1737 | ||
1738 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
1739 | ||
1740 | config_wakeups(); | |
1741 | ||
1742 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
1743 | } | |
1744 | ||
1745 | static void prcmu_irq_mask(struct irq_data *d) | |
1746 | { | |
1747 | unsigned long flags; | |
1748 | ||
1749 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
1750 | ||
1751 | mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; | |
1752 | ||
1753 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
1754 | ||
1755 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
1756 | schedule_work(&mb0_transfer.mask_work); | |
1757 | } | |
1758 | ||
1759 | static void prcmu_irq_unmask(struct irq_data *d) | |
1760 | { | |
1761 | unsigned long flags; | |
1762 | ||
1763 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
1764 | ||
1765 | mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; | |
1766 | ||
1767 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
1768 | ||
1769 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
1770 | schedule_work(&mb0_transfer.mask_work); | |
1771 | } | |
1772 | ||
1773 | static void noop(struct irq_data *d) | |
1774 | { | |
1775 | } | |
1776 | ||
1777 | static struct irq_chip prcmu_irq_chip = { | |
1778 | .name = "prcmu", | |
1779 | .irq_disable = prcmu_irq_mask, | |
1780 | .irq_ack = noop, | |
1781 | .irq_mask = prcmu_irq_mask, | |
1782 | .irq_unmask = prcmu_irq_unmask, | |
1783 | }; | |
1784 | ||
fcbd458e MW |
1785 | void __init prcmu_early_init(void) |
1786 | { | |
3df57bcf MN |
1787 | unsigned int i; |
1788 | ||
1789 | if (cpu_is_u8500v1()) { | |
fcbd458e MW |
1790 | tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1); |
1791 | } else if (cpu_is_u8500v2()) { | |
3df57bcf MN |
1792 | void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); |
1793 | ||
1794 | if (tcpm_base != NULL) { | |
1795 | int version; | |
1796 | version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); | |
1797 | prcmu_version.project_number = version & 0xFF; | |
1798 | prcmu_version.api_version = (version >> 8) & 0xFF; | |
1799 | prcmu_version.func_version = (version >> 16) & 0xFF; | |
1800 | prcmu_version.errata = (version >> 24) & 0xFF; | |
1801 | pr_info("PRCMU firmware version %d.%d.%d\n", | |
1802 | (version >> 8) & 0xFF, (version >> 16) & 0xFF, | |
1803 | (version >> 24) & 0xFF); | |
1804 | iounmap(tcpm_base); | |
1805 | } | |
1806 | ||
fcbd458e MW |
1807 | tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); |
1808 | } else { | |
1809 | pr_err("prcmu: Unsupported chip version\n"); | |
1810 | BUG(); | |
1811 | } | |
e0befb23 | 1812 | |
3df57bcf MN |
1813 | spin_lock_init(&mb0_transfer.lock); |
1814 | spin_lock_init(&mb0_transfer.dbb_irqs_lock); | |
1815 | mutex_init(&mb0_transfer.ac_wake_lock); | |
1816 | init_completion(&mb0_transfer.ac_wake_work); | |
e0befb23 MP |
1817 | mutex_init(&mb1_transfer.lock); |
1818 | init_completion(&mb1_transfer.work); | |
3df57bcf MN |
1819 | mutex_init(&mb2_transfer.lock); |
1820 | init_completion(&mb2_transfer.work); | |
1821 | spin_lock_init(&mb2_transfer.auto_pm_lock); | |
1822 | spin_lock_init(&mb3_transfer.lock); | |
1823 | mutex_init(&mb3_transfer.sysclk_lock); | |
1824 | init_completion(&mb3_transfer.sysclk_work); | |
1825 | mutex_init(&mb4_transfer.lock); | |
1826 | init_completion(&mb4_transfer.work); | |
e3726fcf LW |
1827 | mutex_init(&mb5_transfer.lock); |
1828 | init_completion(&mb5_transfer.work); | |
1829 | ||
3df57bcf MN |
1830 | INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); |
1831 | ||
1832 | /* Initalize irqs. */ | |
1833 | for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) { | |
1834 | unsigned int irq; | |
1835 | ||
1836 | irq = IRQ_PRCMU_BASE + i; | |
1837 | irq_set_chip_and_handler(irq, &prcmu_irq_chip, | |
1838 | handle_simple_irq); | |
1839 | set_irq_flags(irq, IRQF_VALID); | |
1840 | } | |
1841 | } | |
1842 | ||
1032fbfd BJ |
1843 | /* |
1844 | * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC | |
1845 | */ | |
1846 | static struct regulator_consumer_supply db8500_vape_consumers[] = { | |
1847 | REGULATOR_SUPPLY("v-ape", NULL), | |
1848 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), | |
1849 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), | |
1850 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), | |
1851 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), | |
1852 | /* "v-mmc" changed to "vcore" in the mainline kernel */ | |
1853 | REGULATOR_SUPPLY("vcore", "sdi0"), | |
1854 | REGULATOR_SUPPLY("vcore", "sdi1"), | |
1855 | REGULATOR_SUPPLY("vcore", "sdi2"), | |
1856 | REGULATOR_SUPPLY("vcore", "sdi3"), | |
1857 | REGULATOR_SUPPLY("vcore", "sdi4"), | |
1858 | REGULATOR_SUPPLY("v-dma", "dma40.0"), | |
1859 | REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), | |
1860 | /* "v-uart" changed to "vcore" in the mainline kernel */ | |
1861 | REGULATOR_SUPPLY("vcore", "uart0"), | |
1862 | REGULATOR_SUPPLY("vcore", "uart1"), | |
1863 | REGULATOR_SUPPLY("vcore", "uart2"), | |
1864 | REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), | |
1865 | }; | |
1866 | ||
1867 | static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { | |
1868 | /* CG2900 and CW1200 power to off-chip peripherals */ | |
1869 | REGULATOR_SUPPLY("gbf_1v8", "cg2900-uart.0"), | |
1870 | REGULATOR_SUPPLY("wlan_1v8", "cw1200.0"), | |
1871 | REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), | |
1872 | /* AV8100 regulator */ | |
1873 | REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), | |
1874 | }; | |
1875 | ||
1876 | static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { | |
1877 | REGULATOR_SUPPLY("vsupply", "b2r2.0"), | |
1878 | REGULATOR_SUPPLY("vsupply", "mcde.0"), | |
1879 | }; | |
1880 | ||
1881 | static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { | |
1882 | [DB8500_REGULATOR_VAPE] = { | |
1883 | .constraints = { | |
1884 | .name = "db8500-vape", | |
1885 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1886 | }, | |
1887 | .consumer_supplies = db8500_vape_consumers, | |
1888 | .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), | |
1889 | }, | |
1890 | [DB8500_REGULATOR_VARM] = { | |
1891 | .constraints = { | |
1892 | .name = "db8500-varm", | |
1893 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1894 | }, | |
1895 | }, | |
1896 | [DB8500_REGULATOR_VMODEM] = { | |
1897 | .constraints = { | |
1898 | .name = "db8500-vmodem", | |
1899 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1900 | }, | |
1901 | }, | |
1902 | [DB8500_REGULATOR_VPLL] = { | |
1903 | .constraints = { | |
1904 | .name = "db8500-vpll", | |
1905 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1906 | }, | |
1907 | }, | |
1908 | [DB8500_REGULATOR_VSMPS1] = { | |
1909 | .constraints = { | |
1910 | .name = "db8500-vsmps1", | |
1911 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1912 | }, | |
1913 | }, | |
1914 | [DB8500_REGULATOR_VSMPS2] = { | |
1915 | .constraints = { | |
1916 | .name = "db8500-vsmps2", | |
1917 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1918 | }, | |
1919 | .consumer_supplies = db8500_vsmps2_consumers, | |
1920 | .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), | |
1921 | }, | |
1922 | [DB8500_REGULATOR_VSMPS3] = { | |
1923 | .constraints = { | |
1924 | .name = "db8500-vsmps3", | |
1925 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1926 | }, | |
1927 | }, | |
1928 | [DB8500_REGULATOR_VRF1] = { | |
1929 | .constraints = { | |
1930 | .name = "db8500-vrf1", | |
1931 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1932 | }, | |
1933 | }, | |
1934 | [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { | |
1935 | .supply_regulator = "db8500-vape", | |
1936 | .constraints = { | |
1937 | .name = "db8500-sva-mmdsp", | |
1938 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1939 | }, | |
1940 | }, | |
1941 | [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { | |
1942 | .constraints = { | |
1943 | /* "ret" means "retention" */ | |
1944 | .name = "db8500-sva-mmdsp-ret", | |
1945 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1946 | }, | |
1947 | }, | |
1948 | [DB8500_REGULATOR_SWITCH_SVAPIPE] = { | |
1949 | .supply_regulator = "db8500-vape", | |
1950 | .constraints = { | |
1951 | .name = "db8500-sva-pipe", | |
1952 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1953 | }, | |
1954 | }, | |
1955 | [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { | |
1956 | .supply_regulator = "db8500-vape", | |
1957 | .constraints = { | |
1958 | .name = "db8500-sia-mmdsp", | |
1959 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1960 | }, | |
1961 | }, | |
1962 | [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { | |
1963 | .constraints = { | |
1964 | .name = "db8500-sia-mmdsp-ret", | |
1965 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1966 | }, | |
1967 | }, | |
1968 | [DB8500_REGULATOR_SWITCH_SIAPIPE] = { | |
1969 | .supply_regulator = "db8500-vape", | |
1970 | .constraints = { | |
1971 | .name = "db8500-sia-pipe", | |
1972 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1973 | }, | |
1974 | }, | |
1975 | [DB8500_REGULATOR_SWITCH_SGA] = { | |
1976 | .supply_regulator = "db8500-vape", | |
1977 | .constraints = { | |
1978 | .name = "db8500-sga", | |
1979 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1980 | }, | |
1981 | }, | |
1982 | [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { | |
1983 | .supply_regulator = "db8500-vape", | |
1984 | .constraints = { | |
1985 | .name = "db8500-b2r2-mcde", | |
1986 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1987 | }, | |
1988 | .consumer_supplies = db8500_b2r2_mcde_consumers, | |
1989 | .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), | |
1990 | }, | |
1991 | [DB8500_REGULATOR_SWITCH_ESRAM12] = { | |
1992 | .supply_regulator = "db8500-vape", | |
1993 | .constraints = { | |
1994 | .name = "db8500-esram12", | |
1995 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1996 | }, | |
1997 | }, | |
1998 | [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { | |
1999 | .constraints = { | |
2000 | .name = "db8500-esram12-ret", | |
2001 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2002 | }, | |
2003 | }, | |
2004 | [DB8500_REGULATOR_SWITCH_ESRAM34] = { | |
2005 | .supply_regulator = "db8500-vape", | |
2006 | .constraints = { | |
2007 | .name = "db8500-esram34", | |
2008 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2009 | }, | |
2010 | }, | |
2011 | [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { | |
2012 | .constraints = { | |
2013 | .name = "db8500-esram34-ret", | |
2014 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2015 | }, | |
2016 | }, | |
2017 | }; | |
2018 | ||
3df57bcf MN |
2019 | static struct mfd_cell db8500_prcmu_devs[] = { |
2020 | { | |
2021 | .name = "db8500-prcmu-regulators", | |
1ed7891f MW |
2022 | .platform_data = &db8500_regulators, |
2023 | .pdata_size = sizeof(db8500_regulators), | |
3df57bcf MN |
2024 | }, |
2025 | { | |
2026 | .name = "cpufreq-u8500", | |
2027 | }, | |
2028 | }; | |
2029 | ||
2030 | /** | |
2031 | * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic | |
2032 | * | |
2033 | */ | |
2034 | static int __init db8500_prcmu_probe(struct platform_device *pdev) | |
2035 | { | |
2036 | int err = 0; | |
2037 | ||
2038 | if (ux500_is_svp()) | |
2039 | return -ENODEV; | |
2040 | ||
e3726fcf | 2041 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
c553b3ca | 2042 | writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2043 | |
2044 | err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, | |
2045 | prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); | |
2046 | if (err < 0) { | |
2047 | pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); | |
2048 | err = -EBUSY; | |
2049 | goto no_irq_return; | |
2050 | } | |
2051 | ||
2052 | if (cpu_is_u8500v20_or_later()) | |
2053 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); | |
2054 | ||
2055 | err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, | |
2056 | ARRAY_SIZE(db8500_prcmu_devs), NULL, | |
2057 | 0); | |
e3726fcf | 2058 | |
3df57bcf MN |
2059 | if (err) |
2060 | pr_err("prcmu: Failed to add subdevices\n"); | |
2061 | else | |
2062 | pr_info("DB8500 PRCMU initialized\n"); | |
2063 | ||
2064 | no_irq_return: | |
2065 | return err; | |
2066 | } | |
2067 | ||
2068 | static struct platform_driver db8500_prcmu_driver = { | |
2069 | .driver = { | |
2070 | .name = "db8500-prcmu", | |
2071 | .owner = THIS_MODULE, | |
2072 | }, | |
2073 | }; | |
2074 | ||
2075 | static int __init db8500_prcmu_init(void) | |
2076 | { | |
2077 | return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe); | |
e3726fcf LW |
2078 | } |
2079 | ||
3df57bcf MN |
2080 | arch_initcall(db8500_prcmu_init); |
2081 | ||
2082 | MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); | |
2083 | MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); | |
2084 | MODULE_LICENSE("GPL v2"); |