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e3726fcf | 1 | /* |
e0befb23 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
e3726fcf LW |
4 | * |
5 | * License Terms: GNU General Public License v2 | |
e0befb23 MP |
6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | |
e3726fcf LW |
8 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
9 | * | |
e0befb23 MP |
10 | * U8500 PRCM Unit interface driver |
11 | * | |
e3726fcf | 12 | */ |
e3726fcf | 13 | #include <linux/module.h> |
3df57bcf MN |
14 | #include <linux/kernel.h> |
15 | #include <linux/delay.h> | |
e3726fcf LW |
16 | #include <linux/errno.h> |
17 | #include <linux/err.h> | |
3df57bcf | 18 | #include <linux/spinlock.h> |
e3726fcf | 19 | #include <linux/io.h> |
3df57bcf | 20 | #include <linux/slab.h> |
e3726fcf LW |
21 | #include <linux/mutex.h> |
22 | #include <linux/completion.h> | |
3df57bcf | 23 | #include <linux/irq.h> |
e3726fcf LW |
24 | #include <linux/jiffies.h> |
25 | #include <linux/bitops.h> | |
3df57bcf MN |
26 | #include <linux/fs.h> |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
29 | #include <linux/mfd/core.h> | |
73180f85 | 30 | #include <linux/mfd/dbx500-prcmu.h> |
3a8e39c9 | 31 | #include <linux/mfd/abx500/ab8500.h> |
1032fbfd BJ |
32 | #include <linux/regulator/db8500-prcmu.h> |
33 | #include <linux/regulator/machine.h> | |
c280f45f | 34 | #include <linux/cpufreq.h> |
b3aac62b | 35 | #include <linux/platform_data/ux500_wdt.h> |
3df57bcf | 36 | #include <mach/irqs.h> |
73180f85 | 37 | #include "dbx500-prcmu-regs.h" |
3df57bcf | 38 | |
3df57bcf MN |
39 | /* Index of different voltages to be used when accessing AVSData */ |
40 | #define PRCM_AVS_BASE 0x2FC | |
41 | #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) | |
42 | #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) | |
43 | #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) | |
44 | #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) | |
45 | #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) | |
46 | #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) | |
47 | #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) | |
48 | #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) | |
49 | #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) | |
50 | #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) | |
51 | #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) | |
52 | #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) | |
53 | #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) | |
54 | ||
55 | #define PRCM_AVS_VOLTAGE 0 | |
56 | #define PRCM_AVS_VOLTAGE_MASK 0x3f | |
57 | #define PRCM_AVS_ISSLOWSTARTUP 6 | |
58 | #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) | |
59 | #define PRCM_AVS_ISMODEENABLE 7 | |
60 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) | |
61 | ||
62 | #define PRCM_BOOT_STATUS 0xFFF | |
63 | #define PRCM_ROMCODE_A2P 0xFFE | |
64 | #define PRCM_ROMCODE_P2A 0xFFD | |
65 | #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ | |
66 | ||
67 | #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ | |
68 | ||
69 | #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ | |
70 | #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) | |
71 | #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) | |
72 | #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) | |
73 | #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) | |
74 | #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) | |
75 | #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) | |
76 | #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) | |
77 | ||
78 | /* Req Mailboxes */ | |
79 | #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ | |
80 | #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ | |
81 | #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ | |
82 | #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ | |
83 | #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ | |
84 | #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ | |
85 | ||
86 | /* Ack Mailboxes */ | |
87 | #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ | |
88 | #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ | |
89 | #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ | |
90 | #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ | |
91 | #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ | |
92 | #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ | |
93 | ||
94 | /* Mailbox 0 headers */ | |
95 | #define MB0H_POWER_STATE_TRANS 0 | |
96 | #define MB0H_CONFIG_WAKEUPS_EXE 1 | |
97 | #define MB0H_READ_WAKEUP_ACK 3 | |
98 | #define MB0H_CONFIG_WAKEUPS_SLEEP 4 | |
99 | ||
100 | #define MB0H_WAKEUP_EXE 2 | |
101 | #define MB0H_WAKEUP_SLEEP 5 | |
102 | ||
103 | /* Mailbox 0 REQs */ | |
104 | #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) | |
105 | #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) | |
106 | #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) | |
107 | #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) | |
108 | #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) | |
109 | #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) | |
110 | ||
111 | /* Mailbox 0 ACKs */ | |
112 | #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) | |
113 | #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) | |
114 | #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) | |
115 | #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) | |
116 | #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) | |
117 | #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) | |
118 | #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 | |
119 | ||
120 | /* Mailbox 1 headers */ | |
121 | #define MB1H_ARM_APE_OPP 0x0 | |
122 | #define MB1H_RESET_MODEM 0x2 | |
123 | #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 | |
124 | #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 | |
125 | #define MB1H_RELEASE_USB_WAKEUP 0x5 | |
a592c2e2 | 126 | #define MB1H_PLL_ON_OFF 0x6 |
3df57bcf MN |
127 | |
128 | /* Mailbox 1 Requests */ | |
129 | #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) | |
130 | #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) | |
a592c2e2 | 131 | #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) |
6b6fae2b MN |
132 | #define PLL_SOC0_OFF 0x1 |
133 | #define PLL_SOC0_ON 0x2 | |
a592c2e2 MN |
134 | #define PLL_SOC1_OFF 0x4 |
135 | #define PLL_SOC1_ON 0x8 | |
3df57bcf MN |
136 | |
137 | /* Mailbox 1 ACKs */ | |
138 | #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) | |
139 | #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) | |
140 | #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) | |
141 | #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) | |
142 | ||
143 | /* Mailbox 2 headers */ | |
144 | #define MB2H_DPS 0x0 | |
145 | #define MB2H_AUTO_PWR 0x1 | |
146 | ||
147 | /* Mailbox 2 REQs */ | |
148 | #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) | |
149 | #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) | |
150 | #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) | |
151 | #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) | |
152 | #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) | |
153 | #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) | |
154 | #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) | |
155 | #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) | |
156 | #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) | |
157 | #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) | |
158 | ||
159 | /* Mailbox 2 ACKs */ | |
160 | #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) | |
161 | #define HWACC_PWR_ST_OK 0xFE | |
162 | ||
163 | /* Mailbox 3 headers */ | |
164 | #define MB3H_ANC 0x0 | |
165 | #define MB3H_SIDETONE 0x1 | |
166 | #define MB3H_SYSCLK 0xE | |
167 | ||
168 | /* Mailbox 3 Requests */ | |
169 | #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) | |
170 | #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) | |
171 | #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) | |
172 | #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) | |
173 | #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) | |
174 | #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) | |
175 | #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) | |
176 | ||
177 | /* Mailbox 4 headers */ | |
178 | #define MB4H_DDR_INIT 0x0 | |
179 | #define MB4H_MEM_ST 0x1 | |
180 | #define MB4H_HOTDOG 0x12 | |
181 | #define MB4H_HOTMON 0x13 | |
182 | #define MB4H_HOT_PERIOD 0x14 | |
a592c2e2 MN |
183 | #define MB4H_A9WDOG_CONF 0x16 |
184 | #define MB4H_A9WDOG_EN 0x17 | |
185 | #define MB4H_A9WDOG_DIS 0x18 | |
186 | #define MB4H_A9WDOG_LOAD 0x19 | |
187 | #define MB4H_A9WDOG_KICK 0x20 | |
3df57bcf MN |
188 | |
189 | /* Mailbox 4 Requests */ | |
190 | #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) | |
191 | #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) | |
192 | #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) | |
193 | #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) | |
194 | #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) | |
195 | #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) | |
196 | #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) | |
197 | #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) | |
198 | #define HOTMON_CONFIG_LOW BIT(0) | |
199 | #define HOTMON_CONFIG_HIGH BIT(1) | |
a592c2e2 MN |
200 | #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) |
201 | #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) | |
202 | #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) | |
203 | #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) | |
204 | #define A9WDOG_AUTO_OFF_EN BIT(7) | |
205 | #define A9WDOG_AUTO_OFF_DIS 0 | |
206 | #define A9WDOG_ID_MASK 0xf | |
3df57bcf MN |
207 | |
208 | /* Mailbox 5 Requests */ | |
209 | #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) | |
210 | #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) | |
211 | #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) | |
212 | #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) | |
7a4f2609 LW |
213 | #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) |
214 | #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) | |
3df57bcf MN |
215 | #define PRCMU_I2C_STOP_EN BIT(3) |
216 | ||
217 | /* Mailbox 5 ACKs */ | |
218 | #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) | |
219 | #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) | |
220 | #define I2C_WR_OK 0x1 | |
221 | #define I2C_RD_OK 0x2 | |
222 | ||
223 | #define NUM_MB 8 | |
224 | #define MBOX_BIT BIT | |
225 | #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) | |
226 | ||
227 | /* | |
228 | * Wakeups/IRQs | |
229 | */ | |
230 | ||
231 | #define WAKEUP_BIT_RTC BIT(0) | |
232 | #define WAKEUP_BIT_RTT0 BIT(1) | |
233 | #define WAKEUP_BIT_RTT1 BIT(2) | |
234 | #define WAKEUP_BIT_HSI0 BIT(3) | |
235 | #define WAKEUP_BIT_HSI1 BIT(4) | |
236 | #define WAKEUP_BIT_CA_WAKE BIT(5) | |
237 | #define WAKEUP_BIT_USB BIT(6) | |
238 | #define WAKEUP_BIT_ABB BIT(7) | |
239 | #define WAKEUP_BIT_ABB_FIFO BIT(8) | |
240 | #define WAKEUP_BIT_SYSCLK_OK BIT(9) | |
241 | #define WAKEUP_BIT_CA_SLEEP BIT(10) | |
242 | #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) | |
243 | #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) | |
244 | #define WAKEUP_BIT_ANC_OK BIT(13) | |
245 | #define WAKEUP_BIT_SW_ERROR BIT(14) | |
246 | #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) | |
247 | #define WAKEUP_BIT_ARM BIT(17) | |
248 | #define WAKEUP_BIT_HOTMON_LOW BIT(18) | |
249 | #define WAKEUP_BIT_HOTMON_HIGH BIT(19) | |
250 | #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) | |
251 | #define WAKEUP_BIT_GPIO0 BIT(23) | |
252 | #define WAKEUP_BIT_GPIO1 BIT(24) | |
253 | #define WAKEUP_BIT_GPIO2 BIT(25) | |
254 | #define WAKEUP_BIT_GPIO3 BIT(26) | |
255 | #define WAKEUP_BIT_GPIO4 BIT(27) | |
256 | #define WAKEUP_BIT_GPIO5 BIT(28) | |
257 | #define WAKEUP_BIT_GPIO6 BIT(29) | |
258 | #define WAKEUP_BIT_GPIO7 BIT(30) | |
259 | #define WAKEUP_BIT_GPIO8 BIT(31) | |
260 | ||
b58d12fe MN |
261 | static struct { |
262 | bool valid; | |
263 | struct prcmu_fw_version version; | |
264 | } fw_info; | |
265 | ||
f3f1f0a1 LJ |
266 | static struct irq_domain *db8500_irq_domain; |
267 | ||
3df57bcf MN |
268 | /* |
269 | * This vector maps irq numbers to the bits in the bit field used in | |
270 | * communication with the PRCMU firmware. | |
271 | * | |
272 | * The reason for having this is to keep the irq numbers contiguous even though | |
273 | * the bits in the bit field are not. (The bits also have a tendency to move | |
274 | * around, to further complicate matters.) | |
275 | */ | |
276 | #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) | |
277 | #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) | |
278 | static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { | |
279 | IRQ_ENTRY(RTC), | |
280 | IRQ_ENTRY(RTT0), | |
281 | IRQ_ENTRY(RTT1), | |
282 | IRQ_ENTRY(HSI0), | |
283 | IRQ_ENTRY(HSI1), | |
284 | IRQ_ENTRY(CA_WAKE), | |
285 | IRQ_ENTRY(USB), | |
286 | IRQ_ENTRY(ABB), | |
287 | IRQ_ENTRY(ABB_FIFO), | |
288 | IRQ_ENTRY(CA_SLEEP), | |
289 | IRQ_ENTRY(ARM), | |
290 | IRQ_ENTRY(HOTMON_LOW), | |
291 | IRQ_ENTRY(HOTMON_HIGH), | |
292 | IRQ_ENTRY(MODEM_SW_RESET_REQ), | |
293 | IRQ_ENTRY(GPIO0), | |
294 | IRQ_ENTRY(GPIO1), | |
295 | IRQ_ENTRY(GPIO2), | |
296 | IRQ_ENTRY(GPIO3), | |
297 | IRQ_ENTRY(GPIO4), | |
298 | IRQ_ENTRY(GPIO5), | |
299 | IRQ_ENTRY(GPIO6), | |
300 | IRQ_ENTRY(GPIO7), | |
301 | IRQ_ENTRY(GPIO8) | |
302 | }; | |
303 | ||
304 | #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) | |
305 | #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) | |
306 | static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { | |
307 | WAKEUP_ENTRY(RTC), | |
308 | WAKEUP_ENTRY(RTT0), | |
309 | WAKEUP_ENTRY(RTT1), | |
310 | WAKEUP_ENTRY(HSI0), | |
311 | WAKEUP_ENTRY(HSI1), | |
312 | WAKEUP_ENTRY(USB), | |
313 | WAKEUP_ENTRY(ABB), | |
314 | WAKEUP_ENTRY(ABB_FIFO), | |
315 | WAKEUP_ENTRY(ARM) | |
316 | }; | |
317 | ||
318 | /* | |
319 | * mb0_transfer - state needed for mailbox 0 communication. | |
320 | * @lock: The transaction lock. | |
321 | * @dbb_events_lock: A lock used to handle concurrent access to (parts of) | |
322 | * the request data. | |
323 | * @mask_work: Work structure used for (un)masking wakeup interrupts. | |
324 | * @req: Request data that need to persist between requests. | |
325 | */ | |
326 | static struct { | |
327 | spinlock_t lock; | |
328 | spinlock_t dbb_irqs_lock; | |
329 | struct work_struct mask_work; | |
330 | struct mutex ac_wake_lock; | |
331 | struct completion ac_wake_work; | |
332 | struct { | |
333 | u32 dbb_irqs; | |
334 | u32 dbb_wakeups; | |
335 | u32 abb_events; | |
336 | } req; | |
337 | } mb0_transfer; | |
338 | ||
339 | /* | |
340 | * mb1_transfer - state needed for mailbox 1 communication. | |
341 | * @lock: The transaction lock. | |
342 | * @work: The transaction completion structure. | |
4d64d2e3 | 343 | * @ape_opp: The current APE OPP. |
3df57bcf MN |
344 | * @ack: Reply ("acknowledge") data. |
345 | */ | |
346 | static struct { | |
347 | struct mutex lock; | |
348 | struct completion work; | |
4d64d2e3 | 349 | u8 ape_opp; |
3df57bcf MN |
350 | struct { |
351 | u8 header; | |
352 | u8 arm_opp; | |
353 | u8 ape_opp; | |
354 | u8 ape_voltage_status; | |
355 | } ack; | |
356 | } mb1_transfer; | |
357 | ||
358 | /* | |
359 | * mb2_transfer - state needed for mailbox 2 communication. | |
360 | * @lock: The transaction lock. | |
361 | * @work: The transaction completion structure. | |
362 | * @auto_pm_lock: The autonomous power management configuration lock. | |
363 | * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. | |
364 | * @req: Request data that need to persist between requests. | |
365 | * @ack: Reply ("acknowledge") data. | |
366 | */ | |
367 | static struct { | |
368 | struct mutex lock; | |
369 | struct completion work; | |
370 | spinlock_t auto_pm_lock; | |
371 | bool auto_pm_enabled; | |
372 | struct { | |
373 | u8 status; | |
374 | } ack; | |
375 | } mb2_transfer; | |
376 | ||
377 | /* | |
378 | * mb3_transfer - state needed for mailbox 3 communication. | |
379 | * @lock: The request lock. | |
380 | * @sysclk_lock: A lock used to handle concurrent sysclk requests. | |
381 | * @sysclk_work: Work structure used for sysclk requests. | |
382 | */ | |
383 | static struct { | |
384 | spinlock_t lock; | |
385 | struct mutex sysclk_lock; | |
386 | struct completion sysclk_work; | |
387 | } mb3_transfer; | |
388 | ||
389 | /* | |
390 | * mb4_transfer - state needed for mailbox 4 communication. | |
391 | * @lock: The transaction lock. | |
392 | * @work: The transaction completion structure. | |
393 | */ | |
394 | static struct { | |
395 | struct mutex lock; | |
396 | struct completion work; | |
397 | } mb4_transfer; | |
398 | ||
399 | /* | |
400 | * mb5_transfer - state needed for mailbox 5 communication. | |
401 | * @lock: The transaction lock. | |
402 | * @work: The transaction completion structure. | |
403 | * @ack: Reply ("acknowledge") data. | |
404 | */ | |
405 | static struct { | |
406 | struct mutex lock; | |
407 | struct completion work; | |
408 | struct { | |
409 | u8 status; | |
410 | u8 value; | |
411 | } ack; | |
412 | } mb5_transfer; | |
413 | ||
414 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); | |
415 | ||
416 | /* Spinlocks */ | |
b4a6dbd5 | 417 | static DEFINE_SPINLOCK(prcmu_lock); |
3df57bcf | 418 | static DEFINE_SPINLOCK(clkout_lock); |
3df57bcf MN |
419 | |
420 | /* Global var to runtime determine TCDM base for v2 or v1 */ | |
421 | static __iomem void *tcdm_base; | |
b047d981 | 422 | static __iomem void *prcmu_base; |
3df57bcf MN |
423 | |
424 | struct clk_mgt { | |
b047d981 | 425 | u32 offset; |
3df57bcf | 426 | u32 pllsw; |
6b6fae2b MN |
427 | int branch; |
428 | bool clk38div; | |
429 | }; | |
430 | ||
431 | enum { | |
432 | PLL_RAW, | |
433 | PLL_FIX, | |
434 | PLL_DIV | |
3df57bcf MN |
435 | }; |
436 | ||
437 | static DEFINE_SPINLOCK(clk_mgt_lock); | |
438 | ||
6b6fae2b MN |
439 | #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ |
440 | { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} | |
3df57bcf | 441 | struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { |
6b6fae2b MN |
442 | CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), |
443 | CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), | |
444 | CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), | |
445 | CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), | |
446 | CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), | |
447 | CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), | |
448 | CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), | |
449 | CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), | |
450 | CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), | |
451 | CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), | |
452 | CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), | |
453 | CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), | |
454 | CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), | |
455 | CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), | |
456 | CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), | |
457 | CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), | |
458 | CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), | |
459 | CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), | |
460 | CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), | |
461 | CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), | |
462 | CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), | |
463 | CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), | |
464 | CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), | |
465 | CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), | |
466 | CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), | |
467 | CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), | |
468 | CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), | |
469 | CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), | |
470 | CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), | |
471 | }; | |
472 | ||
473 | struct dsiclk { | |
474 | u32 divsel_mask; | |
475 | u32 divsel_shift; | |
476 | u32 divsel; | |
477 | }; | |
478 | ||
479 | static struct dsiclk dsiclk[2] = { | |
480 | { | |
481 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, | |
482 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, | |
483 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, | |
484 | }, | |
485 | { | |
486 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, | |
487 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, | |
488 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, | |
489 | } | |
490 | }; | |
491 | ||
492 | struct dsiescclk { | |
493 | u32 en; | |
494 | u32 div_mask; | |
495 | u32 div_shift; | |
496 | }; | |
497 | ||
498 | static struct dsiescclk dsiescclk[3] = { | |
499 | { | |
500 | .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, | |
501 | .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, | |
502 | .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, | |
503 | }, | |
504 | { | |
505 | .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, | |
506 | .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, | |
507 | .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, | |
508 | }, | |
509 | { | |
510 | .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, | |
511 | .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, | |
512 | .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, | |
513 | } | |
3df57bcf MN |
514 | }; |
515 | ||
20aee5b6 | 516 | |
3df57bcf MN |
517 | /* |
518 | * Used by MCDE to setup all necessary PRCMU registers | |
519 | */ | |
520 | #define PRCMU_RESET_DSIPLL 0x00004000 | |
521 | #define PRCMU_UNCLAMP_DSIPLL 0x00400800 | |
522 | ||
523 | #define PRCMU_CLK_PLL_DIV_SHIFT 0 | |
524 | #define PRCMU_CLK_PLL_SW_SHIFT 5 | |
525 | #define PRCMU_CLK_38 (1 << 9) | |
526 | #define PRCMU_CLK_38_SRC (1 << 10) | |
527 | #define PRCMU_CLK_38_DIV (1 << 11) | |
528 | ||
529 | /* PLLDIV=12, PLLSW=4 (PLLDDR) */ | |
530 | #define PRCMU_DSI_CLOCK_SETTING 0x0000008C | |
531 | ||
3df57bcf MN |
532 | /* DPI 50000000 Hz */ |
533 | #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ | |
534 | (16 << PRCMU_CLK_PLL_DIV_SHIFT)) | |
535 | #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 | |
536 | ||
537 | /* D=101, N=1, R=4, SELDIV2=0 */ | |
538 | #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 | |
539 | ||
3df57bcf MN |
540 | #define PRCMU_ENABLE_PLLDSI 0x00000001 |
541 | #define PRCMU_DISABLE_PLLDSI 0x00000000 | |
542 | #define PRCMU_RELEASE_RESET_DSS 0x0000400C | |
543 | #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 | |
544 | /* ESC clk, div0=1, div1=1, div2=3 */ | |
545 | #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 | |
546 | #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 | |
547 | #define PRCMU_DSI_RESET_SW 0x00000007 | |
548 | ||
549 | #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 | |
550 | ||
73180f85 | 551 | int db8500_prcmu_enable_dsipll(void) |
3df57bcf MN |
552 | { |
553 | int i; | |
3df57bcf MN |
554 | |
555 | /* Clear DSIPLL_RESETN */ | |
c553b3ca | 556 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); |
3df57bcf | 557 | /* Unclamp DSIPLL in/out */ |
c553b3ca | 558 | writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); |
3df57bcf | 559 | |
3df57bcf | 560 | /* Set DSI PLL FREQ */ |
c72fe851 | 561 | writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); |
c553b3ca | 562 | writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); |
3df57bcf | 563 | /* Enable Escape clocks */ |
c553b3ca | 564 | writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
565 | |
566 | /* Start DSI PLL */ | |
c553b3ca | 567 | writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 568 | /* Reset DSI PLL */ |
c553b3ca | 569 | writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); |
3df57bcf | 570 | for (i = 0; i < 10; i++) { |
c553b3ca | 571 | if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) |
3df57bcf MN |
572 | == PRCMU_PLLDSI_LOCKP_LOCKED) |
573 | break; | |
574 | udelay(100); | |
575 | } | |
576 | /* Set DSIPLL_RESETN */ | |
c553b3ca | 577 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); |
3df57bcf MN |
578 | return 0; |
579 | } | |
580 | ||
73180f85 | 581 | int db8500_prcmu_disable_dsipll(void) |
3df57bcf MN |
582 | { |
583 | /* Disable dsi pll */ | |
c553b3ca | 584 | writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 585 | /* Disable escapeclock */ |
c553b3ca | 586 | writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
587 | return 0; |
588 | } | |
589 | ||
73180f85 | 590 | int db8500_prcmu_set_display_clocks(void) |
3df57bcf MN |
591 | { |
592 | unsigned long flags; | |
3df57bcf MN |
593 | |
594 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
595 | ||
596 | /* Grab the HW semaphore. */ | |
c553b3ca | 597 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
598 | cpu_relax(); |
599 | ||
b047d981 LW |
600 | writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT); |
601 | writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT); | |
602 | writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT); | |
3df57bcf MN |
603 | |
604 | /* Release the HW semaphore. */ | |
c553b3ca | 605 | writel(0, PRCM_SEM); |
3df57bcf MN |
606 | |
607 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
b4a6dbd5 MN |
612 | u32 db8500_prcmu_read(unsigned int reg) |
613 | { | |
b047d981 | 614 | return readl(prcmu_base + reg); |
b4a6dbd5 MN |
615 | } |
616 | ||
617 | void db8500_prcmu_write(unsigned int reg, u32 value) | |
3df57bcf | 618 | { |
3df57bcf MN |
619 | unsigned long flags; |
620 | ||
b4a6dbd5 | 621 | spin_lock_irqsave(&prcmu_lock, flags); |
b047d981 | 622 | writel(value, (prcmu_base + reg)); |
b4a6dbd5 | 623 | spin_unlock_irqrestore(&prcmu_lock, flags); |
3df57bcf MN |
624 | } |
625 | ||
b4a6dbd5 | 626 | void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) |
3df57bcf | 627 | { |
b4a6dbd5 | 628 | u32 val; |
3df57bcf MN |
629 | unsigned long flags; |
630 | ||
b4a6dbd5 | 631 | spin_lock_irqsave(&prcmu_lock, flags); |
b047d981 | 632 | val = readl(prcmu_base + reg); |
b4a6dbd5 | 633 | val = ((val & ~mask) | (value & mask)); |
b047d981 | 634 | writel(val, (prcmu_base + reg)); |
b4a6dbd5 | 635 | spin_unlock_irqrestore(&prcmu_lock, flags); |
3df57bcf MN |
636 | } |
637 | ||
b58d12fe MN |
638 | struct prcmu_fw_version *prcmu_get_fw_version(void) |
639 | { | |
640 | return fw_info.valid ? &fw_info.version : NULL; | |
641 | } | |
642 | ||
3df57bcf MN |
643 | bool prcmu_has_arm_maxopp(void) |
644 | { | |
645 | return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & | |
646 | PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; | |
647 | } | |
648 | ||
3df57bcf MN |
649 | /** |
650 | * prcmu_get_boot_status - PRCMU boot status checking | |
651 | * Returns: the current PRCMU boot status | |
652 | */ | |
653 | int prcmu_get_boot_status(void) | |
654 | { | |
655 | return readb(tcdm_base + PRCM_BOOT_STATUS); | |
656 | } | |
657 | ||
658 | /** | |
659 | * prcmu_set_rc_a2p - This function is used to run few power state sequences | |
660 | * @val: Value to be set, i.e. transition requested | |
661 | * Returns: 0 on success, -EINVAL on invalid argument | |
662 | * | |
663 | * This function is used to run the following power state sequences - | |
664 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
665 | */ | |
666 | int prcmu_set_rc_a2p(enum romcode_write val) | |
667 | { | |
668 | if (val < RDY_2_DS || val > RDY_2_XP70_RST) | |
669 | return -EINVAL; | |
670 | writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); | |
671 | return 0; | |
672 | } | |
673 | ||
674 | /** | |
675 | * prcmu_get_rc_p2a - This function is used to get power state sequences | |
676 | * Returns: the power transition that has last happened | |
677 | * | |
678 | * This function can return the following transitions- | |
679 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
680 | */ | |
681 | enum romcode_read prcmu_get_rc_p2a(void) | |
682 | { | |
683 | return readb(tcdm_base + PRCM_ROMCODE_P2A); | |
684 | } | |
685 | ||
686 | /** | |
687 | * prcmu_get_current_mode - Return the current XP70 power mode | |
688 | * Returns: Returns the current AP(ARM) power mode: init, | |
689 | * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset | |
690 | */ | |
691 | enum ap_pwrst prcmu_get_xp70_current_state(void) | |
692 | { | |
693 | return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); | |
694 | } | |
695 | ||
696 | /** | |
697 | * prcmu_config_clkout - Configure one of the programmable clock outputs. | |
698 | * @clkout: The CLKOUT number (0 or 1). | |
699 | * @source: The clock to be used (one of the PRCMU_CLKSRC_*). | |
700 | * @div: The divider to be applied. | |
701 | * | |
702 | * Configures one of the programmable clock outputs (CLKOUTs). | |
703 | * @div should be in the range [1,63] to request a configuration, or 0 to | |
704 | * inform that the configuration is no longer requested. | |
705 | */ | |
706 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div) | |
707 | { | |
708 | static int requests[2]; | |
709 | int r = 0; | |
710 | unsigned long flags; | |
711 | u32 val; | |
712 | u32 bits; | |
713 | u32 mask; | |
714 | u32 div_mask; | |
715 | ||
716 | BUG_ON(clkout > 1); | |
717 | BUG_ON(div > 63); | |
718 | BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); | |
719 | ||
720 | if (!div && !requests[clkout]) | |
721 | return -EINVAL; | |
722 | ||
723 | switch (clkout) { | |
724 | case 0: | |
725 | div_mask = PRCM_CLKOCR_CLKODIV0_MASK; | |
726 | mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); | |
727 | bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | | |
728 | (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); | |
729 | break; | |
730 | case 1: | |
731 | div_mask = PRCM_CLKOCR_CLKODIV1_MASK; | |
732 | mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | | |
733 | PRCM_CLKOCR_CLK1TYPE); | |
734 | bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | | |
735 | (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); | |
736 | break; | |
737 | } | |
738 | bits &= mask; | |
739 | ||
740 | spin_lock_irqsave(&clkout_lock, flags); | |
741 | ||
c553b3ca | 742 | val = readl(PRCM_CLKOCR); |
3df57bcf MN |
743 | if (val & div_mask) { |
744 | if (div) { | |
745 | if ((val & mask) != bits) { | |
746 | r = -EBUSY; | |
747 | goto unlock_and_return; | |
748 | } | |
749 | } else { | |
750 | if ((val & mask & ~div_mask) != bits) { | |
751 | r = -EINVAL; | |
752 | goto unlock_and_return; | |
753 | } | |
754 | } | |
755 | } | |
c553b3ca | 756 | writel((bits | (val & ~mask)), PRCM_CLKOCR); |
3df57bcf MN |
757 | requests[clkout] += (div ? 1 : -1); |
758 | ||
759 | unlock_and_return: | |
760 | spin_unlock_irqrestore(&clkout_lock, flags); | |
761 | ||
762 | return r; | |
763 | } | |
764 | ||
73180f85 | 765 | int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) |
3df57bcf MN |
766 | { |
767 | unsigned long flags; | |
768 | ||
769 | BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); | |
770 | ||
771 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
772 | ||
c553b3ca | 773 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
774 | cpu_relax(); |
775 | ||
776 | writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
777 | writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); | |
778 | writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); | |
779 | writeb((keep_ulp_clk ? 1 : 0), | |
780 | (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); | |
781 | writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); | |
c553b3ca | 782 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
783 | |
784 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
4d64d2e3 MN |
789 | u8 db8500_prcmu_get_power_state_result(void) |
790 | { | |
791 | return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); | |
792 | } | |
793 | ||
3df57bcf MN |
794 | /* This function should only be called while mb0_transfer.lock is held. */ |
795 | static void config_wakeups(void) | |
796 | { | |
797 | const u8 header[2] = { | |
798 | MB0H_CONFIG_WAKEUPS_EXE, | |
799 | MB0H_CONFIG_WAKEUPS_SLEEP | |
800 | }; | |
801 | static u32 last_dbb_events; | |
802 | static u32 last_abb_events; | |
803 | u32 dbb_events; | |
804 | u32 abb_events; | |
805 | unsigned int i; | |
806 | ||
807 | dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; | |
808 | dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); | |
809 | ||
810 | abb_events = mb0_transfer.req.abb_events; | |
811 | ||
812 | if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) | |
813 | return; | |
814 | ||
815 | for (i = 0; i < 2; i++) { | |
c553b3ca | 816 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
817 | cpu_relax(); |
818 | writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); | |
819 | writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); | |
820 | writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 821 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
822 | } |
823 | last_dbb_events = dbb_events; | |
824 | last_abb_events = abb_events; | |
825 | } | |
826 | ||
73180f85 | 827 | void db8500_prcmu_enable_wakeups(u32 wakeups) |
3df57bcf MN |
828 | { |
829 | unsigned long flags; | |
830 | u32 bits; | |
831 | int i; | |
832 | ||
833 | BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); | |
834 | ||
835 | for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { | |
836 | if (wakeups & BIT(i)) | |
837 | bits |= prcmu_wakeup_bit[i]; | |
838 | } | |
839 | ||
840 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
841 | ||
842 | mb0_transfer.req.dbb_wakeups = bits; | |
843 | config_wakeups(); | |
844 | ||
845 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
846 | } | |
847 | ||
73180f85 | 848 | void db8500_prcmu_config_abb_event_readout(u32 abb_events) |
3df57bcf MN |
849 | { |
850 | unsigned long flags; | |
851 | ||
852 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
853 | ||
854 | mb0_transfer.req.abb_events = abb_events; | |
855 | config_wakeups(); | |
856 | ||
857 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
858 | } | |
859 | ||
73180f85 | 860 | void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) |
3df57bcf MN |
861 | { |
862 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
863 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); | |
864 | else | |
865 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); | |
866 | } | |
867 | ||
868 | /** | |
73180f85 | 869 | * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP |
3df57bcf MN |
870 | * @opp: The new ARM operating point to which transition is to be made |
871 | * Returns: 0 on success, non-zero on failure | |
872 | * | |
873 | * This function sets the the operating point of the ARM. | |
874 | */ | |
73180f85 | 875 | int db8500_prcmu_set_arm_opp(u8 opp) |
3df57bcf MN |
876 | { |
877 | int r; | |
878 | ||
879 | if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) | |
880 | return -EINVAL; | |
881 | ||
882 | r = 0; | |
883 | ||
884 | mutex_lock(&mb1_transfer.lock); | |
885 | ||
c553b3ca | 886 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
887 | cpu_relax(); |
888 | ||
889 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
890 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
891 | writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
892 | ||
c553b3ca | 893 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
894 | wait_for_completion(&mb1_transfer.work); |
895 | ||
896 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
897 | (mb1_transfer.ack.arm_opp != opp)) | |
898 | r = -EIO; | |
899 | ||
900 | mutex_unlock(&mb1_transfer.lock); | |
901 | ||
902 | return r; | |
903 | } | |
904 | ||
905 | /** | |
73180f85 | 906 | * db8500_prcmu_get_arm_opp - get the current ARM OPP |
3df57bcf MN |
907 | * |
908 | * Returns: the current ARM OPP | |
909 | */ | |
73180f85 | 910 | int db8500_prcmu_get_arm_opp(void) |
3df57bcf MN |
911 | { |
912 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
913 | } | |
914 | ||
915 | /** | |
0508901c | 916 | * db8500_prcmu_get_ddr_opp - get the current DDR OPP |
3df57bcf MN |
917 | * |
918 | * Returns: the current DDR OPP | |
919 | */ | |
0508901c | 920 | int db8500_prcmu_get_ddr_opp(void) |
3df57bcf | 921 | { |
c553b3ca | 922 | return readb(PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
923 | } |
924 | ||
925 | /** | |
0508901c | 926 | * db8500_set_ddr_opp - set the appropriate DDR OPP |
3df57bcf MN |
927 | * @opp: The new DDR operating point to which transition is to be made |
928 | * Returns: 0 on success, non-zero on failure | |
929 | * | |
930 | * This function sets the operating point of the DDR. | |
931 | */ | |
7a4f2609 | 932 | static bool enable_set_ddr_opp; |
0508901c | 933 | int db8500_prcmu_set_ddr_opp(u8 opp) |
3df57bcf MN |
934 | { |
935 | if (opp < DDR_100_OPP || opp > DDR_25_OPP) | |
936 | return -EINVAL; | |
937 | /* Changing the DDR OPP can hang the hardware pre-v21 */ | |
7a4f2609 | 938 | if (enable_set_ddr_opp) |
c553b3ca | 939 | writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
940 | |
941 | return 0; | |
942 | } | |
6b6fae2b | 943 | |
4d64d2e3 MN |
944 | /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ |
945 | static void request_even_slower_clocks(bool enable) | |
946 | { | |
b047d981 | 947 | u32 clock_reg[] = { |
4d64d2e3 MN |
948 | PRCM_ACLK_MGT, |
949 | PRCM_DMACLK_MGT | |
950 | }; | |
951 | unsigned long flags; | |
952 | unsigned int i; | |
953 | ||
954 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
955 | ||
956 | /* Grab the HW semaphore. */ | |
957 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) | |
958 | cpu_relax(); | |
959 | ||
960 | for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { | |
961 | u32 val; | |
962 | u32 div; | |
963 | ||
b047d981 | 964 | val = readl(prcmu_base + clock_reg[i]); |
4d64d2e3 MN |
965 | div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); |
966 | if (enable) { | |
967 | if ((div <= 1) || (div > 15)) { | |
968 | pr_err("prcmu: Bad clock divider %d in %s\n", | |
969 | div, __func__); | |
970 | goto unlock_and_return; | |
971 | } | |
972 | div <<= 1; | |
973 | } else { | |
974 | if (div <= 2) | |
975 | goto unlock_and_return; | |
976 | div >>= 1; | |
977 | } | |
978 | val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | | |
979 | (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); | |
b047d981 | 980 | writel(val, prcmu_base + clock_reg[i]); |
4d64d2e3 MN |
981 | } |
982 | ||
983 | unlock_and_return: | |
984 | /* Release the HW semaphore. */ | |
985 | writel(0, PRCM_SEM); | |
986 | ||
987 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
988 | } | |
989 | ||
3df57bcf | 990 | /** |
0508901c | 991 | * db8500_set_ape_opp - set the appropriate APE OPP |
3df57bcf MN |
992 | * @opp: The new APE operating point to which transition is to be made |
993 | * Returns: 0 on success, non-zero on failure | |
994 | * | |
995 | * This function sets the operating point of the APE. | |
996 | */ | |
0508901c | 997 | int db8500_prcmu_set_ape_opp(u8 opp) |
3df57bcf MN |
998 | { |
999 | int r = 0; | |
1000 | ||
4d64d2e3 MN |
1001 | if (opp == mb1_transfer.ape_opp) |
1002 | return 0; | |
1003 | ||
3df57bcf MN |
1004 | mutex_lock(&mb1_transfer.lock); |
1005 | ||
4d64d2e3 MN |
1006 | if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) |
1007 | request_even_slower_clocks(false); | |
1008 | ||
1009 | if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) | |
1010 | goto skip_message; | |
1011 | ||
c553b3ca | 1012 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1013 | cpu_relax(); |
1014 | ||
1015 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1016 | writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
4d64d2e3 MN |
1017 | writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), |
1018 | (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
3df57bcf | 1019 | |
c553b3ca | 1020 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1021 | wait_for_completion(&mb1_transfer.work); |
1022 | ||
1023 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
1024 | (mb1_transfer.ack.ape_opp != opp)) | |
1025 | r = -EIO; | |
1026 | ||
4d64d2e3 MN |
1027 | skip_message: |
1028 | if ((!r && (opp == APE_50_PARTLY_25_OPP)) || | |
1029 | (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) | |
1030 | request_even_slower_clocks(true); | |
1031 | if (!r) | |
1032 | mb1_transfer.ape_opp = opp; | |
1033 | ||
3df57bcf MN |
1034 | mutex_unlock(&mb1_transfer.lock); |
1035 | ||
1036 | return r; | |
1037 | } | |
1038 | ||
1039 | /** | |
0508901c | 1040 | * db8500_prcmu_get_ape_opp - get the current APE OPP |
3df57bcf MN |
1041 | * |
1042 | * Returns: the current APE OPP | |
1043 | */ | |
0508901c | 1044 | int db8500_prcmu_get_ape_opp(void) |
3df57bcf MN |
1045 | { |
1046 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); | |
1047 | } | |
1048 | ||
1049 | /** | |
686f871b | 1050 | * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage |
3df57bcf MN |
1051 | * @enable: true to request the higher voltage, false to drop a request. |
1052 | * | |
1053 | * Calls to this function to enable and disable requests must be balanced. | |
1054 | */ | |
686f871b | 1055 | int db8500_prcmu_request_ape_opp_100_voltage(bool enable) |
3df57bcf MN |
1056 | { |
1057 | int r = 0; | |
1058 | u8 header; | |
1059 | static unsigned int requests; | |
1060 | ||
1061 | mutex_lock(&mb1_transfer.lock); | |
1062 | ||
1063 | if (enable) { | |
1064 | if (0 != requests++) | |
1065 | goto unlock_and_return; | |
1066 | header = MB1H_REQUEST_APE_OPP_100_VOLT; | |
1067 | } else { | |
1068 | if (requests == 0) { | |
1069 | r = -EIO; | |
1070 | goto unlock_and_return; | |
1071 | } else if (1 != requests--) { | |
1072 | goto unlock_and_return; | |
1073 | } | |
1074 | header = MB1H_RELEASE_APE_OPP_100_VOLT; | |
1075 | } | |
1076 | ||
c553b3ca | 1077 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1078 | cpu_relax(); |
1079 | ||
1080 | writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1081 | ||
c553b3ca | 1082 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1083 | wait_for_completion(&mb1_transfer.work); |
1084 | ||
1085 | if ((mb1_transfer.ack.header != header) || | |
1086 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1087 | r = -EIO; | |
1088 | ||
1089 | unlock_and_return: | |
1090 | mutex_unlock(&mb1_transfer.lock); | |
1091 | ||
1092 | return r; | |
1093 | } | |
1094 | ||
1095 | /** | |
1096 | * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup | |
1097 | * | |
1098 | * This function releases the power state requirements of a USB wakeup. | |
1099 | */ | |
1100 | int prcmu_release_usb_wakeup_state(void) | |
1101 | { | |
1102 | int r = 0; | |
1103 | ||
1104 | mutex_lock(&mb1_transfer.lock); | |
1105 | ||
c553b3ca | 1106 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1107 | cpu_relax(); |
1108 | ||
1109 | writeb(MB1H_RELEASE_USB_WAKEUP, | |
1110 | (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1111 | ||
c553b3ca | 1112 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1113 | wait_for_completion(&mb1_transfer.work); |
1114 | ||
1115 | if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || | |
1116 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1117 | r = -EIO; | |
1118 | ||
1119 | mutex_unlock(&mb1_transfer.lock); | |
1120 | ||
1121 | return r; | |
1122 | } | |
1123 | ||
0837bb72 MN |
1124 | static int request_pll(u8 clock, bool enable) |
1125 | { | |
1126 | int r = 0; | |
1127 | ||
6b6fae2b MN |
1128 | if (clock == PRCMU_PLLSOC0) |
1129 | clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); | |
1130 | else if (clock == PRCMU_PLLSOC1) | |
0837bb72 MN |
1131 | clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); |
1132 | else | |
1133 | return -EINVAL; | |
1134 | ||
1135 | mutex_lock(&mb1_transfer.lock); | |
1136 | ||
1137 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) | |
1138 | cpu_relax(); | |
1139 | ||
1140 | writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1141 | writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); | |
1142 | ||
1143 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); | |
1144 | wait_for_completion(&mb1_transfer.work); | |
1145 | ||
1146 | if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) | |
1147 | r = -EIO; | |
1148 | ||
1149 | mutex_unlock(&mb1_transfer.lock); | |
1150 | ||
1151 | return r; | |
1152 | } | |
1153 | ||
3df57bcf | 1154 | /** |
73180f85 | 1155 | * db8500_prcmu_set_epod - set the state of a EPOD (power domain) |
3df57bcf MN |
1156 | * @epod_id: The EPOD to set |
1157 | * @epod_state: The new EPOD state | |
1158 | * | |
1159 | * This function sets the state of a EPOD (power domain). It may not be called | |
1160 | * from interrupt context. | |
1161 | */ | |
73180f85 | 1162 | int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) |
3df57bcf MN |
1163 | { |
1164 | int r = 0; | |
1165 | bool ram_retention = false; | |
1166 | int i; | |
1167 | ||
1168 | /* check argument */ | |
1169 | BUG_ON(epod_id >= NUM_EPOD_ID); | |
1170 | ||
1171 | /* set flag if retention is possible */ | |
1172 | switch (epod_id) { | |
1173 | case EPOD_ID_SVAMMDSP: | |
1174 | case EPOD_ID_SIAMMDSP: | |
1175 | case EPOD_ID_ESRAM12: | |
1176 | case EPOD_ID_ESRAM34: | |
1177 | ram_retention = true; | |
1178 | break; | |
1179 | } | |
1180 | ||
1181 | /* check argument */ | |
1182 | BUG_ON(epod_state > EPOD_STATE_ON); | |
1183 | BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); | |
1184 | ||
1185 | /* get lock */ | |
1186 | mutex_lock(&mb2_transfer.lock); | |
1187 | ||
1188 | /* wait for mailbox */ | |
c553b3ca | 1189 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) |
3df57bcf MN |
1190 | cpu_relax(); |
1191 | ||
1192 | /* fill in mailbox */ | |
1193 | for (i = 0; i < NUM_EPOD_ID; i++) | |
1194 | writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); | |
1195 | writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); | |
1196 | ||
1197 | writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); | |
1198 | ||
c553b3ca | 1199 | writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1200 | |
1201 | /* | |
1202 | * The current firmware version does not handle errors correctly, | |
1203 | * and we cannot recover if there is an error. | |
1204 | * This is expected to change when the firmware is updated. | |
1205 | */ | |
1206 | if (!wait_for_completion_timeout(&mb2_transfer.work, | |
1207 | msecs_to_jiffies(20000))) { | |
1208 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1209 | __func__); | |
1210 | r = -EIO; | |
1211 | goto unlock_and_return; | |
1212 | } | |
1213 | ||
1214 | if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) | |
1215 | r = -EIO; | |
1216 | ||
1217 | unlock_and_return: | |
1218 | mutex_unlock(&mb2_transfer.lock); | |
1219 | return r; | |
1220 | } | |
1221 | ||
1222 | /** | |
1223 | * prcmu_configure_auto_pm - Configure autonomous power management. | |
1224 | * @sleep: Configuration for ApSleep. | |
1225 | * @idle: Configuration for ApIdle. | |
1226 | */ | |
1227 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, | |
1228 | struct prcmu_auto_pm_config *idle) | |
1229 | { | |
1230 | u32 sleep_cfg; | |
1231 | u32 idle_cfg; | |
1232 | unsigned long flags; | |
e3726fcf | 1233 | |
3df57bcf | 1234 | BUG_ON((sleep == NULL) || (idle == NULL)); |
650c2a21 | 1235 | |
3df57bcf MN |
1236 | sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); |
1237 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); | |
1238 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); | |
1239 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); | |
1240 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); | |
1241 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); | |
e3726fcf | 1242 | |
3df57bcf MN |
1243 | idle_cfg = (idle->sva_auto_pm_enable & 0xF); |
1244 | idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); | |
1245 | idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); | |
1246 | idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); | |
1247 | idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); | |
1248 | idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); | |
e3726fcf | 1249 | |
3df57bcf | 1250 | spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); |
e0befb23 | 1251 | |
3df57bcf MN |
1252 | /* |
1253 | * The autonomous power management configuration is done through | |
1254 | * fields in mailbox 2, but these fields are only used as shared | |
1255 | * variables - i.e. there is no need to send a message. | |
1256 | */ | |
1257 | writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); | |
1258 | writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); | |
e0befb23 | 1259 | |
3df57bcf MN |
1260 | mb2_transfer.auto_pm_enabled = |
1261 | ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1262 | (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1263 | (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1264 | (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); | |
e0befb23 | 1265 | |
3df57bcf MN |
1266 | spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); |
1267 | } | |
1268 | EXPORT_SYMBOL(prcmu_configure_auto_pm); | |
e3726fcf | 1269 | |
3df57bcf MN |
1270 | bool prcmu_is_auto_pm_enabled(void) |
1271 | { | |
1272 | return mb2_transfer.auto_pm_enabled; | |
1273 | } | |
e0befb23 | 1274 | |
3df57bcf MN |
1275 | static int request_sysclk(bool enable) |
1276 | { | |
1277 | int r; | |
1278 | unsigned long flags; | |
e3726fcf | 1279 | |
3df57bcf | 1280 | r = 0; |
e3726fcf | 1281 | |
3df57bcf | 1282 | mutex_lock(&mb3_transfer.sysclk_lock); |
e0befb23 | 1283 | |
3df57bcf | 1284 | spin_lock_irqsave(&mb3_transfer.lock, flags); |
e0befb23 | 1285 | |
c553b3ca | 1286 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) |
3df57bcf | 1287 | cpu_relax(); |
e0befb23 | 1288 | |
3df57bcf | 1289 | writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); |
e3726fcf | 1290 | |
3df57bcf | 1291 | writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); |
c553b3ca | 1292 | writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); |
e3726fcf | 1293 | |
3df57bcf MN |
1294 | spin_unlock_irqrestore(&mb3_transfer.lock, flags); |
1295 | ||
1296 | /* | |
1297 | * The firmware only sends an ACK if we want to enable the | |
1298 | * SysClk, and it succeeds. | |
1299 | */ | |
1300 | if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, | |
1301 | msecs_to_jiffies(20000))) { | |
1302 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1303 | __func__); | |
1304 | r = -EIO; | |
1305 | } | |
1306 | ||
1307 | mutex_unlock(&mb3_transfer.sysclk_lock); | |
1308 | ||
1309 | return r; | |
1310 | } | |
1311 | ||
1312 | static int request_timclk(bool enable) | |
1313 | { | |
1314 | u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); | |
1315 | ||
1316 | if (!enable) | |
1317 | val |= PRCM_TCR_STOP_TIMERS; | |
c553b3ca | 1318 | writel(val, PRCM_TCR); |
3df57bcf MN |
1319 | |
1320 | return 0; | |
1321 | } | |
1322 | ||
6b6fae2b | 1323 | static int request_clock(u8 clock, bool enable) |
3df57bcf MN |
1324 | { |
1325 | u32 val; | |
1326 | unsigned long flags; | |
1327 | ||
1328 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1329 | ||
1330 | /* Grab the HW semaphore. */ | |
c553b3ca | 1331 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
1332 | cpu_relax(); |
1333 | ||
b047d981 | 1334 | val = readl(prcmu_base + clk_mgt[clock].offset); |
3df57bcf MN |
1335 | if (enable) { |
1336 | val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); | |
1337 | } else { | |
1338 | clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1339 | val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1340 | } | |
b047d981 | 1341 | writel(val, prcmu_base + clk_mgt[clock].offset); |
3df57bcf MN |
1342 | |
1343 | /* Release the HW semaphore. */ | |
c553b3ca | 1344 | writel(0, PRCM_SEM); |
3df57bcf MN |
1345 | |
1346 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | ||
0837bb72 MN |
1351 | static int request_sga_clock(u8 clock, bool enable) |
1352 | { | |
1353 | u32 val; | |
1354 | int ret; | |
1355 | ||
1356 | if (enable) { | |
1357 | val = readl(PRCM_CGATING_BYPASS); | |
1358 | writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1359 | } | |
1360 | ||
6b6fae2b | 1361 | ret = request_clock(clock, enable); |
0837bb72 MN |
1362 | |
1363 | if (!ret && !enable) { | |
1364 | val = readl(PRCM_CGATING_BYPASS); | |
1365 | writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1366 | } | |
1367 | ||
1368 | return ret; | |
1369 | } | |
1370 | ||
6b6fae2b MN |
1371 | static inline bool plldsi_locked(void) |
1372 | { | |
1373 | return (readl(PRCM_PLLDSI_LOCKP) & | |
1374 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | | |
1375 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == | |
1376 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | | |
1377 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); | |
1378 | } | |
1379 | ||
1380 | static int request_plldsi(bool enable) | |
1381 | { | |
1382 | int r = 0; | |
1383 | u32 val; | |
1384 | ||
1385 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | | |
1386 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? | |
1387 | PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); | |
1388 | ||
1389 | val = readl(PRCM_PLLDSI_ENABLE); | |
1390 | if (enable) | |
1391 | val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1392 | else | |
1393 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1394 | writel(val, PRCM_PLLDSI_ENABLE); | |
1395 | ||
1396 | if (enable) { | |
1397 | unsigned int i; | |
1398 | bool locked = plldsi_locked(); | |
1399 | ||
1400 | for (i = 10; !locked && (i > 0); --i) { | |
1401 | udelay(100); | |
1402 | locked = plldsi_locked(); | |
1403 | } | |
1404 | if (locked) { | |
1405 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, | |
1406 | PRCM_APE_RESETN_SET); | |
1407 | } else { | |
1408 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | | |
1409 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), | |
1410 | PRCM_MMIP_LS_CLAMP_SET); | |
1411 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1412 | writel(val, PRCM_PLLDSI_ENABLE); | |
1413 | r = -EAGAIN; | |
1414 | } | |
1415 | } else { | |
1416 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); | |
1417 | } | |
1418 | return r; | |
1419 | } | |
1420 | ||
1421 | static int request_dsiclk(u8 n, bool enable) | |
1422 | { | |
1423 | u32 val; | |
1424 | ||
1425 | val = readl(PRCM_DSI_PLLOUT_SEL); | |
1426 | val &= ~dsiclk[n].divsel_mask; | |
1427 | val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << | |
1428 | dsiclk[n].divsel_shift); | |
1429 | writel(val, PRCM_DSI_PLLOUT_SEL); | |
1430 | return 0; | |
1431 | } | |
1432 | ||
1433 | static int request_dsiescclk(u8 n, bool enable) | |
1434 | { | |
1435 | u32 val; | |
1436 | ||
1437 | val = readl(PRCM_DSITVCLK_DIV); | |
1438 | enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); | |
1439 | writel(val, PRCM_DSITVCLK_DIV); | |
1440 | return 0; | |
1441 | } | |
1442 | ||
3df57bcf | 1443 | /** |
73180f85 | 1444 | * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. |
3df57bcf MN |
1445 | * @clock: The clock for which the request is made. |
1446 | * @enable: Whether the clock should be enabled (true) or disabled (false). | |
1447 | * | |
1448 | * This function should only be used by the clock implementation. | |
1449 | * Do not use it from any other place! | |
1450 | */ | |
73180f85 | 1451 | int db8500_prcmu_request_clock(u8 clock, bool enable) |
3df57bcf | 1452 | { |
6b6fae2b | 1453 | if (clock == PRCMU_SGACLK) |
0837bb72 | 1454 | return request_sga_clock(clock, enable); |
6b6fae2b MN |
1455 | else if (clock < PRCMU_NUM_REG_CLOCKS) |
1456 | return request_clock(clock, enable); | |
1457 | else if (clock == PRCMU_TIMCLK) | |
3df57bcf | 1458 | return request_timclk(enable); |
6b6fae2b MN |
1459 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
1460 | return request_dsiclk((clock - PRCMU_DSI0CLK), enable); | |
1461 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1462 | return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); | |
1463 | else if (clock == PRCMU_PLLDSI) | |
1464 | return request_plldsi(enable); | |
1465 | else if (clock == PRCMU_SYSCLK) | |
3df57bcf | 1466 | return request_sysclk(enable); |
6b6fae2b | 1467 | else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) |
0837bb72 | 1468 | return request_pll(clock, enable); |
6b6fae2b MN |
1469 | else |
1470 | return -EINVAL; | |
1471 | } | |
1472 | ||
1473 | static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, | |
1474 | int branch) | |
1475 | { | |
1476 | u64 rate; | |
1477 | u32 val; | |
1478 | u32 d; | |
1479 | u32 div = 1; | |
1480 | ||
1481 | val = readl(reg); | |
1482 | ||
1483 | rate = src_rate; | |
1484 | rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); | |
1485 | ||
1486 | d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); | |
1487 | if (d > 1) | |
1488 | div *= d; | |
1489 | ||
1490 | d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); | |
1491 | if (d > 1) | |
1492 | div *= d; | |
1493 | ||
1494 | if (val & PRCM_PLL_FREQ_SELDIV2) | |
1495 | div *= 2; | |
1496 | ||
1497 | if ((branch == PLL_FIX) || ((branch == PLL_DIV) && | |
1498 | (val & PRCM_PLL_FREQ_DIV2EN) && | |
1499 | ((reg == PRCM_PLLSOC0_FREQ) || | |
20aee5b6 | 1500 | (reg == PRCM_PLLARM_FREQ) || |
6b6fae2b MN |
1501 | (reg == PRCM_PLLDDR_FREQ)))) |
1502 | div *= 2; | |
1503 | ||
1504 | (void)do_div(rate, div); | |
1505 | ||
1506 | return (unsigned long)rate; | |
1507 | } | |
1508 | ||
1509 | #define ROOT_CLOCK_RATE 38400000 | |
1510 | ||
1511 | static unsigned long clock_rate(u8 clock) | |
1512 | { | |
1513 | u32 val; | |
1514 | u32 pllsw; | |
1515 | unsigned long rate = ROOT_CLOCK_RATE; | |
1516 | ||
b047d981 | 1517 | val = readl(prcmu_base + clk_mgt[clock].offset); |
6b6fae2b MN |
1518 | |
1519 | if (val & PRCM_CLK_MGT_CLK38) { | |
1520 | if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) | |
1521 | rate /= 2; | |
1522 | return rate; | |
1523 | } | |
1524 | ||
1525 | val |= clk_mgt[clock].pllsw; | |
1526 | pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1527 | ||
1528 | if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) | |
1529 | rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); | |
1530 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) | |
1531 | rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); | |
1532 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) | |
1533 | rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); | |
1534 | else | |
1535 | return 0; | |
1536 | ||
1537 | if ((clock == PRCMU_SGACLK) && | |
1538 | (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { | |
1539 | u64 r = (rate * 10); | |
1540 | ||
1541 | (void)do_div(r, 25); | |
1542 | return (unsigned long)r; | |
1543 | } | |
1544 | val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1545 | if (val) | |
1546 | return rate / val; | |
1547 | else | |
1548 | return 0; | |
1549 | } | |
20aee5b6 | 1550 | |
b2302c87 | 1551 | static unsigned long armss_rate(void) |
20aee5b6 MJ |
1552 | { |
1553 | u32 r; | |
1554 | unsigned long rate; | |
1555 | ||
1556 | r = readl(PRCM_ARM_CHGCLKREQ); | |
1557 | ||
1558 | if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { | |
1559 | /* External ARMCLKFIX clock */ | |
1560 | ||
1561 | rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); | |
1562 | ||
1563 | /* Check PRCM_ARM_CHGCLKREQ divider */ | |
1564 | if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) | |
1565 | rate /= 2; | |
1566 | ||
1567 | /* Check PRCM_ARMCLKFIX_MGT divider */ | |
1568 | r = readl(PRCM_ARMCLKFIX_MGT); | |
1569 | r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1570 | rate /= r; | |
1571 | ||
1572 | } else {/* ARM PLL */ | |
1573 | rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); | |
1574 | } | |
1575 | ||
b2302c87 | 1576 | return rate; |
20aee5b6 | 1577 | } |
6b6fae2b MN |
1578 | |
1579 | static unsigned long dsiclk_rate(u8 n) | |
1580 | { | |
1581 | u32 divsel; | |
1582 | u32 div = 1; | |
1583 | ||
1584 | divsel = readl(PRCM_DSI_PLLOUT_SEL); | |
1585 | divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); | |
1586 | ||
1587 | if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) | |
1588 | divsel = dsiclk[n].divsel; | |
1589 | ||
1590 | switch (divsel) { | |
1591 | case PRCM_DSI_PLLOUT_SEL_PHI_4: | |
1592 | div *= 2; | |
1593 | case PRCM_DSI_PLLOUT_SEL_PHI_2: | |
1594 | div *= 2; | |
1595 | case PRCM_DSI_PLLOUT_SEL_PHI: | |
1596 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1597 | PLL_RAW) / div; | |
e62ccf3a | 1598 | default: |
6b6fae2b | 1599 | return 0; |
e62ccf3a | 1600 | } |
6b6fae2b MN |
1601 | } |
1602 | ||
1603 | static unsigned long dsiescclk_rate(u8 n) | |
1604 | { | |
1605 | u32 div; | |
1606 | ||
1607 | div = readl(PRCM_DSITVCLK_DIV); | |
1608 | div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); | |
1609 | return clock_rate(PRCMU_TVCLK) / max((u32)1, div); | |
1610 | } | |
1611 | ||
1612 | unsigned long prcmu_clock_rate(u8 clock) | |
1613 | { | |
e62ccf3a | 1614 | if (clock < PRCMU_NUM_REG_CLOCKS) |
6b6fae2b MN |
1615 | return clock_rate(clock); |
1616 | else if (clock == PRCMU_TIMCLK) | |
1617 | return ROOT_CLOCK_RATE / 16; | |
1618 | else if (clock == PRCMU_SYSCLK) | |
1619 | return ROOT_CLOCK_RATE; | |
1620 | else if (clock == PRCMU_PLLSOC0) | |
1621 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1622 | else if (clock == PRCMU_PLLSOC1) | |
1623 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
20aee5b6 MJ |
1624 | else if (clock == PRCMU_ARMSS) |
1625 | return armss_rate(); | |
6b6fae2b MN |
1626 | else if (clock == PRCMU_PLLDDR) |
1627 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1628 | else if (clock == PRCMU_PLLDSI) | |
1629 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1630 | PLL_RAW); | |
1631 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1632 | return dsiclk_rate(clock - PRCMU_DSI0CLK); | |
1633 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1634 | return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); | |
1635 | else | |
1636 | return 0; | |
1637 | } | |
1638 | ||
1639 | static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) | |
1640 | { | |
1641 | if (clk_mgt_val & PRCM_CLK_MGT_CLK38) | |
1642 | return ROOT_CLOCK_RATE; | |
1643 | clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; | |
1644 | if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) | |
1645 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); | |
1646 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) | |
1647 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); | |
1648 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) | |
1649 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); | |
1650 | else | |
1651 | return 0; | |
1652 | } | |
1653 | ||
1654 | static u32 clock_divider(unsigned long src_rate, unsigned long rate) | |
1655 | { | |
1656 | u32 div; | |
1657 | ||
1658 | div = (src_rate / rate); | |
1659 | if (div == 0) | |
1660 | return 1; | |
1661 | if (rate < (src_rate / div)) | |
1662 | div++; | |
1663 | return div; | |
1664 | } | |
1665 | ||
1666 | static long round_clock_rate(u8 clock, unsigned long rate) | |
1667 | { | |
1668 | u32 val; | |
1669 | u32 div; | |
1670 | unsigned long src_rate; | |
1671 | long rounded_rate; | |
1672 | ||
b047d981 | 1673 | val = readl(prcmu_base + clk_mgt[clock].offset); |
6b6fae2b MN |
1674 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), |
1675 | clk_mgt[clock].branch); | |
1676 | div = clock_divider(src_rate, rate); | |
1677 | if (val & PRCM_CLK_MGT_CLK38) { | |
1678 | if (clk_mgt[clock].clk38div) { | |
1679 | if (div > 2) | |
1680 | div = 2; | |
1681 | } else { | |
1682 | div = 1; | |
1683 | } | |
1684 | } else if ((clock == PRCMU_SGACLK) && (div == 3)) { | |
1685 | u64 r = (src_rate * 10); | |
1686 | ||
1687 | (void)do_div(r, 25); | |
1688 | if (r <= rate) | |
1689 | return (unsigned long)r; | |
1690 | } | |
1691 | rounded_rate = (src_rate / min(div, (u32)31)); | |
1692 | ||
1693 | return rounded_rate; | |
1694 | } | |
1695 | ||
b2302c87 UH |
1696 | /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ |
1697 | static struct cpufreq_frequency_table db8500_cpufreq_table[] = { | |
1698 | { .frequency = 200000, .index = ARM_EXTCLK,}, | |
1699 | { .frequency = 400000, .index = ARM_50_OPP,}, | |
1700 | { .frequency = 800000, .index = ARM_100_OPP,}, | |
1701 | { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ | |
1702 | { .frequency = CPUFREQ_TABLE_END,}, | |
1703 | }; | |
1704 | ||
1705 | static long round_armss_rate(unsigned long rate) | |
1706 | { | |
1707 | long freq = 0; | |
1708 | int i = 0; | |
1709 | ||
1710 | /* cpufreq table frequencies is in KHz. */ | |
1711 | rate = rate / 1000; | |
1712 | ||
1713 | /* Find the corresponding arm opp from the cpufreq table. */ | |
1714 | while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) { | |
1715 | freq = db8500_cpufreq_table[i].frequency; | |
1716 | if (freq == rate) | |
1717 | break; | |
1718 | i++; | |
1719 | } | |
1720 | ||
1721 | /* Return the last valid value, even if a match was not found. */ | |
1722 | return freq * 1000; | |
1723 | } | |
1724 | ||
6b6fae2b MN |
1725 | #define MIN_PLL_VCO_RATE 600000000ULL |
1726 | #define MAX_PLL_VCO_RATE 1680640000ULL | |
1727 | ||
1728 | static long round_plldsi_rate(unsigned long rate) | |
1729 | { | |
1730 | long rounded_rate = 0; | |
1731 | unsigned long src_rate; | |
1732 | unsigned long rem; | |
1733 | u32 r; | |
1734 | ||
1735 | src_rate = clock_rate(PRCMU_HDMICLK); | |
1736 | rem = rate; | |
1737 | ||
1738 | for (r = 7; (rem > 0) && (r > 0); r--) { | |
1739 | u64 d; | |
1740 | ||
1741 | d = (r * rate); | |
1742 | (void)do_div(d, src_rate); | |
1743 | if (d < 6) | |
1744 | d = 6; | |
1745 | else if (d > 255) | |
1746 | d = 255; | |
1747 | d *= src_rate; | |
1748 | if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || | |
1749 | ((r * MAX_PLL_VCO_RATE) < (2 * d))) | |
1750 | continue; | |
1751 | (void)do_div(d, r); | |
1752 | if (rate < d) { | |
1753 | if (rounded_rate == 0) | |
1754 | rounded_rate = (long)d; | |
1755 | break; | |
1756 | } | |
1757 | if ((rate - d) < rem) { | |
1758 | rem = (rate - d); | |
1759 | rounded_rate = (long)d; | |
1760 | } | |
1761 | } | |
1762 | return rounded_rate; | |
1763 | } | |
1764 | ||
1765 | static long round_dsiclk_rate(unsigned long rate) | |
1766 | { | |
1767 | u32 div; | |
1768 | unsigned long src_rate; | |
1769 | long rounded_rate; | |
1770 | ||
1771 | src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1772 | PLL_RAW); | |
1773 | div = clock_divider(src_rate, rate); | |
1774 | rounded_rate = (src_rate / ((div > 2) ? 4 : div)); | |
1775 | ||
1776 | return rounded_rate; | |
1777 | } | |
1778 | ||
1779 | static long round_dsiescclk_rate(unsigned long rate) | |
1780 | { | |
1781 | u32 div; | |
1782 | unsigned long src_rate; | |
1783 | long rounded_rate; | |
1784 | ||
1785 | src_rate = clock_rate(PRCMU_TVCLK); | |
1786 | div = clock_divider(src_rate, rate); | |
1787 | rounded_rate = (src_rate / min(div, (u32)255)); | |
1788 | ||
1789 | return rounded_rate; | |
1790 | } | |
1791 | ||
1792 | long prcmu_round_clock_rate(u8 clock, unsigned long rate) | |
1793 | { | |
1794 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
1795 | return round_clock_rate(clock, rate); | |
b2302c87 UH |
1796 | else if (clock == PRCMU_ARMSS) |
1797 | return round_armss_rate(rate); | |
6b6fae2b MN |
1798 | else if (clock == PRCMU_PLLDSI) |
1799 | return round_plldsi_rate(rate); | |
1800 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1801 | return round_dsiclk_rate(rate); | |
1802 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1803 | return round_dsiescclk_rate(rate); | |
1804 | else | |
1805 | return (long)prcmu_clock_rate(clock); | |
1806 | } | |
1807 | ||
1808 | static void set_clock_rate(u8 clock, unsigned long rate) | |
1809 | { | |
1810 | u32 val; | |
1811 | u32 div; | |
1812 | unsigned long src_rate; | |
1813 | unsigned long flags; | |
1814 | ||
1815 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1816 | ||
1817 | /* Grab the HW semaphore. */ | |
1818 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) | |
1819 | cpu_relax(); | |
1820 | ||
b047d981 | 1821 | val = readl(prcmu_base + clk_mgt[clock].offset); |
6b6fae2b MN |
1822 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), |
1823 | clk_mgt[clock].branch); | |
1824 | div = clock_divider(src_rate, rate); | |
1825 | if (val & PRCM_CLK_MGT_CLK38) { | |
1826 | if (clk_mgt[clock].clk38div) { | |
1827 | if (div > 1) | |
1828 | val |= PRCM_CLK_MGT_CLK38DIV; | |
1829 | else | |
1830 | val &= ~PRCM_CLK_MGT_CLK38DIV; | |
1831 | } | |
1832 | } else if (clock == PRCMU_SGACLK) { | |
1833 | val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | | |
1834 | PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); | |
1835 | if (div == 3) { | |
1836 | u64 r = (src_rate * 10); | |
1837 | ||
1838 | (void)do_div(r, 25); | |
1839 | if (r <= rate) { | |
1840 | val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; | |
1841 | div = 0; | |
1842 | } | |
1843 | } | |
1844 | val |= min(div, (u32)31); | |
1845 | } else { | |
1846 | val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1847 | val |= min(div, (u32)31); | |
1848 | } | |
b047d981 | 1849 | writel(val, prcmu_base + clk_mgt[clock].offset); |
6b6fae2b MN |
1850 | |
1851 | /* Release the HW semaphore. */ | |
1852 | writel(0, PRCM_SEM); | |
1853 | ||
1854 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1855 | } | |
1856 | ||
b2302c87 UH |
1857 | static int set_armss_rate(unsigned long rate) |
1858 | { | |
1859 | int i = 0; | |
1860 | ||
1861 | /* cpufreq table frequencies is in KHz. */ | |
1862 | rate = rate / 1000; | |
1863 | ||
1864 | /* Find the corresponding arm opp from the cpufreq table. */ | |
1865 | while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) { | |
1866 | if (db8500_cpufreq_table[i].frequency == rate) | |
1867 | break; | |
1868 | i++; | |
1869 | } | |
1870 | ||
1871 | if (db8500_cpufreq_table[i].frequency != rate) | |
1872 | return -EINVAL; | |
1873 | ||
1874 | /* Set the new arm opp. */ | |
1875 | return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index); | |
1876 | } | |
1877 | ||
6b6fae2b MN |
1878 | static int set_plldsi_rate(unsigned long rate) |
1879 | { | |
1880 | unsigned long src_rate; | |
1881 | unsigned long rem; | |
1882 | u32 pll_freq = 0; | |
1883 | u32 r; | |
1884 | ||
1885 | src_rate = clock_rate(PRCMU_HDMICLK); | |
1886 | rem = rate; | |
1887 | ||
1888 | for (r = 7; (rem > 0) && (r > 0); r--) { | |
1889 | u64 d; | |
1890 | u64 hwrate; | |
1891 | ||
1892 | d = (r * rate); | |
1893 | (void)do_div(d, src_rate); | |
1894 | if (d < 6) | |
1895 | d = 6; | |
1896 | else if (d > 255) | |
1897 | d = 255; | |
1898 | hwrate = (d * src_rate); | |
1899 | if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || | |
1900 | ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) | |
1901 | continue; | |
1902 | (void)do_div(hwrate, r); | |
1903 | if (rate < hwrate) { | |
1904 | if (pll_freq == 0) | |
1905 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | | |
1906 | (r << PRCM_PLL_FREQ_R_SHIFT)); | |
1907 | break; | |
1908 | } | |
1909 | if ((rate - hwrate) < rem) { | |
1910 | rem = (rate - hwrate); | |
1911 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | | |
1912 | (r << PRCM_PLL_FREQ_R_SHIFT)); | |
1913 | } | |
1914 | } | |
1915 | if (pll_freq == 0) | |
1916 | return -EINVAL; | |
1917 | ||
1918 | pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); | |
1919 | writel(pll_freq, PRCM_PLLDSI_FREQ); | |
1920 | ||
1921 | return 0; | |
1922 | } | |
1923 | ||
1924 | static void set_dsiclk_rate(u8 n, unsigned long rate) | |
1925 | { | |
1926 | u32 val; | |
1927 | u32 div; | |
1928 | ||
1929 | div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, | |
1930 | clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); | |
1931 | ||
1932 | dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : | |
1933 | (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : | |
1934 | /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; | |
1935 | ||
1936 | val = readl(PRCM_DSI_PLLOUT_SEL); | |
1937 | val &= ~dsiclk[n].divsel_mask; | |
1938 | val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); | |
1939 | writel(val, PRCM_DSI_PLLOUT_SEL); | |
1940 | } | |
1941 | ||
1942 | static void set_dsiescclk_rate(u8 n, unsigned long rate) | |
1943 | { | |
1944 | u32 val; | |
1945 | u32 div; | |
1946 | ||
1947 | div = clock_divider(clock_rate(PRCMU_TVCLK), rate); | |
1948 | val = readl(PRCM_DSITVCLK_DIV); | |
1949 | val &= ~dsiescclk[n].div_mask; | |
1950 | val |= (min(div, (u32)255) << dsiescclk[n].div_shift); | |
1951 | writel(val, PRCM_DSITVCLK_DIV); | |
1952 | } | |
1953 | ||
1954 | int prcmu_set_clock_rate(u8 clock, unsigned long rate) | |
1955 | { | |
1956 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
1957 | set_clock_rate(clock, rate); | |
b2302c87 UH |
1958 | else if (clock == PRCMU_ARMSS) |
1959 | return set_armss_rate(rate); | |
6b6fae2b MN |
1960 | else if (clock == PRCMU_PLLDSI) |
1961 | return set_plldsi_rate(rate); | |
1962 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1963 | set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); | |
1964 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1965 | set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); | |
1966 | return 0; | |
3df57bcf MN |
1967 | } |
1968 | ||
73180f85 | 1969 | int db8500_prcmu_config_esram0_deep_sleep(u8 state) |
3df57bcf MN |
1970 | { |
1971 | if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || | |
1972 | (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) | |
1973 | return -EINVAL; | |
1974 | ||
1975 | mutex_lock(&mb4_transfer.lock); | |
1976 | ||
c553b3ca | 1977 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1978 | cpu_relax(); |
1979 | ||
1980 | writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1981 | writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), | |
1982 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); | |
1983 | writeb(DDR_PWR_STATE_ON, | |
1984 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); | |
1985 | writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); | |
1986 | ||
c553b3ca | 1987 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1988 | wait_for_completion(&mb4_transfer.work); |
1989 | ||
1990 | mutex_unlock(&mb4_transfer.lock); | |
1991 | ||
1992 | return 0; | |
1993 | } | |
1994 | ||
0508901c | 1995 | int db8500_prcmu_config_hotdog(u8 threshold) |
3df57bcf MN |
1996 | { |
1997 | mutex_lock(&mb4_transfer.lock); | |
1998 | ||
c553b3ca | 1999 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2000 | cpu_relax(); |
2001 | ||
2002 | writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); | |
2003 | writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2004 | ||
c553b3ca | 2005 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2006 | wait_for_completion(&mb4_transfer.work); |
2007 | ||
2008 | mutex_unlock(&mb4_transfer.lock); | |
2009 | ||
2010 | return 0; | |
2011 | } | |
2012 | ||
0508901c | 2013 | int db8500_prcmu_config_hotmon(u8 low, u8 high) |
3df57bcf MN |
2014 | { |
2015 | mutex_lock(&mb4_transfer.lock); | |
2016 | ||
c553b3ca | 2017 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2018 | cpu_relax(); |
2019 | ||
2020 | writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); | |
2021 | writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); | |
2022 | writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), | |
2023 | (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); | |
2024 | writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2025 | ||
c553b3ca | 2026 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2027 | wait_for_completion(&mb4_transfer.work); |
2028 | ||
2029 | mutex_unlock(&mb4_transfer.lock); | |
2030 | ||
2031 | return 0; | |
2032 | } | |
2033 | ||
2034 | static int config_hot_period(u16 val) | |
2035 | { | |
2036 | mutex_lock(&mb4_transfer.lock); | |
2037 | ||
c553b3ca | 2038 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2039 | cpu_relax(); |
2040 | ||
2041 | writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); | |
2042 | writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2043 | ||
c553b3ca | 2044 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2045 | wait_for_completion(&mb4_transfer.work); |
2046 | ||
2047 | mutex_unlock(&mb4_transfer.lock); | |
2048 | ||
2049 | return 0; | |
2050 | } | |
2051 | ||
0508901c | 2052 | int db8500_prcmu_start_temp_sense(u16 cycles32k) |
3df57bcf MN |
2053 | { |
2054 | if (cycles32k == 0xFFFF) | |
2055 | return -EINVAL; | |
2056 | ||
2057 | return config_hot_period(cycles32k); | |
2058 | } | |
2059 | ||
0508901c | 2060 | int db8500_prcmu_stop_temp_sense(void) |
3df57bcf MN |
2061 | { |
2062 | return config_hot_period(0xFFFF); | |
2063 | } | |
2064 | ||
84165b80 JA |
2065 | static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) |
2066 | { | |
2067 | ||
2068 | mutex_lock(&mb4_transfer.lock); | |
2069 | ||
2070 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) | |
2071 | cpu_relax(); | |
2072 | ||
2073 | writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); | |
2074 | writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); | |
2075 | writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); | |
2076 | writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); | |
2077 | ||
2078 | writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2079 | ||
2080 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); | |
2081 | wait_for_completion(&mb4_transfer.work); | |
2082 | ||
2083 | mutex_unlock(&mb4_transfer.lock); | |
2084 | ||
2085 | return 0; | |
2086 | ||
2087 | } | |
2088 | ||
0508901c | 2089 | int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) |
84165b80 JA |
2090 | { |
2091 | BUG_ON(num == 0 || num > 0xf); | |
2092 | return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, | |
2093 | sleep_auto_off ? A9WDOG_AUTO_OFF_EN : | |
2094 | A9WDOG_AUTO_OFF_DIS); | |
2095 | } | |
6f8cfa99 | 2096 | EXPORT_SYMBOL(db8500_prcmu_config_a9wdog); |
84165b80 | 2097 | |
0508901c | 2098 | int db8500_prcmu_enable_a9wdog(u8 id) |
84165b80 JA |
2099 | { |
2100 | return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); | |
2101 | } | |
6f8cfa99 | 2102 | EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog); |
84165b80 | 2103 | |
0508901c | 2104 | int db8500_prcmu_disable_a9wdog(u8 id) |
84165b80 JA |
2105 | { |
2106 | return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); | |
2107 | } | |
6f8cfa99 | 2108 | EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog); |
84165b80 | 2109 | |
0508901c | 2110 | int db8500_prcmu_kick_a9wdog(u8 id) |
84165b80 JA |
2111 | { |
2112 | return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); | |
2113 | } | |
6f8cfa99 | 2114 | EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog); |
84165b80 JA |
2115 | |
2116 | /* | |
2117 | * timeout is 28 bit, in ms. | |
2118 | */ | |
0508901c | 2119 | int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) |
84165b80 | 2120 | { |
84165b80 JA |
2121 | return prcmu_a9wdog(MB4H_A9WDOG_LOAD, |
2122 | (id & A9WDOG_ID_MASK) | | |
2123 | /* | |
2124 | * Put the lowest 28 bits of timeout at | |
2125 | * offset 4. Four first bits are used for id. | |
2126 | */ | |
2127 | (u8)((timeout << 4) & 0xf0), | |
2128 | (u8)((timeout >> 4) & 0xff), | |
2129 | (u8)((timeout >> 12) & 0xff), | |
2130 | (u8)((timeout >> 20) & 0xff)); | |
2131 | } | |
6f8cfa99 | 2132 | EXPORT_SYMBOL(db8500_prcmu_load_a9wdog); |
84165b80 | 2133 | |
e3726fcf LW |
2134 | /** |
2135 | * prcmu_abb_read() - Read register value(s) from the ABB. | |
2136 | * @slave: The I2C slave address. | |
2137 | * @reg: The (start) register address. | |
2138 | * @value: The read out value(s). | |
2139 | * @size: The number of registers to read. | |
2140 | * | |
2141 | * Reads register value(s) from the ABB. | |
2142 | * @size has to be 1 for the current firmware version. | |
2143 | */ | |
2144 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
2145 | { | |
2146 | int r; | |
2147 | ||
2148 | if (size != 1) | |
2149 | return -EINVAL; | |
2150 | ||
3df57bcf | 2151 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 2152 | |
c553b3ca | 2153 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
2154 | cpu_relax(); |
2155 | ||
3c3e4898 | 2156 | writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
3df57bcf MN |
2157 | writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2158 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
2159 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
2160 | writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
2161 | ||
c553b3ca | 2162 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 2163 | |
e3726fcf | 2164 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
2165 | msecs_to_jiffies(20000))) { |
2166 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
2167 | __func__); | |
e3726fcf | 2168 | r = -EIO; |
3df57bcf MN |
2169 | } else { |
2170 | r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); | |
e3726fcf | 2171 | } |
3df57bcf | 2172 | |
e3726fcf LW |
2173 | if (!r) |
2174 | *value = mb5_transfer.ack.value; | |
2175 | ||
e3726fcf | 2176 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 2177 | |
e3726fcf LW |
2178 | return r; |
2179 | } | |
e3726fcf LW |
2180 | |
2181 | /** | |
3c3e4898 | 2182 | * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. |
e3726fcf LW |
2183 | * @slave: The I2C slave address. |
2184 | * @reg: The (start) register address. | |
2185 | * @value: The value(s) to write. | |
3c3e4898 | 2186 | * @mask: The mask(s) to use. |
e3726fcf LW |
2187 | * @size: The number of registers to write. |
2188 | * | |
3c3e4898 MN |
2189 | * Writes masked register value(s) to the ABB. |
2190 | * For each @value, only the bits set to 1 in the corresponding @mask | |
2191 | * will be written. The other bits are not changed. | |
e3726fcf LW |
2192 | * @size has to be 1 for the current firmware version. |
2193 | */ | |
3c3e4898 | 2194 | int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) |
e3726fcf LW |
2195 | { |
2196 | int r; | |
2197 | ||
2198 | if (size != 1) | |
2199 | return -EINVAL; | |
2200 | ||
3df57bcf | 2201 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 2202 | |
c553b3ca | 2203 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
2204 | cpu_relax(); |
2205 | ||
3c3e4898 | 2206 | writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
3df57bcf MN |
2207 | writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2208 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
2209 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
2210 | writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
2211 | ||
c553b3ca | 2212 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 2213 | |
e3726fcf | 2214 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
2215 | msecs_to_jiffies(20000))) { |
2216 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
2217 | __func__); | |
e3726fcf | 2218 | r = -EIO; |
3df57bcf MN |
2219 | } else { |
2220 | r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); | |
e3726fcf | 2221 | } |
e3726fcf | 2222 | |
e3726fcf | 2223 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 2224 | |
e3726fcf LW |
2225 | return r; |
2226 | } | |
e3726fcf | 2227 | |
3c3e4898 MN |
2228 | /** |
2229 | * prcmu_abb_write() - Write register value(s) to the ABB. | |
2230 | * @slave: The I2C slave address. | |
2231 | * @reg: The (start) register address. | |
2232 | * @value: The value(s) to write. | |
2233 | * @size: The number of registers to write. | |
2234 | * | |
2235 | * Writes register value(s) to the ABB. | |
2236 | * @size has to be 1 for the current firmware version. | |
2237 | */ | |
2238 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
2239 | { | |
2240 | u8 mask = ~0; | |
2241 | ||
2242 | return prcmu_abb_write_masked(slave, reg, value, &mask, size); | |
2243 | } | |
2244 | ||
3df57bcf MN |
2245 | /** |
2246 | * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem | |
2247 | */ | |
5261e101 | 2248 | int prcmu_ac_wake_req(void) |
e0befb23 | 2249 | { |
3df57bcf | 2250 | u32 val; |
5261e101 | 2251 | int ret = 0; |
e0befb23 | 2252 | |
3df57bcf | 2253 | mutex_lock(&mb0_transfer.ac_wake_lock); |
e0befb23 | 2254 | |
c553b3ca | 2255 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2256 | if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) |
2257 | goto unlock_and_return; | |
e0befb23 | 2258 | |
3df57bcf | 2259 | atomic_set(&ac_wake_req_state, 1); |
e0befb23 | 2260 | |
5261e101 AM |
2261 | /* |
2262 | * Force Modem Wake-up before hostaccess_req ping-pong. | |
2263 | * It prevents Modem to enter in Sleep while acking the hostaccess | |
2264 | * request. The 31us delay has been calculated by HWI. | |
2265 | */ | |
2266 | val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; | |
2267 | writel(val, PRCM_HOSTACCESS_REQ); | |
2268 | ||
2269 | udelay(31); | |
2270 | ||
2271 | val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; | |
2272 | writel(val, PRCM_HOSTACCESS_REQ); | |
e0befb23 | 2273 | |
3df57bcf | 2274 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
d6e3002e | 2275 | msecs_to_jiffies(5000))) { |
5261e101 AM |
2276 | #if defined(CONFIG_DBX500_PRCMU_DEBUG) |
2277 | db8500_prcmu_debug_dump(__func__, true, true); | |
2278 | #endif | |
57265bc1 | 2279 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
d6e3002e | 2280 | __func__); |
5261e101 | 2281 | ret = -EFAULT; |
3df57bcf | 2282 | } |
e0befb23 | 2283 | |
3df57bcf MN |
2284 | unlock_and_return: |
2285 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
5261e101 | 2286 | return ret; |
e0befb23 MP |
2287 | } |
2288 | ||
2289 | /** | |
3df57bcf | 2290 | * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem |
e0befb23 | 2291 | */ |
3df57bcf | 2292 | void prcmu_ac_sleep_req() |
e0befb23 | 2293 | { |
3df57bcf MN |
2294 | u32 val; |
2295 | ||
2296 | mutex_lock(&mb0_transfer.ac_wake_lock); | |
2297 | ||
c553b3ca | 2298 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2299 | if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) |
2300 | goto unlock_and_return; | |
2301 | ||
2302 | writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), | |
c553b3ca | 2303 | PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2304 | |
2305 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, | |
d6e3002e | 2306 | msecs_to_jiffies(5000))) { |
57265bc1 | 2307 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
3df57bcf MN |
2308 | __func__); |
2309 | } | |
2310 | ||
2311 | atomic_set(&ac_wake_req_state, 0); | |
2312 | ||
2313 | unlock_and_return: | |
2314 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 | 2315 | } |
e0befb23 | 2316 | |
73180f85 | 2317 | bool db8500_prcmu_is_ac_wake_requested(void) |
e0befb23 | 2318 | { |
3df57bcf | 2319 | return (atomic_read(&ac_wake_req_state) != 0); |
e0befb23 | 2320 | } |
e0befb23 MP |
2321 | |
2322 | /** | |
73180f85 | 2323 | * db8500_prcmu_system_reset - System reset |
e0befb23 | 2324 | * |
73180f85 | 2325 | * Saves the reset reason code and then sets the APE_SOFTRST register which |
3df57bcf | 2326 | * fires interrupt to fw |
e0befb23 | 2327 | */ |
73180f85 | 2328 | void db8500_prcmu_system_reset(u16 reset_code) |
e0befb23 | 2329 | { |
3df57bcf | 2330 | writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); |
c553b3ca | 2331 | writel(1, PRCM_APE_SOFTRST); |
e0befb23 | 2332 | } |
e0befb23 | 2333 | |
597045de SR |
2334 | /** |
2335 | * db8500_prcmu_get_reset_code - Retrieve SW reset reason code | |
2336 | * | |
2337 | * Retrieves the reset reason code stored by prcmu_system_reset() before | |
2338 | * last restart. | |
2339 | */ | |
2340 | u16 db8500_prcmu_get_reset_code(void) | |
2341 | { | |
2342 | return readw(tcdm_base + PRCM_SW_RST_REASON); | |
2343 | } | |
2344 | ||
e0befb23 | 2345 | /** |
0508901c | 2346 | * db8500_prcmu_reset_modem - ask the PRCMU to reset modem |
e0befb23 | 2347 | */ |
0508901c | 2348 | void db8500_prcmu_modem_reset(void) |
e0befb23 | 2349 | { |
3df57bcf MN |
2350 | mutex_lock(&mb1_transfer.lock); |
2351 | ||
c553b3ca | 2352 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
2353 | cpu_relax(); |
2354 | ||
2355 | writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
c553b3ca | 2356 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2357 | wait_for_completion(&mb1_transfer.work); |
2358 | ||
2359 | /* | |
2360 | * No need to check return from PRCMU as modem should go in reset state | |
2361 | * This state is already managed by upper layer | |
2362 | */ | |
2363 | ||
2364 | mutex_unlock(&mb1_transfer.lock); | |
e0befb23 | 2365 | } |
e0befb23 | 2366 | |
3df57bcf | 2367 | static void ack_dbb_wakeup(void) |
e0befb23 | 2368 | { |
3df57bcf MN |
2369 | unsigned long flags; |
2370 | ||
2371 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2372 | ||
c553b3ca | 2373 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
2374 | cpu_relax(); |
2375 | ||
2376 | writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 2377 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2378 | |
2379 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
e0befb23 | 2380 | } |
e0befb23 | 2381 | |
3df57bcf | 2382 | static inline void print_unknown_header_warning(u8 n, u8 header) |
e0befb23 | 2383 | { |
3df57bcf MN |
2384 | pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", |
2385 | header, n); | |
e0befb23 MP |
2386 | } |
2387 | ||
3df57bcf | 2388 | static bool read_mailbox_0(void) |
e3726fcf | 2389 | { |
3df57bcf MN |
2390 | bool r; |
2391 | u32 ev; | |
2392 | unsigned int n; | |
2393 | u8 header; | |
2394 | ||
2395 | header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); | |
2396 | switch (header) { | |
2397 | case MB0H_WAKEUP_EXE: | |
2398 | case MB0H_WAKEUP_SLEEP: | |
2399 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
2400 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); | |
2401 | else | |
2402 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); | |
2403 | ||
2404 | if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) | |
2405 | complete(&mb0_transfer.ac_wake_work); | |
2406 | if (ev & WAKEUP_BIT_SYSCLK_OK) | |
2407 | complete(&mb3_transfer.sysclk_work); | |
2408 | ||
2409 | ev &= mb0_transfer.req.dbb_irqs; | |
2410 | ||
2411 | for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { | |
2412 | if (ev & prcmu_irq_bit[n]) | |
89d9b1c9 | 2413 | generic_handle_irq(irq_find_mapping(db8500_irq_domain, n)); |
3df57bcf MN |
2414 | } |
2415 | r = true; | |
2416 | break; | |
2417 | default: | |
2418 | print_unknown_header_warning(0, header); | |
2419 | r = false; | |
2420 | break; | |
2421 | } | |
c553b3ca | 2422 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); |
3df57bcf | 2423 | return r; |
e3726fcf LW |
2424 | } |
2425 | ||
3df57bcf | 2426 | static bool read_mailbox_1(void) |
e3726fcf | 2427 | { |
3df57bcf MN |
2428 | mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); |
2429 | mb1_transfer.ack.arm_opp = readb(tcdm_base + | |
2430 | PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
2431 | mb1_transfer.ack.ape_opp = readb(tcdm_base + | |
2432 | PRCM_ACK_MB1_CURRENT_APE_OPP); | |
2433 | mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + | |
2434 | PRCM_ACK_MB1_APE_VOLTAGE_STATUS); | |
c553b3ca | 2435 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); |
e0befb23 | 2436 | complete(&mb1_transfer.work); |
3df57bcf | 2437 | return false; |
e3726fcf LW |
2438 | } |
2439 | ||
3df57bcf | 2440 | static bool read_mailbox_2(void) |
e3726fcf | 2441 | { |
3df57bcf | 2442 | mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); |
c553b3ca | 2443 | writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2444 | complete(&mb2_transfer.work); |
2445 | return false; | |
e3726fcf LW |
2446 | } |
2447 | ||
3df57bcf | 2448 | static bool read_mailbox_3(void) |
e3726fcf | 2449 | { |
c553b3ca | 2450 | writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); |
3df57bcf | 2451 | return false; |
e3726fcf LW |
2452 | } |
2453 | ||
3df57bcf | 2454 | static bool read_mailbox_4(void) |
e3726fcf | 2455 | { |
3df57bcf MN |
2456 | u8 header; |
2457 | bool do_complete = true; | |
2458 | ||
2459 | header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); | |
2460 | switch (header) { | |
2461 | case MB4H_MEM_ST: | |
2462 | case MB4H_HOTDOG: | |
2463 | case MB4H_HOTMON: | |
2464 | case MB4H_HOT_PERIOD: | |
a592c2e2 MN |
2465 | case MB4H_A9WDOG_CONF: |
2466 | case MB4H_A9WDOG_EN: | |
2467 | case MB4H_A9WDOG_DIS: | |
2468 | case MB4H_A9WDOG_LOAD: | |
2469 | case MB4H_A9WDOG_KICK: | |
3df57bcf MN |
2470 | break; |
2471 | default: | |
2472 | print_unknown_header_warning(4, header); | |
2473 | do_complete = false; | |
2474 | break; | |
2475 | } | |
2476 | ||
c553b3ca | 2477 | writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2478 | |
2479 | if (do_complete) | |
2480 | complete(&mb4_transfer.work); | |
2481 | ||
2482 | return false; | |
e3726fcf LW |
2483 | } |
2484 | ||
3df57bcf | 2485 | static bool read_mailbox_5(void) |
e3726fcf | 2486 | { |
3df57bcf MN |
2487 | mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); |
2488 | mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); | |
c553b3ca | 2489 | writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); |
e3726fcf | 2490 | complete(&mb5_transfer.work); |
3df57bcf | 2491 | return false; |
e3726fcf LW |
2492 | } |
2493 | ||
3df57bcf | 2494 | static bool read_mailbox_6(void) |
e3726fcf | 2495 | { |
c553b3ca | 2496 | writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); |
3df57bcf | 2497 | return false; |
e3726fcf LW |
2498 | } |
2499 | ||
3df57bcf | 2500 | static bool read_mailbox_7(void) |
e3726fcf | 2501 | { |
c553b3ca | 2502 | writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); |
3df57bcf | 2503 | return false; |
e3726fcf LW |
2504 | } |
2505 | ||
3df57bcf | 2506 | static bool (* const read_mailbox[NUM_MB])(void) = { |
e3726fcf LW |
2507 | read_mailbox_0, |
2508 | read_mailbox_1, | |
2509 | read_mailbox_2, | |
2510 | read_mailbox_3, | |
2511 | read_mailbox_4, | |
2512 | read_mailbox_5, | |
2513 | read_mailbox_6, | |
2514 | read_mailbox_7 | |
2515 | }; | |
2516 | ||
2517 | static irqreturn_t prcmu_irq_handler(int irq, void *data) | |
2518 | { | |
2519 | u32 bits; | |
2520 | u8 n; | |
3df57bcf | 2521 | irqreturn_t r; |
e3726fcf | 2522 | |
c553b3ca | 2523 | bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); |
e3726fcf LW |
2524 | if (unlikely(!bits)) |
2525 | return IRQ_NONE; | |
2526 | ||
3df57bcf | 2527 | r = IRQ_HANDLED; |
e3726fcf LW |
2528 | for (n = 0; bits; n++) { |
2529 | if (bits & MBOX_BIT(n)) { | |
2530 | bits -= MBOX_BIT(n); | |
3df57bcf MN |
2531 | if (read_mailbox[n]()) |
2532 | r = IRQ_WAKE_THREAD; | |
e3726fcf LW |
2533 | } |
2534 | } | |
3df57bcf MN |
2535 | return r; |
2536 | } | |
2537 | ||
2538 | static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) | |
2539 | { | |
2540 | ack_dbb_wakeup(); | |
e3726fcf LW |
2541 | return IRQ_HANDLED; |
2542 | } | |
2543 | ||
3df57bcf MN |
2544 | static void prcmu_mask_work(struct work_struct *work) |
2545 | { | |
2546 | unsigned long flags; | |
2547 | ||
2548 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2549 | ||
2550 | config_wakeups(); | |
2551 | ||
2552 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
2553 | } | |
2554 | ||
2555 | static void prcmu_irq_mask(struct irq_data *d) | |
2556 | { | |
2557 | unsigned long flags; | |
2558 | ||
2559 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2560 | ||
f3f1f0a1 | 2561 | mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; |
3df57bcf MN |
2562 | |
2563 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2564 | ||
2565 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2566 | schedule_work(&mb0_transfer.mask_work); | |
2567 | } | |
2568 | ||
2569 | static void prcmu_irq_unmask(struct irq_data *d) | |
2570 | { | |
2571 | unsigned long flags; | |
2572 | ||
2573 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2574 | ||
f3f1f0a1 | 2575 | mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; |
3df57bcf MN |
2576 | |
2577 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2578 | ||
2579 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2580 | schedule_work(&mb0_transfer.mask_work); | |
2581 | } | |
2582 | ||
2583 | static void noop(struct irq_data *d) | |
2584 | { | |
2585 | } | |
2586 | ||
2587 | static struct irq_chip prcmu_irq_chip = { | |
2588 | .name = "prcmu", | |
2589 | .irq_disable = prcmu_irq_mask, | |
2590 | .irq_ack = noop, | |
2591 | .irq_mask = prcmu_irq_mask, | |
2592 | .irq_unmask = prcmu_irq_unmask, | |
2593 | }; | |
2594 | ||
05ec260e | 2595 | static __init char *fw_project_name(u32 project) |
b58d12fe MN |
2596 | { |
2597 | switch (project) { | |
2598 | case PRCMU_FW_PROJECT_U8500: | |
2599 | return "U8500"; | |
05ec260e LW |
2600 | case PRCMU_FW_PROJECT_U8400: |
2601 | return "U8400"; | |
b58d12fe MN |
2602 | case PRCMU_FW_PROJECT_U9500: |
2603 | return "U9500"; | |
05ec260e LW |
2604 | case PRCMU_FW_PROJECT_U8500_MBB: |
2605 | return "U8500 MBB"; | |
2606 | case PRCMU_FW_PROJECT_U8500_C1: | |
2607 | return "U8500 C1"; | |
2608 | case PRCMU_FW_PROJECT_U8500_C2: | |
2609 | return "U8500 C2"; | |
2610 | case PRCMU_FW_PROJECT_U8500_C3: | |
2611 | return "U8500 C3"; | |
2612 | case PRCMU_FW_PROJECT_U8500_C4: | |
2613 | return "U8500 C4"; | |
2614 | case PRCMU_FW_PROJECT_U9500_MBL: | |
2615 | return "U9500 MBL"; | |
2616 | case PRCMU_FW_PROJECT_U8500_MBL: | |
2617 | return "U8500 MBL"; | |
2618 | case PRCMU_FW_PROJECT_U8500_MBL2: | |
2619 | return "U8500 MBL2"; | |
5f96a1a6 | 2620 | case PRCMU_FW_PROJECT_U8520: |
05ec260e | 2621 | return "U8520 MBL"; |
1927ddf6 BJ |
2622 | case PRCMU_FW_PROJECT_U8420: |
2623 | return "U8420"; | |
05ec260e LW |
2624 | case PRCMU_FW_PROJECT_U9540: |
2625 | return "U9540"; | |
2626 | case PRCMU_FW_PROJECT_A9420: | |
2627 | return "A9420"; | |
2628 | case PRCMU_FW_PROJECT_L8540: | |
2629 | return "L8540"; | |
2630 | case PRCMU_FW_PROJECT_L8580: | |
2631 | return "L8580"; | |
b58d12fe MN |
2632 | default: |
2633 | return "Unknown"; | |
2634 | } | |
2635 | } | |
2636 | ||
f3f1f0a1 LJ |
2637 | static int db8500_irq_map(struct irq_domain *d, unsigned int virq, |
2638 | irq_hw_number_t hwirq) | |
2639 | { | |
2640 | irq_set_chip_and_handler(virq, &prcmu_irq_chip, | |
2641 | handle_simple_irq); | |
2642 | set_irq_flags(virq, IRQF_VALID); | |
2643 | ||
2644 | return 0; | |
2645 | } | |
2646 | ||
2647 | static struct irq_domain_ops db8500_irq_ops = { | |
89d9b1c9 LW |
2648 | .map = db8500_irq_map, |
2649 | .xlate = irq_domain_xlate_twocell, | |
f3f1f0a1 LJ |
2650 | }; |
2651 | ||
2652 | static int db8500_irq_init(struct device_node *np) | |
2653 | { | |
89d9b1c9 LW |
2654 | int irq_base = 0; |
2655 | int i; | |
a7238e43 LW |
2656 | |
2657 | /* In the device tree case, just take some IRQs */ | |
2658 | if (!np) | |
2659 | irq_base = IRQ_PRCMU_BASE; | |
2660 | ||
2661 | db8500_irq_domain = irq_domain_add_simple( | |
2662 | np, NUM_PRCMU_WAKEUPS, irq_base, | |
2663 | &db8500_irq_ops, NULL); | |
f3f1f0a1 LJ |
2664 | |
2665 | if (!db8500_irq_domain) { | |
2666 | pr_err("Failed to create irqdomain\n"); | |
2667 | return -ENOSYS; | |
2668 | } | |
2669 | ||
89d9b1c9 LW |
2670 | /* All wakeups will be used, so create mappings for all */ |
2671 | for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) | |
2672 | irq_create_mapping(db8500_irq_domain, i); | |
2673 | ||
f3f1f0a1 LJ |
2674 | return 0; |
2675 | } | |
2676 | ||
05ec260e LW |
2677 | static void dbx500_fw_version_init(struct platform_device *pdev, |
2678 | u32 version_offset) | |
fcbd458e | 2679 | { |
05ec260e LW |
2680 | struct resource *res; |
2681 | void __iomem *tcpm_base; | |
3df57bcf | 2682 | |
05ec260e LW |
2683 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2684 | "prcmu-tcpm"); | |
2685 | if (!res) { | |
2686 | dev_err(&pdev->dev, | |
2687 | "Error: no prcmu tcpm memory region provided\n"); | |
2688 | return; | |
2689 | } | |
2690 | tcpm_base = ioremap(res->start, resource_size(res)); | |
2691 | if (tcpm_base != NULL) { | |
2692 | u32 version; | |
2693 | ||
2694 | version = readl(tcpm_base + version_offset); | |
2695 | fw_info.version.project = (version & 0xFF); | |
2696 | fw_info.version.api_version = (version >> 8) & 0xFF; | |
2697 | fw_info.version.func_version = (version >> 16) & 0xFF; | |
2698 | fw_info.version.errata = (version >> 24) & 0xFF; | |
2699 | strncpy(fw_info.version.project_name, | |
2700 | fw_project_name(fw_info.version.project), | |
2701 | PRCMU_FW_PROJECT_NAME_LEN); | |
2702 | fw_info.valid = true; | |
2703 | pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n", | |
2704 | fw_info.version.project_name, | |
2705 | fw_info.version.project, | |
2706 | fw_info.version.api_version, | |
2707 | fw_info.version.func_version, | |
2708 | fw_info.version.errata); | |
2709 | iounmap(tcpm_base); | |
fcbd458e | 2710 | } |
05ec260e | 2711 | } |
e0befb23 | 2712 | |
9a47a8dc | 2713 | void __init db8500_prcmu_early_init(u32 phy_base, u32 size) |
05ec260e | 2714 | { |
9a47a8dc LW |
2715 | /* |
2716 | * This is a temporary remap to bring up the clocks. It is | |
2717 | * subsequently replaces with a real remap. After the merge of | |
2718 | * the mailbox subsystem all of this early code goes away, and the | |
2719 | * clock driver can probe independently. An early initcall will | |
2720 | * still be needed, but it can be diverted into drivers/clk/ux500. | |
2721 | */ | |
2722 | prcmu_base = ioremap(phy_base, size); | |
2723 | if (!prcmu_base) | |
2724 | pr_err("%s: ioremap() of prcmu registers failed!\n", __func__); | |
2725 | ||
3df57bcf MN |
2726 | spin_lock_init(&mb0_transfer.lock); |
2727 | spin_lock_init(&mb0_transfer.dbb_irqs_lock); | |
2728 | mutex_init(&mb0_transfer.ac_wake_lock); | |
2729 | init_completion(&mb0_transfer.ac_wake_work); | |
e0befb23 MP |
2730 | mutex_init(&mb1_transfer.lock); |
2731 | init_completion(&mb1_transfer.work); | |
4d64d2e3 | 2732 | mb1_transfer.ape_opp = APE_NO_CHANGE; |
3df57bcf MN |
2733 | mutex_init(&mb2_transfer.lock); |
2734 | init_completion(&mb2_transfer.work); | |
2735 | spin_lock_init(&mb2_transfer.auto_pm_lock); | |
2736 | spin_lock_init(&mb3_transfer.lock); | |
2737 | mutex_init(&mb3_transfer.sysclk_lock); | |
2738 | init_completion(&mb3_transfer.sysclk_work); | |
2739 | mutex_init(&mb4_transfer.lock); | |
2740 | init_completion(&mb4_transfer.work); | |
e3726fcf LW |
2741 | mutex_init(&mb5_transfer.lock); |
2742 | init_completion(&mb5_transfer.work); | |
2743 | ||
3df57bcf | 2744 | INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); |
3df57bcf MN |
2745 | } |
2746 | ||
0508901c | 2747 | static void __init init_prcm_registers(void) |
d65e12d7 MN |
2748 | { |
2749 | u32 val; | |
2750 | ||
2751 | val = readl(PRCM_A9PL_FORCE_CLKEN); | |
2752 | val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | | |
2753 | PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); | |
2754 | writel(val, (PRCM_A9PL_FORCE_CLKEN)); | |
2755 | } | |
2756 | ||
1032fbfd BJ |
2757 | /* |
2758 | * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC | |
2759 | */ | |
2760 | static struct regulator_consumer_supply db8500_vape_consumers[] = { | |
2761 | REGULATOR_SUPPLY("v-ape", NULL), | |
2762 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), | |
2763 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), | |
2764 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), | |
2765 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), | |
ae840635 | 2766 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), |
1032fbfd BJ |
2767 | /* "v-mmc" changed to "vcore" in the mainline kernel */ |
2768 | REGULATOR_SUPPLY("vcore", "sdi0"), | |
2769 | REGULATOR_SUPPLY("vcore", "sdi1"), | |
2770 | REGULATOR_SUPPLY("vcore", "sdi2"), | |
2771 | REGULATOR_SUPPLY("vcore", "sdi3"), | |
2772 | REGULATOR_SUPPLY("vcore", "sdi4"), | |
2773 | REGULATOR_SUPPLY("v-dma", "dma40.0"), | |
2774 | REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), | |
2775 | /* "v-uart" changed to "vcore" in the mainline kernel */ | |
2776 | REGULATOR_SUPPLY("vcore", "uart0"), | |
2777 | REGULATOR_SUPPLY("vcore", "uart1"), | |
2778 | REGULATOR_SUPPLY("vcore", "uart2"), | |
2779 | REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), | |
992b133a | 2780 | REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), |
bc367481 | 2781 | REGULATOR_SUPPLY("vddvario", "smsc911x.0"), |
1032fbfd BJ |
2782 | }; |
2783 | ||
2784 | static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { | |
1032fbfd BJ |
2785 | REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), |
2786 | /* AV8100 regulator */ | |
2787 | REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), | |
2788 | }; | |
2789 | ||
2790 | static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { | |
992b133a | 2791 | REGULATOR_SUPPLY("vsupply", "b2r2_bus"), |
624e87c2 BJ |
2792 | REGULATOR_SUPPLY("vsupply", "mcde"), |
2793 | }; | |
2794 | ||
2795 | /* SVA MMDSP regulator switch */ | |
2796 | static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { | |
2797 | REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), | |
2798 | }; | |
2799 | ||
2800 | /* SVA pipe regulator switch */ | |
2801 | static struct regulator_consumer_supply db8500_svapipe_consumers[] = { | |
2802 | REGULATOR_SUPPLY("sva-pipe", "cm_control"), | |
2803 | }; | |
2804 | ||
2805 | /* SIA MMDSP regulator switch */ | |
2806 | static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { | |
2807 | REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), | |
2808 | }; | |
2809 | ||
2810 | /* SIA pipe regulator switch */ | |
2811 | static struct regulator_consumer_supply db8500_siapipe_consumers[] = { | |
2812 | REGULATOR_SUPPLY("sia-pipe", "cm_control"), | |
2813 | }; | |
2814 | ||
2815 | static struct regulator_consumer_supply db8500_sga_consumers[] = { | |
2816 | REGULATOR_SUPPLY("v-mali", NULL), | |
2817 | }; | |
2818 | ||
2819 | /* ESRAM1 and 2 regulator switch */ | |
2820 | static struct regulator_consumer_supply db8500_esram12_consumers[] = { | |
2821 | REGULATOR_SUPPLY("esram12", "cm_control"), | |
2822 | }; | |
2823 | ||
2824 | /* ESRAM3 and 4 regulator switch */ | |
2825 | static struct regulator_consumer_supply db8500_esram34_consumers[] = { | |
2826 | REGULATOR_SUPPLY("v-esram34", "mcde"), | |
2827 | REGULATOR_SUPPLY("esram34", "cm_control"), | |
992b133a | 2828 | REGULATOR_SUPPLY("lcla_esram", "dma40.0"), |
1032fbfd BJ |
2829 | }; |
2830 | ||
2831 | static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { | |
2832 | [DB8500_REGULATOR_VAPE] = { | |
2833 | .constraints = { | |
2834 | .name = "db8500-vape", | |
2835 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1e45860f | 2836 | .always_on = true, |
1032fbfd BJ |
2837 | }, |
2838 | .consumer_supplies = db8500_vape_consumers, | |
2839 | .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), | |
2840 | }, | |
2841 | [DB8500_REGULATOR_VARM] = { | |
2842 | .constraints = { | |
2843 | .name = "db8500-varm", | |
2844 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2845 | }, | |
2846 | }, | |
2847 | [DB8500_REGULATOR_VMODEM] = { | |
2848 | .constraints = { | |
2849 | .name = "db8500-vmodem", | |
2850 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2851 | }, | |
2852 | }, | |
2853 | [DB8500_REGULATOR_VPLL] = { | |
2854 | .constraints = { | |
2855 | .name = "db8500-vpll", | |
2856 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2857 | }, | |
2858 | }, | |
2859 | [DB8500_REGULATOR_VSMPS1] = { | |
2860 | .constraints = { | |
2861 | .name = "db8500-vsmps1", | |
2862 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2863 | }, | |
2864 | }, | |
2865 | [DB8500_REGULATOR_VSMPS2] = { | |
2866 | .constraints = { | |
2867 | .name = "db8500-vsmps2", | |
2868 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2869 | }, | |
2870 | .consumer_supplies = db8500_vsmps2_consumers, | |
2871 | .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), | |
2872 | }, | |
2873 | [DB8500_REGULATOR_VSMPS3] = { | |
2874 | .constraints = { | |
2875 | .name = "db8500-vsmps3", | |
2876 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2877 | }, | |
2878 | }, | |
2879 | [DB8500_REGULATOR_VRF1] = { | |
2880 | .constraints = { | |
2881 | .name = "db8500-vrf1", | |
2882 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2883 | }, | |
2884 | }, | |
2885 | [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { | |
992b133a | 2886 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2887 | .constraints = { |
2888 | .name = "db8500-sva-mmdsp", | |
2889 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2890 | }, | |
624e87c2 BJ |
2891 | .consumer_supplies = db8500_svammdsp_consumers, |
2892 | .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), | |
1032fbfd BJ |
2893 | }, |
2894 | [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { | |
2895 | .constraints = { | |
2896 | /* "ret" means "retention" */ | |
2897 | .name = "db8500-sva-mmdsp-ret", | |
2898 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2899 | }, | |
2900 | }, | |
2901 | [DB8500_REGULATOR_SWITCH_SVAPIPE] = { | |
992b133a | 2902 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2903 | .constraints = { |
2904 | .name = "db8500-sva-pipe", | |
2905 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2906 | }, | |
624e87c2 BJ |
2907 | .consumer_supplies = db8500_svapipe_consumers, |
2908 | .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), | |
1032fbfd BJ |
2909 | }, |
2910 | [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { | |
992b133a | 2911 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2912 | .constraints = { |
2913 | .name = "db8500-sia-mmdsp", | |
2914 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2915 | }, | |
624e87c2 BJ |
2916 | .consumer_supplies = db8500_siammdsp_consumers, |
2917 | .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), | |
1032fbfd BJ |
2918 | }, |
2919 | [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { | |
2920 | .constraints = { | |
2921 | .name = "db8500-sia-mmdsp-ret", | |
2922 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2923 | }, | |
2924 | }, | |
2925 | [DB8500_REGULATOR_SWITCH_SIAPIPE] = { | |
992b133a | 2926 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2927 | .constraints = { |
2928 | .name = "db8500-sia-pipe", | |
2929 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2930 | }, | |
624e87c2 BJ |
2931 | .consumer_supplies = db8500_siapipe_consumers, |
2932 | .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), | |
1032fbfd BJ |
2933 | }, |
2934 | [DB8500_REGULATOR_SWITCH_SGA] = { | |
2935 | .supply_regulator = "db8500-vape", | |
2936 | .constraints = { | |
2937 | .name = "db8500-sga", | |
2938 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2939 | }, | |
624e87c2 BJ |
2940 | .consumer_supplies = db8500_sga_consumers, |
2941 | .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), | |
2942 | ||
1032fbfd BJ |
2943 | }, |
2944 | [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { | |
2945 | .supply_regulator = "db8500-vape", | |
2946 | .constraints = { | |
2947 | .name = "db8500-b2r2-mcde", | |
2948 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2949 | }, | |
2950 | .consumer_supplies = db8500_b2r2_mcde_consumers, | |
2951 | .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), | |
2952 | }, | |
2953 | [DB8500_REGULATOR_SWITCH_ESRAM12] = { | |
992b133a BJ |
2954 | /* |
2955 | * esram12 is set in retention and supplied by Vsafe when Vape is off, | |
2956 | * no need to hold Vape | |
2957 | */ | |
1032fbfd BJ |
2958 | .constraints = { |
2959 | .name = "db8500-esram12", | |
2960 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2961 | }, | |
624e87c2 BJ |
2962 | .consumer_supplies = db8500_esram12_consumers, |
2963 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), | |
1032fbfd BJ |
2964 | }, |
2965 | [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { | |
2966 | .constraints = { | |
2967 | .name = "db8500-esram12-ret", | |
2968 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2969 | }, | |
2970 | }, | |
2971 | [DB8500_REGULATOR_SWITCH_ESRAM34] = { | |
992b133a BJ |
2972 | /* |
2973 | * esram34 is set in retention and supplied by Vsafe when Vape is off, | |
2974 | * no need to hold Vape | |
2975 | */ | |
1032fbfd BJ |
2976 | .constraints = { |
2977 | .name = "db8500-esram34", | |
2978 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2979 | }, | |
624e87c2 BJ |
2980 | .consumer_supplies = db8500_esram34_consumers, |
2981 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), | |
1032fbfd BJ |
2982 | }, |
2983 | [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { | |
2984 | .constraints = { | |
2985 | .name = "db8500-esram34-ret", | |
2986 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2987 | }, | |
2988 | }, | |
2989 | }; | |
2990 | ||
6d11d135 LJ |
2991 | static struct resource ab8500_resources[] = { |
2992 | [0] = { | |
2993 | .start = IRQ_DB8500_AB8500, | |
2994 | .end = IRQ_DB8500_AB8500, | |
2995 | .flags = IORESOURCE_IRQ | |
2996 | } | |
2997 | }; | |
2998 | ||
b3aac62b FB |
2999 | static struct ux500_wdt_data db8500_wdt_pdata = { |
3000 | .timeout = 600, /* 10 minutes */ | |
3001 | .has_28_bits_resolution = true, | |
3002 | }; | |
3003 | ||
3df57bcf MN |
3004 | static struct mfd_cell db8500_prcmu_devs[] = { |
3005 | { | |
3006 | .name = "db8500-prcmu-regulators", | |
5d90322b | 3007 | .of_compatible = "stericsson,db8500-prcmu-regulator", |
1ed7891f MW |
3008 | .platform_data = &db8500_regulators, |
3009 | .pdata_size = sizeof(db8500_regulators), | |
3df57bcf MN |
3010 | }, |
3011 | { | |
84c7c20f LJ |
3012 | .name = "cpufreq-ux500", |
3013 | .of_compatible = "stericsson,cpufreq-ux500", | |
c280f45f UH |
3014 | .platform_data = &db8500_cpufreq_table, |
3015 | .pdata_size = sizeof(db8500_cpufreq_table), | |
3df57bcf | 3016 | }, |
b3aac62b FB |
3017 | { |
3018 | .name = "ux500_wdt", | |
3019 | .platform_data = &db8500_wdt_pdata, | |
3020 | .pdata_size = sizeof(db8500_wdt_pdata), | |
3021 | .id = -1, | |
3022 | }, | |
6d11d135 LJ |
3023 | { |
3024 | .name = "ab8500-core", | |
3025 | .of_compatible = "stericsson,ab8500", | |
3026 | .num_resources = ARRAY_SIZE(ab8500_resources), | |
3027 | .resources = ab8500_resources, | |
3028 | .id = AB8500_VERSION_AB8500, | |
3029 | }, | |
3df57bcf MN |
3030 | }; |
3031 | ||
c280f45f UH |
3032 | static void db8500_prcmu_update_cpufreq(void) |
3033 | { | |
3034 | if (prcmu_has_arm_maxopp()) { | |
3035 | db8500_cpufreq_table[3].frequency = 1000000; | |
3036 | db8500_cpufreq_table[3].index = ARM_MAX_OPP; | |
3037 | } | |
3038 | } | |
3039 | ||
3df57bcf MN |
3040 | /** |
3041 | * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic | |
3042 | * | |
3043 | */ | |
f791be49 | 3044 | static int db8500_prcmu_probe(struct platform_device *pdev) |
3df57bcf | 3045 | { |
ca7edd16 | 3046 | struct device_node *np = pdev->dev.of_node; |
05ec260e | 3047 | struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev); |
3a8e39c9 | 3048 | int irq = 0, err = 0, i; |
05ec260e | 3049 | struct resource *res; |
3df57bcf | 3050 | |
b047d981 LW |
3051 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu"); |
3052 | if (!res) { | |
3053 | dev_err(&pdev->dev, "no prcmu memory region provided\n"); | |
3054 | return -ENOENT; | |
3055 | } | |
3056 | prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | |
3057 | if (!prcmu_base) { | |
3058 | dev_err(&pdev->dev, | |
3059 | "failed to ioremap prcmu register memory\n"); | |
3060 | return -ENOENT; | |
3061 | } | |
0508901c | 3062 | init_prcm_registers(); |
05ec260e LW |
3063 | dbx500_fw_version_init(pdev, pdata->version_offset); |
3064 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); | |
3065 | if (!res) { | |
3066 | dev_err(&pdev->dev, "no prcmu tcdm region provided\n"); | |
3067 | return -ENOENT; | |
3068 | } | |
3069 | tcdm_base = devm_ioremap(&pdev->dev, res->start, | |
3070 | resource_size(res)); | |
3071 | ||
e3726fcf | 3072 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
c553b3ca | 3073 | writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); |
3df57bcf | 3074 | |
05ec260e LW |
3075 | irq = platform_get_irq(pdev, 0); |
3076 | if (irq <= 0) { | |
3077 | dev_err(&pdev->dev, "no prcmu irq provided\n"); | |
3078 | return -ENOENT; | |
3079 | } | |
ca7edd16 LJ |
3080 | |
3081 | err = request_threaded_irq(irq, prcmu_irq_handler, | |
3082 | prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); | |
3df57bcf MN |
3083 | if (err < 0) { |
3084 | pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); | |
3085 | err = -EBUSY; | |
3086 | goto no_irq_return; | |
3087 | } | |
3088 | ||
f3f1f0a1 LJ |
3089 | db8500_irq_init(np); |
3090 | ||
3a8e39c9 LJ |
3091 | for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) { |
3092 | if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) { | |
05ec260e | 3093 | db8500_prcmu_devs[i].platform_data = pdata->ab_platdata; |
3c1534c7 | 3094 | db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data); |
3a8e39c9 LJ |
3095 | } |
3096 | } | |
3097 | ||
7a4f2609 | 3098 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); |
3df57bcf | 3099 | |
c280f45f UH |
3100 | db8500_prcmu_update_cpufreq(); |
3101 | ||
5d90322b | 3102 | err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, |
0848c94f | 3103 | ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL); |
5d90322b LJ |
3104 | if (err) { |
3105 | pr_err("prcmu: Failed to add subdevices\n"); | |
3106 | return err; | |
ca7edd16 | 3107 | } |
e3726fcf | 3108 | |
ca7edd16 | 3109 | pr_info("DB8500 PRCMU initialized\n"); |
3df57bcf MN |
3110 | |
3111 | no_irq_return: | |
3112 | return err; | |
3113 | } | |
3c144762 LJ |
3114 | static const struct of_device_id db8500_prcmu_match[] = { |
3115 | { .compatible = "stericsson,db8500-prcmu"}, | |
3116 | { }, | |
3117 | }; | |
3df57bcf MN |
3118 | |
3119 | static struct platform_driver db8500_prcmu_driver = { | |
3120 | .driver = { | |
3121 | .name = "db8500-prcmu", | |
3122 | .owner = THIS_MODULE, | |
3c144762 | 3123 | .of_match_table = db8500_prcmu_match, |
3df57bcf | 3124 | }, |
9fc63f67 | 3125 | .probe = db8500_prcmu_probe, |
3df57bcf MN |
3126 | }; |
3127 | ||
3128 | static int __init db8500_prcmu_init(void) | |
3129 | { | |
9fc63f67 | 3130 | return platform_driver_register(&db8500_prcmu_driver); |
e3726fcf LW |
3131 | } |
3132 | ||
a661aca4 | 3133 | core_initcall(db8500_prcmu_init); |
3df57bcf MN |
3134 | |
3135 | MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); | |
3136 | MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); | |
3137 | MODULE_LICENSE("GPL v2"); |