Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
9b40b030 | 2 | /* |
656211b1 ST |
3 | * Core, IRQ and I2C device driver for DA9061 and DA9062 PMICs |
4 | * Copyright (C) 2015-2017 Dialog Semiconductor | |
9b40b030 T |
5 | */ |
6 | ||
7 | #include <linux/kernel.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/regmap.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/mfd/core.h> | |
15 | #include <linux/i2c.h> | |
16 | #include <linux/mfd/da9062/core.h> | |
17 | #include <linux/mfd/da9062/registers.h> | |
18 | #include <linux/regulator/of_regulator.h> | |
19 | ||
20 | #define DA9062_REG_EVENT_A_OFFSET 0 | |
21 | #define DA9062_REG_EVENT_B_OFFSET 1 | |
22 | #define DA9062_REG_EVENT_C_OFFSET 2 | |
23 | ||
656211b1 ST |
24 | static struct regmap_irq da9061_irqs[] = { |
25 | /* EVENT A */ | |
26 | [DA9061_IRQ_ONKEY] = { | |
27 | .reg_offset = DA9062_REG_EVENT_A_OFFSET, | |
28 | .mask = DA9062AA_M_NONKEY_MASK, | |
29 | }, | |
30 | [DA9061_IRQ_WDG_WARN] = { | |
31 | .reg_offset = DA9062_REG_EVENT_A_OFFSET, | |
32 | .mask = DA9062AA_M_WDG_WARN_MASK, | |
33 | }, | |
34 | [DA9061_IRQ_SEQ_RDY] = { | |
35 | .reg_offset = DA9062_REG_EVENT_A_OFFSET, | |
36 | .mask = DA9062AA_M_SEQ_RDY_MASK, | |
37 | }, | |
38 | /* EVENT B */ | |
39 | [DA9061_IRQ_TEMP] = { | |
40 | .reg_offset = DA9062_REG_EVENT_B_OFFSET, | |
41 | .mask = DA9062AA_M_TEMP_MASK, | |
42 | }, | |
43 | [DA9061_IRQ_LDO_LIM] = { | |
44 | .reg_offset = DA9062_REG_EVENT_B_OFFSET, | |
45 | .mask = DA9062AA_M_LDO_LIM_MASK, | |
46 | }, | |
47 | [DA9061_IRQ_DVC_RDY] = { | |
48 | .reg_offset = DA9062_REG_EVENT_B_OFFSET, | |
49 | .mask = DA9062AA_M_DVC_RDY_MASK, | |
50 | }, | |
51 | [DA9061_IRQ_VDD_WARN] = { | |
52 | .reg_offset = DA9062_REG_EVENT_B_OFFSET, | |
53 | .mask = DA9062AA_M_VDD_WARN_MASK, | |
54 | }, | |
55 | /* EVENT C */ | |
56 | [DA9061_IRQ_GPI0] = { | |
57 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
58 | .mask = DA9062AA_M_GPI0_MASK, | |
59 | }, | |
60 | [DA9061_IRQ_GPI1] = { | |
61 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
62 | .mask = DA9062AA_M_GPI1_MASK, | |
63 | }, | |
64 | [DA9061_IRQ_GPI2] = { | |
65 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
66 | .mask = DA9062AA_M_GPI2_MASK, | |
67 | }, | |
68 | [DA9061_IRQ_GPI3] = { | |
69 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
70 | .mask = DA9062AA_M_GPI3_MASK, | |
71 | }, | |
72 | [DA9061_IRQ_GPI4] = { | |
73 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
74 | .mask = DA9062AA_M_GPI4_MASK, | |
75 | }, | |
76 | }; | |
77 | ||
78 | static struct regmap_irq_chip da9061_irq_chip = { | |
79 | .name = "da9061-irq", | |
80 | .irqs = da9061_irqs, | |
81 | .num_irqs = DA9061_NUM_IRQ, | |
82 | .num_regs = 3, | |
83 | .status_base = DA9062AA_EVENT_A, | |
84 | .mask_base = DA9062AA_IRQ_MASK_A, | |
85 | .ack_base = DA9062AA_EVENT_A, | |
86 | }; | |
87 | ||
9b40b030 T |
88 | static struct regmap_irq da9062_irqs[] = { |
89 | /* EVENT A */ | |
90 | [DA9062_IRQ_ONKEY] = { | |
91 | .reg_offset = DA9062_REG_EVENT_A_OFFSET, | |
92 | .mask = DA9062AA_M_NONKEY_MASK, | |
93 | }, | |
94 | [DA9062_IRQ_ALARM] = { | |
95 | .reg_offset = DA9062_REG_EVENT_A_OFFSET, | |
96 | .mask = DA9062AA_M_ALARM_MASK, | |
97 | }, | |
98 | [DA9062_IRQ_TICK] = { | |
99 | .reg_offset = DA9062_REG_EVENT_A_OFFSET, | |
100 | .mask = DA9062AA_M_TICK_MASK, | |
101 | }, | |
102 | [DA9062_IRQ_WDG_WARN] = { | |
103 | .reg_offset = DA9062_REG_EVENT_A_OFFSET, | |
104 | .mask = DA9062AA_M_WDG_WARN_MASK, | |
105 | }, | |
106 | [DA9062_IRQ_SEQ_RDY] = { | |
107 | .reg_offset = DA9062_REG_EVENT_A_OFFSET, | |
108 | .mask = DA9062AA_M_SEQ_RDY_MASK, | |
109 | }, | |
110 | /* EVENT B */ | |
111 | [DA9062_IRQ_TEMP] = { | |
112 | .reg_offset = DA9062_REG_EVENT_B_OFFSET, | |
113 | .mask = DA9062AA_M_TEMP_MASK, | |
114 | }, | |
115 | [DA9062_IRQ_LDO_LIM] = { | |
116 | .reg_offset = DA9062_REG_EVENT_B_OFFSET, | |
117 | .mask = DA9062AA_M_LDO_LIM_MASK, | |
118 | }, | |
119 | [DA9062_IRQ_DVC_RDY] = { | |
120 | .reg_offset = DA9062_REG_EVENT_B_OFFSET, | |
121 | .mask = DA9062AA_M_DVC_RDY_MASK, | |
122 | }, | |
123 | [DA9062_IRQ_VDD_WARN] = { | |
124 | .reg_offset = DA9062_REG_EVENT_B_OFFSET, | |
125 | .mask = DA9062AA_M_VDD_WARN_MASK, | |
126 | }, | |
127 | /* EVENT C */ | |
128 | [DA9062_IRQ_GPI0] = { | |
129 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
130 | .mask = DA9062AA_M_GPI0_MASK, | |
131 | }, | |
132 | [DA9062_IRQ_GPI1] = { | |
133 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
134 | .mask = DA9062AA_M_GPI1_MASK, | |
135 | }, | |
136 | [DA9062_IRQ_GPI2] = { | |
137 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
138 | .mask = DA9062AA_M_GPI2_MASK, | |
139 | }, | |
140 | [DA9062_IRQ_GPI3] = { | |
141 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
142 | .mask = DA9062AA_M_GPI3_MASK, | |
143 | }, | |
144 | [DA9062_IRQ_GPI4] = { | |
145 | .reg_offset = DA9062_REG_EVENT_C_OFFSET, | |
146 | .mask = DA9062AA_M_GPI4_MASK, | |
147 | }, | |
148 | }; | |
149 | ||
150 | static struct regmap_irq_chip da9062_irq_chip = { | |
151 | .name = "da9062-irq", | |
152 | .irqs = da9062_irqs, | |
153 | .num_irqs = DA9062_NUM_IRQ, | |
154 | .num_regs = 3, | |
155 | .status_base = DA9062AA_EVENT_A, | |
156 | .mask_base = DA9062AA_IRQ_MASK_A, | |
157 | .ack_base = DA9062AA_EVENT_A, | |
158 | }; | |
159 | ||
656211b1 ST |
160 | static struct resource da9061_core_resources[] = { |
161 | DEFINE_RES_IRQ_NAMED(DA9061_IRQ_VDD_WARN, "VDD_WARN"), | |
162 | }; | |
163 | ||
164 | static struct resource da9061_regulators_resources[] = { | |
165 | DEFINE_RES_IRQ_NAMED(DA9061_IRQ_LDO_LIM, "LDO_LIM"), | |
166 | }; | |
167 | ||
168 | static struct resource da9061_thermal_resources[] = { | |
169 | DEFINE_RES_IRQ_NAMED(DA9061_IRQ_TEMP, "THERMAL"), | |
170 | }; | |
171 | ||
172 | static struct resource da9061_wdt_resources[] = { | |
173 | DEFINE_RES_IRQ_NAMED(DA9061_IRQ_WDG_WARN, "WD_WARN"), | |
174 | }; | |
175 | ||
176 | static struct resource da9061_onkey_resources[] = { | |
177 | DEFINE_RES_IRQ_NAMED(DA9061_IRQ_ONKEY, "ONKEY"), | |
178 | }; | |
179 | ||
180 | static const struct mfd_cell da9061_devs[] = { | |
181 | { | |
182 | .name = "da9061-core", | |
183 | .num_resources = ARRAY_SIZE(da9061_core_resources), | |
184 | .resources = da9061_core_resources, | |
185 | }, | |
186 | { | |
187 | .name = "da9062-regulators", | |
188 | .num_resources = ARRAY_SIZE(da9061_regulators_resources), | |
189 | .resources = da9061_regulators_resources, | |
190 | }, | |
191 | { | |
192 | .name = "da9061-watchdog", | |
193 | .num_resources = ARRAY_SIZE(da9061_wdt_resources), | |
194 | .resources = da9061_wdt_resources, | |
195 | .of_compatible = "dlg,da9061-watchdog", | |
196 | }, | |
197 | { | |
198 | .name = "da9061-thermal", | |
199 | .num_resources = ARRAY_SIZE(da9061_thermal_resources), | |
200 | .resources = da9061_thermal_resources, | |
201 | .of_compatible = "dlg,da9061-thermal", | |
202 | }, | |
203 | { | |
204 | .name = "da9061-onkey", | |
205 | .num_resources = ARRAY_SIZE(da9061_onkey_resources), | |
206 | .resources = da9061_onkey_resources, | |
207 | .of_compatible = "dlg,da9061-onkey", | |
208 | }, | |
209 | }; | |
210 | ||
9b40b030 T |
211 | static struct resource da9062_core_resources[] = { |
212 | DEFINE_RES_NAMED(DA9062_IRQ_VDD_WARN, 1, "VDD_WARN", IORESOURCE_IRQ), | |
213 | }; | |
214 | ||
215 | static struct resource da9062_regulators_resources[] = { | |
216 | DEFINE_RES_NAMED(DA9062_IRQ_LDO_LIM, 1, "LDO_LIM", IORESOURCE_IRQ), | |
217 | }; | |
218 | ||
219 | static struct resource da9062_thermal_resources[] = { | |
220 | DEFINE_RES_NAMED(DA9062_IRQ_TEMP, 1, "THERMAL", IORESOURCE_IRQ), | |
221 | }; | |
222 | ||
223 | static struct resource da9062_wdt_resources[] = { | |
224 | DEFINE_RES_NAMED(DA9062_IRQ_WDG_WARN, 1, "WD_WARN", IORESOURCE_IRQ), | |
225 | }; | |
226 | ||
ca1ce176 T |
227 | static struct resource da9062_rtc_resources[] = { |
228 | DEFINE_RES_NAMED(DA9062_IRQ_ALARM, 1, "ALARM", IORESOURCE_IRQ), | |
229 | DEFINE_RES_NAMED(DA9062_IRQ_TICK, 1, "TICK", IORESOURCE_IRQ), | |
230 | }; | |
231 | ||
68b6fd02 T |
232 | static struct resource da9062_onkey_resources[] = { |
233 | DEFINE_RES_NAMED(DA9062_IRQ_ONKEY, 1, "ONKEY", IORESOURCE_IRQ), | |
234 | }; | |
235 | ||
9b40b030 T |
236 | static const struct mfd_cell da9062_devs[] = { |
237 | { | |
238 | .name = "da9062-core", | |
239 | .num_resources = ARRAY_SIZE(da9062_core_resources), | |
240 | .resources = da9062_core_resources, | |
241 | }, | |
242 | { | |
243 | .name = "da9062-regulators", | |
244 | .num_resources = ARRAY_SIZE(da9062_regulators_resources), | |
245 | .resources = da9062_regulators_resources, | |
246 | }, | |
247 | { | |
248 | .name = "da9062-watchdog", | |
249 | .num_resources = ARRAY_SIZE(da9062_wdt_resources), | |
250 | .resources = da9062_wdt_resources, | |
251 | .of_compatible = "dlg,da9062-wdt", | |
252 | }, | |
253 | { | |
254 | .name = "da9062-thermal", | |
255 | .num_resources = ARRAY_SIZE(da9062_thermal_resources), | |
256 | .resources = da9062_thermal_resources, | |
257 | .of_compatible = "dlg,da9062-thermal", | |
258 | }, | |
ca1ce176 T |
259 | { |
260 | .name = "da9062-rtc", | |
261 | .num_resources = ARRAY_SIZE(da9062_rtc_resources), | |
262 | .resources = da9062_rtc_resources, | |
263 | .of_compatible = "dlg,da9062-rtc", | |
264 | }, | |
68b6fd02 T |
265 | { |
266 | .name = "da9062-onkey", | |
267 | .num_resources = ARRAY_SIZE(da9062_onkey_resources), | |
268 | .resources = da9062_onkey_resources, | |
269 | .of_compatible = "dlg,da9062-onkey", | |
270 | }, | |
9b40b030 T |
271 | }; |
272 | ||
273 | static int da9062_clear_fault_log(struct da9062 *chip) | |
274 | { | |
275 | int ret; | |
276 | int fault_log; | |
277 | ||
278 | ret = regmap_read(chip->regmap, DA9062AA_FAULT_LOG, &fault_log); | |
279 | if (ret < 0) | |
280 | return ret; | |
281 | ||
282 | if (fault_log) { | |
283 | if (fault_log & DA9062AA_TWD_ERROR_MASK) | |
284 | dev_dbg(chip->dev, "Fault log entry detected: TWD_ERROR\n"); | |
285 | if (fault_log & DA9062AA_POR_MASK) | |
286 | dev_dbg(chip->dev, "Fault log entry detected: POR\n"); | |
287 | if (fault_log & DA9062AA_VDD_FAULT_MASK) | |
288 | dev_dbg(chip->dev, "Fault log entry detected: VDD_FAULT\n"); | |
289 | if (fault_log & DA9062AA_VDD_START_MASK) | |
290 | dev_dbg(chip->dev, "Fault log entry detected: VDD_START\n"); | |
291 | if (fault_log & DA9062AA_TEMP_CRIT_MASK) | |
292 | dev_dbg(chip->dev, "Fault log entry detected: TEMP_CRIT\n"); | |
293 | if (fault_log & DA9062AA_KEY_RESET_MASK) | |
294 | dev_dbg(chip->dev, "Fault log entry detected: KEY_RESET\n"); | |
295 | if (fault_log & DA9062AA_NSHUTDOWN_MASK) | |
296 | dev_dbg(chip->dev, "Fault log entry detected: NSHUTDOWN\n"); | |
297 | if (fault_log & DA9062AA_WAIT_SHUT_MASK) | |
298 | dev_dbg(chip->dev, "Fault log entry detected: WAIT_SHUT\n"); | |
299 | ||
300 | ret = regmap_write(chip->regmap, DA9062AA_FAULT_LOG, | |
301 | fault_log); | |
302 | } | |
303 | ||
304 | return ret; | |
305 | } | |
306 | ||
6f44b148 | 307 | static int da9062_get_device_type(struct da9062 *chip) |
9b40b030 | 308 | { |
656211b1 ST |
309 | int device_id, variant_id, variant_mrc, variant_vrc; |
310 | char *type; | |
9b40b030 T |
311 | int ret; |
312 | ||
313 | ret = regmap_read(chip->regmap, DA9062AA_DEVICE_ID, &device_id); | |
314 | if (ret < 0) { | |
315 | dev_err(chip->dev, "Cannot read chip ID.\n"); | |
316 | return -EIO; | |
317 | } | |
318 | if (device_id != DA9062_PMIC_DEVICE_ID) { | |
319 | dev_err(chip->dev, "Invalid device ID: 0x%02x\n", device_id); | |
320 | return -ENODEV; | |
321 | } | |
322 | ||
323 | ret = regmap_read(chip->regmap, DA9062AA_VARIANT_ID, &variant_id); | |
324 | if (ret < 0) { | |
325 | dev_err(chip->dev, "Cannot read chip variant id.\n"); | |
326 | return -EIO; | |
327 | } | |
328 | ||
656211b1 ST |
329 | variant_vrc = (variant_id & DA9062AA_VRC_MASK) >> DA9062AA_VRC_SHIFT; |
330 | ||
331 | switch (variant_vrc) { | |
332 | case DA9062_PMIC_VARIANT_VRC_DA9061: | |
333 | type = "DA9061"; | |
334 | break; | |
335 | case DA9062_PMIC_VARIANT_VRC_DA9062: | |
336 | type = "DA9062"; | |
337 | break; | |
338 | default: | |
339 | type = "Unknown"; | |
340 | break; | |
341 | } | |
342 | ||
9b40b030 | 343 | dev_info(chip->dev, |
656211b1 ST |
344 | "Device detected (device-ID: 0x%02X, var-ID: 0x%02X, %s)\n", |
345 | device_id, variant_id, type); | |
9b40b030 T |
346 | |
347 | variant_mrc = (variant_id & DA9062AA_MRC_MASK) >> DA9062AA_MRC_SHIFT; | |
348 | ||
349 | if (variant_mrc < DA9062_PMIC_VARIANT_MRC_AA) { | |
350 | dev_err(chip->dev, | |
351 | "Cannot support variant MRC: 0x%02X\n", variant_mrc); | |
352 | return -ENODEV; | |
353 | } | |
354 | ||
355 | return ret; | |
356 | } | |
357 | ||
656211b1 | 358 | static const struct regmap_range da9061_aa_readable_ranges[] = { |
b16d2393 ST |
359 | regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B), |
360 | regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C), | |
361 | regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C), | |
362 | regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4), | |
363 | regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4), | |
364 | regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT), | |
365 | regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT), | |
366 | regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT), | |
367 | regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1), | |
368 | regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3), | |
369 | regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15), | |
370 | regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31), | |
371 | regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT), | |
372 | regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C), | |
373 | regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG), | |
374 | regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A), | |
375 | regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A), | |
376 | regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A), | |
377 | regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B), | |
378 | regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B), | |
379 | regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B), | |
380 | regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E), | |
381 | regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K), | |
382 | regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M), | |
383 | regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19), | |
384 | regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID), | |
656211b1 ST |
385 | }; |
386 | ||
387 | static const struct regmap_range da9061_aa_writeable_ranges[] = { | |
b16d2393 ST |
388 | regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON), |
389 | regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C), | |
390 | regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C), | |
391 | regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4), | |
392 | regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4), | |
393 | regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT), | |
394 | regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT), | |
395 | regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT), | |
396 | regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1), | |
397 | regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3), | |
398 | regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15), | |
399 | regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31), | |
400 | regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT), | |
401 | regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C), | |
402 | regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG), | |
403 | regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A), | |
404 | regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A), | |
405 | regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A), | |
406 | regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B), | |
407 | regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B), | |
408 | regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B), | |
409 | regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19), | |
656211b1 ST |
410 | }; |
411 | ||
412 | static const struct regmap_range da9061_aa_volatile_ranges[] = { | |
b16d2393 ST |
413 | regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B), |
414 | regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C), | |
415 | regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B), | |
416 | regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F), | |
417 | regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT), | |
418 | regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT), | |
419 | regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT), | |
420 | regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1), | |
421 | regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ), | |
656211b1 ST |
422 | }; |
423 | ||
424 | static const struct regmap_access_table da9061_aa_readable_table = { | |
425 | .yes_ranges = da9061_aa_readable_ranges, | |
426 | .n_yes_ranges = ARRAY_SIZE(da9061_aa_readable_ranges), | |
427 | }; | |
428 | ||
429 | static const struct regmap_access_table da9061_aa_writeable_table = { | |
430 | .yes_ranges = da9061_aa_writeable_ranges, | |
431 | .n_yes_ranges = ARRAY_SIZE(da9061_aa_writeable_ranges), | |
432 | }; | |
433 | ||
434 | static const struct regmap_access_table da9061_aa_volatile_table = { | |
435 | .yes_ranges = da9061_aa_volatile_ranges, | |
436 | .n_yes_ranges = ARRAY_SIZE(da9061_aa_volatile_ranges), | |
437 | }; | |
438 | ||
439 | static const struct regmap_range_cfg da9061_range_cfg[] = { | |
440 | { | |
441 | .range_min = DA9062AA_PAGE_CON, | |
442 | .range_max = DA9062AA_CONFIG_ID, | |
443 | .selector_reg = DA9062AA_PAGE_CON, | |
444 | .selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT, | |
445 | .selector_shift = DA9062_I2C_PAGE_SEL_SHIFT, | |
446 | .window_start = 0, | |
447 | .window_len = 256, | |
448 | } | |
449 | }; | |
450 | ||
451 | static struct regmap_config da9061_regmap_config = { | |
452 | .reg_bits = 8, | |
453 | .val_bits = 8, | |
454 | .ranges = da9061_range_cfg, | |
455 | .num_ranges = ARRAY_SIZE(da9061_range_cfg), | |
456 | .max_register = DA9062AA_CONFIG_ID, | |
457 | .cache_type = REGCACHE_RBTREE, | |
458 | .rd_table = &da9061_aa_readable_table, | |
459 | .wr_table = &da9061_aa_writeable_table, | |
460 | .volatile_table = &da9061_aa_volatile_table, | |
461 | }; | |
462 | ||
9b40b030 | 463 | static const struct regmap_range da9062_aa_readable_ranges[] = { |
b16d2393 ST |
464 | regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B), |
465 | regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C), | |
466 | regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C), | |
467 | regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4), | |
468 | regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT), | |
469 | regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT), | |
470 | regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT), | |
471 | regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1), | |
472 | regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D), | |
473 | regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3), | |
474 | regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15), | |
475 | regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31), | |
476 | regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG), | |
477 | regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A), | |
478 | regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A), | |
479 | regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A), | |
480 | regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B), | |
481 | regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B), | |
482 | regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B), | |
483 | regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT), | |
484 | regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E), | |
485 | regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K), | |
486 | regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M), | |
487 | regmap_reg_range(DA9062AA_TRIM_CLDR, DA9062AA_GP_ID_19), | |
488 | regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID), | |
9b40b030 T |
489 | }; |
490 | ||
491 | static const struct regmap_range da9062_aa_writeable_ranges[] = { | |
b16d2393 ST |
492 | regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON), |
493 | regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C), | |
494 | regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C), | |
495 | regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4), | |
496 | regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT), | |
497 | regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT), | |
498 | regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT), | |
499 | regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1), | |
500 | regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_ALARM_Y), | |
501 | regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3), | |
502 | regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15), | |
503 | regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31), | |
504 | regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG), | |
505 | regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A), | |
506 | regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A), | |
507 | regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A), | |
508 | regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B), | |
509 | regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B), | |
510 | regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B), | |
511 | regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT), | |
512 | regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19), | |
9b40b030 T |
513 | }; |
514 | ||
515 | static const struct regmap_range da9062_aa_volatile_ranges[] = { | |
b16d2393 ST |
516 | regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B), |
517 | regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C), | |
518 | regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B), | |
519 | regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F), | |
520 | regmap_reg_range(DA9062AA_BUCK2_CONT, DA9062AA_BUCK4_CONT), | |
521 | regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT), | |
522 | regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT), | |
523 | regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1), | |
524 | regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D), | |
525 | regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ), | |
526 | regmap_reg_range(DA9062AA_EN_32K, DA9062AA_EN_32K), | |
9b40b030 T |
527 | }; |
528 | ||
529 | static const struct regmap_access_table da9062_aa_readable_table = { | |
530 | .yes_ranges = da9062_aa_readable_ranges, | |
531 | .n_yes_ranges = ARRAY_SIZE(da9062_aa_readable_ranges), | |
532 | }; | |
533 | ||
534 | static const struct regmap_access_table da9062_aa_writeable_table = { | |
535 | .yes_ranges = da9062_aa_writeable_ranges, | |
536 | .n_yes_ranges = ARRAY_SIZE(da9062_aa_writeable_ranges), | |
537 | }; | |
538 | ||
539 | static const struct regmap_access_table da9062_aa_volatile_table = { | |
540 | .yes_ranges = da9062_aa_volatile_ranges, | |
541 | .n_yes_ranges = ARRAY_SIZE(da9062_aa_volatile_ranges), | |
542 | }; | |
543 | ||
544 | static const struct regmap_range_cfg da9062_range_cfg[] = { | |
545 | { | |
546 | .range_min = DA9062AA_PAGE_CON, | |
547 | .range_max = DA9062AA_CONFIG_ID, | |
548 | .selector_reg = DA9062AA_PAGE_CON, | |
549 | .selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT, | |
550 | .selector_shift = DA9062_I2C_PAGE_SEL_SHIFT, | |
551 | .window_start = 0, | |
552 | .window_len = 256, | |
553 | } | |
554 | }; | |
555 | ||
556 | static struct regmap_config da9062_regmap_config = { | |
557 | .reg_bits = 8, | |
558 | .val_bits = 8, | |
559 | .ranges = da9062_range_cfg, | |
560 | .num_ranges = ARRAY_SIZE(da9062_range_cfg), | |
561 | .max_register = DA9062AA_CONFIG_ID, | |
562 | .cache_type = REGCACHE_RBTREE, | |
563 | .rd_table = &da9062_aa_readable_table, | |
564 | .wr_table = &da9062_aa_writeable_table, | |
565 | .volatile_table = &da9062_aa_volatile_table, | |
566 | }; | |
567 | ||
656211b1 ST |
568 | static const struct of_device_id da9062_dt_ids[] = { |
569 | { .compatible = "dlg,da9061", .data = (void *)COMPAT_TYPE_DA9061, }, | |
570 | { .compatible = "dlg,da9062", .data = (void *)COMPAT_TYPE_DA9062, }, | |
571 | { } | |
572 | }; | |
573 | MODULE_DEVICE_TABLE(of, da9062_dt_ids); | |
574 | ||
9b40b030 T |
575 | static int da9062_i2c_probe(struct i2c_client *i2c, |
576 | const struct i2c_device_id *id) | |
577 | { | |
578 | struct da9062 *chip; | |
656211b1 | 579 | const struct of_device_id *match; |
9b40b030 | 580 | unsigned int irq_base; |
656211b1 ST |
581 | const struct mfd_cell *cell; |
582 | const struct regmap_irq_chip *irq_chip; | |
583 | const struct regmap_config *config; | |
584 | int cell_num; | |
9b40b030 T |
585 | int ret; |
586 | ||
587 | chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL); | |
588 | if (!chip) | |
589 | return -ENOMEM; | |
590 | ||
656211b1 ST |
591 | if (i2c->dev.of_node) { |
592 | match = of_match_node(da9062_dt_ids, i2c->dev.of_node); | |
593 | if (!match) | |
594 | return -EINVAL; | |
595 | ||
596 | chip->chip_type = (uintptr_t)match->data; | |
597 | } else { | |
598 | chip->chip_type = id->driver_data; | |
599 | } | |
600 | ||
9b40b030 T |
601 | i2c_set_clientdata(i2c, chip); |
602 | chip->dev = &i2c->dev; | |
603 | ||
604 | if (!i2c->irq) { | |
605 | dev_err(chip->dev, "No IRQ configured\n"); | |
606 | return -EINVAL; | |
607 | } | |
608 | ||
656211b1 ST |
609 | switch (chip->chip_type) { |
610 | case COMPAT_TYPE_DA9061: | |
611 | cell = da9061_devs; | |
612 | cell_num = ARRAY_SIZE(da9061_devs); | |
613 | irq_chip = &da9061_irq_chip; | |
614 | config = &da9061_regmap_config; | |
615 | break; | |
616 | case COMPAT_TYPE_DA9062: | |
617 | cell = da9062_devs; | |
618 | cell_num = ARRAY_SIZE(da9062_devs); | |
619 | irq_chip = &da9062_irq_chip; | |
620 | config = &da9062_regmap_config; | |
621 | break; | |
622 | default: | |
623 | dev_err(chip->dev, "Unrecognised chip type\n"); | |
624 | return -ENODEV; | |
625 | } | |
626 | ||
627 | chip->regmap = devm_regmap_init_i2c(i2c, config); | |
9b40b030 T |
628 | if (IS_ERR(chip->regmap)) { |
629 | ret = PTR_ERR(chip->regmap); | |
630 | dev_err(chip->dev, "Failed to allocate register map: %d\n", | |
631 | ret); | |
632 | return ret; | |
633 | } | |
634 | ||
635 | ret = da9062_clear_fault_log(chip); | |
636 | if (ret < 0) | |
637 | dev_warn(chip->dev, "Cannot clear fault log\n"); | |
638 | ||
6f44b148 | 639 | ret = da9062_get_device_type(chip); |
9b40b030 T |
640 | if (ret) |
641 | return ret; | |
642 | ||
643 | ret = regmap_add_irq_chip(chip->regmap, i2c->irq, | |
644 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_SHARED, | |
656211b1 | 645 | -1, irq_chip, |
9b40b030 T |
646 | &chip->regmap_irq); |
647 | if (ret) { | |
648 | dev_err(chip->dev, "Failed to request IRQ %d: %d\n", | |
649 | i2c->irq, ret); | |
650 | return ret; | |
651 | } | |
652 | ||
653 | irq_base = regmap_irq_chip_get_base(chip->regmap_irq); | |
654 | ||
656211b1 ST |
655 | ret = mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, cell, |
656 | cell_num, NULL, irq_base, | |
9b40b030 T |
657 | NULL); |
658 | if (ret) { | |
659 | dev_err(chip->dev, "Cannot register child devices\n"); | |
660 | regmap_del_irq_chip(i2c->irq, chip->regmap_irq); | |
661 | return ret; | |
662 | } | |
663 | ||
664 | return ret; | |
665 | } | |
666 | ||
667 | static int da9062_i2c_remove(struct i2c_client *i2c) | |
668 | { | |
669 | struct da9062 *chip = i2c_get_clientdata(i2c); | |
670 | ||
671 | mfd_remove_devices(chip->dev); | |
672 | regmap_del_irq_chip(i2c->irq, chip->regmap_irq); | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | static const struct i2c_device_id da9062_i2c_id[] = { | |
656211b1 ST |
678 | { "da9061", COMPAT_TYPE_DA9061 }, |
679 | { "da9062", COMPAT_TYPE_DA9062 }, | |
9b40b030 T |
680 | { }, |
681 | }; | |
682 | MODULE_DEVICE_TABLE(i2c, da9062_i2c_id); | |
683 | ||
9b40b030 T |
684 | static struct i2c_driver da9062_i2c_driver = { |
685 | .driver = { | |
686 | .name = "da9062", | |
687 | .of_match_table = of_match_ptr(da9062_dt_ids), | |
688 | }, | |
689 | .probe = da9062_i2c_probe, | |
690 | .remove = da9062_i2c_remove, | |
691 | .id_table = da9062_i2c_id, | |
692 | }; | |
693 | ||
694 | module_i2c_driver(da9062_i2c_driver); | |
695 | ||
656211b1 | 696 | MODULE_DESCRIPTION("Core device driver for Dialog DA9061 and DA9062"); |
9b40b030 T |
697 | MODULE_AUTHOR("Steve Twiss <stwiss.opensource@diasemi.com>"); |
698 | MODULE_LICENSE("GPL"); |