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Merge tag 'for-6.16-rc4-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave...
[linux-2.6-block.git] / drivers / mfd / axp20x.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
cfb61a41 2/*
4fd41151 3 * MFD core driver for the X-Powers' Power Management ICs
cfb61a41 4 *
af7e9069
JP		 5 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
6 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
7 * as well as configurable GPIOs.
cfb61a41 8 *
4fd41151
CYT		 9 * This file contains the interface independent core functions.
10 *
e740235d
CYT		 11 * Copyright (C) 2014 Carlo Caione
12 *
cfb61a41 13 * Author: Carlo Caione <carlo@caione.org>
cfb61a41
CC		 14 */
15
dcea4d5c
OS		 16#include <linux/acpi.h>
17#include <linux/bitops.h>
179dc63d 18#include <linux/delay.h>
dcea4d5c 19#include <linux/err.h>
cfb61a41
CC		 20#include <linux/interrupt.h>
21#include <linux/kernel.h>
dcea4d5c
OS		 22#include <linux/mfd/axp20x.h>
23#include <linux/mfd/core.h>
cfb61a41 24#include <linux/module.h>
830fafce
RH		 25#include <linux/of.h>
26#include <linux/property.h>
1b1305e9 27#include <linux/reboot.h>
cfb61a41 28#include <linux/regmap.h>
cfb61a41 29#include <linux/regulator/consumer.h>
cfb61a41 30
82b4d997 31#define AXP20X_OFF BIT(7)
cfb61a41 32
c0369698 33#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
696f0b3f
CYT		 34#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
35
c31e858b 36static const char * const axp20x_model_names[] = {
697a4001
AP		 37 [AXP152_ID] = "AXP152",
38 [AXP192_ID] = "AXP192",
39 [AXP202_ID] = "AXP202",
40 [AXP209_ID] = "AXP209",
41 [AXP221_ID] = "AXP221",
42 [AXP223_ID] = "AXP223",
43 [AXP288_ID] = "AXP288",
44 [AXP313A_ID] = "AXP313a",
35fec94a 45 [AXP323_ID] = "AXP323",
697a4001
AP		 46 [AXP717_ID] = "AXP717",
47 [AXP803_ID] = "AXP803",
48 [AXP806_ID] = "AXP806",
49 [AXP809_ID] = "AXP809",
50 [AXP813_ID] = "AXP813",
51 [AXP15060_ID] = "AXP15060",
af7e9069
JP		 52};
53
d8d79f8f
MS		 54static const struct regmap_range axp152_writeable_ranges[] = {
55 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
56 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
57};
58
59static const struct regmap_range axp152_volatile_ranges[] = {
60 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
61 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
62 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
63};
64
65static const struct regmap_access_table axp152_writeable_table = {
66 .yes_ranges = axp152_writeable_ranges,
67 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
68};
69
70static const struct regmap_access_table axp152_volatile_table = {
71 .yes_ranges = axp152_volatile_ranges,
72 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
73};
74
cfb61a41
CC		 75static const struct regmap_range axp20x_writeable_ranges[] = {
76 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
97602370 77 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
cfb61a41 78 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
553ed4b5 79 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
cfb61a41
CC		 80};
81
82static const struct regmap_range axp20x_volatile_ranges[] = {
553ed4b5
BP		 83 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
84 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
cfb61a41 85 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
553ed4b5
BP		 86 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
87 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
88 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
cfb61a41
CC		 89};
90
91static const struct regmap_access_table axp20x_writeable_table = {
92 .yes_ranges = axp20x_writeable_ranges,
93 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
94};
95
96static const struct regmap_access_table axp20x_volatile_table = {
97 .yes_ranges = axp20x_volatile_ranges,
98 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
99};
100
63eeabbc
AM		 101static const struct regmap_range axp192_writeable_ranges[] = {
102 regmap_reg_range(AXP192_DATACACHE(0), AXP192_DATACACHE(5)),
103 regmap_reg_range(AXP192_PWR_OUT_CTRL, AXP192_IRQ5_STATE),
104 regmap_reg_range(AXP20X_DCDC_MODE, AXP192_N_RSTO_CTRL),
105 regmap_reg_range(AXP20X_CC_CTRL, AXP20X_CC_CTRL),
106};
107
108static const struct regmap_range axp192_volatile_ranges[] = {
109 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP192_USB_OTG_STATUS),
110 regmap_reg_range(AXP192_IRQ1_STATE, AXP192_IRQ4_STATE),
111 regmap_reg_range(AXP192_IRQ5_STATE, AXP192_IRQ5_STATE),
112 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
113 regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
114 regmap_reg_range(AXP192_GPIO2_0_STATE, AXP192_GPIO2_0_STATE),
115 regmap_reg_range(AXP192_GPIO4_3_STATE, AXP192_GPIO4_3_STATE),
116 regmap_reg_range(AXP192_N_RSTO_CTRL, AXP192_N_RSTO_CTRL),
117 regmap_reg_range(AXP20X_CHRG_CC_31_24, AXP20X_CC_CTRL),
118};
119
120static const struct regmap_access_table axp192_writeable_table = {
121 .yes_ranges = axp192_writeable_ranges,
122 .n_yes_ranges = ARRAY_SIZE(axp192_writeable_ranges),
123};
124
125static const struct regmap_access_table axp192_volatile_table = {
126 .yes_ranges = axp192_volatile_ranges,
127 .n_yes_ranges = ARRAY_SIZE(axp192_volatile_ranges),
128};
129
20147f0d 130/* AXP22x ranges are shared with the AXP809, as they cover the same range */
f05be589
BB		 131static const struct regmap_range axp22x_writeable_ranges[] = {
132 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
97602370 133 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3),
f05be589
BB		 134 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
135};
136
137static const struct regmap_range axp22x_volatile_ranges[] = {
15093250 138 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
f05be589 139 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
15093250 140 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
ed7311f0 141 regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
15093250 142 regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
f05be589
BB		 143};
144
145static const struct regmap_access_table axp22x_writeable_table = {
146 .yes_ranges = axp22x_writeable_ranges,
147 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
148};
149
150static const struct regmap_access_table axp22x_volatile_table = {
151 .yes_ranges = axp22x_volatile_ranges,
152 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
153};
154
1578353e 155/* AXP288 ranges are shared with the AXP803, as they cover the same range */
af7e9069 156static const struct regmap_range axp288_writeable_ranges[] = {
2405fbfb 157 regmap_reg_range(AXP288_POWER_REASON, AXP288_POWER_REASON),
af7e9069
JP		 158 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
159 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
160};
161
162static const struct regmap_range axp288_volatile_ranges[] = {
cd532166 163 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
f949a9eb 164 regmap_reg_range(AXP22X_PWR_OUT_CTRL1, AXP22X_ALDO3_V_OUT),
cd532166 165 regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
dc91c3b6 166 regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT),
0c384fc8 167 regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
af7e9069 168 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
cd532166 169 regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
f949a9eb 170 regmap_reg_range(AXP20X_GPIO1_CTRL, AXP22X_GPIO_STATE),
cd532166
HG		 171 regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
172 regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
af7e9069
JP		 173};
174
175static const struct regmap_access_table axp288_writeable_table = {
176 .yes_ranges = axp288_writeable_ranges,
177 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
178};
179
180static const struct regmap_access_table axp288_volatile_table = {
181 .yes_ranges = axp288_volatile_ranges,
182 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
183};
184
8824ee85
CYT		 185static const struct regmap_range axp806_writeable_ranges[] = {
186 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
187 regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
188 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
189 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
34d9030b 190 regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
8824ee85
CYT		 191};
192
75c8cb2f
MB		 193static const struct regmap_range axp313a_writeable_ranges[] = {
194 regmap_reg_range(AXP313A_ON_INDICATE, AXP313A_IRQ_STATE),
195};
196
35fec94a
AP		 197static const struct regmap_range axp323_writeable_ranges[] = {
198 regmap_reg_range(AXP313A_ON_INDICATE, AXP323_DCDC_MODE_CTRL2),
199};
200
75c8cb2f
MB		 201static const struct regmap_range axp313a_volatile_ranges[] = {
202 regmap_reg_range(AXP313A_SHUTDOWN_CTRL, AXP313A_SHUTDOWN_CTRL),
203 regmap_reg_range(AXP313A_IRQ_STATE, AXP313A_IRQ_STATE),
204};
205
206static const struct regmap_access_table axp313a_writeable_table = {
207 .yes_ranges = axp313a_writeable_ranges,
208 .n_yes_ranges = ARRAY_SIZE(axp313a_writeable_ranges),
209};
210
35fec94a
AP		 211static const struct regmap_access_table axp323_writeable_table = {
212 .yes_ranges = axp323_writeable_ranges,
213 .n_yes_ranges = ARRAY_SIZE(axp323_writeable_ranges),
214};
215
75c8cb2f
MB		 216static const struct regmap_access_table axp313a_volatile_table = {
217 .yes_ranges = axp313a_volatile_ranges,
218 .n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges),
219};
220
b5bfc8ab 221static const struct regmap_range axp717_writeable_ranges[] = {
2e1a57d5
CM		 222 regmap_reg_range(AXP717_PMU_FAULT, AXP717_MODULE_EN_CONTROL_1),
223 regmap_reg_range(AXP717_MIN_SYS_V_CONTROL, AXP717_BOOST_CONTROL),
224 regmap_reg_range(AXP717_VSYS_V_POWEROFF, AXP717_VSYS_V_POWEROFF),
b5bfc8ab 225 regmap_reg_range(AXP717_IRQ0_EN, AXP717_IRQ4_EN),
68f86042 226 regmap_reg_range(AXP717_IRQ0_STATE, AXP717_IRQ4_STATE),
bfad07fe 227 regmap_reg_range(AXP717_TS_PIN_CFG, AXP717_TS_PIN_CFG),
2e1a57d5 228 regmap_reg_range(AXP717_ICC_CHG_SET, AXP717_CV_CHG_SET),
b5bfc8ab 229 regmap_reg_range(AXP717_DCDC_OUTPUT_CONTROL, AXP717_CPUSLDO_CONTROL),
2e1a57d5
CM		 230 regmap_reg_range(AXP717_ADC_CH_EN_CONTROL, AXP717_ADC_CH_EN_CONTROL),
231 regmap_reg_range(AXP717_ADC_DATA_SEL, AXP717_ADC_DATA_SEL),
b5bfc8ab
AP		 232};
233
234static const struct regmap_range axp717_volatile_ranges[] = {
2e1a57d5 235 regmap_reg_range(AXP717_ON_INDICATE, AXP717_PMU_FAULT),
b5bfc8ab 236 regmap_reg_range(AXP717_IRQ0_STATE, AXP717_IRQ4_STATE),
2e1a57d5
CM		 237 regmap_reg_range(AXP717_BATT_PERCENT_DATA, AXP717_BATT_PERCENT_DATA),
238 regmap_reg_range(AXP717_BATT_V_H, AXP717_BATT_CHRG_I_L),
239 regmap_reg_range(AXP717_ADC_DATA_H, AXP717_ADC_DATA_L),
b5bfc8ab
AP		 240};
241
242static const struct regmap_access_table axp717_writeable_table = {
243 .yes_ranges = axp717_writeable_ranges,
244 .n_yes_ranges = ARRAY_SIZE(axp717_writeable_ranges),
245};
246
247static const struct regmap_access_table axp717_volatile_table = {
248 .yes_ranges = axp717_volatile_ranges,
249 .n_yes_ranges = ARRAY_SIZE(axp717_volatile_ranges),
250};
251
8824ee85
CYT		 252static const struct regmap_range axp806_volatile_ranges[] = {
253 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
254};
255
256static const struct regmap_access_table axp806_writeable_table = {
257 .yes_ranges = axp806_writeable_ranges,
258 .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
259};
260
261static const struct regmap_access_table axp806_volatile_table = {
262 .yes_ranges = axp806_volatile_ranges,
263 .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
264};
265
e0f8ad2a
SQ		 266static const struct regmap_range axp15060_writeable_ranges[] = {
267 regmap_reg_range(AXP15060_PWR_OUT_CTRL1, AXP15060_DCDC_MODE_CTRL2),
268 regmap_reg_range(AXP15060_OUTPUT_MONITOR_DISCHARGE, AXP15060_CPUSLDO_V_CTRL),
269 regmap_reg_range(AXP15060_PWR_WAKEUP_CTRL, AXP15060_PWR_DISABLE_DOWN_SEQ),
270 regmap_reg_range(AXP15060_PEK_KEY, AXP15060_PEK_KEY),
271 regmap_reg_range(AXP15060_IRQ1_EN, AXP15060_IRQ2_EN),
272 regmap_reg_range(AXP15060_IRQ1_STATE, AXP15060_IRQ2_STATE),
273};
274
275static const struct regmap_range axp15060_volatile_ranges[] = {
276 regmap_reg_range(AXP15060_STARTUP_SRC, AXP15060_STARTUP_SRC),
277 regmap_reg_range(AXP15060_PWR_WAKEUP_CTRL, AXP15060_PWR_DISABLE_DOWN_SEQ),
278 regmap_reg_range(AXP15060_IRQ1_STATE, AXP15060_IRQ2_STATE),
279};
280
281static const struct regmap_access_table axp15060_writeable_table = {
282 .yes_ranges = axp15060_writeable_ranges,
283 .n_yes_ranges = ARRAY_SIZE(axp15060_writeable_ranges),
284};
285
286static const struct regmap_access_table axp15060_volatile_table = {
287 .yes_ranges = axp15060_volatile_ranges,
288 .n_yes_ranges = ARRAY_SIZE(axp15060_volatile_ranges),
289};
290
531a469e 291static const struct resource axp152_pek_resources[] = {
d8d79f8f
MS		 292 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
293 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
294};
295
63eeabbc
AM		 296static const struct resource axp192_ac_power_supply_resources[] = {
297 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
298 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
299 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
300};
301
302static const struct resource axp192_usb_power_supply_resources[] = {
303 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
304 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
305 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_VALID, "VBUS_VALID"),
306 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
307};
308
531a469e 309static const struct resource axp20x_ac_power_supply_resources[] = {
cd7cf27b
MH		 310 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
311 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
312 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
313};
314
531a469e 315static const struct resource axp20x_pek_resources[] = {
e26f87e5
CYT		 316 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
317 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
cfb61a41
CC		 318};
319
531a469e 320static const struct resource axp20x_usb_power_supply_resources[] = {
8de4efda
HG		 321 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
322 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
323 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
324 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
325};
326
531a469e 327static const struct resource axp22x_usb_power_supply_resources[] = {
ecd98cce
HG		 328 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
329 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
330};
331
2e1a57d5
CM		 332static const struct resource axp717_usb_power_supply_resources[] = {
333 DEFINE_RES_IRQ_NAMED(AXP717_IRQ_VBUS_OVER_V, "VBUS_OVER_V"),
334 DEFINE_RES_IRQ_NAMED(AXP717_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
335 DEFINE_RES_IRQ_NAMED(AXP717_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
336};
337
129fc677
QS		 338/* AXP803 and AXP813/AXP818 share the same interrupts */
339static const struct resource axp803_usb_power_supply_resources[] = {
340 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
341 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
342};
343
531a469e 344static const struct resource axp22x_pek_resources[] = {
e26f87e5
CYT		 345 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
346 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
f05be589
BB		 347};
348
531a469e 349static const struct resource axp288_power_button_resources[] = {
e26f87e5
CYT		 350 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKP, "PEK_DBR"),
351 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKN, "PEK_DBF"),
e56e5ad6
BF		 352};
353
531a469e 354static const struct resource axp288_fuel_gauge_resources[] = {
e26f87e5
CYT		 355 DEFINE_RES_IRQ(AXP288_IRQ_QWBTU),
356 DEFINE_RES_IRQ(AXP288_IRQ_WBTU),
357 DEFINE_RES_IRQ(AXP288_IRQ_QWBTO),
358 DEFINE_RES_IRQ(AXP288_IRQ_WBTO),
359 DEFINE_RES_IRQ(AXP288_IRQ_WL2),
360 DEFINE_RES_IRQ(AXP288_IRQ_WL1),
af7e9069
JP		 361};
362
75c8cb2f
MB		 363static const struct resource axp313a_pek_resources[] = {
364 DEFINE_RES_IRQ_NAMED(AXP313A_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
365 DEFINE_RES_IRQ_NAMED(AXP313A_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
366};
367
b5bfc8ab
AP		 368static const struct resource axp717_pek_resources[] = {
369 DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
370 DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
371};
372
531a469e 373static const struct resource axp803_pek_resources[] = {
e26f87e5
CYT		 374 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
375 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
1578353e
IZ		 376};
377
06f49010
CYT		 378static const struct resource axp806_pek_resources[] = {
379 DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_RISE, "PEK_DBR"),
380 DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_FALL, "PEK_DBF"),
381};
382
531a469e 383static const struct resource axp809_pek_resources[] = {
e26f87e5
CYT		 384 DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
385 DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
20147f0d
CYT		 386};
387
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SQ		 388static const struct resource axp15060_pek_resources[] = {
389 DEFINE_RES_IRQ_NAMED(AXP15060_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
390 DEFINE_RES_IRQ_NAMED(AXP15060_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
391};
392
d8d79f8f
MS		 393static const struct regmap_config axp152_regmap_config = {
394 .reg_bits = 8,
395 .val_bits = 8,
396 .wr_table = &axp152_writeable_table,
397 .volatile_table = &axp152_volatile_table,
398 .max_register = AXP152_PWM1_DUTY_CYCLE,
cdc707f7 399 .cache_type = REGCACHE_MAPLE,
d8d79f8f
MS		 400};
401
63eeabbc
AM		 402static const struct regmap_config axp192_regmap_config = {
403 .reg_bits = 8,
404 .val_bits = 8,
405 .wr_table = &axp192_writeable_table,
406 .volatile_table = &axp192_volatile_table,
407 .max_register = AXP20X_CC_CTRL,
38df0f25 408 .cache_type = REGCACHE_MAPLE,
63eeabbc
AM		 409};
410
cfb61a41
CC		 411static const struct regmap_config axp20x_regmap_config = {
412 .reg_bits = 8,
413 .val_bits = 8,
414 .wr_table = &axp20x_writeable_table,
415 .volatile_table = &axp20x_volatile_table,
553ed4b5 416 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
cdc707f7 417 .cache_type = REGCACHE_MAPLE,
cfb61a41
CC		 418};
419
f05be589
BB		 420static const struct regmap_config axp22x_regmap_config = {
421 .reg_bits = 8,
422 .val_bits = 8,
423 .wr_table = &axp22x_writeable_table,
424 .volatile_table = &axp22x_volatile_table,
425 .max_register = AXP22X_BATLOW_THRES1,
cdc707f7 426 .cache_type = REGCACHE_MAPLE,
f05be589
BB		 427};
428
af7e9069
JP		 429static const struct regmap_config axp288_regmap_config = {
430 .reg_bits = 8,
431 .val_bits = 8,
432 .wr_table = &axp288_writeable_table,
433 .volatile_table = &axp288_volatile_table,
434 .max_register = AXP288_FG_TUNE5,
cdc707f7 435 .cache_type = REGCACHE_MAPLE,
af7e9069
JP		 436};
437
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MB		 438static const struct regmap_config axp313a_regmap_config = {
439 .reg_bits = 8,
440 .val_bits = 8,
441 .wr_table = &axp313a_writeable_table,
442 .volatile_table = &axp313a_volatile_table,
443 .max_register = AXP313A_IRQ_STATE,
38df0f25 444 .cache_type = REGCACHE_MAPLE,
75c8cb2f
MB		 445};
446
35fec94a
AP		 447static const struct regmap_config axp323_regmap_config = {
448 .reg_bits = 8,
449 .val_bits = 8,
450 .wr_table = &axp323_writeable_table,
451 .volatile_table = &axp313a_volatile_table,
452 .max_register = AXP323_DCDC_MODE_CTRL2,
453 .cache_type = REGCACHE_MAPLE,
454};
455
b5bfc8ab
AP		 456static const struct regmap_config axp717_regmap_config = {
457 .reg_bits = 8,
458 .val_bits = 8,
459 .wr_table = &axp717_writeable_table,
460 .volatile_table = &axp717_volatile_table,
2e1a57d5 461 .max_register = AXP717_ADC_DATA_L,
248327d6 462 .cache_type = REGCACHE_MAPLE,
b5bfc8ab
AP		 463};
464
8824ee85
CYT		 465static const struct regmap_config axp806_regmap_config = {
466 .reg_bits = 8,
467 .val_bits = 8,
468 .wr_table = &axp806_writeable_table,
469 .volatile_table = &axp806_volatile_table,
34d9030b 470 .max_register = AXP806_REG_ADDR_EXT,
cdc707f7 471 .cache_type = REGCACHE_MAPLE,
8824ee85
CYT		 472};
473
e0f8ad2a
SQ		 474static const struct regmap_config axp15060_regmap_config = {
475 .reg_bits = 8,
476 .val_bits = 8,
477 .wr_table = &axp15060_writeable_table,
478 .volatile_table = &axp15060_volatile_table,
479 .max_register = AXP15060_IRQ2_STATE,
cdc707f7 480 .cache_type = REGCACHE_MAPLE,
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SQ		 481};
482
af7e9069
JP		 483#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
484 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
cfb61a41 485
d8d79f8f
MS		 486static const struct regmap_irq axp152_regmap_irqs[] = {
487 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
488 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
489 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
490 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
491 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
492 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
493 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
494 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
495 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
496 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
497 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
498 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
499 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
500 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
501 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
502 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
503 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
504};
505
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AM		 506static const struct regmap_irq axp192_regmap_irqs[] = {
507 INIT_REGMAP_IRQ(AXP192, ACIN_OVER_V, 0, 7),
508 INIT_REGMAP_IRQ(AXP192, ACIN_PLUGIN, 0, 6),
509 INIT_REGMAP_IRQ(AXP192, ACIN_REMOVAL, 0, 5),
510 INIT_REGMAP_IRQ(AXP192, VBUS_OVER_V, 0, 4),
511 INIT_REGMAP_IRQ(AXP192, VBUS_PLUGIN, 0, 3),
512 INIT_REGMAP_IRQ(AXP192, VBUS_REMOVAL, 0, 2),
513 INIT_REGMAP_IRQ(AXP192, VBUS_V_LOW, 0, 1),
514 INIT_REGMAP_IRQ(AXP192, BATT_PLUGIN, 1, 7),
515 INIT_REGMAP_IRQ(AXP192, BATT_REMOVAL, 1, 6),
516 INIT_REGMAP_IRQ(AXP192, BATT_ENT_ACT_MODE, 1, 5),
517 INIT_REGMAP_IRQ(AXP192, BATT_EXIT_ACT_MODE, 1, 4),
518 INIT_REGMAP_IRQ(AXP192, CHARG, 1, 3),
519 INIT_REGMAP_IRQ(AXP192, CHARG_DONE, 1, 2),
520 INIT_REGMAP_IRQ(AXP192, BATT_TEMP_HIGH, 1, 1),
521 INIT_REGMAP_IRQ(AXP192, BATT_TEMP_LOW, 1, 0),
522 INIT_REGMAP_IRQ(AXP192, DIE_TEMP_HIGH, 2, 7),
523 INIT_REGMAP_IRQ(AXP192, CHARG_I_LOW, 2, 6),
524 INIT_REGMAP_IRQ(AXP192, DCDC1_V_LONG, 2, 5),
525 INIT_REGMAP_IRQ(AXP192, DCDC2_V_LONG, 2, 4),
526 INIT_REGMAP_IRQ(AXP192, DCDC3_V_LONG, 2, 3),
527 INIT_REGMAP_IRQ(AXP192, PEK_SHORT, 2, 1),
528 INIT_REGMAP_IRQ(AXP192, PEK_LONG, 2, 0),
529 INIT_REGMAP_IRQ(AXP192, N_OE_PWR_ON, 3, 7),
530 INIT_REGMAP_IRQ(AXP192, N_OE_PWR_OFF, 3, 6),
531 INIT_REGMAP_IRQ(AXP192, VBUS_VALID, 3, 5),
532 INIT_REGMAP_IRQ(AXP192, VBUS_NOT_VALID, 3, 4),
533 INIT_REGMAP_IRQ(AXP192, VBUS_SESS_VALID, 3, 3),
534 INIT_REGMAP_IRQ(AXP192, VBUS_SESS_END, 3, 2),
535 INIT_REGMAP_IRQ(AXP192, LOW_PWR_LVL, 3, 0),
536 INIT_REGMAP_IRQ(AXP192, TIMER, 4, 7),
537 INIT_REGMAP_IRQ(AXP192, GPIO2_INPUT, 4, 2),
538 INIT_REGMAP_IRQ(AXP192, GPIO1_INPUT, 4, 1),
539 INIT_REGMAP_IRQ(AXP192, GPIO0_INPUT, 4, 0),
540};
541
cfb61a41 542static const struct regmap_irq axp20x_regmap_irqs[] = {
af7e9069
JP		 543 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
544 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
545 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
546 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
547 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
548 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
549 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
550 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
551 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
552 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
553 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
554 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
555 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
556 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
557 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
558 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
559 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
560 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
561 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
562 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
563 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
564 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
565 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
566 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
567 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
568 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
569 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
570 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
571 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
572 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
573 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
574 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
575 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
576 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
577 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
578 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
579 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
580};
581
f05be589
BB		 582static const struct regmap_irq axp22x_regmap_irqs[] = {
583 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
584 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
585 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
586 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
587 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
588 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
589 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
590 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
591 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
592 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
593 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
594 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
595 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
596 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
597 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
598 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
599 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
600 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
601 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
602 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
603 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
604 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
605 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
606 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
607 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
608};
609
af7e9069
JP		 610/* some IRQs are compatible with axp20x models */
611static const struct regmap_irq axp288_regmap_irqs[] = {
ff3bbc5c
JP		 612 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
613 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
614 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
8b44e678
HG		 615 INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
616 INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
617 INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
af7e9069 618
ff3bbc5c
JP		 619 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
620 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
af7e9069
JP		 621 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
622 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
ff3bbc5c
JP		 623 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
624 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
af7e9069
JP		 625
626 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
627 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
628 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
ff3bbc5c 629 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
af7e9069
JP		 630 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
631 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
632 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
633 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
634
635 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
636 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
637 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
638 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
639
640 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
641 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
642 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
643 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
644 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
645 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
646 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
ff3bbc5c 647 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
af7e9069
JP		 648
649 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
650 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
cfb61a41
CC		 651};
652
75c8cb2f
MB		 653static const struct regmap_irq axp313a_regmap_irqs[] = {
654 INIT_REGMAP_IRQ(AXP313A, PEK_RIS_EDGE, 0, 7),
655 INIT_REGMAP_IRQ(AXP313A, PEK_FAL_EDGE, 0, 6),
656 INIT_REGMAP_IRQ(AXP313A, PEK_SHORT, 0, 5),
657 INIT_REGMAP_IRQ(AXP313A, PEK_LONG, 0, 4),
658 INIT_REGMAP_IRQ(AXP313A, DCDC3_V_LOW, 0, 3),
659 INIT_REGMAP_IRQ(AXP313A, DCDC2_V_LOW, 0, 2),
660 INIT_REGMAP_IRQ(AXP313A, DIE_TEMP_HIGH, 0, 0),
661};
662
b5bfc8ab
AP		 663static const struct regmap_irq axp717_regmap_irqs[] = {
664 INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL2, 0, 7),
665 INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL1, 0, 6),
666 INIT_REGMAP_IRQ(AXP717, GAUGE_NEW_SOC, 0, 4),
667 INIT_REGMAP_IRQ(AXP717, BOOST_OVER_V, 0, 2),
668 INIT_REGMAP_IRQ(AXP717, VBUS_OVER_V, 0, 1),
669 INIT_REGMAP_IRQ(AXP717, VBUS_FAULT, 0, 0),
670 INIT_REGMAP_IRQ(AXP717, VBUS_PLUGIN, 1, 7),
671 INIT_REGMAP_IRQ(AXP717, VBUS_REMOVAL, 1, 6),
672 INIT_REGMAP_IRQ(AXP717, BATT_PLUGIN, 1, 5),
673 INIT_REGMAP_IRQ(AXP717, BATT_REMOVAL, 1, 4),
674 INIT_REGMAP_IRQ(AXP717, PEK_SHORT, 1, 3),
675 INIT_REGMAP_IRQ(AXP717, PEK_LONG, 1, 2),
676 INIT_REGMAP_IRQ(AXP717, PEK_FAL_EDGE, 1, 1),
677 INIT_REGMAP_IRQ(AXP717, PEK_RIS_EDGE, 1, 0),
678 INIT_REGMAP_IRQ(AXP717, WDOG_EXPIRE, 2, 7),
679 INIT_REGMAP_IRQ(AXP717, LDO_OVER_CURR, 2, 6),
680 INIT_REGMAP_IRQ(AXP717, BATT_OVER_CURR, 2, 5),
681 INIT_REGMAP_IRQ(AXP717, CHARG_DONE, 2, 4),
682 INIT_REGMAP_IRQ(AXP717, CHARG, 2, 3),
683 INIT_REGMAP_IRQ(AXP717, DIE_TEMP_HIGH, 2, 2),
684 INIT_REGMAP_IRQ(AXP717, CHARG_TIMER, 2, 1),
685 INIT_REGMAP_IRQ(AXP717, BATT_OVER_V, 2, 0),
686 INIT_REGMAP_IRQ(AXP717, BC_USB_DONE, 3, 7),
687 INIT_REGMAP_IRQ(AXP717, BC_USB_CHNG, 3, 6),
688 INIT_REGMAP_IRQ(AXP717, BATT_QUIT_TEMP_HIGH, 3, 4),
689 INIT_REGMAP_IRQ(AXP717, BATT_CHG_TEMP_HIGH, 3, 3),
690 INIT_REGMAP_IRQ(AXP717, BATT_CHG_TEMP_LOW, 3, 2),
691 INIT_REGMAP_IRQ(AXP717, BATT_ACT_TEMP_HIGH, 3, 1),
692 INIT_REGMAP_IRQ(AXP717, BATT_ACT_TEMP_LOW, 3, 0),
693 INIT_REGMAP_IRQ(AXP717, TYPEC_REMOVE, 4, 6),
694 INIT_REGMAP_IRQ(AXP717, TYPEC_PLUGIN, 4, 5),
695};
696
1578353e
IZ		 697static const struct regmap_irq axp803_regmap_irqs[] = {
698 INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V, 0, 7),
699 INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN, 0, 6),
700 INIT_REGMAP_IRQ(AXP803, ACIN_REMOVAL, 0, 5),
701 INIT_REGMAP_IRQ(AXP803, VBUS_OVER_V, 0, 4),
702 INIT_REGMAP_IRQ(AXP803, VBUS_PLUGIN, 0, 3),
703 INIT_REGMAP_IRQ(AXP803, VBUS_REMOVAL, 0, 2),
704 INIT_REGMAP_IRQ(AXP803, BATT_PLUGIN, 1, 7),
705 INIT_REGMAP_IRQ(AXP803, BATT_REMOVAL, 1, 6),
706 INIT_REGMAP_IRQ(AXP803, BATT_ENT_ACT_MODE, 1, 5),
707 INIT_REGMAP_IRQ(AXP803, BATT_EXIT_ACT_MODE, 1, 4),
708 INIT_REGMAP_IRQ(AXP803, CHARG, 1, 3),
709 INIT_REGMAP_IRQ(AXP803, CHARG_DONE, 1, 2),
710 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH, 2, 7),
711 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH_END, 2, 6),
712 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW, 2, 5),
713 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW_END, 2, 4),
714 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH, 2, 3),
715 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH_END, 2, 2),
716 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW, 2, 1),
717 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW_END, 2, 0),
718 INIT_REGMAP_IRQ(AXP803, DIE_TEMP_HIGH, 3, 7),
719 INIT_REGMAP_IRQ(AXP803, GPADC, 3, 2),
720 INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL1, 3, 1),
721 INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL2, 3, 0),
722 INIT_REGMAP_IRQ(AXP803, TIMER, 4, 7),
723 INIT_REGMAP_IRQ(AXP803, PEK_RIS_EDGE, 4, 6),
724 INIT_REGMAP_IRQ(AXP803, PEK_FAL_EDGE, 4, 5),
725 INIT_REGMAP_IRQ(AXP803, PEK_SHORT, 4, 4),
726 INIT_REGMAP_IRQ(AXP803, PEK_LONG, 4, 3),
727 INIT_REGMAP_IRQ(AXP803, PEK_OVER_OFF, 4, 2),
728 INIT_REGMAP_IRQ(AXP803, GPIO1_INPUT, 4, 1),
729 INIT_REGMAP_IRQ(AXP803, GPIO0_INPUT, 4, 0),
730 INIT_REGMAP_IRQ(AXP803, BC_USB_CHNG, 5, 1),
731 INIT_REGMAP_IRQ(AXP803, MV_CHNG, 5, 0),
732};
733
8824ee85
CYT		 734static const struct regmap_irq axp806_regmap_irqs[] = {
735 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
736 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
737 INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
738 INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
739 INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
740 INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
741 INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
eef2b53a
CYT		 742 INIT_REGMAP_IRQ(AXP806, POK_LONG, 1, 0),
743 INIT_REGMAP_IRQ(AXP806, POK_SHORT, 1, 1),
8824ee85 744 INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
eef2b53a
CYT		 745 INIT_REGMAP_IRQ(AXP806, POK_FALL, 1, 5),
746 INIT_REGMAP_IRQ(AXP806, POK_RISE, 1, 6),
8824ee85
CYT		 747};
748
20147f0d
CYT		 749static const struct regmap_irq axp809_regmap_irqs[] = {
750 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
751 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
752 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
753 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
754 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
755 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
756 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
757 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
758 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
759 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
760 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
761 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
762 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
763 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
764 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
765 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
766 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
767 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
768 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
769 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
770 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
771 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
772 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
773 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
774 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
775 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
776 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
777 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
778 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
779 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
780 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
781 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
782};
783
e0f8ad2a
SQ		 784static const struct regmap_irq axp15060_regmap_irqs[] = {
785 INIT_REGMAP_IRQ(AXP15060, DIE_TEMP_HIGH_LV1, 0, 0),
786 INIT_REGMAP_IRQ(AXP15060, DIE_TEMP_HIGH_LV2, 0, 1),
787 INIT_REGMAP_IRQ(AXP15060, DCDC1_V_LOW, 0, 2),
788 INIT_REGMAP_IRQ(AXP15060, DCDC2_V_LOW, 0, 3),
789 INIT_REGMAP_IRQ(AXP15060, DCDC3_V_LOW, 0, 4),
790 INIT_REGMAP_IRQ(AXP15060, DCDC4_V_LOW, 0, 5),
791 INIT_REGMAP_IRQ(AXP15060, DCDC5_V_LOW, 0, 6),
792 INIT_REGMAP_IRQ(AXP15060, DCDC6_V_LOW, 0, 7),
793 INIT_REGMAP_IRQ(AXP15060, PEK_LONG, 1, 0),
794 INIT_REGMAP_IRQ(AXP15060, PEK_SHORT, 1, 1),
795 INIT_REGMAP_IRQ(AXP15060, GPIO1_INPUT, 1, 2),
796 INIT_REGMAP_IRQ(AXP15060, PEK_FAL_EDGE, 1, 3),
797 INIT_REGMAP_IRQ(AXP15060, PEK_RIS_EDGE, 1, 4),
798 INIT_REGMAP_IRQ(AXP15060, GPIO2_INPUT, 1, 5),
799};
800
d8d79f8f
MS		 801static const struct regmap_irq_chip axp152_regmap_irq_chip = {
802 .name = "axp152_irq_chip",
803 .status_base = AXP152_IRQ1_STATE,
804 .ack_base = AXP152_IRQ1_STATE,
acc247b2 805 .unmask_base = AXP152_IRQ1_EN,
d8d79f8f
MS		 806 .init_ack_masked = true,
807 .irqs = axp152_regmap_irqs,
808 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
809 .num_regs = 3,
810};
811
63eeabbc
AM		 812static unsigned int axp192_get_irq_reg(struct regmap_irq_chip_data *data,
813 unsigned int base, int index)
814{
815 /* linear mapping for IRQ1 to IRQ4 */
816 if (index < 4)
817 return base + index;
818
819 /* handle IRQ5 separately */
820 if (base == AXP192_IRQ1_EN)
821 return AXP192_IRQ5_EN;
822
823 return AXP192_IRQ5_STATE;
824}
825
826static const struct regmap_irq_chip axp192_regmap_irq_chip = {
827 .name = "axp192_irq_chip",
828 .status_base = AXP192_IRQ1_STATE,
829 .ack_base = AXP192_IRQ1_STATE,
830 .unmask_base = AXP192_IRQ1_EN,
831 .init_ack_masked = true,
832 .irqs = axp192_regmap_irqs,
833 .num_irqs = ARRAY_SIZE(axp192_regmap_irqs),
834 .num_regs = 5,
835 .get_irq_reg = axp192_get_irq_reg,
836};
837
cfb61a41
CC		 838static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
839 .name = "axp20x_irq_chip",
840 .status_base = AXP20X_IRQ1_STATE,
841 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 842 .unmask_base = AXP20X_IRQ1_EN,
af7e9069 843 .init_ack_masked = true,
cfb61a41
CC		 844 .irqs = axp20x_regmap_irqs,
845 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
af7e9069
JP		 846 .num_regs = 5,
847
848};
849
f05be589
BB		 850static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
851 .name = "axp22x_irq_chip",
852 .status_base = AXP20X_IRQ1_STATE,
853 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 854 .unmask_base = AXP20X_IRQ1_EN,
f05be589
BB		 855 .init_ack_masked = true,
856 .irqs = axp22x_regmap_irqs,
857 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
858 .num_regs = 5,
859};
860
af7e9069
JP		 861static const struct regmap_irq_chip axp288_regmap_irq_chip = {
862 .name = "axp288_irq_chip",
863 .status_base = AXP20X_IRQ1_STATE,
864 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 865 .unmask_base = AXP20X_IRQ1_EN,
cfb61a41 866 .init_ack_masked = true,
af7e9069
JP		 867 .irqs = axp288_regmap_irqs,
868 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
869 .num_regs = 6,
870
cfb61a41
CC		 871};
872
75c8cb2f
MB		 873static const struct regmap_irq_chip axp313a_regmap_irq_chip = {
874 .name = "axp313a_irq_chip",
875 .status_base = AXP313A_IRQ_STATE,
876 .ack_base = AXP313A_IRQ_STATE,
877 .unmask_base = AXP313A_IRQ_EN,
878 .init_ack_masked = true,
879 .irqs = axp313a_regmap_irqs,
880 .num_irqs = ARRAY_SIZE(axp313a_regmap_irqs),
881 .num_regs = 1,
882};
883
b5bfc8ab
AP		 884static const struct regmap_irq_chip axp717_regmap_irq_chip = {
885 .name = "axp717_irq_chip",
886 .status_base = AXP717_IRQ0_STATE,
887 .ack_base = AXP717_IRQ0_STATE,
888 .unmask_base = AXP717_IRQ0_EN,
889 .init_ack_masked = true,
890 .irqs = axp717_regmap_irqs,
891 .num_irqs = ARRAY_SIZE(axp717_regmap_irqs),
892 .num_regs = 5,
893};
894
1578353e
IZ		 895static const struct regmap_irq_chip axp803_regmap_irq_chip = {
896 .name = "axp803",
897 .status_base = AXP20X_IRQ1_STATE,
898 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 899 .unmask_base = AXP20X_IRQ1_EN,
1578353e
IZ		 900 .init_ack_masked = true,
901 .irqs = axp803_regmap_irqs,
902 .num_irqs = ARRAY_SIZE(axp803_regmap_irqs),
903 .num_regs = 6,
904};
905
8824ee85
CYT		 906static const struct regmap_irq_chip axp806_regmap_irq_chip = {
907 .name = "axp806",
908 .status_base = AXP20X_IRQ1_STATE,
909 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 910 .unmask_base = AXP20X_IRQ1_EN,
8824ee85
CYT		 911 .init_ack_masked = true,
912 .irqs = axp806_regmap_irqs,
913 .num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
914 .num_regs = 2,
915};
916
20147f0d
CYT		 917static const struct regmap_irq_chip axp809_regmap_irq_chip = {
918 .name = "axp809",
919 .status_base = AXP20X_IRQ1_STATE,
920 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 921 .unmask_base = AXP20X_IRQ1_EN,
20147f0d
CYT		 922 .init_ack_masked = true,
923 .irqs = axp809_regmap_irqs,
924 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
925 .num_regs = 5,
926};
927
e0f8ad2a
SQ		 928static const struct regmap_irq_chip axp15060_regmap_irq_chip = {
929 .name = "axp15060",
930 .status_base = AXP15060_IRQ1_STATE,
931 .ack_base = AXP15060_IRQ1_STATE,
932 .unmask_base = AXP15060_IRQ1_EN,
933 .init_ack_masked = true,
934 .irqs = axp15060_regmap_irqs,
935 .num_irqs = ARRAY_SIZE(axp15060_regmap_irqs),
936 .num_regs = 2,
937};
938
63eeabbc
AM		 939static const struct mfd_cell axp192_cells[] = {
940 {
941 .name = "axp192-adc",
942 .of_compatible = "x-powers,axp192-adc",
943 }, {
944 .name = "axp20x-battery-power-supply",
945 .of_compatible = "x-powers,axp192-battery-power-supply",
946 }, {
947 .name = "axp20x-ac-power-supply",
948 .of_compatible = "x-powers,axp202-ac-power-supply",
949 .num_resources = ARRAY_SIZE(axp192_ac_power_supply_resources),
950 .resources = axp192_ac_power_supply_resources,
951 }, {
952 .name = "axp20x-usb-power-supply",
953 .of_compatible = "x-powers,axp192-usb-power-supply",
954 .num_resources = ARRAY_SIZE(axp192_usb_power_supply_resources),
955 .resources = axp192_usb_power_supply_resources,
956 },
957 { .name = "axp20x-regulator" },
958};
959
531a469e 960static const struct mfd_cell axp20x_cells[] = {
cfb61a41 961 {
b419c16b
MR		 962 .name = "axp20x-gpio",
963 .of_compatible = "x-powers,axp209-gpio",
964 }, {
8de4efda
HG		 965 .name = "axp20x-pek",
966 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
967 .resources = axp20x_pek_resources,
cfb61a41 968 }, {
8de4efda 969 .name = "axp20x-regulator",
4d5e5c34
QS		 970 }, {
971 .name = "axp20x-adc",
034c3c95 972 .of_compatible = "x-powers,axp209-adc",
b4aeceb6
QS		 973 }, {
974 .name = "axp20x-battery-power-supply",
975 .of_compatible = "x-powers,axp209-battery-power-supply",
cd7cf27b
MH		 976 }, {
977 .name = "axp20x-ac-power-supply",
978 .of_compatible = "x-powers,axp202-ac-power-supply",
979 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
980 .resources = axp20x_ac_power_supply_resources,
8de4efda
HG		 981 }, {
982 .name = "axp20x-usb-power-supply",
983 .of_compatible = "x-powers,axp202-usb-power-supply",
984 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
985 .resources = axp20x_usb_power_supply_resources,
cfb61a41
CC		 986 },
987};
988
531a469e 989static const struct mfd_cell axp221_cells[] = {
4c650561 990 {
371a9fca
SH		 991 .name = "axp20x-gpio",
992 .of_compatible = "x-powers,axp221-gpio",
993 }, {
f4463633 994 .name = "axp221-pek",
4c650561
QS		 995 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
996 .resources = axp22x_pek_resources,
997 }, {
998 .name = "axp20x-regulator",
4d5e5c34 999 }, {
034c3c95
QS		 1000 .name = "axp22x-adc",
1001 .of_compatible = "x-powers,axp221-adc",
95c4f531
QS		 1002 }, {
1003 .name = "axp20x-ac-power-supply",
1004 .of_compatible = "x-powers,axp221-ac-power-supply",
1005 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
1006 .resources = axp20x_ac_power_supply_resources,
b4aeceb6
QS		 1007 }, {
1008 .name = "axp20x-battery-power-supply",
1009 .of_compatible = "x-powers,axp221-battery-power-supply",
4c650561
QS		 1010 }, {
1011 .name = "axp20x-usb-power-supply",
1012 .of_compatible = "x-powers,axp221-usb-power-supply",
1013 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
1014 .resources = axp22x_usb_power_supply_resources,
1015 },
1016};
1017
531a469e 1018static const struct mfd_cell axp223_cells[] = {
f05be589 1019 {
371a9fca
SH		 1020 .name = "axp20x-gpio",
1021 .of_compatible = "x-powers,axp221-gpio",
1022 }, {
753a8d08
CYT		 1023 .name = "axp221-pek",
1024 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
1025 .resources = axp22x_pek_resources,
4d5e5c34
QS		 1026 }, {
1027 .name = "axp22x-adc",
034c3c95 1028 .of_compatible = "x-powers,axp221-adc",
b4aeceb6
QS		 1029 }, {
1030 .name = "axp20x-battery-power-supply",
1031 .of_compatible = "x-powers,axp221-battery-power-supply",
6d4fa89d 1032 }, {
753a8d08 1033 .name = "axp20x-regulator",
95c4f531
QS		 1034 }, {
1035 .name = "axp20x-ac-power-supply",
1036 .of_compatible = "x-powers,axp221-ac-power-supply",
1037 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
1038 .resources = axp20x_ac_power_supply_resources,
ecd98cce
HG		 1039 }, {
1040 .name = "axp20x-usb-power-supply",
4c650561 1041 .of_compatible = "x-powers,axp223-usb-power-supply",
ecd98cce
HG		 1042 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
1043 .resources = axp22x_usb_power_supply_resources,
f05be589
BB		 1044 },
1045};
1046
531a469e 1047static const struct mfd_cell axp152_cells[] = {
d8d79f8f 1048 {
753a8d08
CYT		 1049 .name = "axp20x-pek",
1050 .num_resources = ARRAY_SIZE(axp152_pek_resources),
1051 .resources = axp152_pek_resources,
d8d79f8f
MS		 1052 },
1053};
1054
75c8cb2f
MB		 1055static struct mfd_cell axp313a_cells[] = {
1056 MFD_CELL_NAME("axp20x-regulator"),
1057 MFD_CELL_RES("axp313a-pek", axp313a_pek_resources),
1058};
1059
b5bfc8ab
AP		 1060static struct mfd_cell axp717_cells[] = {
1061 MFD_CELL_NAME("axp20x-regulator"),
1062 MFD_CELL_RES("axp20x-pek", axp717_pek_resources),
2e1a57d5
CM		 1063 MFD_CELL_OF("axp717-adc",
1064 NULL, NULL, 0, 0, "x-powers,axp717-adc"),
1065 MFD_CELL_OF("axp20x-usb-power-supply",
1066 axp717_usb_power_supply_resources, NULL, 0, 0,
1067 "x-powers,axp717-usb-power-supply"),
1068 MFD_CELL_OF("axp20x-battery-power-supply",
1069 NULL, NULL, 0, 0, "x-powers,axp717-battery-power-supply"),
b5bfc8ab
AP		 1070};
1071
531a469e 1072static const struct resource axp288_adc_resources[] = {
e26f87e5 1073 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_GPADC, "GPADC"),
af7e9069
JP		 1074};
1075
531a469e 1076static const struct resource axp288_extcon_resources[] = {
e26f87e5
CYT		 1077 DEFINE_RES_IRQ(AXP288_IRQ_VBUS_FALL),
1078 DEFINE_RES_IRQ(AXP288_IRQ_VBUS_RISE),
1079 DEFINE_RES_IRQ(AXP288_IRQ_MV_CHNG),
1080 DEFINE_RES_IRQ(AXP288_IRQ_BC_USB_CHNG),
bdb01f78
RP		 1081};
1082
531a469e 1083static const struct resource axp288_charger_resources[] = {
e26f87e5
CYT		 1084 DEFINE_RES_IRQ(AXP288_IRQ_OV),
1085 DEFINE_RES_IRQ(AXP288_IRQ_DONE),
1086 DEFINE_RES_IRQ(AXP288_IRQ_CHARGING),
1087 DEFINE_RES_IRQ(AXP288_IRQ_SAFE_QUIT),
1088 DEFINE_RES_IRQ(AXP288_IRQ_SAFE_ENTER),
1089 DEFINE_RES_IRQ(AXP288_IRQ_QCBTU),
1090 DEFINE_RES_IRQ(AXP288_IRQ_CBTU),
1091 DEFINE_RES_IRQ(AXP288_IRQ_QCBTO),
1092 DEFINE_RES_IRQ(AXP288_IRQ_CBTO),
af7e9069
JP		 1093};
1094
32679a7a
HG		 1095static const char * const axp288_fuel_gauge_suppliers[] = { "axp288_charger" };
1096
1097static const struct property_entry axp288_fuel_gauge_properties[] = {
1098 PROPERTY_ENTRY_STRING_ARRAY("supplied-from", axp288_fuel_gauge_suppliers),
1099 { }
1100};
1101
1102static const struct software_node axp288_fuel_gauge_sw_node = {
1103 .name = "axp288_fuel_gauge",
1104 .properties = axp288_fuel_gauge_properties,
1105};
1106
531a469e 1107static const struct mfd_cell axp288_cells[] = {
af7e9069 1108 {
753a8d08
CYT		 1109 .name = "axp288_adc",
1110 .num_resources = ARRAY_SIZE(axp288_adc_resources),
1111 .resources = axp288_adc_resources,
1112 }, {
1113 .name = "axp288_extcon",
1114 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
1115 .resources = axp288_extcon_resources,
1116 }, {
1117 .name = "axp288_charger",
1118 .num_resources = ARRAY_SIZE(axp288_charger_resources),
1119 .resources = axp288_charger_resources,
1120 }, {
1121 .name = "axp288_fuel_gauge",
1122 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
1123 .resources = axp288_fuel_gauge_resources,
32679a7a 1124 .swnode = &axp288_fuel_gauge_sw_node,
753a8d08
CYT		 1125 }, {
1126 .name = "axp221-pek",
1127 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
1128 .resources = axp288_power_button_resources,
1129 }, {
1130 .name = "axp288_pmic_acpi",
d8139f63 1131 },
af7e9069
JP		 1132};
1133
531a469e 1134static const struct mfd_cell axp803_cells[] = {
1578353e 1135 {
753a8d08
CYT		 1136 .name = "axp221-pek",
1137 .num_resources = ARRAY_SIZE(axp803_pek_resources),
1138 .resources = axp803_pek_resources,
ea90e7b4
OL		 1139 }, {
1140 .name = "axp20x-gpio",
1141 .of_compatible = "x-powers,axp813-gpio",
1142 }, {
1143 .name = "axp813-adc",
1144 .of_compatible = "x-powers,axp813-adc",
1145 }, {
1146 .name = "axp20x-battery-power-supply",
1147 .of_compatible = "x-powers,axp813-battery-power-supply",
1148 }, {
1149 .name = "axp20x-ac-power-supply",
1150 .of_compatible = "x-powers,axp813-ac-power-supply",
1151 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
1152 .resources = axp20x_ac_power_supply_resources,
e7037d75
CYT		 1153 }, {
1154 .name = "axp20x-usb-power-supply",
1155 .num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources),
1156 .resources = axp803_usb_power_supply_resources,
1157 .of_compatible = "x-powers,axp813-usb-power-supply",
9b79ff10 1158 },
753a8d08 1159 { .name = "axp20x-regulator" },
1578353e
IZ		 1160};
1161
06f49010
CYT		 1162static const struct mfd_cell axp806_self_working_cells[] = {
1163 {
753a8d08
CYT		 1164 .name = "axp221-pek",
1165 .num_resources = ARRAY_SIZE(axp806_pek_resources),
1166 .resources = axp806_pek_resources,
06f49010 1167 },
753a8d08 1168 { .name = "axp20x-regulator" },
06f49010
CYT		 1169};
1170
531a469e 1171static const struct mfd_cell axp806_cells[] = {
8824ee85 1172 {
753a8d08
CYT		 1173 .id = 2,
1174 .name = "axp20x-regulator",
8824ee85
CYT		 1175 },
1176};
1177
531a469e 1178static const struct mfd_cell axp809_cells[] = {
20147f0d 1179 {
371a9fca
SH		 1180 .name = "axp20x-gpio",
1181 .of_compatible = "x-powers,axp221-gpio",
1182 }, {
753a8d08
CYT		 1183 .name = "axp221-pek",
1184 .num_resources = ARRAY_SIZE(axp809_pek_resources),
1185 .resources = axp809_pek_resources,
20147f0d 1186 }, {
753a8d08
CYT		 1187 .id = 1,
1188 .name = "axp20x-regulator",
20147f0d
CYT		 1189 },
1190};
1191
531a469e 1192static const struct mfd_cell axp813_cells[] = {
7303733a 1193 {
753a8d08
CYT		 1194 .name = "axp221-pek",
1195 .num_resources = ARRAY_SIZE(axp803_pek_resources),
1196 .resources = axp803_pek_resources,
9a43206b 1197 }, {
753a8d08 1198 .name = "axp20x-regulator",
2bb3253c 1199 }, {
753a8d08
CYT		 1200 .name = "axp20x-gpio",
1201 .of_compatible = "x-powers,axp813-gpio",
e5d590fa 1202 }, {
753a8d08
CYT		 1203 .name = "axp813-adc",
1204 .of_compatible = "x-powers,axp813-adc",
6720328f
QS		 1205 }, {
1206 .name = "axp20x-battery-power-supply",
1207 .of_compatible = "x-powers,axp813-battery-power-supply",
4a19f9a6
OL		 1208 }, {
1209 .name = "axp20x-ac-power-supply",
1210 .of_compatible = "x-powers,axp813-ac-power-supply",
1211 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
1212 .resources = axp20x_ac_power_supply_resources,
129fc677
QS		 1213 }, {
1214 .name = "axp20x-usb-power-supply",
1215 .num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources),
1216 .resources = axp803_usb_power_supply_resources,
1217 .of_compatible = "x-powers,axp813-usb-power-supply",
e5d590fa 1218 },
7303733a
CYT		 1219};
1220
e0f8ad2a
SQ		 1221static const struct mfd_cell axp15060_cells[] = {
1222 {
1223 .name = "axp221-pek",
1224 .num_resources = ARRAY_SIZE(axp15060_pek_resources),
1225 .resources = axp15060_pek_resources,
1226 }, {
1227 .name = "axp20x-regulator",
1228 },
1229};
1230
1231/* For boards that don't have IRQ line connected to SOC. */
1232static const struct mfd_cell axp_regulator_only_cells[] = {
1233 {
1234 .name = "axp20x-regulator",
1235 },
1236};
1237
1b1305e9 1238static int axp20x_power_off(struct sys_off_data *data)
cfb61a41 1239{
1b1305e9 1240 struct axp20x_dev *axp20x = data->cb_data;
75c8cb2f 1241 unsigned int shutdown_reg;
af7e9069 1242
75c8cb2f 1243 switch (axp20x->variant) {
35fec94a 1244 case AXP323_ID:
75c8cb2f
MB		 1245 case AXP313A_ID:
1246 shutdown_reg = AXP313A_SHUTDOWN_CTRL;
1247 break;
1248 default:
1249 shutdown_reg = AXP20X_OFF_CTRL;
1250 break;
1251 }
1252
1253 regmap_write(axp20x->regmap, shutdown_reg, AXP20X_OFF);
179dc63d
HG		 1254
1255 /* Give capacitors etc. time to drain to avoid kernel panic msg. */
3f37d4f6 1256 mdelay(500);
1b1305e9
SH		 1257
1258 return NOTIFY_DONE;
cfb61a41
CC		 1259}
1260
4fd41151 1261int axp20x_match_device(struct axp20x_dev *axp20x)
af7e9069 1262{
e47a3cf7 1263 struct device *dev = axp20x->dev;
b2cb2ae2
AP		 1264 const struct mfd_cell *cells_no_irq = NULL;
1265 int nr_cells_no_irq = 0;
af7e9069 1266
830fafce 1267 axp20x->variant = (long)device_get_match_data(dev);
af7e9069 1268 switch (axp20x->variant) {
d8d79f8f
MS		 1269 case AXP152_ID:
1270 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
1271 axp20x->cells = axp152_cells;
1272 axp20x->regmap_cfg = &axp152_regmap_config;
1273 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
1274 break;
63eeabbc
AM		 1275 case AXP192_ID:
1276 axp20x->nr_cells = ARRAY_SIZE(axp192_cells);
1277 axp20x->cells = axp192_cells;
1278 axp20x->regmap_cfg = &axp192_regmap_config;
1279 axp20x->regmap_irq_chip = &axp192_regmap_irq_chip;
1280 break;
af7e9069
JP		 1281 case AXP202_ID:
1282 case AXP209_ID:
1283 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
1284 axp20x->cells = axp20x_cells;
1285 axp20x->regmap_cfg = &axp20x_regmap_config;
1286 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
1287 break;
f05be589 1288 case AXP221_ID:
4c650561
QS		 1289 axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
1290 axp20x->cells = axp221_cells;
1291 axp20x->regmap_cfg = &axp22x_regmap_config;
1292 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
1293 break;
02071f0f 1294 case AXP223_ID:
4c650561
QS		 1295 axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
1296 axp20x->cells = axp223_cells;
f05be589
BB		 1297 axp20x->regmap_cfg = &axp22x_regmap_config;
1298 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
1299 break;
af7e9069
JP		 1300 case AXP288_ID:
1301 axp20x->cells = axp288_cells;
1302 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
1303 axp20x->regmap_cfg = &axp288_regmap_config;
1304 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
0a5454c9 1305 axp20x->irq_flags = IRQF_TRIGGER_LOW;
af7e9069 1306 break;
75c8cb2f
MB		 1307 case AXP313A_ID:
1308 axp20x->nr_cells = ARRAY_SIZE(axp313a_cells);
1309 axp20x->cells = axp313a_cells;
1310 axp20x->regmap_cfg = &axp313a_regmap_config;
1311 axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
1312 break;
35fec94a
AP		 1313 case AXP323_ID:
1314 axp20x->nr_cells = ARRAY_SIZE(axp313a_cells);
1315 axp20x->cells = axp313a_cells;
1316 axp20x->regmap_cfg = &axp323_regmap_config;
1317 axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
1318 break;
b5bfc8ab
AP		 1319 case AXP717_ID:
1320 axp20x->nr_cells = ARRAY_SIZE(axp717_cells);
1321 axp20x->cells = axp717_cells;
1322 axp20x->regmap_cfg = &axp717_regmap_config;
1323 axp20x->regmap_irq_chip = &axp717_regmap_irq_chip;
1324 break;
1578353e
IZ		 1325 case AXP803_ID:
1326 axp20x->nr_cells = ARRAY_SIZE(axp803_cells);
1327 axp20x->cells = axp803_cells;
1328 axp20x->regmap_cfg = &axp288_regmap_config;
1329 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
1330 break;
8824ee85 1331 case AXP806_ID:
3efc465f
AP		 1332 /*
1333 * Don't register the power key part if in slave mode or
1334 * if there is no interrupt line.
1335 */
06f49010 1336 if (of_property_read_bool(axp20x->dev->of_node,
b2cb2ae2 1337 "x-powers,self-working-mode")) {
06f49010
CYT		 1338 axp20x->nr_cells = ARRAY_SIZE(axp806_self_working_cells);
1339 axp20x->cells = axp806_self_working_cells;
1340 } else {
1341 axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
1342 axp20x->cells = axp806_cells;
1343 }
b2cb2ae2
AP		 1344 nr_cells_no_irq = ARRAY_SIZE(axp806_cells);
1345 cells_no_irq = axp806_cells;
8824ee85
CYT		 1346 axp20x->regmap_cfg = &axp806_regmap_config;
1347 axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
1348 break;
20147f0d
CYT		 1349 case AXP809_ID:
1350 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
1351 axp20x->cells = axp809_cells;
1352 axp20x->regmap_cfg = &axp22x_regmap_config;
1353 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
1354 break;
7303733a
CYT		 1355 case AXP813_ID:
1356 axp20x->nr_cells = ARRAY_SIZE(axp813_cells);
1357 axp20x->cells = axp813_cells;
1358 axp20x->regmap_cfg = &axp288_regmap_config;
1359 /*
1360 * The IRQ table given in the datasheet is incorrect.
1361 * In IRQ enable/status registers 1, there are separate
1362 * IRQs for ACIN and VBUS, instead of bits [7:5] being
1363 * the same as bits [4:2]. So it shares the same IRQs
1364 * as the AXP803, rather than the AXP288.
1365 */
1366 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
1367 break;
e0f8ad2a 1368 case AXP15060_ID:
b2cb2ae2
AP		 1369 axp20x->nr_cells = ARRAY_SIZE(axp15060_cells);
1370 axp20x->cells = axp15060_cells;
e0f8ad2a
SQ		 1371 axp20x->regmap_cfg = &axp15060_regmap_config;
1372 axp20x->regmap_irq_chip = &axp15060_regmap_irq_chip;
1373 break;
af7e9069 1374 default:
697a4001 1375 dev_err(dev, "unsupported AXP20X ID %u\n", axp20x->variant);
af7e9069
JP		 1376 return -EINVAL;
1377 }
b2cb2ae2
AP		 1378
1379 /*
1380 * Use an alternative cell array when no interrupt line is connected,
1381 * since IRQs are required by some drivers.
1382 * The default is the safe "regulator-only", as this works fine without
1383 * an interrupt specified.
1384 */
1385 if (axp20x->irq <= 0) {
1386 if (cells_no_irq) {
1387 axp20x->nr_cells = nr_cells_no_irq;
1388 axp20x->cells = cells_no_irq;
1389 } else {
1390 axp20x->nr_cells = ARRAY_SIZE(axp_regulator_only_cells);
1391 axp20x->cells = axp_regulator_only_cells;
1392 }
1393 }
1394
af7e9069 1395 dev_info(dev, "AXP20x variant %s found\n",
2260a453 1396 axp20x_model_names[axp20x->variant]);
af7e9069
JP		 1397
1398 return 0;
1399}
4fd41151 1400EXPORT_SYMBOL(axp20x_match_device);
af7e9069 1401
4fd41151 1402int axp20x_device_probe(struct axp20x_dev *axp20x)
cfb61a41 1403{
cfb61a41
CC		 1404 int ret;
1405
696f0b3f
CYT		 1406 /*
1407 * The AXP806 supports either master/standalone or slave mode.
1408 * Slave mode allows sharing the serial bus, even with multiple
1409 * AXP806 which all have the same hardware address.
1410 *
1411 * This is done with extra "serial interface address extension",
1412 * or AXP806_BUS_ADDR_EXT, and "register address extension", or
1413 * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
1414 * 1 bit customizable at the factory, and 1 bit depending on the
1415 * state of an external pin. The latter is writable. The device
1416 * will only respond to operations to its other registers when
1417 * the these device addressing bits (in the upper 4 bits of the
1418 * registers) match.
1419 *
c0369698
RIL		 1420 * By default we support an AXP806 chained to an AXP809 in slave
1421 * mode. Boards which use an AXP806 in master mode can set the
1422 * property "x-powers,master-mode" to override the default.
696f0b3f 1423 */
c0369698
RIL		 1424 if (axp20x->variant == AXP806_ID) {
1425 if (of_property_read_bool(axp20x->dev->of_node,
06f49010
CYT		 1426 "x-powers,master-mode") ||
1427 of_property_read_bool(axp20x->dev->of_node,
1428 "x-powers,self-working-mode"))
c0369698
RIL		 1429 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
1430 AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
1431 else
1432 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
1433 AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
1434 }
696f0b3f 1435
3efc465f
AP		 1436 /* Only if there is an interrupt line connected towards the CPU. */
1437 if (axp20x->irq > 0) {
1438 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
1439 IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
1440 -1, axp20x->regmap_irq_chip,
1441 &axp20x->regmap_irqc);
1442 if (ret) {
1443 dev_err(axp20x->dev, "failed to add irq chip: %d\n",
1444 ret);
1445 return ret;
1446 }
cfb61a41
CC		 1447 }
1448
b246bd32 1449 ret = mfd_add_devices(axp20x->dev, PLATFORM_DEVID_NONE, axp20x->cells,
2260a453 1450 axp20x->nr_cells, NULL, 0, NULL);
cfb61a41
CC		 1451
1452 if (ret) {
4fd41151
CYT		 1453 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
1454 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41
CC		 1455 return ret;
1456 }
1457
1b1305e9 1458 if (axp20x->variant != AXP288_ID)
88dfdd03 1459 devm_register_power_off_handler(axp20x->dev, axp20x_power_off, axp20x);
cfb61a41 1460
4fd41151 1461 dev_info(axp20x->dev, "AXP20X driver loaded\n");
cfb61a41
CC		 1462
1463 return 0;
1464}
4fd41151 1465EXPORT_SYMBOL(axp20x_device_probe);
cfb61a41 1466
3c15e00e 1467void axp20x_device_remove(struct axp20x_dev *axp20x)
cfb61a41 1468{
cfb61a41 1469 mfd_remove_devices(axp20x->dev);
4fd41151 1470 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41 1471}
4fd41151 1472EXPORT_SYMBOL(axp20x_device_remove);
cfb61a41
CC		 1473
1474MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
1475MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1476MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)