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Linux 6.10-rc1
[linux-2.6-block.git] / drivers / mfd / axp20x.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
cfb61a41 2/*
4fd41151 3 * MFD core driver for the X-Powers' Power Management ICs
cfb61a41 4 *
af7e9069
JP		 5 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
6 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
7 * as well as configurable GPIOs.
cfb61a41 8 *
4fd41151
CYT		 9 * This file contains the interface independent core functions.
10 *
e740235d
CYT		 11 * Copyright (C) 2014 Carlo Caione
12 *
cfb61a41 13 * Author: Carlo Caione <carlo@caione.org>
cfb61a41
CC		 14 */
15
dcea4d5c
OS		 16#include <linux/acpi.h>
17#include <linux/bitops.h>
179dc63d 18#include <linux/delay.h>
dcea4d5c 19#include <linux/err.h>
cfb61a41
CC		 20#include <linux/interrupt.h>
21#include <linux/kernel.h>
dcea4d5c
OS		 22#include <linux/mfd/axp20x.h>
23#include <linux/mfd/core.h>
cfb61a41 24#include <linux/module.h>
830fafce
RH		 25#include <linux/of.h>
26#include <linux/property.h>
1b1305e9 27#include <linux/reboot.h>
cfb61a41 28#include <linux/regmap.h>
cfb61a41 29#include <linux/regulator/consumer.h>
cfb61a41 30
82b4d997 31#define AXP20X_OFF BIT(7)
cfb61a41 32
c0369698 33#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
696f0b3f
CYT		 34#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
35
c31e858b 36static const char * const axp20x_model_names[] = {
d8d79f8f 37 "AXP152",
63eeabbc 38 "AXP192",
af7e9069
JP		 39 "AXP202",
40 "AXP209",
f05be589 41 "AXP221",
02071f0f 42 "AXP223",
af7e9069 43 "AXP288",
75c8cb2f 44 "AXP313a",
b5bfc8ab 45 "AXP717",
1578353e 46 "AXP803",
8824ee85 47 "AXP806",
20147f0d 48 "AXP809",
7303733a 49 "AXP813",
e0f8ad2a 50 "AXP15060",
af7e9069
JP		 51};
52
d8d79f8f
MS		 53static const struct regmap_range axp152_writeable_ranges[] = {
54 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
55 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
56};
57
58static const struct regmap_range axp152_volatile_ranges[] = {
59 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
60 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
61 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
62};
63
64static const struct regmap_access_table axp152_writeable_table = {
65 .yes_ranges = axp152_writeable_ranges,
66 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
67};
68
69static const struct regmap_access_table axp152_volatile_table = {
70 .yes_ranges = axp152_volatile_ranges,
71 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
72};
73
cfb61a41
CC		 74static const struct regmap_range axp20x_writeable_ranges[] = {
75 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
97602370 76 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
cfb61a41 77 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
553ed4b5 78 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
cfb61a41
CC		 79};
80
81static const struct regmap_range axp20x_volatile_ranges[] = {
553ed4b5
BP		 82 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
83 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
cfb61a41 84 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
553ed4b5
BP		 85 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
86 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
87 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
cfb61a41
CC		 88};
89
90static const struct regmap_access_table axp20x_writeable_table = {
91 .yes_ranges = axp20x_writeable_ranges,
92 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
93};
94
95static const struct regmap_access_table axp20x_volatile_table = {
96 .yes_ranges = axp20x_volatile_ranges,
97 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
98};
99
63eeabbc
AM		 100static const struct regmap_range axp192_writeable_ranges[] = {
101 regmap_reg_range(AXP192_DATACACHE(0), AXP192_DATACACHE(5)),
102 regmap_reg_range(AXP192_PWR_OUT_CTRL, AXP192_IRQ5_STATE),
103 regmap_reg_range(AXP20X_DCDC_MODE, AXP192_N_RSTO_CTRL),
104 regmap_reg_range(AXP20X_CC_CTRL, AXP20X_CC_CTRL),
105};
106
107static const struct regmap_range axp192_volatile_ranges[] = {
108 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP192_USB_OTG_STATUS),
109 regmap_reg_range(AXP192_IRQ1_STATE, AXP192_IRQ4_STATE),
110 regmap_reg_range(AXP192_IRQ5_STATE, AXP192_IRQ5_STATE),
111 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
112 regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
113 regmap_reg_range(AXP192_GPIO2_0_STATE, AXP192_GPIO2_0_STATE),
114 regmap_reg_range(AXP192_GPIO4_3_STATE, AXP192_GPIO4_3_STATE),
115 regmap_reg_range(AXP192_N_RSTO_CTRL, AXP192_N_RSTO_CTRL),
116 regmap_reg_range(AXP20X_CHRG_CC_31_24, AXP20X_CC_CTRL),
117};
118
119static const struct regmap_access_table axp192_writeable_table = {
120 .yes_ranges = axp192_writeable_ranges,
121 .n_yes_ranges = ARRAY_SIZE(axp192_writeable_ranges),
122};
123
124static const struct regmap_access_table axp192_volatile_table = {
125 .yes_ranges = axp192_volatile_ranges,
126 .n_yes_ranges = ARRAY_SIZE(axp192_volatile_ranges),
127};
128
20147f0d 129/* AXP22x ranges are shared with the AXP809, as they cover the same range */
f05be589
BB		 130static const struct regmap_range axp22x_writeable_ranges[] = {
131 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
97602370 132 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3),
f05be589
BB		 133 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
134};
135
136static const struct regmap_range axp22x_volatile_ranges[] = {
15093250 137 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
f05be589 138 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
15093250 139 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
ed7311f0 140 regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
15093250 141 regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
f05be589
BB		 142};
143
144static const struct regmap_access_table axp22x_writeable_table = {
145 .yes_ranges = axp22x_writeable_ranges,
146 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
147};
148
149static const struct regmap_access_table axp22x_volatile_table = {
150 .yes_ranges = axp22x_volatile_ranges,
151 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
152};
153
1578353e 154/* AXP288 ranges are shared with the AXP803, as they cover the same range */
af7e9069 155static const struct regmap_range axp288_writeable_ranges[] = {
2405fbfb 156 regmap_reg_range(AXP288_POWER_REASON, AXP288_POWER_REASON),
af7e9069
JP		 157 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
158 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
159};
160
161static const struct regmap_range axp288_volatile_ranges[] = {
cd532166 162 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
f949a9eb 163 regmap_reg_range(AXP22X_PWR_OUT_CTRL1, AXP22X_ALDO3_V_OUT),
cd532166 164 regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
dc91c3b6 165 regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT),
0c384fc8 166 regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
af7e9069 167 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
cd532166 168 regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
f949a9eb 169 regmap_reg_range(AXP20X_GPIO1_CTRL, AXP22X_GPIO_STATE),
cd532166
HG		 170 regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
171 regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
af7e9069
JP		 172};
173
174static const struct regmap_access_table axp288_writeable_table = {
175 .yes_ranges = axp288_writeable_ranges,
176 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
177};
178
179static const struct regmap_access_table axp288_volatile_table = {
180 .yes_ranges = axp288_volatile_ranges,
181 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
182};
183
8824ee85
CYT		 184static const struct regmap_range axp806_writeable_ranges[] = {
185 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
186 regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
187 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
188 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
34d9030b 189 regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
8824ee85
CYT		 190};
191
75c8cb2f
MB		 192static const struct regmap_range axp313a_writeable_ranges[] = {
193 regmap_reg_range(AXP313A_ON_INDICATE, AXP313A_IRQ_STATE),
194};
195
196static const struct regmap_range axp313a_volatile_ranges[] = {
197 regmap_reg_range(AXP313A_SHUTDOWN_CTRL, AXP313A_SHUTDOWN_CTRL),
198 regmap_reg_range(AXP313A_IRQ_STATE, AXP313A_IRQ_STATE),
199};
200
201static const struct regmap_access_table axp313a_writeable_table = {
202 .yes_ranges = axp313a_writeable_ranges,
203 .n_yes_ranges = ARRAY_SIZE(axp313a_writeable_ranges),
204};
205
206static const struct regmap_access_table axp313a_volatile_table = {
207 .yes_ranges = axp313a_volatile_ranges,
208 .n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges),
209};
210
b5bfc8ab
AP		 211static const struct regmap_range axp717_writeable_ranges[] = {
212 regmap_reg_range(AXP717_IRQ0_EN, AXP717_IRQ4_EN),
213 regmap_reg_range(AXP717_DCDC_OUTPUT_CONTROL, AXP717_CPUSLDO_CONTROL),
214};
215
216static const struct regmap_range axp717_volatile_ranges[] = {
217 regmap_reg_range(AXP717_IRQ0_STATE, AXP717_IRQ4_STATE),
218};
219
220static const struct regmap_access_table axp717_writeable_table = {
221 .yes_ranges = axp717_writeable_ranges,
222 .n_yes_ranges = ARRAY_SIZE(axp717_writeable_ranges),
223};
224
225static const struct regmap_access_table axp717_volatile_table = {
226 .yes_ranges = axp717_volatile_ranges,
227 .n_yes_ranges = ARRAY_SIZE(axp717_volatile_ranges),
228};
229
8824ee85
CYT		 230static const struct regmap_range axp806_volatile_ranges[] = {
231 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
232};
233
234static const struct regmap_access_table axp806_writeable_table = {
235 .yes_ranges = axp806_writeable_ranges,
236 .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
237};
238
239static const struct regmap_access_table axp806_volatile_table = {
240 .yes_ranges = axp806_volatile_ranges,
241 .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
242};
243
e0f8ad2a
SQ		 244static const struct regmap_range axp15060_writeable_ranges[] = {
245 regmap_reg_range(AXP15060_PWR_OUT_CTRL1, AXP15060_DCDC_MODE_CTRL2),
246 regmap_reg_range(AXP15060_OUTPUT_MONITOR_DISCHARGE, AXP15060_CPUSLDO_V_CTRL),
247 regmap_reg_range(AXP15060_PWR_WAKEUP_CTRL, AXP15060_PWR_DISABLE_DOWN_SEQ),
248 regmap_reg_range(AXP15060_PEK_KEY, AXP15060_PEK_KEY),
249 regmap_reg_range(AXP15060_IRQ1_EN, AXP15060_IRQ2_EN),
250 regmap_reg_range(AXP15060_IRQ1_STATE, AXP15060_IRQ2_STATE),
251};
252
253static const struct regmap_range axp15060_volatile_ranges[] = {
254 regmap_reg_range(AXP15060_STARTUP_SRC, AXP15060_STARTUP_SRC),
255 regmap_reg_range(AXP15060_PWR_WAKEUP_CTRL, AXP15060_PWR_DISABLE_DOWN_SEQ),
256 regmap_reg_range(AXP15060_IRQ1_STATE, AXP15060_IRQ2_STATE),
257};
258
259static const struct regmap_access_table axp15060_writeable_table = {
260 .yes_ranges = axp15060_writeable_ranges,
261 .n_yes_ranges = ARRAY_SIZE(axp15060_writeable_ranges),
262};
263
264static const struct regmap_access_table axp15060_volatile_table = {
265 .yes_ranges = axp15060_volatile_ranges,
266 .n_yes_ranges = ARRAY_SIZE(axp15060_volatile_ranges),
267};
268
531a469e 269static const struct resource axp152_pek_resources[] = {
d8d79f8f
MS		 270 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
271 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
272};
273
63eeabbc
AM		 274static const struct resource axp192_ac_power_supply_resources[] = {
275 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
276 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
277 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
278};
279
280static const struct resource axp192_usb_power_supply_resources[] = {
281 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
282 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
283 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_VALID, "VBUS_VALID"),
284 DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
285};
286
531a469e 287static const struct resource axp20x_ac_power_supply_resources[] = {
cd7cf27b
MH		 288 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
289 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
290 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
291};
292
531a469e 293static const struct resource axp20x_pek_resources[] = {
e26f87e5
CYT		 294 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
295 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
cfb61a41
CC		 296};
297
531a469e 298static const struct resource axp20x_usb_power_supply_resources[] = {
8de4efda
HG		 299 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
300 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
301 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
302 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
303};
304
531a469e 305static const struct resource axp22x_usb_power_supply_resources[] = {
ecd98cce
HG		 306 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
307 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
308};
309
129fc677
QS		 310/* AXP803 and AXP813/AXP818 share the same interrupts */
311static const struct resource axp803_usb_power_supply_resources[] = {
312 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
313 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
314};
315
531a469e 316static const struct resource axp22x_pek_resources[] = {
e26f87e5
CYT		 317 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
318 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
f05be589
BB		 319};
320
531a469e 321static const struct resource axp288_power_button_resources[] = {
e26f87e5
CYT		 322 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKP, "PEK_DBR"),
323 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKN, "PEK_DBF"),
e56e5ad6
BF		 324};
325
531a469e 326static const struct resource axp288_fuel_gauge_resources[] = {
e26f87e5
CYT		 327 DEFINE_RES_IRQ(AXP288_IRQ_QWBTU),
328 DEFINE_RES_IRQ(AXP288_IRQ_WBTU),
329 DEFINE_RES_IRQ(AXP288_IRQ_QWBTO),
330 DEFINE_RES_IRQ(AXP288_IRQ_WBTO),
331 DEFINE_RES_IRQ(AXP288_IRQ_WL2),
332 DEFINE_RES_IRQ(AXP288_IRQ_WL1),
af7e9069
JP		 333};
334
75c8cb2f
MB		 335static const struct resource axp313a_pek_resources[] = {
336 DEFINE_RES_IRQ_NAMED(AXP313A_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
337 DEFINE_RES_IRQ_NAMED(AXP313A_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
338};
339
b5bfc8ab
AP		 340static const struct resource axp717_pek_resources[] = {
341 DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
342 DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
343};
344
531a469e 345static const struct resource axp803_pek_resources[] = {
e26f87e5
CYT		 346 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
347 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
1578353e
IZ		 348};
349
06f49010
CYT		 350static const struct resource axp806_pek_resources[] = {
351 DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_RISE, "PEK_DBR"),
352 DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_FALL, "PEK_DBF"),
353};
354
531a469e 355static const struct resource axp809_pek_resources[] = {
e26f87e5
CYT		 356 DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
357 DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
20147f0d
CYT		 358};
359
e0f8ad2a
SQ		 360static const struct resource axp15060_pek_resources[] = {
361 DEFINE_RES_IRQ_NAMED(AXP15060_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
362 DEFINE_RES_IRQ_NAMED(AXP15060_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
363};
364
d8d79f8f
MS		 365static const struct regmap_config axp152_regmap_config = {
366 .reg_bits = 8,
367 .val_bits = 8,
368 .wr_table = &axp152_writeable_table,
369 .volatile_table = &axp152_volatile_table,
370 .max_register = AXP152_PWM1_DUTY_CYCLE,
cdc707f7 371 .cache_type = REGCACHE_MAPLE,
d8d79f8f
MS		 372};
373
63eeabbc
AM		 374static const struct regmap_config axp192_regmap_config = {
375 .reg_bits = 8,
376 .val_bits = 8,
377 .wr_table = &axp192_writeable_table,
378 .volatile_table = &axp192_volatile_table,
379 .max_register = AXP20X_CC_CTRL,
38df0f25 380 .cache_type = REGCACHE_MAPLE,
63eeabbc
AM		 381};
382
cfb61a41
CC		 383static const struct regmap_config axp20x_regmap_config = {
384 .reg_bits = 8,
385 .val_bits = 8,
386 .wr_table = &axp20x_writeable_table,
387 .volatile_table = &axp20x_volatile_table,
553ed4b5 388 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
cdc707f7 389 .cache_type = REGCACHE_MAPLE,
cfb61a41
CC		 390};
391
f05be589
BB		 392static const struct regmap_config axp22x_regmap_config = {
393 .reg_bits = 8,
394 .val_bits = 8,
395 .wr_table = &axp22x_writeable_table,
396 .volatile_table = &axp22x_volatile_table,
397 .max_register = AXP22X_BATLOW_THRES1,
cdc707f7 398 .cache_type = REGCACHE_MAPLE,
f05be589
BB		 399};
400
af7e9069
JP		 401static const struct regmap_config axp288_regmap_config = {
402 .reg_bits = 8,
403 .val_bits = 8,
404 .wr_table = &axp288_writeable_table,
405 .volatile_table = &axp288_volatile_table,
406 .max_register = AXP288_FG_TUNE5,
cdc707f7 407 .cache_type = REGCACHE_MAPLE,
af7e9069
JP		 408};
409
75c8cb2f
MB		 410static const struct regmap_config axp313a_regmap_config = {
411 .reg_bits = 8,
412 .val_bits = 8,
413 .wr_table = &axp313a_writeable_table,
414 .volatile_table = &axp313a_volatile_table,
415 .max_register = AXP313A_IRQ_STATE,
38df0f25 416 .cache_type = REGCACHE_MAPLE,
75c8cb2f
MB		 417};
418
b5bfc8ab
AP		 419static const struct regmap_config axp717_regmap_config = {
420 .reg_bits = 8,
421 .val_bits = 8,
422 .wr_table = &axp717_writeable_table,
423 .volatile_table = &axp717_volatile_table,
424 .max_register = AXP717_CPUSLDO_CONTROL,
248327d6 425 .cache_type = REGCACHE_MAPLE,
b5bfc8ab
AP		 426};
427
8824ee85
CYT		 428static const struct regmap_config axp806_regmap_config = {
429 .reg_bits = 8,
430 .val_bits = 8,
431 .wr_table = &axp806_writeable_table,
432 .volatile_table = &axp806_volatile_table,
34d9030b 433 .max_register = AXP806_REG_ADDR_EXT,
cdc707f7 434 .cache_type = REGCACHE_MAPLE,
8824ee85
CYT		 435};
436
e0f8ad2a
SQ		 437static const struct regmap_config axp15060_regmap_config = {
438 .reg_bits = 8,
439 .val_bits = 8,
440 .wr_table = &axp15060_writeable_table,
441 .volatile_table = &axp15060_volatile_table,
442 .max_register = AXP15060_IRQ2_STATE,
cdc707f7 443 .cache_type = REGCACHE_MAPLE,
e0f8ad2a
SQ		 444};
445
af7e9069
JP		 446#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
447 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
cfb61a41 448
d8d79f8f
MS		 449static const struct regmap_irq axp152_regmap_irqs[] = {
450 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
451 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
452 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
453 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
454 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
455 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
456 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
457 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
458 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
459 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
460 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
461 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
462 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
463 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
464 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
465 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
466 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
467};
468
63eeabbc
AM		 469static const struct regmap_irq axp192_regmap_irqs[] = {
470 INIT_REGMAP_IRQ(AXP192, ACIN_OVER_V, 0, 7),
471 INIT_REGMAP_IRQ(AXP192, ACIN_PLUGIN, 0, 6),
472 INIT_REGMAP_IRQ(AXP192, ACIN_REMOVAL, 0, 5),
473 INIT_REGMAP_IRQ(AXP192, VBUS_OVER_V, 0, 4),
474 INIT_REGMAP_IRQ(AXP192, VBUS_PLUGIN, 0, 3),
475 INIT_REGMAP_IRQ(AXP192, VBUS_REMOVAL, 0, 2),
476 INIT_REGMAP_IRQ(AXP192, VBUS_V_LOW, 0, 1),
477 INIT_REGMAP_IRQ(AXP192, BATT_PLUGIN, 1, 7),
478 INIT_REGMAP_IRQ(AXP192, BATT_REMOVAL, 1, 6),
479 INIT_REGMAP_IRQ(AXP192, BATT_ENT_ACT_MODE, 1, 5),
480 INIT_REGMAP_IRQ(AXP192, BATT_EXIT_ACT_MODE, 1, 4),
481 INIT_REGMAP_IRQ(AXP192, CHARG, 1, 3),
482 INIT_REGMAP_IRQ(AXP192, CHARG_DONE, 1, 2),
483 INIT_REGMAP_IRQ(AXP192, BATT_TEMP_HIGH, 1, 1),
484 INIT_REGMAP_IRQ(AXP192, BATT_TEMP_LOW, 1, 0),
485 INIT_REGMAP_IRQ(AXP192, DIE_TEMP_HIGH, 2, 7),
486 INIT_REGMAP_IRQ(AXP192, CHARG_I_LOW, 2, 6),
487 INIT_REGMAP_IRQ(AXP192, DCDC1_V_LONG, 2, 5),
488 INIT_REGMAP_IRQ(AXP192, DCDC2_V_LONG, 2, 4),
489 INIT_REGMAP_IRQ(AXP192, DCDC3_V_LONG, 2, 3),
490 INIT_REGMAP_IRQ(AXP192, PEK_SHORT, 2, 1),
491 INIT_REGMAP_IRQ(AXP192, PEK_LONG, 2, 0),
492 INIT_REGMAP_IRQ(AXP192, N_OE_PWR_ON, 3, 7),
493 INIT_REGMAP_IRQ(AXP192, N_OE_PWR_OFF, 3, 6),
494 INIT_REGMAP_IRQ(AXP192, VBUS_VALID, 3, 5),
495 INIT_REGMAP_IRQ(AXP192, VBUS_NOT_VALID, 3, 4),
496 INIT_REGMAP_IRQ(AXP192, VBUS_SESS_VALID, 3, 3),
497 INIT_REGMAP_IRQ(AXP192, VBUS_SESS_END, 3, 2),
498 INIT_REGMAP_IRQ(AXP192, LOW_PWR_LVL, 3, 0),
499 INIT_REGMAP_IRQ(AXP192, TIMER, 4, 7),
500 INIT_REGMAP_IRQ(AXP192, GPIO2_INPUT, 4, 2),
501 INIT_REGMAP_IRQ(AXP192, GPIO1_INPUT, 4, 1),
502 INIT_REGMAP_IRQ(AXP192, GPIO0_INPUT, 4, 0),
503};
504
cfb61a41 505static const struct regmap_irq axp20x_regmap_irqs[] = {
af7e9069
JP		 506 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
507 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
508 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
509 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
510 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
511 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
512 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
513 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
514 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
515 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
516 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
517 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
518 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
519 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
520 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
521 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
522 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
523 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
524 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
525 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
526 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
527 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
528 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
529 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
530 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
531 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
532 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
533 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
534 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
535 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
536 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
537 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
538 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
539 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
540 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
541 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
542 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
543};
544
f05be589
BB		 545static const struct regmap_irq axp22x_regmap_irqs[] = {
546 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
547 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
548 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
549 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
550 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
551 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
552 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
553 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
554 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
555 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
556 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
557 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
558 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
559 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
560 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
561 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
562 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
563 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
564 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
565 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
566 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
567 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
568 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
569 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
570 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
571};
572
af7e9069
JP		 573/* some IRQs are compatible with axp20x models */
574static const struct regmap_irq axp288_regmap_irqs[] = {
ff3bbc5c
JP		 575 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
576 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
577 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
8b44e678
HG		 578 INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
579 INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
580 INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
af7e9069 581
ff3bbc5c
JP		 582 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
583 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
af7e9069
JP		 584 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
585 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
ff3bbc5c
JP		 586 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
587 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
af7e9069
JP		 588
589 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
590 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
591 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
ff3bbc5c 592 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
af7e9069
JP		 593 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
594 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
595 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
596 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
597
598 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
599 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
600 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
601 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
602
603 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
604 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
605 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
606 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
607 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
608 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
609 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
ff3bbc5c 610 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
af7e9069
JP		 611
612 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
613 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
cfb61a41
CC		 614};
615
75c8cb2f
MB		 616static const struct regmap_irq axp313a_regmap_irqs[] = {
617 INIT_REGMAP_IRQ(AXP313A, PEK_RIS_EDGE, 0, 7),
618 INIT_REGMAP_IRQ(AXP313A, PEK_FAL_EDGE, 0, 6),
619 INIT_REGMAP_IRQ(AXP313A, PEK_SHORT, 0, 5),
620 INIT_REGMAP_IRQ(AXP313A, PEK_LONG, 0, 4),
621 INIT_REGMAP_IRQ(AXP313A, DCDC3_V_LOW, 0, 3),
622 INIT_REGMAP_IRQ(AXP313A, DCDC2_V_LOW, 0, 2),
623 INIT_REGMAP_IRQ(AXP313A, DIE_TEMP_HIGH, 0, 0),
624};
625
b5bfc8ab
AP		 626static const struct regmap_irq axp717_regmap_irqs[] = {
627 INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL2, 0, 7),
628 INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL1, 0, 6),
629 INIT_REGMAP_IRQ(AXP717, GAUGE_NEW_SOC, 0, 4),
630 INIT_REGMAP_IRQ(AXP717, BOOST_OVER_V, 0, 2),
631 INIT_REGMAP_IRQ(AXP717, VBUS_OVER_V, 0, 1),
632 INIT_REGMAP_IRQ(AXP717, VBUS_FAULT, 0, 0),
633 INIT_REGMAP_IRQ(AXP717, VBUS_PLUGIN, 1, 7),
634 INIT_REGMAP_IRQ(AXP717, VBUS_REMOVAL, 1, 6),
635 INIT_REGMAP_IRQ(AXP717, BATT_PLUGIN, 1, 5),
636 INIT_REGMAP_IRQ(AXP717, BATT_REMOVAL, 1, 4),
637 INIT_REGMAP_IRQ(AXP717, PEK_SHORT, 1, 3),
638 INIT_REGMAP_IRQ(AXP717, PEK_LONG, 1, 2),
639 INIT_REGMAP_IRQ(AXP717, PEK_FAL_EDGE, 1, 1),
640 INIT_REGMAP_IRQ(AXP717, PEK_RIS_EDGE, 1, 0),
641 INIT_REGMAP_IRQ(AXP717, WDOG_EXPIRE, 2, 7),
642 INIT_REGMAP_IRQ(AXP717, LDO_OVER_CURR, 2, 6),
643 INIT_REGMAP_IRQ(AXP717, BATT_OVER_CURR, 2, 5),
644 INIT_REGMAP_IRQ(AXP717, CHARG_DONE, 2, 4),
645 INIT_REGMAP_IRQ(AXP717, CHARG, 2, 3),
646 INIT_REGMAP_IRQ(AXP717, DIE_TEMP_HIGH, 2, 2),
647 INIT_REGMAP_IRQ(AXP717, CHARG_TIMER, 2, 1),
648 INIT_REGMAP_IRQ(AXP717, BATT_OVER_V, 2, 0),
649 INIT_REGMAP_IRQ(AXP717, BC_USB_DONE, 3, 7),
650 INIT_REGMAP_IRQ(AXP717, BC_USB_CHNG, 3, 6),
651 INIT_REGMAP_IRQ(AXP717, BATT_QUIT_TEMP_HIGH, 3, 4),
652 INIT_REGMAP_IRQ(AXP717, BATT_CHG_TEMP_HIGH, 3, 3),
653 INIT_REGMAP_IRQ(AXP717, BATT_CHG_TEMP_LOW, 3, 2),
654 INIT_REGMAP_IRQ(AXP717, BATT_ACT_TEMP_HIGH, 3, 1),
655 INIT_REGMAP_IRQ(AXP717, BATT_ACT_TEMP_LOW, 3, 0),
656 INIT_REGMAP_IRQ(AXP717, TYPEC_REMOVE, 4, 6),
657 INIT_REGMAP_IRQ(AXP717, TYPEC_PLUGIN, 4, 5),
658};
659
1578353e
IZ		 660static const struct regmap_irq axp803_regmap_irqs[] = {
661 INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V, 0, 7),
662 INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN, 0, 6),
663 INIT_REGMAP_IRQ(AXP803, ACIN_REMOVAL, 0, 5),
664 INIT_REGMAP_IRQ(AXP803, VBUS_OVER_V, 0, 4),
665 INIT_REGMAP_IRQ(AXP803, VBUS_PLUGIN, 0, 3),
666 INIT_REGMAP_IRQ(AXP803, VBUS_REMOVAL, 0, 2),
667 INIT_REGMAP_IRQ(AXP803, BATT_PLUGIN, 1, 7),
668 INIT_REGMAP_IRQ(AXP803, BATT_REMOVAL, 1, 6),
669 INIT_REGMAP_IRQ(AXP803, BATT_ENT_ACT_MODE, 1, 5),
670 INIT_REGMAP_IRQ(AXP803, BATT_EXIT_ACT_MODE, 1, 4),
671 INIT_REGMAP_IRQ(AXP803, CHARG, 1, 3),
672 INIT_REGMAP_IRQ(AXP803, CHARG_DONE, 1, 2),
673 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH, 2, 7),
674 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH_END, 2, 6),
675 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW, 2, 5),
676 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW_END, 2, 4),
677 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH, 2, 3),
678 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH_END, 2, 2),
679 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW, 2, 1),
680 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW_END, 2, 0),
681 INIT_REGMAP_IRQ(AXP803, DIE_TEMP_HIGH, 3, 7),
682 INIT_REGMAP_IRQ(AXP803, GPADC, 3, 2),
683 INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL1, 3, 1),
684 INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL2, 3, 0),
685 INIT_REGMAP_IRQ(AXP803, TIMER, 4, 7),
686 INIT_REGMAP_IRQ(AXP803, PEK_RIS_EDGE, 4, 6),
687 INIT_REGMAP_IRQ(AXP803, PEK_FAL_EDGE, 4, 5),
688 INIT_REGMAP_IRQ(AXP803, PEK_SHORT, 4, 4),
689 INIT_REGMAP_IRQ(AXP803, PEK_LONG, 4, 3),
690 INIT_REGMAP_IRQ(AXP803, PEK_OVER_OFF, 4, 2),
691 INIT_REGMAP_IRQ(AXP803, GPIO1_INPUT, 4, 1),
692 INIT_REGMAP_IRQ(AXP803, GPIO0_INPUT, 4, 0),
693 INIT_REGMAP_IRQ(AXP803, BC_USB_CHNG, 5, 1),
694 INIT_REGMAP_IRQ(AXP803, MV_CHNG, 5, 0),
695};
696
8824ee85
CYT		 697static const struct regmap_irq axp806_regmap_irqs[] = {
698 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
699 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
700 INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
701 INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
702 INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
703 INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
704 INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
eef2b53a
CYT		 705 INIT_REGMAP_IRQ(AXP806, POK_LONG, 1, 0),
706 INIT_REGMAP_IRQ(AXP806, POK_SHORT, 1, 1),
8824ee85 707 INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
eef2b53a
CYT		 708 INIT_REGMAP_IRQ(AXP806, POK_FALL, 1, 5),
709 INIT_REGMAP_IRQ(AXP806, POK_RISE, 1, 6),
8824ee85
CYT		 710};
711
20147f0d
CYT		 712static const struct regmap_irq axp809_regmap_irqs[] = {
713 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
714 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
715 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
716 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
717 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
718 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
719 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
720 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
721 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
722 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
723 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
724 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
725 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
726 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
727 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
728 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
729 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
730 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
731 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
732 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
733 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
734 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
735 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
736 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
737 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
738 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
739 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
740 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
741 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
742 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
743 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
744 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
745};
746
e0f8ad2a
SQ		 747static const struct regmap_irq axp15060_regmap_irqs[] = {
748 INIT_REGMAP_IRQ(AXP15060, DIE_TEMP_HIGH_LV1, 0, 0),
749 INIT_REGMAP_IRQ(AXP15060, DIE_TEMP_HIGH_LV2, 0, 1),
750 INIT_REGMAP_IRQ(AXP15060, DCDC1_V_LOW, 0, 2),
751 INIT_REGMAP_IRQ(AXP15060, DCDC2_V_LOW, 0, 3),
752 INIT_REGMAP_IRQ(AXP15060, DCDC3_V_LOW, 0, 4),
753 INIT_REGMAP_IRQ(AXP15060, DCDC4_V_LOW, 0, 5),
754 INIT_REGMAP_IRQ(AXP15060, DCDC5_V_LOW, 0, 6),
755 INIT_REGMAP_IRQ(AXP15060, DCDC6_V_LOW, 0, 7),
756 INIT_REGMAP_IRQ(AXP15060, PEK_LONG, 1, 0),
757 INIT_REGMAP_IRQ(AXP15060, PEK_SHORT, 1, 1),
758 INIT_REGMAP_IRQ(AXP15060, GPIO1_INPUT, 1, 2),
759 INIT_REGMAP_IRQ(AXP15060, PEK_FAL_EDGE, 1, 3),
760 INIT_REGMAP_IRQ(AXP15060, PEK_RIS_EDGE, 1, 4),
761 INIT_REGMAP_IRQ(AXP15060, GPIO2_INPUT, 1, 5),
762};
763
d8d79f8f
MS		 764static const struct regmap_irq_chip axp152_regmap_irq_chip = {
765 .name = "axp152_irq_chip",
766 .status_base = AXP152_IRQ1_STATE,
767 .ack_base = AXP152_IRQ1_STATE,
acc247b2 768 .unmask_base = AXP152_IRQ1_EN,
d8d79f8f
MS		 769 .init_ack_masked = true,
770 .irqs = axp152_regmap_irqs,
771 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
772 .num_regs = 3,
773};
774
63eeabbc
AM		 775static unsigned int axp192_get_irq_reg(struct regmap_irq_chip_data *data,
776 unsigned int base, int index)
777{
778 /* linear mapping for IRQ1 to IRQ4 */
779 if (index < 4)
780 return base + index;
781
782 /* handle IRQ5 separately */
783 if (base == AXP192_IRQ1_EN)
784 return AXP192_IRQ5_EN;
785
786 return AXP192_IRQ5_STATE;
787}
788
789static const struct regmap_irq_chip axp192_regmap_irq_chip = {
790 .name = "axp192_irq_chip",
791 .status_base = AXP192_IRQ1_STATE,
792 .ack_base = AXP192_IRQ1_STATE,
793 .unmask_base = AXP192_IRQ1_EN,
794 .init_ack_masked = true,
795 .irqs = axp192_regmap_irqs,
796 .num_irqs = ARRAY_SIZE(axp192_regmap_irqs),
797 .num_regs = 5,
798 .get_irq_reg = axp192_get_irq_reg,
799};
800
cfb61a41
CC		 801static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
802 .name = "axp20x_irq_chip",
803 .status_base = AXP20X_IRQ1_STATE,
804 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 805 .unmask_base = AXP20X_IRQ1_EN,
af7e9069 806 .init_ack_masked = true,
cfb61a41
CC		 807 .irqs = axp20x_regmap_irqs,
808 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
af7e9069
JP		 809 .num_regs = 5,
810
811};
812
f05be589
BB		 813static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
814 .name = "axp22x_irq_chip",
815 .status_base = AXP20X_IRQ1_STATE,
816 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 817 .unmask_base = AXP20X_IRQ1_EN,
f05be589
BB		 818 .init_ack_masked = true,
819 .irqs = axp22x_regmap_irqs,
820 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
821 .num_regs = 5,
822};
823
af7e9069
JP		 824static const struct regmap_irq_chip axp288_regmap_irq_chip = {
825 .name = "axp288_irq_chip",
826 .status_base = AXP20X_IRQ1_STATE,
827 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 828 .unmask_base = AXP20X_IRQ1_EN,
cfb61a41 829 .init_ack_masked = true,
af7e9069
JP		 830 .irqs = axp288_regmap_irqs,
831 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
832 .num_regs = 6,
833
cfb61a41
CC		 834};
835
75c8cb2f
MB		 836static const struct regmap_irq_chip axp313a_regmap_irq_chip = {
837 .name = "axp313a_irq_chip",
838 .status_base = AXP313A_IRQ_STATE,
839 .ack_base = AXP313A_IRQ_STATE,
840 .unmask_base = AXP313A_IRQ_EN,
841 .init_ack_masked = true,
842 .irqs = axp313a_regmap_irqs,
843 .num_irqs = ARRAY_SIZE(axp313a_regmap_irqs),
844 .num_regs = 1,
845};
846
b5bfc8ab
AP		 847static const struct regmap_irq_chip axp717_regmap_irq_chip = {
848 .name = "axp717_irq_chip",
849 .status_base = AXP717_IRQ0_STATE,
850 .ack_base = AXP717_IRQ0_STATE,
851 .unmask_base = AXP717_IRQ0_EN,
852 .init_ack_masked = true,
853 .irqs = axp717_regmap_irqs,
854 .num_irqs = ARRAY_SIZE(axp717_regmap_irqs),
855 .num_regs = 5,
856};
857
1578353e
IZ		 858static const struct regmap_irq_chip axp803_regmap_irq_chip = {
859 .name = "axp803",
860 .status_base = AXP20X_IRQ1_STATE,
861 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 862 .unmask_base = AXP20X_IRQ1_EN,
1578353e
IZ		 863 .init_ack_masked = true,
864 .irqs = axp803_regmap_irqs,
865 .num_irqs = ARRAY_SIZE(axp803_regmap_irqs),
866 .num_regs = 6,
867};
868
8824ee85
CYT		 869static const struct regmap_irq_chip axp806_regmap_irq_chip = {
870 .name = "axp806",
871 .status_base = AXP20X_IRQ1_STATE,
872 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 873 .unmask_base = AXP20X_IRQ1_EN,
8824ee85
CYT		 874 .init_ack_masked = true,
875 .irqs = axp806_regmap_irqs,
876 .num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
877 .num_regs = 2,
878};
879
20147f0d
CYT		 880static const struct regmap_irq_chip axp809_regmap_irq_chip = {
881 .name = "axp809",
882 .status_base = AXP20X_IRQ1_STATE,
883 .ack_base = AXP20X_IRQ1_STATE,
acc247b2 884 .unmask_base = AXP20X_IRQ1_EN,
20147f0d
CYT		 885 .init_ack_masked = true,
886 .irqs = axp809_regmap_irqs,
887 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
888 .num_regs = 5,
889};
890
e0f8ad2a
SQ		 891static const struct regmap_irq_chip axp15060_regmap_irq_chip = {
892 .name = "axp15060",
893 .status_base = AXP15060_IRQ1_STATE,
894 .ack_base = AXP15060_IRQ1_STATE,
895 .unmask_base = AXP15060_IRQ1_EN,
896 .init_ack_masked = true,
897 .irqs = axp15060_regmap_irqs,
898 .num_irqs = ARRAY_SIZE(axp15060_regmap_irqs),
899 .num_regs = 2,
900};
901
63eeabbc
AM		 902static const struct mfd_cell axp192_cells[] = {
903 {
904 .name = "axp192-adc",
905 .of_compatible = "x-powers,axp192-adc",
906 }, {
907 .name = "axp20x-battery-power-supply",
908 .of_compatible = "x-powers,axp192-battery-power-supply",
909 }, {
910 .name = "axp20x-ac-power-supply",
911 .of_compatible = "x-powers,axp202-ac-power-supply",
912 .num_resources = ARRAY_SIZE(axp192_ac_power_supply_resources),
913 .resources = axp192_ac_power_supply_resources,
914 }, {
915 .name = "axp20x-usb-power-supply",
916 .of_compatible = "x-powers,axp192-usb-power-supply",
917 .num_resources = ARRAY_SIZE(axp192_usb_power_supply_resources),
918 .resources = axp192_usb_power_supply_resources,
919 },
920 { .name = "axp20x-regulator" },
921};
922
531a469e 923static const struct mfd_cell axp20x_cells[] = {
cfb61a41 924 {
b419c16b
MR		 925 .name = "axp20x-gpio",
926 .of_compatible = "x-powers,axp209-gpio",
927 }, {
8de4efda
HG		 928 .name = "axp20x-pek",
929 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
930 .resources = axp20x_pek_resources,
cfb61a41 931 }, {
8de4efda 932 .name = "axp20x-regulator",
4d5e5c34
QS		 933 }, {
934 .name = "axp20x-adc",
034c3c95 935 .of_compatible = "x-powers,axp209-adc",
b4aeceb6
QS		 936 }, {
937 .name = "axp20x-battery-power-supply",
938 .of_compatible = "x-powers,axp209-battery-power-supply",
cd7cf27b
MH		 939 }, {
940 .name = "axp20x-ac-power-supply",
941 .of_compatible = "x-powers,axp202-ac-power-supply",
942 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
943 .resources = axp20x_ac_power_supply_resources,
8de4efda
HG		 944 }, {
945 .name = "axp20x-usb-power-supply",
946 .of_compatible = "x-powers,axp202-usb-power-supply",
947 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
948 .resources = axp20x_usb_power_supply_resources,
cfb61a41
CC		 949 },
950};
951
531a469e 952static const struct mfd_cell axp221_cells[] = {
4c650561 953 {
371a9fca
SH		 954 .name = "axp20x-gpio",
955 .of_compatible = "x-powers,axp221-gpio",
956 }, {
f4463633 957 .name = "axp221-pek",
4c650561
QS		 958 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
959 .resources = axp22x_pek_resources,
960 }, {
961 .name = "axp20x-regulator",
4d5e5c34 962 }, {
034c3c95
QS		 963 .name = "axp22x-adc",
964 .of_compatible = "x-powers,axp221-adc",
95c4f531
QS		 965 }, {
966 .name = "axp20x-ac-power-supply",
967 .of_compatible = "x-powers,axp221-ac-power-supply",
968 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
969 .resources = axp20x_ac_power_supply_resources,
b4aeceb6
QS		 970 }, {
971 .name = "axp20x-battery-power-supply",
972 .of_compatible = "x-powers,axp221-battery-power-supply",
4c650561
QS		 973 }, {
974 .name = "axp20x-usb-power-supply",
975 .of_compatible = "x-powers,axp221-usb-power-supply",
976 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
977 .resources = axp22x_usb_power_supply_resources,
978 },
979};
980
531a469e 981static const struct mfd_cell axp223_cells[] = {
f05be589 982 {
371a9fca
SH		 983 .name = "axp20x-gpio",
984 .of_compatible = "x-powers,axp221-gpio",
985 }, {
753a8d08
CYT		 986 .name = "axp221-pek",
987 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
988 .resources = axp22x_pek_resources,
4d5e5c34
QS		 989 }, {
990 .name = "axp22x-adc",
034c3c95 991 .of_compatible = "x-powers,axp221-adc",
b4aeceb6
QS		 992 }, {
993 .name = "axp20x-battery-power-supply",
994 .of_compatible = "x-powers,axp221-battery-power-supply",
6d4fa89d 995 }, {
753a8d08 996 .name = "axp20x-regulator",
95c4f531
QS		 997 }, {
998 .name = "axp20x-ac-power-supply",
999 .of_compatible = "x-powers,axp221-ac-power-supply",
1000 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
1001 .resources = axp20x_ac_power_supply_resources,
ecd98cce
HG		 1002 }, {
1003 .name = "axp20x-usb-power-supply",
4c650561 1004 .of_compatible = "x-powers,axp223-usb-power-supply",
ecd98cce
HG		 1005 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
1006 .resources = axp22x_usb_power_supply_resources,
f05be589
BB		 1007 },
1008};
1009
531a469e 1010static const struct mfd_cell axp152_cells[] = {
d8d79f8f 1011 {
753a8d08
CYT		 1012 .name = "axp20x-pek",
1013 .num_resources = ARRAY_SIZE(axp152_pek_resources),
1014 .resources = axp152_pek_resources,
d8d79f8f
MS		 1015 },
1016};
1017
75c8cb2f
MB		 1018static struct mfd_cell axp313a_cells[] = {
1019 MFD_CELL_NAME("axp20x-regulator"),
1020 MFD_CELL_RES("axp313a-pek", axp313a_pek_resources),
1021};
1022
b5bfc8ab
AP		 1023static struct mfd_cell axp717_cells[] = {
1024 MFD_CELL_NAME("axp20x-regulator"),
1025 MFD_CELL_RES("axp20x-pek", axp717_pek_resources),
1026};
1027
531a469e 1028static const struct resource axp288_adc_resources[] = {
e26f87e5 1029 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_GPADC, "GPADC"),
af7e9069
JP		 1030};
1031
531a469e 1032static const struct resource axp288_extcon_resources[] = {
e26f87e5
CYT		 1033 DEFINE_RES_IRQ(AXP288_IRQ_VBUS_FALL),
1034 DEFINE_RES_IRQ(AXP288_IRQ_VBUS_RISE),
1035 DEFINE_RES_IRQ(AXP288_IRQ_MV_CHNG),
1036 DEFINE_RES_IRQ(AXP288_IRQ_BC_USB_CHNG),
bdb01f78
RP		 1037};
1038
531a469e 1039static const struct resource axp288_charger_resources[] = {
e26f87e5
CYT		 1040 DEFINE_RES_IRQ(AXP288_IRQ_OV),
1041 DEFINE_RES_IRQ(AXP288_IRQ_DONE),
1042 DEFINE_RES_IRQ(AXP288_IRQ_CHARGING),
1043 DEFINE_RES_IRQ(AXP288_IRQ_SAFE_QUIT),
1044 DEFINE_RES_IRQ(AXP288_IRQ_SAFE_ENTER),
1045 DEFINE_RES_IRQ(AXP288_IRQ_QCBTU),
1046 DEFINE_RES_IRQ(AXP288_IRQ_CBTU),
1047 DEFINE_RES_IRQ(AXP288_IRQ_QCBTO),
1048 DEFINE_RES_IRQ(AXP288_IRQ_CBTO),
af7e9069
JP		 1049};
1050
32679a7a
HG		 1051static const char * const axp288_fuel_gauge_suppliers[] = { "axp288_charger" };
1052
1053static const struct property_entry axp288_fuel_gauge_properties[] = {
1054 PROPERTY_ENTRY_STRING_ARRAY("supplied-from", axp288_fuel_gauge_suppliers),
1055 { }
1056};
1057
1058static const struct software_node axp288_fuel_gauge_sw_node = {
1059 .name = "axp288_fuel_gauge",
1060 .properties = axp288_fuel_gauge_properties,
1061};
1062
531a469e 1063static const struct mfd_cell axp288_cells[] = {
af7e9069 1064 {
753a8d08
CYT		 1065 .name = "axp288_adc",
1066 .num_resources = ARRAY_SIZE(axp288_adc_resources),
1067 .resources = axp288_adc_resources,
1068 }, {
1069 .name = "axp288_extcon",
1070 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
1071 .resources = axp288_extcon_resources,
1072 }, {
1073 .name = "axp288_charger",
1074 .num_resources = ARRAY_SIZE(axp288_charger_resources),
1075 .resources = axp288_charger_resources,
1076 }, {
1077 .name = "axp288_fuel_gauge",
1078 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
1079 .resources = axp288_fuel_gauge_resources,
32679a7a 1080 .swnode = &axp288_fuel_gauge_sw_node,
753a8d08
CYT		 1081 }, {
1082 .name = "axp221-pek",
1083 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
1084 .resources = axp288_power_button_resources,
1085 }, {
1086 .name = "axp288_pmic_acpi",
d8139f63 1087 },
af7e9069
JP		 1088};
1089
531a469e 1090static const struct mfd_cell axp803_cells[] = {
1578353e 1091 {
753a8d08
CYT		 1092 .name = "axp221-pek",
1093 .num_resources = ARRAY_SIZE(axp803_pek_resources),
1094 .resources = axp803_pek_resources,
ea90e7b4
OL		 1095 }, {
1096 .name = "axp20x-gpio",
1097 .of_compatible = "x-powers,axp813-gpio",
1098 }, {
1099 .name = "axp813-adc",
1100 .of_compatible = "x-powers,axp813-adc",
1101 }, {
1102 .name = "axp20x-battery-power-supply",
1103 .of_compatible = "x-powers,axp813-battery-power-supply",
1104 }, {
1105 .name = "axp20x-ac-power-supply",
1106 .of_compatible = "x-powers,axp813-ac-power-supply",
1107 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
1108 .resources = axp20x_ac_power_supply_resources,
e7037d75
CYT		 1109 }, {
1110 .name = "axp20x-usb-power-supply",
1111 .num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources),
1112 .resources = axp803_usb_power_supply_resources,
1113 .of_compatible = "x-powers,axp813-usb-power-supply",
9b79ff10 1114 },
753a8d08 1115 { .name = "axp20x-regulator" },
1578353e
IZ		 1116};
1117
06f49010
CYT		 1118static const struct mfd_cell axp806_self_working_cells[] = {
1119 {
753a8d08
CYT		 1120 .name = "axp221-pek",
1121 .num_resources = ARRAY_SIZE(axp806_pek_resources),
1122 .resources = axp806_pek_resources,
06f49010 1123 },
753a8d08 1124 { .name = "axp20x-regulator" },
06f49010
CYT		 1125};
1126
531a469e 1127static const struct mfd_cell axp806_cells[] = {
8824ee85 1128 {
753a8d08
CYT		 1129 .id = 2,
1130 .name = "axp20x-regulator",
8824ee85
CYT		 1131 },
1132};
1133
531a469e 1134static const struct mfd_cell axp809_cells[] = {
20147f0d 1135 {
371a9fca
SH		 1136 .name = "axp20x-gpio",
1137 .of_compatible = "x-powers,axp221-gpio",
1138 }, {
753a8d08
CYT		 1139 .name = "axp221-pek",
1140 .num_resources = ARRAY_SIZE(axp809_pek_resources),
1141 .resources = axp809_pek_resources,
20147f0d 1142 }, {
753a8d08
CYT		 1143 .id = 1,
1144 .name = "axp20x-regulator",
20147f0d
CYT		 1145 },
1146};
1147
531a469e 1148static const struct mfd_cell axp813_cells[] = {
7303733a 1149 {
753a8d08
CYT		 1150 .name = "axp221-pek",
1151 .num_resources = ARRAY_SIZE(axp803_pek_resources),
1152 .resources = axp803_pek_resources,
9a43206b 1153 }, {
753a8d08 1154 .name = "axp20x-regulator",
2bb3253c 1155 }, {
753a8d08
CYT		 1156 .name = "axp20x-gpio",
1157 .of_compatible = "x-powers,axp813-gpio",
e5d590fa 1158 }, {
753a8d08
CYT		 1159 .name = "axp813-adc",
1160 .of_compatible = "x-powers,axp813-adc",
6720328f
QS		 1161 }, {
1162 .name = "axp20x-battery-power-supply",
1163 .of_compatible = "x-powers,axp813-battery-power-supply",
4a19f9a6
OL		 1164 }, {
1165 .name = "axp20x-ac-power-supply",
1166 .of_compatible = "x-powers,axp813-ac-power-supply",
1167 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
1168 .resources = axp20x_ac_power_supply_resources,
129fc677
QS		 1169 }, {
1170 .name = "axp20x-usb-power-supply",
1171 .num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources),
1172 .resources = axp803_usb_power_supply_resources,
1173 .of_compatible = "x-powers,axp813-usb-power-supply",
e5d590fa 1174 },
7303733a
CYT		 1175};
1176
e0f8ad2a
SQ		 1177static const struct mfd_cell axp15060_cells[] = {
1178 {
1179 .name = "axp221-pek",
1180 .num_resources = ARRAY_SIZE(axp15060_pek_resources),
1181 .resources = axp15060_pek_resources,
1182 }, {
1183 .name = "axp20x-regulator",
1184 },
1185};
1186
1187/* For boards that don't have IRQ line connected to SOC. */
1188static const struct mfd_cell axp_regulator_only_cells[] = {
1189 {
1190 .name = "axp20x-regulator",
1191 },
1192};
1193
1b1305e9 1194static int axp20x_power_off(struct sys_off_data *data)
cfb61a41 1195{
1b1305e9 1196 struct axp20x_dev *axp20x = data->cb_data;
75c8cb2f 1197 unsigned int shutdown_reg;
af7e9069 1198
75c8cb2f
MB		 1199 switch (axp20x->variant) {
1200 case AXP313A_ID:
1201 shutdown_reg = AXP313A_SHUTDOWN_CTRL;
1202 break;
1203 default:
1204 shutdown_reg = AXP20X_OFF_CTRL;
1205 break;
1206 }
1207
1208 regmap_write(axp20x->regmap, shutdown_reg, AXP20X_OFF);
179dc63d
HG		 1209
1210 /* Give capacitors etc. time to drain to avoid kernel panic msg. */
3f37d4f6 1211 mdelay(500);
1b1305e9
SH		 1212
1213 return NOTIFY_DONE;
cfb61a41
CC		 1214}
1215
4fd41151 1216int axp20x_match_device(struct axp20x_dev *axp20x)
af7e9069 1217{
e47a3cf7 1218 struct device *dev = axp20x->dev;
b2cb2ae2
AP		 1219 const struct mfd_cell *cells_no_irq = NULL;
1220 int nr_cells_no_irq = 0;
af7e9069 1221
830fafce 1222 axp20x->variant = (long)device_get_match_data(dev);
af7e9069 1223 switch (axp20x->variant) {
d8d79f8f
MS		 1224 case AXP152_ID:
1225 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
1226 axp20x->cells = axp152_cells;
1227 axp20x->regmap_cfg = &axp152_regmap_config;
1228 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
1229 break;
63eeabbc
AM		 1230 case AXP192_ID:
1231 axp20x->nr_cells = ARRAY_SIZE(axp192_cells);
1232 axp20x->cells = axp192_cells;
1233 axp20x->regmap_cfg = &axp192_regmap_config;
1234 axp20x->regmap_irq_chip = &axp192_regmap_irq_chip;
1235 break;
af7e9069
JP		 1236 case AXP202_ID:
1237 case AXP209_ID:
1238 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
1239 axp20x->cells = axp20x_cells;
1240 axp20x->regmap_cfg = &axp20x_regmap_config;
1241 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
1242 break;
f05be589 1243 case AXP221_ID:
4c650561
QS		 1244 axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
1245 axp20x->cells = axp221_cells;
1246 axp20x->regmap_cfg = &axp22x_regmap_config;
1247 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
1248 break;
02071f0f 1249 case AXP223_ID:
4c650561
QS		 1250 axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
1251 axp20x->cells = axp223_cells;
f05be589
BB		 1252 axp20x->regmap_cfg = &axp22x_regmap_config;
1253 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
1254 break;
af7e9069
JP		 1255 case AXP288_ID:
1256 axp20x->cells = axp288_cells;
1257 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
1258 axp20x->regmap_cfg = &axp288_regmap_config;
1259 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
0a5454c9 1260 axp20x->irq_flags = IRQF_TRIGGER_LOW;
af7e9069 1261 break;
75c8cb2f
MB		 1262 case AXP313A_ID:
1263 axp20x->nr_cells = ARRAY_SIZE(axp313a_cells);
1264 axp20x->cells = axp313a_cells;
1265 axp20x->regmap_cfg = &axp313a_regmap_config;
1266 axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
1267 break;
b5bfc8ab
AP		 1268 case AXP717_ID:
1269 axp20x->nr_cells = ARRAY_SIZE(axp717_cells);
1270 axp20x->cells = axp717_cells;
1271 axp20x->regmap_cfg = &axp717_regmap_config;
1272 axp20x->regmap_irq_chip = &axp717_regmap_irq_chip;
1273 break;
1578353e
IZ		 1274 case AXP803_ID:
1275 axp20x->nr_cells = ARRAY_SIZE(axp803_cells);
1276 axp20x->cells = axp803_cells;
1277 axp20x->regmap_cfg = &axp288_regmap_config;
1278 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
1279 break;
8824ee85 1280 case AXP806_ID:
3efc465f
AP		 1281 /*
1282 * Don't register the power key part if in slave mode or
1283 * if there is no interrupt line.
1284 */
06f49010 1285 if (of_property_read_bool(axp20x->dev->of_node,
b2cb2ae2 1286 "x-powers,self-working-mode")) {
06f49010
CYT		 1287 axp20x->nr_cells = ARRAY_SIZE(axp806_self_working_cells);
1288 axp20x->cells = axp806_self_working_cells;
1289 } else {
1290 axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
1291 axp20x->cells = axp806_cells;
1292 }
b2cb2ae2
AP		 1293 nr_cells_no_irq = ARRAY_SIZE(axp806_cells);
1294 cells_no_irq = axp806_cells;
8824ee85
CYT		 1295 axp20x->regmap_cfg = &axp806_regmap_config;
1296 axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
1297 break;
20147f0d
CYT		 1298 case AXP809_ID:
1299 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
1300 axp20x->cells = axp809_cells;
1301 axp20x->regmap_cfg = &axp22x_regmap_config;
1302 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
1303 break;
7303733a
CYT		 1304 case AXP813_ID:
1305 axp20x->nr_cells = ARRAY_SIZE(axp813_cells);
1306 axp20x->cells = axp813_cells;
1307 axp20x->regmap_cfg = &axp288_regmap_config;
1308 /*
1309 * The IRQ table given in the datasheet is incorrect.
1310 * In IRQ enable/status registers 1, there are separate
1311 * IRQs for ACIN and VBUS, instead of bits [7:5] being
1312 * the same as bits [4:2]. So it shares the same IRQs
1313 * as the AXP803, rather than the AXP288.
1314 */
1315 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
1316 break;
e0f8ad2a 1317 case AXP15060_ID:
b2cb2ae2
AP		 1318 axp20x->nr_cells = ARRAY_SIZE(axp15060_cells);
1319 axp20x->cells = axp15060_cells;
e0f8ad2a
SQ		 1320 axp20x->regmap_cfg = &axp15060_regmap_config;
1321 axp20x->regmap_irq_chip = &axp15060_regmap_irq_chip;
1322 break;
af7e9069
JP		 1323 default:
1324 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
1325 return -EINVAL;
1326 }
b2cb2ae2
AP		 1327
1328 /*
1329 * Use an alternative cell array when no interrupt line is connected,
1330 * since IRQs are required by some drivers.
1331 * The default is the safe "regulator-only", as this works fine without
1332 * an interrupt specified.
1333 */
1334 if (axp20x->irq <= 0) {
1335 if (cells_no_irq) {
1336 axp20x->nr_cells = nr_cells_no_irq;
1337 axp20x->cells = cells_no_irq;
1338 } else {
1339 axp20x->nr_cells = ARRAY_SIZE(axp_regulator_only_cells);
1340 axp20x->cells = axp_regulator_only_cells;
1341 }
1342 }
1343
af7e9069 1344 dev_info(dev, "AXP20x variant %s found\n",
2260a453 1345 axp20x_model_names[axp20x->variant]);
af7e9069
JP		 1346
1347 return 0;
1348}
4fd41151 1349EXPORT_SYMBOL(axp20x_match_device);
af7e9069 1350
4fd41151 1351int axp20x_device_probe(struct axp20x_dev *axp20x)
cfb61a41 1352{
cfb61a41
CC		 1353 int ret;
1354
696f0b3f
CYT		 1355 /*
1356 * The AXP806 supports either master/standalone or slave mode.
1357 * Slave mode allows sharing the serial bus, even with multiple
1358 * AXP806 which all have the same hardware address.
1359 *
1360 * This is done with extra "serial interface address extension",
1361 * or AXP806_BUS_ADDR_EXT, and "register address extension", or
1362 * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
1363 * 1 bit customizable at the factory, and 1 bit depending on the
1364 * state of an external pin. The latter is writable. The device
1365 * will only respond to operations to its other registers when
1366 * the these device addressing bits (in the upper 4 bits of the
1367 * registers) match.
1368 *
c0369698
RIL		 1369 * By default we support an AXP806 chained to an AXP809 in slave
1370 * mode. Boards which use an AXP806 in master mode can set the
1371 * property "x-powers,master-mode" to override the default.
696f0b3f 1372 */
c0369698
RIL		 1373 if (axp20x->variant == AXP806_ID) {
1374 if (of_property_read_bool(axp20x->dev->of_node,
06f49010
CYT		 1375 "x-powers,master-mode") ||
1376 of_property_read_bool(axp20x->dev->of_node,
1377 "x-powers,self-working-mode"))
c0369698
RIL		 1378 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
1379 AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
1380 else
1381 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
1382 AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
1383 }
696f0b3f 1384
3efc465f
AP		 1385 /* Only if there is an interrupt line connected towards the CPU. */
1386 if (axp20x->irq > 0) {
1387 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
1388 IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
1389 -1, axp20x->regmap_irq_chip,
1390 &axp20x->regmap_irqc);
1391 if (ret) {
1392 dev_err(axp20x->dev, "failed to add irq chip: %d\n",
1393 ret);
1394 return ret;
1395 }
cfb61a41
CC		 1396 }
1397
af7e9069 1398 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
2260a453 1399 axp20x->nr_cells, NULL, 0, NULL);
cfb61a41
CC		 1400
1401 if (ret) {
4fd41151
CYT		 1402 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
1403 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41
CC		 1404 return ret;
1405 }
1406
1b1305e9
SH		 1407 if (axp20x->variant != AXP288_ID)
1408 devm_register_sys_off_handler(axp20x->dev,
1409 SYS_OFF_MODE_POWER_OFF,
1410 SYS_OFF_PRIO_DEFAULT,
1411 axp20x_power_off, axp20x);
cfb61a41 1412
4fd41151 1413 dev_info(axp20x->dev, "AXP20X driver loaded\n");
cfb61a41
CC		 1414
1415 return 0;
1416}
4fd41151 1417EXPORT_SYMBOL(axp20x_device_probe);
cfb61a41 1418
3c15e00e 1419void axp20x_device_remove(struct axp20x_dev *axp20x)
cfb61a41 1420{
cfb61a41 1421 mfd_remove_devices(axp20x->dev);
4fd41151 1422 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41 1423}
4fd41151 1424EXPORT_SYMBOL(axp20x_device_remove);
cfb61a41
CC		 1425
1426MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
1427MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1428MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)