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powerpc/mm: Rename pte fragment functions
[linux-2.6-block.git] / drivers / mfd / axp20x.c
CommitLineData
cfb61a41 1/*
4fd41151 2 * MFD core driver for the X-Powers' Power Management ICs
cfb61a41 3 *
af7e9069
JP		 4 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
cfb61a41 7 *
4fd41151
CYT		 8 * This file contains the interface independent core functions.
9 *
e740235d
CYT		 10 * Copyright (C) 2014 Carlo Caione
11 *
cfb61a41
CC		 12 * Author: Carlo Caione <carlo@caione.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/err.h>
179dc63d 20#include <linux/delay.h>
cfb61a41
CC		 21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <linux/regmap.h>
cfb61a41
CC		 26#include <linux/regulator/consumer.h>
27#include <linux/mfd/axp20x.h>
28#include <linux/mfd/core.h>
29#include <linux/of_device.h>
af7e9069 30#include <linux/acpi.h>
cfb61a41
CC		 31
32#define AXP20X_OFF 0x80
33
c0369698 34#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
696f0b3f
CYT		 35#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
36
c31e858b 37static const char * const axp20x_model_names[] = {
d8d79f8f 38 "AXP152",
af7e9069
JP		 39 "AXP202",
40 "AXP209",
f05be589 41 "AXP221",
02071f0f 42 "AXP223",
af7e9069 43 "AXP288",
1578353e 44 "AXP803",
8824ee85 45 "AXP806",
20147f0d 46 "AXP809",
7303733a 47 "AXP813",
af7e9069
JP		 48};
49
d8d79f8f
MS		 50static const struct regmap_range axp152_writeable_ranges[] = {
51 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
52 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
53};
54
55static const struct regmap_range axp152_volatile_ranges[] = {
56 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
57 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
58 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
59};
60
61static const struct regmap_access_table axp152_writeable_table = {
62 .yes_ranges = axp152_writeable_ranges,
63 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
64};
65
66static const struct regmap_access_table axp152_volatile_table = {
67 .yes_ranges = axp152_volatile_ranges,
68 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
69};
70
cfb61a41
CC		 71static const struct regmap_range axp20x_writeable_ranges[] = {
72 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
97602370 73 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
cfb61a41 74 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
553ed4b5 75 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
cfb61a41
CC		 76};
77
78static const struct regmap_range axp20x_volatile_ranges[] = {
553ed4b5
BP		 79 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
80 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
cfb61a41 81 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
553ed4b5
BP		 82 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
83 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
84 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
cfb61a41
CC		 85};
86
87static const struct regmap_access_table axp20x_writeable_table = {
88 .yes_ranges = axp20x_writeable_ranges,
89 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
90};
91
92static const struct regmap_access_table axp20x_volatile_table = {
93 .yes_ranges = axp20x_volatile_ranges,
94 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
95};
96
20147f0d 97/* AXP22x ranges are shared with the AXP809, as they cover the same range */
f05be589
BB		 98static const struct regmap_range axp22x_writeable_ranges[] = {
99 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
97602370 100 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3),
f05be589
BB		 101 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
102};
103
104static const struct regmap_range axp22x_volatile_ranges[] = {
15093250 105 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
f05be589 106 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
15093250 107 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
ed7311f0 108 regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
15093250 109 regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
f05be589
BB		 110};
111
112static const struct regmap_access_table axp22x_writeable_table = {
113 .yes_ranges = axp22x_writeable_ranges,
114 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
115};
116
117static const struct regmap_access_table axp22x_volatile_table = {
118 .yes_ranges = axp22x_volatile_ranges,
119 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
120};
121
1578353e 122/* AXP288 ranges are shared with the AXP803, as they cover the same range */
af7e9069
JP		 123static const struct regmap_range axp288_writeable_ranges[] = {
124 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
125 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
126};
127
128static const struct regmap_range axp288_volatile_ranges[] = {
cd532166
HG		 129 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
130 regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
131 regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
0c384fc8 132 regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
af7e9069 133 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
cd532166
HG		 134 regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
135 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
136 regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
137 regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
af7e9069
JP		 138};
139
140static const struct regmap_access_table axp288_writeable_table = {
141 .yes_ranges = axp288_writeable_ranges,
142 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
143};
144
145static const struct regmap_access_table axp288_volatile_table = {
146 .yes_ranges = axp288_volatile_ranges,
147 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
148};
149
8824ee85
CYT		 150static const struct regmap_range axp806_writeable_ranges[] = {
151 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
152 regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
153 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
154 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
34d9030b 155 regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
8824ee85
CYT		 156};
157
158static const struct regmap_range axp806_volatile_ranges[] = {
159 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
160};
161
162static const struct regmap_access_table axp806_writeable_table = {
163 .yes_ranges = axp806_writeable_ranges,
164 .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
165};
166
167static const struct regmap_access_table axp806_volatile_table = {
168 .yes_ranges = axp806_volatile_ranges,
169 .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
170};
171
d8d79f8f
MS		 172static struct resource axp152_pek_resources[] = {
173 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
174 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
175};
176
cd7cf27b
MH		 177static struct resource axp20x_ac_power_supply_resources[] = {
178 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
179 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
180 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
181};
182
cfb61a41
CC		 183static struct resource axp20x_pek_resources[] = {
184 {
185 .name = "PEK_DBR",
186 .start = AXP20X_IRQ_PEK_RIS_EDGE,
187 .end = AXP20X_IRQ_PEK_RIS_EDGE,
188 .flags = IORESOURCE_IRQ,
189 }, {
190 .name = "PEK_DBF",
191 .start = AXP20X_IRQ_PEK_FAL_EDGE,
192 .end = AXP20X_IRQ_PEK_FAL_EDGE,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
8de4efda
HG		 197static struct resource axp20x_usb_power_supply_resources[] = {
198 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
199 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
200 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
201 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
202};
203
ecd98cce
HG		 204static struct resource axp22x_usb_power_supply_resources[] = {
205 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
206 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
207};
208
f05be589
BB		 209static struct resource axp22x_pek_resources[] = {
210 {
211 .name = "PEK_DBR",
212 .start = AXP22X_IRQ_PEK_RIS_EDGE,
213 .end = AXP22X_IRQ_PEK_RIS_EDGE,
214 .flags = IORESOURCE_IRQ,
215 }, {
216 .name = "PEK_DBF",
217 .start = AXP22X_IRQ_PEK_FAL_EDGE,
218 .end = AXP22X_IRQ_PEK_FAL_EDGE,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
e56e5ad6
BF		 223static struct resource axp288_power_button_resources[] = {
224 {
225 .name = "PEK_DBR",
1af468eb
HG		 226 .start = AXP288_IRQ_POKP,
227 .end = AXP288_IRQ_POKP,
e56e5ad6
BF		 228 .flags = IORESOURCE_IRQ,
229 },
230 {
231 .name = "PEK_DBF",
1af468eb
HG		 232 .start = AXP288_IRQ_POKN,
233 .end = AXP288_IRQ_POKN,
e56e5ad6
BF		 234 .flags = IORESOURCE_IRQ,
235 },
236};
237
d6387874 238static struct resource axp288_fuel_gauge_resources[] = {
af7e9069
JP		 239 {
240 .start = AXP288_IRQ_QWBTU,
241 .end = AXP288_IRQ_QWBTU,
242 .flags = IORESOURCE_IRQ,
243 },
244 {
245 .start = AXP288_IRQ_WBTU,
246 .end = AXP288_IRQ_WBTU,
247 .flags = IORESOURCE_IRQ,
248 },
249 {
250 .start = AXP288_IRQ_QWBTO,
251 .end = AXP288_IRQ_QWBTO,
252 .flags = IORESOURCE_IRQ,
253 },
254 {
255 .start = AXP288_IRQ_WBTO,
256 .end = AXP288_IRQ_WBTO,
257 .flags = IORESOURCE_IRQ,
258 },
259 {
260 .start = AXP288_IRQ_WL2,
261 .end = AXP288_IRQ_WL2,
262 .flags = IORESOURCE_IRQ,
263 },
264 {
265 .start = AXP288_IRQ_WL1,
266 .end = AXP288_IRQ_WL1,
267 .flags = IORESOURCE_IRQ,
268 },
269};
270
1578353e
IZ		 271static struct resource axp803_pek_resources[] = {
272 {
273 .name = "PEK_DBR",
274 .start = AXP803_IRQ_PEK_RIS_EDGE,
275 .end = AXP803_IRQ_PEK_RIS_EDGE,
276 .flags = IORESOURCE_IRQ,
277 }, {
278 .name = "PEK_DBF",
279 .start = AXP803_IRQ_PEK_FAL_EDGE,
280 .end = AXP803_IRQ_PEK_FAL_EDGE,
281 .flags = IORESOURCE_IRQ,
282 },
283};
284
20147f0d
CYT		 285static struct resource axp809_pek_resources[] = {
286 {
287 .name = "PEK_DBR",
288 .start = AXP809_IRQ_PEK_RIS_EDGE,
289 .end = AXP809_IRQ_PEK_RIS_EDGE,
290 .flags = IORESOURCE_IRQ,
291 }, {
292 .name = "PEK_DBF",
293 .start = AXP809_IRQ_PEK_FAL_EDGE,
294 .end = AXP809_IRQ_PEK_FAL_EDGE,
295 .flags = IORESOURCE_IRQ,
296 },
297};
298
d8d79f8f
MS		 299static const struct regmap_config axp152_regmap_config = {
300 .reg_bits = 8,
301 .val_bits = 8,
302 .wr_table = &axp152_writeable_table,
303 .volatile_table = &axp152_volatile_table,
304 .max_register = AXP152_PWM1_DUTY_CYCLE,
305 .cache_type = REGCACHE_RBTREE,
306};
307
cfb61a41
CC		 308static const struct regmap_config axp20x_regmap_config = {
309 .reg_bits = 8,
310 .val_bits = 8,
311 .wr_table = &axp20x_writeable_table,
312 .volatile_table = &axp20x_volatile_table,
553ed4b5 313 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
cfb61a41
CC		 314 .cache_type = REGCACHE_RBTREE,
315};
316
f05be589
BB		 317static const struct regmap_config axp22x_regmap_config = {
318 .reg_bits = 8,
319 .val_bits = 8,
320 .wr_table = &axp22x_writeable_table,
321 .volatile_table = &axp22x_volatile_table,
322 .max_register = AXP22X_BATLOW_THRES1,
323 .cache_type = REGCACHE_RBTREE,
324};
325
af7e9069
JP		 326static const struct regmap_config axp288_regmap_config = {
327 .reg_bits = 8,
328 .val_bits = 8,
329 .wr_table = &axp288_writeable_table,
330 .volatile_table = &axp288_volatile_table,
331 .max_register = AXP288_FG_TUNE5,
332 .cache_type = REGCACHE_RBTREE,
333};
334
8824ee85
CYT		 335static const struct regmap_config axp806_regmap_config = {
336 .reg_bits = 8,
337 .val_bits = 8,
338 .wr_table = &axp806_writeable_table,
339 .volatile_table = &axp806_volatile_table,
34d9030b 340 .max_register = AXP806_REG_ADDR_EXT,
8824ee85
CYT		 341 .cache_type = REGCACHE_RBTREE,
342};
343
af7e9069
JP		 344#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
345 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
cfb61a41 346
d8d79f8f
MS		 347static const struct regmap_irq axp152_regmap_irqs[] = {
348 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
349 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
350 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
351 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
352 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
353 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
354 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
355 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
356 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
357 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
358 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
359 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
360 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
361 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
362 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
363 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
364 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
365};
366
cfb61a41 367static const struct regmap_irq axp20x_regmap_irqs[] = {
af7e9069
JP		 368 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
369 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
370 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
371 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
372 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
373 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
374 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
375 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
376 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
377 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
378 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
379 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
380 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
381 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
382 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
383 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
384 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
385 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
386 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
387 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
388 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
389 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
390 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
391 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
392 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
393 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
394 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
395 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
396 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
397 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
398 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
399 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
400 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
401 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
402 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
403 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
404 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
405};
406
f05be589
BB		 407static const struct regmap_irq axp22x_regmap_irqs[] = {
408 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
409 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
410 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
411 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
412 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
413 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
414 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
415 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
416 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
417 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
418 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
419 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
420 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
421 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
422 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
423 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
424 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
425 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
426 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
427 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
428 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
429 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
430 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
431 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
432 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
433};
434
af7e9069
JP		 435/* some IRQs are compatible with axp20x models */
436static const struct regmap_irq axp288_regmap_irqs[] = {
ff3bbc5c
JP		 437 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
438 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
439 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
8b44e678
HG		 440 INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
441 INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
442 INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
af7e9069 443
ff3bbc5c
JP		 444 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
445 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
af7e9069
JP		 446 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
447 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
ff3bbc5c
JP		 448 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
449 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
af7e9069
JP		 450
451 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
452 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
453 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
ff3bbc5c 454 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
af7e9069
JP		 455 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
456 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
457 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
458 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
459
460 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
461 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
462 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
463 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
464
465 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
466 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
467 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
468 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
469 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
470 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
471 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
ff3bbc5c 472 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
af7e9069
JP		 473
474 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
475 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
cfb61a41
CC		 476};
477
1578353e
IZ		 478static const struct regmap_irq axp803_regmap_irqs[] = {
479 INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V, 0, 7),
480 INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN, 0, 6),
481 INIT_REGMAP_IRQ(AXP803, ACIN_REMOVAL, 0, 5),
482 INIT_REGMAP_IRQ(AXP803, VBUS_OVER_V, 0, 4),
483 INIT_REGMAP_IRQ(AXP803, VBUS_PLUGIN, 0, 3),
484 INIT_REGMAP_IRQ(AXP803, VBUS_REMOVAL, 0, 2),
485 INIT_REGMAP_IRQ(AXP803, BATT_PLUGIN, 1, 7),
486 INIT_REGMAP_IRQ(AXP803, BATT_REMOVAL, 1, 6),
487 INIT_REGMAP_IRQ(AXP803, BATT_ENT_ACT_MODE, 1, 5),
488 INIT_REGMAP_IRQ(AXP803, BATT_EXIT_ACT_MODE, 1, 4),
489 INIT_REGMAP_IRQ(AXP803, CHARG, 1, 3),
490 INIT_REGMAP_IRQ(AXP803, CHARG_DONE, 1, 2),
491 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH, 2, 7),
492 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH_END, 2, 6),
493 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW, 2, 5),
494 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW_END, 2, 4),
495 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH, 2, 3),
496 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH_END, 2, 2),
497 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW, 2, 1),
498 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW_END, 2, 0),
499 INIT_REGMAP_IRQ(AXP803, DIE_TEMP_HIGH, 3, 7),
500 INIT_REGMAP_IRQ(AXP803, GPADC, 3, 2),
501 INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL1, 3, 1),
502 INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL2, 3, 0),
503 INIT_REGMAP_IRQ(AXP803, TIMER, 4, 7),
504 INIT_REGMAP_IRQ(AXP803, PEK_RIS_EDGE, 4, 6),
505 INIT_REGMAP_IRQ(AXP803, PEK_FAL_EDGE, 4, 5),
506 INIT_REGMAP_IRQ(AXP803, PEK_SHORT, 4, 4),
507 INIT_REGMAP_IRQ(AXP803, PEK_LONG, 4, 3),
508 INIT_REGMAP_IRQ(AXP803, PEK_OVER_OFF, 4, 2),
509 INIT_REGMAP_IRQ(AXP803, GPIO1_INPUT, 4, 1),
510 INIT_REGMAP_IRQ(AXP803, GPIO0_INPUT, 4, 0),
511 INIT_REGMAP_IRQ(AXP803, BC_USB_CHNG, 5, 1),
512 INIT_REGMAP_IRQ(AXP803, MV_CHNG, 5, 0),
513};
514
8824ee85
CYT		 515static const struct regmap_irq axp806_regmap_irqs[] = {
516 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
517 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
518 INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
519 INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
520 INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
521 INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
522 INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
523 INIT_REGMAP_IRQ(AXP806, PWROK_LONG, 1, 0),
524 INIT_REGMAP_IRQ(AXP806, PWROK_SHORT, 1, 1),
525 INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
526 INIT_REGMAP_IRQ(AXP806, PWROK_FALL, 1, 5),
527 INIT_REGMAP_IRQ(AXP806, PWROK_RISE, 1, 6),
528};
529
20147f0d
CYT		 530static const struct regmap_irq axp809_regmap_irqs[] = {
531 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
532 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
533 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
534 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
535 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
536 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
537 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
538 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
539 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
540 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
541 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
542 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
543 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
544 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
545 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
546 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
547 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
548 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
549 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
550 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
551 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
552 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
553 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
554 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
555 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
556 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
557 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
558 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
559 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
560 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
561 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
562 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
563};
564
d8d79f8f
MS		 565static const struct regmap_irq_chip axp152_regmap_irq_chip = {
566 .name = "axp152_irq_chip",
567 .status_base = AXP152_IRQ1_STATE,
568 .ack_base = AXP152_IRQ1_STATE,
569 .mask_base = AXP152_IRQ1_EN,
570 .mask_invert = true,
571 .init_ack_masked = true,
572 .irqs = axp152_regmap_irqs,
573 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
574 .num_regs = 3,
575};
576
cfb61a41
CC		 577static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
578 .name = "axp20x_irq_chip",
579 .status_base = AXP20X_IRQ1_STATE,
580 .ack_base = AXP20X_IRQ1_STATE,
581 .mask_base = AXP20X_IRQ1_EN,
af7e9069
JP		 582 .mask_invert = true,
583 .init_ack_masked = true,
cfb61a41
CC		 584 .irqs = axp20x_regmap_irqs,
585 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
af7e9069
JP		 586 .num_regs = 5,
587
588};
589
f05be589
BB		 590static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
591 .name = "axp22x_irq_chip",
592 .status_base = AXP20X_IRQ1_STATE,
593 .ack_base = AXP20X_IRQ1_STATE,
594 .mask_base = AXP20X_IRQ1_EN,
595 .mask_invert = true,
596 .init_ack_masked = true,
597 .irqs = axp22x_regmap_irqs,
598 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
599 .num_regs = 5,
600};
601
af7e9069
JP		 602static const struct regmap_irq_chip axp288_regmap_irq_chip = {
603 .name = "axp288_irq_chip",
604 .status_base = AXP20X_IRQ1_STATE,
605 .ack_base = AXP20X_IRQ1_STATE,
606 .mask_base = AXP20X_IRQ1_EN,
cfb61a41
CC		 607 .mask_invert = true,
608 .init_ack_masked = true,
af7e9069
JP		 609 .irqs = axp288_regmap_irqs,
610 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
611 .num_regs = 6,
612
cfb61a41
CC		 613};
614
1578353e
IZ		 615static const struct regmap_irq_chip axp803_regmap_irq_chip = {
616 .name = "axp803",
617 .status_base = AXP20X_IRQ1_STATE,
618 .ack_base = AXP20X_IRQ1_STATE,
619 .mask_base = AXP20X_IRQ1_EN,
620 .mask_invert = true,
621 .init_ack_masked = true,
622 .irqs = axp803_regmap_irqs,
623 .num_irqs = ARRAY_SIZE(axp803_regmap_irqs),
624 .num_regs = 6,
625};
626
8824ee85
CYT		 627static const struct regmap_irq_chip axp806_regmap_irq_chip = {
628 .name = "axp806",
629 .status_base = AXP20X_IRQ1_STATE,
630 .ack_base = AXP20X_IRQ1_STATE,
631 .mask_base = AXP20X_IRQ1_EN,
632 .mask_invert = true,
633 .init_ack_masked = true,
634 .irqs = axp806_regmap_irqs,
635 .num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
636 .num_regs = 2,
637};
638
20147f0d
CYT		 639static const struct regmap_irq_chip axp809_regmap_irq_chip = {
640 .name = "axp809",
641 .status_base = AXP20X_IRQ1_STATE,
642 .ack_base = AXP20X_IRQ1_STATE,
643 .mask_base = AXP20X_IRQ1_EN,
644 .mask_invert = true,
645 .init_ack_masked = true,
646 .irqs = axp809_regmap_irqs,
647 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
648 .num_regs = 5,
649};
650
cfb61a41
CC		 651static struct mfd_cell axp20x_cells[] = {
652 {
b419c16b
MR		 653 .name = "axp20x-gpio",
654 .of_compatible = "x-powers,axp209-gpio",
655 }, {
8de4efda
HG		 656 .name = "axp20x-pek",
657 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
658 .resources = axp20x_pek_resources,
cfb61a41 659 }, {
8de4efda 660 .name = "axp20x-regulator",
4d5e5c34
QS		 661 }, {
662 .name = "axp20x-adc",
b4aeceb6
QS		 663 }, {
664 .name = "axp20x-battery-power-supply",
665 .of_compatible = "x-powers,axp209-battery-power-supply",
cd7cf27b
MH		 666 }, {
667 .name = "axp20x-ac-power-supply",
668 .of_compatible = "x-powers,axp202-ac-power-supply",
669 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
670 .resources = axp20x_ac_power_supply_resources,
8de4efda
HG		 671 }, {
672 .name = "axp20x-usb-power-supply",
673 .of_compatible = "x-powers,axp202-usb-power-supply",
674 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
675 .resources = axp20x_usb_power_supply_resources,
cfb61a41
CC		 676 },
677};
678
4c650561
QS		 679static struct mfd_cell axp221_cells[] = {
680 {
f4463633 681 .name = "axp221-pek",
4c650561
QS		 682 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
683 .resources = axp22x_pek_resources,
684 }, {
685 .name = "axp20x-regulator",
4d5e5c34
QS		 686 }, {
687 .name = "axp22x-adc"
95c4f531
QS		 688 }, {
689 .name = "axp20x-ac-power-supply",
690 .of_compatible = "x-powers,axp221-ac-power-supply",
691 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
692 .resources = axp20x_ac_power_supply_resources,
b4aeceb6
QS		 693 }, {
694 .name = "axp20x-battery-power-supply",
695 .of_compatible = "x-powers,axp221-battery-power-supply",
4c650561
QS		 696 }, {
697 .name = "axp20x-usb-power-supply",
698 .of_compatible = "x-powers,axp221-usb-power-supply",
699 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
700 .resources = axp22x_usb_power_supply_resources,
701 },
702};
703
704static struct mfd_cell axp223_cells[] = {
f05be589 705 {
f4463633 706 .name = "axp221-pek",
f05be589
BB		 707 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
708 .resources = axp22x_pek_resources,
4d5e5c34
QS		 709 }, {
710 .name = "axp22x-adc",
b4aeceb6
QS		 711 }, {
712 .name = "axp20x-battery-power-supply",
713 .of_compatible = "x-powers,axp221-battery-power-supply",
6d4fa89d
CYT		 714 }, {
715 .name = "axp20x-regulator",
95c4f531
QS		 716 }, {
717 .name = "axp20x-ac-power-supply",
718 .of_compatible = "x-powers,axp221-ac-power-supply",
719 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
720 .resources = axp20x_ac_power_supply_resources,
ecd98cce
HG		 721 }, {
722 .name = "axp20x-usb-power-supply",
4c650561 723 .of_compatible = "x-powers,axp223-usb-power-supply",
ecd98cce
HG		 724 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
725 .resources = axp22x_usb_power_supply_resources,
f05be589
BB		 726 },
727};
728
d8d79f8f
MS		 729static struct mfd_cell axp152_cells[] = {
730 {
731 .name = "axp20x-pek",
732 .num_resources = ARRAY_SIZE(axp152_pek_resources),
733 .resources = axp152_pek_resources,
734 },
735};
736
af7e9069
JP		 737static struct resource axp288_adc_resources[] = {
738 {
739 .name = "GPADC",
740 .start = AXP288_IRQ_GPADC,
741 .end = AXP288_IRQ_GPADC,
742 .flags = IORESOURCE_IRQ,
743 },
744};
745
bdb01f78
RP		 746static struct resource axp288_extcon_resources[] = {
747 {
748 .start = AXP288_IRQ_VBUS_FALL,
749 .end = AXP288_IRQ_VBUS_FALL,
750 .flags = IORESOURCE_IRQ,
751 },
752 {
753 .start = AXP288_IRQ_VBUS_RISE,
754 .end = AXP288_IRQ_VBUS_RISE,
755 .flags = IORESOURCE_IRQ,
756 },
757 {
758 .start = AXP288_IRQ_MV_CHNG,
759 .end = AXP288_IRQ_MV_CHNG,
760 .flags = IORESOURCE_IRQ,
761 },
762 {
763 .start = AXP288_IRQ_BC_USB_CHNG,
764 .end = AXP288_IRQ_BC_USB_CHNG,
765 .flags = IORESOURCE_IRQ,
766 },
767};
768
af7e9069
JP		 769static struct resource axp288_charger_resources[] = {
770 {
771 .start = AXP288_IRQ_OV,
772 .end = AXP288_IRQ_OV,
773 .flags = IORESOURCE_IRQ,
774 },
775 {
776 .start = AXP288_IRQ_DONE,
777 .end = AXP288_IRQ_DONE,
778 .flags = IORESOURCE_IRQ,
779 },
780 {
781 .start = AXP288_IRQ_CHARGING,
782 .end = AXP288_IRQ_CHARGING,
783 .flags = IORESOURCE_IRQ,
784 },
785 {
786 .start = AXP288_IRQ_SAFE_QUIT,
787 .end = AXP288_IRQ_SAFE_QUIT,
788 .flags = IORESOURCE_IRQ,
789 },
790 {
791 .start = AXP288_IRQ_SAFE_ENTER,
792 .end = AXP288_IRQ_SAFE_ENTER,
793 .flags = IORESOURCE_IRQ,
794 },
795 {
796 .start = AXP288_IRQ_QCBTU,
797 .end = AXP288_IRQ_QCBTU,
798 .flags = IORESOURCE_IRQ,
799 },
800 {
801 .start = AXP288_IRQ_CBTU,
802 .end = AXP288_IRQ_CBTU,
803 .flags = IORESOURCE_IRQ,
804 },
805 {
806 .start = AXP288_IRQ_QCBTO,
807 .end = AXP288_IRQ_QCBTO,
808 .flags = IORESOURCE_IRQ,
809 },
810 {
811 .start = AXP288_IRQ_CBTO,
812 .end = AXP288_IRQ_CBTO,
813 .flags = IORESOURCE_IRQ,
814 },
815};
816
817static struct mfd_cell axp288_cells[] = {
818 {
819 .name = "axp288_adc",
820 .num_resources = ARRAY_SIZE(axp288_adc_resources),
821 .resources = axp288_adc_resources,
822 },
bdb01f78
RP		 823 {
824 .name = "axp288_extcon",
825 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
826 .resources = axp288_extcon_resources,
827 },
af7e9069
JP		 828 {
829 .name = "axp288_charger",
830 .num_resources = ARRAY_SIZE(axp288_charger_resources),
831 .resources = axp288_charger_resources,
832 },
833 {
d6387874
TB		 834 .name = "axp288_fuel_gauge",
835 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
836 .resources = axp288_fuel_gauge_resources,
af7e9069 837 },
e56e5ad6 838 {
f4463633 839 .name = "axp221-pek",
e56e5ad6
BF		 840 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
841 .resources = axp288_power_button_resources,
842 },
d8139f63
AL		 843 {
844 .name = "axp288_pmic_acpi",
845 },
af7e9069
JP		 846};
847
1578353e
IZ		 848static struct mfd_cell axp803_cells[] = {
849 {
f4463633 850 .name = "axp221-pek",
1578353e
IZ		 851 .num_resources = ARRAY_SIZE(axp803_pek_resources),
852 .resources = axp803_pek_resources,
9b79ff10
IZ		 853 },
854 { .name = "axp20x-regulator" },
1578353e
IZ		 855};
856
8824ee85
CYT		 857static struct mfd_cell axp806_cells[] = {
858 {
859 .id = 2,
860 .name = "axp20x-regulator",
861 },
862};
863
20147f0d
CYT		 864static struct mfd_cell axp809_cells[] = {
865 {
f4463633 866 .name = "axp221-pek",
20147f0d
CYT		 867 .num_resources = ARRAY_SIZE(axp809_pek_resources),
868 .resources = axp809_pek_resources,
869 }, {
8824ee85 870 .id = 1,
20147f0d
CYT		 871 .name = "axp20x-regulator",
872 },
873};
874
7303733a
CYT		 875static struct mfd_cell axp813_cells[] = {
876 {
f4463633 877 .name = "axp221-pek",
7303733a
CYT		 878 .num_resources = ARRAY_SIZE(axp803_pek_resources),
879 .resources = axp803_pek_resources,
9a43206b
CYT		 880 }, {
881 .name = "axp20x-regulator",
2bb3253c
QS		 882 }, {
883 .name = "axp20x-gpio",
884 .of_compatible = "x-powers,axp813-gpio",
7303733a
CYT		 885 }
886};
887
cfb61a41
CC		 888static struct axp20x_dev *axp20x_pm_power_off;
889static void axp20x_power_off(void)
890{
af7e9069
JP		 891 if (axp20x_pm_power_off->variant == AXP288_ID)
892 return;
893
cfb61a41
CC		 894 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
895 AXP20X_OFF);
179dc63d
HG		 896
897 /* Give capacitors etc. time to drain to avoid kernel panic msg. */
898 msleep(500);
cfb61a41
CC		 899}
900
4fd41151 901int axp20x_match_device(struct axp20x_dev *axp20x)
af7e9069 902{
e47a3cf7 903 struct device *dev = axp20x->dev;
af7e9069
JP		 904 const struct acpi_device_id *acpi_id;
905 const struct of_device_id *of_id;
906
907 if (dev->of_node) {
af7acc3d 908 of_id = of_match_device(dev->driver->of_match_table, dev);
af7e9069
JP		 909 if (!of_id) {
910 dev_err(dev, "Unable to match OF ID\n");
911 return -ENODEV;
912 }
2260a453 913 axp20x->variant = (long)of_id->data;
af7e9069
JP		 914 } else {
915 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
916 if (!acpi_id || !acpi_id->driver_data) {
917 dev_err(dev, "Unable to match ACPI ID and data\n");
918 return -ENODEV;
919 }
2260a453 920 axp20x->variant = (long)acpi_id->driver_data;
af7e9069
JP		 921 }
922
923 switch (axp20x->variant) {
d8d79f8f
MS		 924 case AXP152_ID:
925 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
926 axp20x->cells = axp152_cells;
927 axp20x->regmap_cfg = &axp152_regmap_config;
928 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
929 break;
af7e9069
JP		 930 case AXP202_ID:
931 case AXP209_ID:
932 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
933 axp20x->cells = axp20x_cells;
934 axp20x->regmap_cfg = &axp20x_regmap_config;
935 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
936 break;
f05be589 937 case AXP221_ID:
4c650561
QS		 938 axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
939 axp20x->cells = axp221_cells;
940 axp20x->regmap_cfg = &axp22x_regmap_config;
941 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
942 break;
02071f0f 943 case AXP223_ID:
4c650561
QS		 944 axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
945 axp20x->cells = axp223_cells;
f05be589
BB		 946 axp20x->regmap_cfg = &axp22x_regmap_config;
947 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
948 break;
af7e9069
JP		 949 case AXP288_ID:
950 axp20x->cells = axp288_cells;
951 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
952 axp20x->regmap_cfg = &axp288_regmap_config;
953 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
0a5454c9 954 axp20x->irq_flags = IRQF_TRIGGER_LOW;
af7e9069 955 break;
1578353e
IZ		 956 case AXP803_ID:
957 axp20x->nr_cells = ARRAY_SIZE(axp803_cells);
958 axp20x->cells = axp803_cells;
959 axp20x->regmap_cfg = &axp288_regmap_config;
960 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
961 break;
8824ee85
CYT		 962 case AXP806_ID:
963 axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
964 axp20x->cells = axp806_cells;
965 axp20x->regmap_cfg = &axp806_regmap_config;
966 axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
967 break;
20147f0d
CYT		 968 case AXP809_ID:
969 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
970 axp20x->cells = axp809_cells;
971 axp20x->regmap_cfg = &axp22x_regmap_config;
972 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
973 break;
7303733a
CYT		 974 case AXP813_ID:
975 axp20x->nr_cells = ARRAY_SIZE(axp813_cells);
976 axp20x->cells = axp813_cells;
977 axp20x->regmap_cfg = &axp288_regmap_config;
978 /*
979 * The IRQ table given in the datasheet is incorrect.
980 * In IRQ enable/status registers 1, there are separate
981 * IRQs for ACIN and VBUS, instead of bits [7:5] being
982 * the same as bits [4:2]. So it shares the same IRQs
983 * as the AXP803, rather than the AXP288.
984 */
985 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
986 break;
af7e9069
JP		 987 default:
988 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
989 return -EINVAL;
990 }
991 dev_info(dev, "AXP20x variant %s found\n",
2260a453 992 axp20x_model_names[axp20x->variant]);
af7e9069
JP		 993
994 return 0;
995}
4fd41151 996EXPORT_SYMBOL(axp20x_match_device);
af7e9069 997
4fd41151 998int axp20x_device_probe(struct axp20x_dev *axp20x)
cfb61a41 999{
cfb61a41
CC		 1000 int ret;
1001
696f0b3f
CYT		 1002 /*
1003 * The AXP806 supports either master/standalone or slave mode.
1004 * Slave mode allows sharing the serial bus, even with multiple
1005 * AXP806 which all have the same hardware address.
1006 *
1007 * This is done with extra "serial interface address extension",
1008 * or AXP806_BUS_ADDR_EXT, and "register address extension", or
1009 * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
1010 * 1 bit customizable at the factory, and 1 bit depending on the
1011 * state of an external pin. The latter is writable. The device
1012 * will only respond to operations to its other registers when
1013 * the these device addressing bits (in the upper 4 bits of the
1014 * registers) match.
1015 *
c0369698
RIL		 1016 * By default we support an AXP806 chained to an AXP809 in slave
1017 * mode. Boards which use an AXP806 in master mode can set the
1018 * property "x-powers,master-mode" to override the default.
696f0b3f 1019 */
c0369698
RIL		 1020 if (axp20x->variant == AXP806_ID) {
1021 if (of_property_read_bool(axp20x->dev->of_node,
1022 "x-powers,master-mode"))
1023 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
1024 AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
1025 else
1026 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
1027 AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
1028 }
696f0b3f 1029
4fd41151 1030 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
0a5454c9
HG		 1031 IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
1032 -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc);
cfb61a41 1033 if (ret) {
4fd41151 1034 dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
cfb61a41
CC		 1035 return ret;
1036 }
1037
af7e9069 1038 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
2260a453 1039 axp20x->nr_cells, NULL, 0, NULL);
cfb61a41
CC		 1040
1041 if (ret) {
4fd41151
CYT		 1042 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
1043 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41
CC		 1044 return ret;
1045 }
1046
1047 if (!pm_power_off) {
1048 axp20x_pm_power_off = axp20x;
1049 pm_power_off = axp20x_power_off;
1050 }
1051
4fd41151 1052 dev_info(axp20x->dev, "AXP20X driver loaded\n");
cfb61a41
CC		 1053
1054 return 0;
1055}
4fd41151 1056EXPORT_SYMBOL(axp20x_device_probe);
cfb61a41 1057
4fd41151 1058int axp20x_device_remove(struct axp20x_dev *axp20x)
cfb61a41 1059{
cfb61a41
CC		 1060 if (axp20x == axp20x_pm_power_off) {
1061 axp20x_pm_power_off = NULL;
1062 pm_power_off = NULL;
1063 }
1064
1065 mfd_remove_devices(axp20x->dev);
4fd41151 1066 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41
CC		 1067
1068 return 0;
1069}
4fd41151 1070EXPORT_SYMBOL(axp20x_device_remove);
cfb61a41
CC		 1071
1072MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
1073MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1074MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)