projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mfd: axp20x: Add AC power supply cells for AXP22X PMICs
[linux-2.6-block.git] / drivers / mfd / axp20x.c
CommitLineData
cfb61a41 1/*
4fd41151 2 * MFD core driver for the X-Powers' Power Management ICs
cfb61a41 3 *
af7e9069
JP		 4 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
cfb61a41 7 *
4fd41151
CYT		 8 * This file contains the interface independent core functions.
9 *
e740235d
CYT		 10 * Copyright (C) 2014 Carlo Caione
11 *
cfb61a41
CC		 12 * Author: Carlo Caione <carlo@caione.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/err.h>
179dc63d 20#include <linux/delay.h>
cfb61a41
CC		 21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <linux/regmap.h>
cfb61a41
CC		 26#include <linux/regulator/consumer.h>
27#include <linux/mfd/axp20x.h>
28#include <linux/mfd/core.h>
29#include <linux/of_device.h>
af7e9069 30#include <linux/acpi.h>
cfb61a41
CC		 31
32#define AXP20X_OFF 0x80
33
c0369698 34#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
696f0b3f
CYT		 35#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
36
c31e858b 37static const char * const axp20x_model_names[] = {
d8d79f8f 38 "AXP152",
af7e9069
JP		 39 "AXP202",
40 "AXP209",
f05be589 41 "AXP221",
02071f0f 42 "AXP223",
af7e9069 43 "AXP288",
8824ee85 44 "AXP806",
20147f0d 45 "AXP809",
af7e9069
JP		 46};
47
d8d79f8f
MS		 48static const struct regmap_range axp152_writeable_ranges[] = {
49 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
50 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
51};
52
53static const struct regmap_range axp152_volatile_ranges[] = {
54 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
55 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
56 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
57};
58
59static const struct regmap_access_table axp152_writeable_table = {
60 .yes_ranges = axp152_writeable_ranges,
61 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
62};
63
64static const struct regmap_access_table axp152_volatile_table = {
65 .yes_ranges = axp152_volatile_ranges,
66 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
67};
68
cfb61a41
CC		 69static const struct regmap_range axp20x_writeable_ranges[] = {
70 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
71 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
553ed4b5 72 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
cfb61a41
CC		 73};
74
75static const struct regmap_range axp20x_volatile_ranges[] = {
553ed4b5
BP		 76 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
77 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
cfb61a41 78 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
553ed4b5
BP		 79 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
80 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
81 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
cfb61a41
CC		 82};
83
84static const struct regmap_access_table axp20x_writeable_table = {
85 .yes_ranges = axp20x_writeable_ranges,
86 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
87};
88
89static const struct regmap_access_table axp20x_volatile_table = {
90 .yes_ranges = axp20x_volatile_ranges,
91 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
92};
93
20147f0d 94/* AXP22x ranges are shared with the AXP809, as they cover the same range */
f05be589
BB		 95static const struct regmap_range axp22x_writeable_ranges[] = {
96 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
97 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
98};
99
100static const struct regmap_range axp22x_volatile_ranges[] = {
15093250 101 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
f05be589 102 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
15093250 103 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
ed7311f0 104 regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
15093250 105 regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
f05be589
BB		 106};
107
108static const struct regmap_access_table axp22x_writeable_table = {
109 .yes_ranges = axp22x_writeable_ranges,
110 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
111};
112
113static const struct regmap_access_table axp22x_volatile_table = {
114 .yes_ranges = axp22x_volatile_ranges,
115 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
116};
117
af7e9069
JP		 118static const struct regmap_range axp288_writeable_ranges[] = {
119 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
120 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
121};
122
123static const struct regmap_range axp288_volatile_ranges[] = {
cd532166
HG		 124 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
125 regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
126 regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
af7e9069 127 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
cd532166
HG		 128 regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
129 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
130 regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
131 regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
af7e9069
JP		 132};
133
134static const struct regmap_access_table axp288_writeable_table = {
135 .yes_ranges = axp288_writeable_ranges,
136 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
137};
138
139static const struct regmap_access_table axp288_volatile_table = {
140 .yes_ranges = axp288_volatile_ranges,
141 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
142};
143
8824ee85
CYT		 144static const struct regmap_range axp806_writeable_ranges[] = {
145 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
146 regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
147 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
148 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
34d9030b 149 regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
8824ee85
CYT		 150};
151
152static const struct regmap_range axp806_volatile_ranges[] = {
153 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
154};
155
156static const struct regmap_access_table axp806_writeable_table = {
157 .yes_ranges = axp806_writeable_ranges,
158 .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
159};
160
161static const struct regmap_access_table axp806_volatile_table = {
162 .yes_ranges = axp806_volatile_ranges,
163 .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
164};
165
d8d79f8f
MS		 166static struct resource axp152_pek_resources[] = {
167 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
168 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
169};
170
cd7cf27b
MH		 171static struct resource axp20x_ac_power_supply_resources[] = {
172 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
173 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
174 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
175};
176
cfb61a41
CC		 177static struct resource axp20x_pek_resources[] = {
178 {
179 .name = "PEK_DBR",
180 .start = AXP20X_IRQ_PEK_RIS_EDGE,
181 .end = AXP20X_IRQ_PEK_RIS_EDGE,
182 .flags = IORESOURCE_IRQ,
183 }, {
184 .name = "PEK_DBF",
185 .start = AXP20X_IRQ_PEK_FAL_EDGE,
186 .end = AXP20X_IRQ_PEK_FAL_EDGE,
187 .flags = IORESOURCE_IRQ,
188 },
189};
190
8de4efda
HG		 191static struct resource axp20x_usb_power_supply_resources[] = {
192 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
193 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
194 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
195 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
196};
197
ecd98cce
HG		 198static struct resource axp22x_usb_power_supply_resources[] = {
199 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
200 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
201};
202
f05be589
BB		 203static struct resource axp22x_pek_resources[] = {
204 {
205 .name = "PEK_DBR",
206 .start = AXP22X_IRQ_PEK_RIS_EDGE,
207 .end = AXP22X_IRQ_PEK_RIS_EDGE,
208 .flags = IORESOURCE_IRQ,
209 }, {
210 .name = "PEK_DBF",
211 .start = AXP22X_IRQ_PEK_FAL_EDGE,
212 .end = AXP22X_IRQ_PEK_FAL_EDGE,
213 .flags = IORESOURCE_IRQ,
214 },
215};
216
e56e5ad6
BF		 217static struct resource axp288_power_button_resources[] = {
218 {
219 .name = "PEK_DBR",
1af468eb
HG		 220 .start = AXP288_IRQ_POKP,
221 .end = AXP288_IRQ_POKP,
e56e5ad6
BF		 222 .flags = IORESOURCE_IRQ,
223 },
224 {
225 .name = "PEK_DBF",
1af468eb
HG		 226 .start = AXP288_IRQ_POKN,
227 .end = AXP288_IRQ_POKN,
e56e5ad6
BF		 228 .flags = IORESOURCE_IRQ,
229 },
230};
231
d6387874 232static struct resource axp288_fuel_gauge_resources[] = {
af7e9069
JP		 233 {
234 .start = AXP288_IRQ_QWBTU,
235 .end = AXP288_IRQ_QWBTU,
236 .flags = IORESOURCE_IRQ,
237 },
238 {
239 .start = AXP288_IRQ_WBTU,
240 .end = AXP288_IRQ_WBTU,
241 .flags = IORESOURCE_IRQ,
242 },
243 {
244 .start = AXP288_IRQ_QWBTO,
245 .end = AXP288_IRQ_QWBTO,
246 .flags = IORESOURCE_IRQ,
247 },
248 {
249 .start = AXP288_IRQ_WBTO,
250 .end = AXP288_IRQ_WBTO,
251 .flags = IORESOURCE_IRQ,
252 },
253 {
254 .start = AXP288_IRQ_WL2,
255 .end = AXP288_IRQ_WL2,
256 .flags = IORESOURCE_IRQ,
257 },
258 {
259 .start = AXP288_IRQ_WL1,
260 .end = AXP288_IRQ_WL1,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
20147f0d
CYT		 265static struct resource axp809_pek_resources[] = {
266 {
267 .name = "PEK_DBR",
268 .start = AXP809_IRQ_PEK_RIS_EDGE,
269 .end = AXP809_IRQ_PEK_RIS_EDGE,
270 .flags = IORESOURCE_IRQ,
271 }, {
272 .name = "PEK_DBF",
273 .start = AXP809_IRQ_PEK_FAL_EDGE,
274 .end = AXP809_IRQ_PEK_FAL_EDGE,
275 .flags = IORESOURCE_IRQ,
276 },
277};
278
d8d79f8f
MS		 279static const struct regmap_config axp152_regmap_config = {
280 .reg_bits = 8,
281 .val_bits = 8,
282 .wr_table = &axp152_writeable_table,
283 .volatile_table = &axp152_volatile_table,
284 .max_register = AXP152_PWM1_DUTY_CYCLE,
285 .cache_type = REGCACHE_RBTREE,
286};
287
cfb61a41
CC		 288static const struct regmap_config axp20x_regmap_config = {
289 .reg_bits = 8,
290 .val_bits = 8,
291 .wr_table = &axp20x_writeable_table,
292 .volatile_table = &axp20x_volatile_table,
553ed4b5 293 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
cfb61a41
CC		 294 .cache_type = REGCACHE_RBTREE,
295};
296
f05be589
BB		 297static const struct regmap_config axp22x_regmap_config = {
298 .reg_bits = 8,
299 .val_bits = 8,
300 .wr_table = &axp22x_writeable_table,
301 .volatile_table = &axp22x_volatile_table,
302 .max_register = AXP22X_BATLOW_THRES1,
303 .cache_type = REGCACHE_RBTREE,
304};
305
af7e9069
JP		 306static const struct regmap_config axp288_regmap_config = {
307 .reg_bits = 8,
308 .val_bits = 8,
309 .wr_table = &axp288_writeable_table,
310 .volatile_table = &axp288_volatile_table,
311 .max_register = AXP288_FG_TUNE5,
312 .cache_type = REGCACHE_RBTREE,
313};
314
8824ee85
CYT		 315static const struct regmap_config axp806_regmap_config = {
316 .reg_bits = 8,
317 .val_bits = 8,
318 .wr_table = &axp806_writeable_table,
319 .volatile_table = &axp806_volatile_table,
34d9030b 320 .max_register = AXP806_REG_ADDR_EXT,
8824ee85
CYT		 321 .cache_type = REGCACHE_RBTREE,
322};
323
af7e9069
JP		 324#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
325 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
cfb61a41 326
d8d79f8f
MS		 327static const struct regmap_irq axp152_regmap_irqs[] = {
328 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
329 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
330 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
331 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
332 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
333 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
334 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
335 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
336 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
337 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
338 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
339 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
340 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
341 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
342 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
343 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
344 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
345};
346
cfb61a41 347static const struct regmap_irq axp20x_regmap_irqs[] = {
af7e9069
JP		 348 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
349 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
350 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
351 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
352 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
353 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
354 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
355 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
356 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
357 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
358 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
359 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
360 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
361 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
362 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
363 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
364 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
365 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
366 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
367 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
368 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
369 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
370 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
371 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
372 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
373 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
374 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
375 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
376 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
377 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
378 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
379 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
380 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
381 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
382 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
383 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
384 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
385};
386
f05be589
BB		 387static const struct regmap_irq axp22x_regmap_irqs[] = {
388 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
389 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
390 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
391 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
392 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
393 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
394 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
395 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
396 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
397 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
398 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
399 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
400 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
401 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
402 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
403 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
404 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
405 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
406 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
407 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
408 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
409 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
410 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
411 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
412 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
413};
414
af7e9069
JP		 415/* some IRQs are compatible with axp20x models */
416static const struct regmap_irq axp288_regmap_irqs[] = {
ff3bbc5c
JP		 417 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
418 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
419 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
8b44e678
HG		 420 INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
421 INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
422 INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
af7e9069 423
ff3bbc5c
JP		 424 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
425 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
af7e9069
JP		 426 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
427 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
ff3bbc5c
JP		 428 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
429 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
af7e9069
JP		 430
431 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
432 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
433 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
ff3bbc5c 434 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
af7e9069
JP		 435 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
436 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
437 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
438 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
439
440 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
441 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
442 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
443 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
444
445 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
446 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
447 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
448 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
449 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
450 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
451 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
ff3bbc5c 452 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
af7e9069
JP		 453
454 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
455 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
cfb61a41
CC		 456};
457
8824ee85
CYT		 458static const struct regmap_irq axp806_regmap_irqs[] = {
459 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
460 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
461 INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
462 INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
463 INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
464 INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
465 INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
466 INIT_REGMAP_IRQ(AXP806, PWROK_LONG, 1, 0),
467 INIT_REGMAP_IRQ(AXP806, PWROK_SHORT, 1, 1),
468 INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
469 INIT_REGMAP_IRQ(AXP806, PWROK_FALL, 1, 5),
470 INIT_REGMAP_IRQ(AXP806, PWROK_RISE, 1, 6),
471};
472
20147f0d
CYT		 473static const struct regmap_irq axp809_regmap_irqs[] = {
474 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
475 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
476 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
477 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
478 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
479 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
480 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
481 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
482 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
483 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
484 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
485 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
486 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
487 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
488 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
489 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
490 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
491 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
492 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
493 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
494 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
495 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
496 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
497 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
498 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
499 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
500 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
501 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
502 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
503 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
504 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
505 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
506};
507
d8d79f8f
MS		 508static const struct regmap_irq_chip axp152_regmap_irq_chip = {
509 .name = "axp152_irq_chip",
510 .status_base = AXP152_IRQ1_STATE,
511 .ack_base = AXP152_IRQ1_STATE,
512 .mask_base = AXP152_IRQ1_EN,
513 .mask_invert = true,
514 .init_ack_masked = true,
515 .irqs = axp152_regmap_irqs,
516 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
517 .num_regs = 3,
518};
519
cfb61a41
CC		 520static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
521 .name = "axp20x_irq_chip",
522 .status_base = AXP20X_IRQ1_STATE,
523 .ack_base = AXP20X_IRQ1_STATE,
524 .mask_base = AXP20X_IRQ1_EN,
af7e9069
JP		 525 .mask_invert = true,
526 .init_ack_masked = true,
cfb61a41
CC		 527 .irqs = axp20x_regmap_irqs,
528 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
af7e9069
JP		 529 .num_regs = 5,
530
531};
532
f05be589
BB		 533static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
534 .name = "axp22x_irq_chip",
535 .status_base = AXP20X_IRQ1_STATE,
536 .ack_base = AXP20X_IRQ1_STATE,
537 .mask_base = AXP20X_IRQ1_EN,
538 .mask_invert = true,
539 .init_ack_masked = true,
540 .irqs = axp22x_regmap_irqs,
541 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
542 .num_regs = 5,
543};
544
af7e9069
JP		 545static const struct regmap_irq_chip axp288_regmap_irq_chip = {
546 .name = "axp288_irq_chip",
547 .status_base = AXP20X_IRQ1_STATE,
548 .ack_base = AXP20X_IRQ1_STATE,
549 .mask_base = AXP20X_IRQ1_EN,
cfb61a41
CC		 550 .mask_invert = true,
551 .init_ack_masked = true,
af7e9069
JP		 552 .irqs = axp288_regmap_irqs,
553 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
554 .num_regs = 6,
555
cfb61a41
CC		 556};
557
8824ee85
CYT		 558static const struct regmap_irq_chip axp806_regmap_irq_chip = {
559 .name = "axp806",
560 .status_base = AXP20X_IRQ1_STATE,
561 .ack_base = AXP20X_IRQ1_STATE,
562 .mask_base = AXP20X_IRQ1_EN,
563 .mask_invert = true,
564 .init_ack_masked = true,
565 .irqs = axp806_regmap_irqs,
566 .num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
567 .num_regs = 2,
568};
569
20147f0d
CYT		 570static const struct regmap_irq_chip axp809_regmap_irq_chip = {
571 .name = "axp809",
572 .status_base = AXP20X_IRQ1_STATE,
573 .ack_base = AXP20X_IRQ1_STATE,
574 .mask_base = AXP20X_IRQ1_EN,
575 .mask_invert = true,
576 .init_ack_masked = true,
577 .irqs = axp809_regmap_irqs,
578 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
579 .num_regs = 5,
580};
581
cfb61a41
CC		 582static struct mfd_cell axp20x_cells[] = {
583 {
b419c16b
MR		 584 .name = "axp20x-gpio",
585 .of_compatible = "x-powers,axp209-gpio",
586 }, {
8de4efda
HG		 587 .name = "axp20x-pek",
588 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
589 .resources = axp20x_pek_resources,
cfb61a41 590 }, {
8de4efda 591 .name = "axp20x-regulator",
4d5e5c34
QS		 592 }, {
593 .name = "axp20x-adc",
cd7cf27b
MH		 594 }, {
595 .name = "axp20x-ac-power-supply",
596 .of_compatible = "x-powers,axp202-ac-power-supply",
597 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
598 .resources = axp20x_ac_power_supply_resources,
8de4efda
HG		 599 }, {
600 .name = "axp20x-usb-power-supply",
601 .of_compatible = "x-powers,axp202-usb-power-supply",
602 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
603 .resources = axp20x_usb_power_supply_resources,
cfb61a41
CC		 604 },
605};
606
4c650561
QS		 607static struct mfd_cell axp221_cells[] = {
608 {
609 .name = "axp20x-pek",
610 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
611 .resources = axp22x_pek_resources,
612 }, {
613 .name = "axp20x-regulator",
4d5e5c34
QS		 614 }, {
615 .name = "axp22x-adc"
95c4f531
QS		 616 }, {
617 .name = "axp20x-ac-power-supply",
618 .of_compatible = "x-powers,axp221-ac-power-supply",
619 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
620 .resources = axp20x_ac_power_supply_resources,
4c650561
QS		 621 }, {
622 .name = "axp20x-usb-power-supply",
623 .of_compatible = "x-powers,axp221-usb-power-supply",
624 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
625 .resources = axp22x_usb_power_supply_resources,
626 },
627};
628
629static struct mfd_cell axp223_cells[] = {
f05be589
BB		 630 {
631 .name = "axp20x-pek",
632 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
633 .resources = axp22x_pek_resources,
4d5e5c34
QS		 634 }, {
635 .name = "axp22x-adc",
6d4fa89d
CYT		 636 }, {
637 .name = "axp20x-regulator",
95c4f531
QS		 638 }, {
639 .name = "axp20x-ac-power-supply",
640 .of_compatible = "x-powers,axp221-ac-power-supply",
641 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
642 .resources = axp20x_ac_power_supply_resources,
ecd98cce
HG		 643 }, {
644 .name = "axp20x-usb-power-supply",
4c650561 645 .of_compatible = "x-powers,axp223-usb-power-supply",
ecd98cce
HG		 646 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
647 .resources = axp22x_usb_power_supply_resources,
f05be589
BB		 648 },
649};
650
d8d79f8f
MS		 651static struct mfd_cell axp152_cells[] = {
652 {
653 .name = "axp20x-pek",
654 .num_resources = ARRAY_SIZE(axp152_pek_resources),
655 .resources = axp152_pek_resources,
656 },
657};
658
af7e9069
JP		 659static struct resource axp288_adc_resources[] = {
660 {
661 .name = "GPADC",
662 .start = AXP288_IRQ_GPADC,
663 .end = AXP288_IRQ_GPADC,
664 .flags = IORESOURCE_IRQ,
665 },
666};
667
bdb01f78
RP		 668static struct resource axp288_extcon_resources[] = {
669 {
670 .start = AXP288_IRQ_VBUS_FALL,
671 .end = AXP288_IRQ_VBUS_FALL,
672 .flags = IORESOURCE_IRQ,
673 },
674 {
675 .start = AXP288_IRQ_VBUS_RISE,
676 .end = AXP288_IRQ_VBUS_RISE,
677 .flags = IORESOURCE_IRQ,
678 },
679 {
680 .start = AXP288_IRQ_MV_CHNG,
681 .end = AXP288_IRQ_MV_CHNG,
682 .flags = IORESOURCE_IRQ,
683 },
684 {
685 .start = AXP288_IRQ_BC_USB_CHNG,
686 .end = AXP288_IRQ_BC_USB_CHNG,
687 .flags = IORESOURCE_IRQ,
688 },
689};
690
af7e9069
JP		 691static struct resource axp288_charger_resources[] = {
692 {
693 .start = AXP288_IRQ_OV,
694 .end = AXP288_IRQ_OV,
695 .flags = IORESOURCE_IRQ,
696 },
697 {
698 .start = AXP288_IRQ_DONE,
699 .end = AXP288_IRQ_DONE,
700 .flags = IORESOURCE_IRQ,
701 },
702 {
703 .start = AXP288_IRQ_CHARGING,
704 .end = AXP288_IRQ_CHARGING,
705 .flags = IORESOURCE_IRQ,
706 },
707 {
708 .start = AXP288_IRQ_SAFE_QUIT,
709 .end = AXP288_IRQ_SAFE_QUIT,
710 .flags = IORESOURCE_IRQ,
711 },
712 {
713 .start = AXP288_IRQ_SAFE_ENTER,
714 .end = AXP288_IRQ_SAFE_ENTER,
715 .flags = IORESOURCE_IRQ,
716 },
717 {
718 .start = AXP288_IRQ_QCBTU,
719 .end = AXP288_IRQ_QCBTU,
720 .flags = IORESOURCE_IRQ,
721 },
722 {
723 .start = AXP288_IRQ_CBTU,
724 .end = AXP288_IRQ_CBTU,
725 .flags = IORESOURCE_IRQ,
726 },
727 {
728 .start = AXP288_IRQ_QCBTO,
729 .end = AXP288_IRQ_QCBTO,
730 .flags = IORESOURCE_IRQ,
731 },
732 {
733 .start = AXP288_IRQ_CBTO,
734 .end = AXP288_IRQ_CBTO,
735 .flags = IORESOURCE_IRQ,
736 },
737};
738
739static struct mfd_cell axp288_cells[] = {
740 {
741 .name = "axp288_adc",
742 .num_resources = ARRAY_SIZE(axp288_adc_resources),
743 .resources = axp288_adc_resources,
744 },
bdb01f78
RP		 745 {
746 .name = "axp288_extcon",
747 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
748 .resources = axp288_extcon_resources,
749 },
af7e9069
JP		 750 {
751 .name = "axp288_charger",
752 .num_resources = ARRAY_SIZE(axp288_charger_resources),
753 .resources = axp288_charger_resources,
754 },
755 {
d6387874
TB		 756 .name = "axp288_fuel_gauge",
757 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
758 .resources = axp288_fuel_gauge_resources,
af7e9069 759 },
e56e5ad6
BF		 760 {
761 .name = "axp20x-pek",
762 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
763 .resources = axp288_power_button_resources,
764 },
d8139f63
AL		 765 {
766 .name = "axp288_pmic_acpi",
767 },
af7e9069
JP		 768};
769
8824ee85
CYT		 770static struct mfd_cell axp806_cells[] = {
771 {
772 .id = 2,
773 .name = "axp20x-regulator",
774 },
775};
776
20147f0d
CYT		 777static struct mfd_cell axp809_cells[] = {
778 {
779 .name = "axp20x-pek",
780 .num_resources = ARRAY_SIZE(axp809_pek_resources),
781 .resources = axp809_pek_resources,
782 }, {
8824ee85 783 .id = 1,
20147f0d
CYT		 784 .name = "axp20x-regulator",
785 },
786};
787
cfb61a41
CC		 788static struct axp20x_dev *axp20x_pm_power_off;
789static void axp20x_power_off(void)
790{
af7e9069
JP		 791 if (axp20x_pm_power_off->variant == AXP288_ID)
792 return;
793
cfb61a41
CC		 794 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
795 AXP20X_OFF);
179dc63d
HG		 796
797 /* Give capacitors etc. time to drain to avoid kernel panic msg. */
798 msleep(500);
cfb61a41
CC		 799}
800
4fd41151 801int axp20x_match_device(struct axp20x_dev *axp20x)
af7e9069 802{
e47a3cf7 803 struct device *dev = axp20x->dev;
af7e9069
JP		 804 const struct acpi_device_id *acpi_id;
805 const struct of_device_id *of_id;
806
807 if (dev->of_node) {
af7acc3d 808 of_id = of_match_device(dev->driver->of_match_table, dev);
af7e9069
JP		 809 if (!of_id) {
810 dev_err(dev, "Unable to match OF ID\n");
811 return -ENODEV;
812 }
2260a453 813 axp20x->variant = (long)of_id->data;
af7e9069
JP		 814 } else {
815 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
816 if (!acpi_id || !acpi_id->driver_data) {
817 dev_err(dev, "Unable to match ACPI ID and data\n");
818 return -ENODEV;
819 }
2260a453 820 axp20x->variant = (long)acpi_id->driver_data;
af7e9069
JP		 821 }
822
823 switch (axp20x->variant) {
d8d79f8f
MS		 824 case AXP152_ID:
825 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
826 axp20x->cells = axp152_cells;
827 axp20x->regmap_cfg = &axp152_regmap_config;
828 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
829 break;
af7e9069
JP		 830 case AXP202_ID:
831 case AXP209_ID:
832 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
833 axp20x->cells = axp20x_cells;
834 axp20x->regmap_cfg = &axp20x_regmap_config;
835 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
836 break;
f05be589 837 case AXP221_ID:
4c650561
QS		 838 axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
839 axp20x->cells = axp221_cells;
840 axp20x->regmap_cfg = &axp22x_regmap_config;
841 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
842 break;
02071f0f 843 case AXP223_ID:
4c650561
QS		 844 axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
845 axp20x->cells = axp223_cells;
f05be589
BB		 846 axp20x->regmap_cfg = &axp22x_regmap_config;
847 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
848 break;
af7e9069
JP		 849 case AXP288_ID:
850 axp20x->cells = axp288_cells;
851 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
852 axp20x->regmap_cfg = &axp288_regmap_config;
853 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
0a5454c9 854 axp20x->irq_flags = IRQF_TRIGGER_LOW;
af7e9069 855 break;
8824ee85
CYT		 856 case AXP806_ID:
857 axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
858 axp20x->cells = axp806_cells;
859 axp20x->regmap_cfg = &axp806_regmap_config;
860 axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
861 break;
20147f0d
CYT		 862 case AXP809_ID:
863 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
864 axp20x->cells = axp809_cells;
865 axp20x->regmap_cfg = &axp22x_regmap_config;
866 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
867 break;
af7e9069
JP		 868 default:
869 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
870 return -EINVAL;
871 }
872 dev_info(dev, "AXP20x variant %s found\n",
2260a453 873 axp20x_model_names[axp20x->variant]);
af7e9069
JP		 874
875 return 0;
876}
4fd41151 877EXPORT_SYMBOL(axp20x_match_device);
af7e9069 878
4fd41151 879int axp20x_device_probe(struct axp20x_dev *axp20x)
cfb61a41 880{
cfb61a41
CC		 881 int ret;
882
696f0b3f
CYT		 883 /*
884 * The AXP806 supports either master/standalone or slave mode.
885 * Slave mode allows sharing the serial bus, even with multiple
886 * AXP806 which all have the same hardware address.
887 *
888 * This is done with extra "serial interface address extension",
889 * or AXP806_BUS_ADDR_EXT, and "register address extension", or
890 * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
891 * 1 bit customizable at the factory, and 1 bit depending on the
892 * state of an external pin. The latter is writable. The device
893 * will only respond to operations to its other registers when
894 * the these device addressing bits (in the upper 4 bits of the
895 * registers) match.
896 *
c0369698
RIL		 897 * By default we support an AXP806 chained to an AXP809 in slave
898 * mode. Boards which use an AXP806 in master mode can set the
899 * property "x-powers,master-mode" to override the default.
696f0b3f 900 */
c0369698
RIL		 901 if (axp20x->variant == AXP806_ID) {
902 if (of_property_read_bool(axp20x->dev->of_node,
903 "x-powers,master-mode"))
904 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
905 AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
906 else
907 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
908 AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
909 }
696f0b3f 910
4fd41151 911 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
0a5454c9
HG		 912 IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
913 -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc);
cfb61a41 914 if (ret) {
4fd41151 915 dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
cfb61a41
CC		 916 return ret;
917 }
918
af7e9069 919 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
2260a453 920 axp20x->nr_cells, NULL, 0, NULL);
cfb61a41
CC		 921
922 if (ret) {
4fd41151
CYT		 923 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
924 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41
CC		 925 return ret;
926 }
927
928 if (!pm_power_off) {
929 axp20x_pm_power_off = axp20x;
930 pm_power_off = axp20x_power_off;
931 }
932
4fd41151 933 dev_info(axp20x->dev, "AXP20X driver loaded\n");
cfb61a41
CC		 934
935 return 0;
936}
4fd41151 937EXPORT_SYMBOL(axp20x_device_probe);
cfb61a41 938
4fd41151 939int axp20x_device_remove(struct axp20x_dev *axp20x)
cfb61a41 940{
cfb61a41
CC		 941 if (axp20x == axp20x_pm_power_off) {
942 axp20x_pm_power_off = NULL;
943 pm_power_off = NULL;
944 }
945
946 mfd_remove_devices(axp20x->dev);
4fd41151 947 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
cfb61a41
CC		 948
949 return 0;
950}
4fd41151 951EXPORT_SYMBOL(axp20x_device_remove);
cfb61a41
CC		 952
953MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
954MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
955MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)