[linux-2.6-block.git] / drivers / mfd / atmel-hlcdc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Free Electrons
 * Copyright (C) 2014 Atmel
 *
 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 */

#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/mfd/atmel-hlcdc.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#define ATMEL_HLCDC_REG_MAX		(0x4000 - 0x4)

struct atmel_hlcdc_regmap {
	void __iomem *regs;
	struct device *dev;
};

static const struct mfd_cell atmel_hlcdc_cells[] = {
	{
		.name = "atmel-hlcdc-pwm",
		.of_compatible = "atmel,hlcdc-pwm",
	},
	{
		.name = "atmel-hlcdc-dc",
		.of_compatible = "atmel,hlcdc-display-controller",
	},
};

static int regmap_atmel_hlcdc_reg_write(void *context, unsigned int reg,
					unsigned int val)
{
	struct atmel_hlcdc_regmap *hregmap = context;

	if (reg <= ATMEL_HLCDC_DIS) {
		u32 status;
		int ret;

		ret = readl_poll_timeout_atomic(hregmap->regs + ATMEL_HLCDC_SR,
						status,
						!(status & ATMEL_HLCDC_SIP),
						1, 100);
		if (ret) {
			dev_err(hregmap->dev,
				"Timeout! Clock domain synchronization is in progress!\n");
			return ret;
		}
	}

	writel(val, hregmap->regs + reg);

	return 0;
}

static int regmap_atmel_hlcdc_reg_read(void *context, unsigned int reg,
				       unsigned int *val)
{
	struct atmel_hlcdc_regmap *hregmap = context;

	*val = readl(hregmap->regs + reg);

	return 0;
}

static const struct regmap_config atmel_hlcdc_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.max_register = ATMEL_HLCDC_REG_MAX,
	.reg_write = regmap_atmel_hlcdc_reg_write,
	.reg_read = regmap_atmel_hlcdc_reg_read,
	.fast_io = true,
};

static int atmel_hlcdc_probe(struct platform_device *pdev)
{
	struct atmel_hlcdc_regmap *hregmap;
	struct device *dev = &pdev->dev;
	struct atmel_hlcdc *hlcdc;

	hregmap = devm_kzalloc(dev, sizeof(*hregmap), GFP_KERNEL);
	if (!hregmap)
		return -ENOMEM;

	hlcdc = devm_kzalloc(dev, sizeof(*hlcdc), GFP_KERNEL);
	if (!hlcdc)
		return -ENOMEM;

	hregmap->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(hregmap->regs))
		return PTR_ERR(hregmap->regs);

	hregmap->dev = &pdev->dev;

	hlcdc->irq = platform_get_irq(pdev, 0);
	if (hlcdc->irq < 0)
		return hlcdc->irq;

	hlcdc->periph_clk = devm_clk_get(dev, "periph_clk");
	if (IS_ERR(hlcdc->periph_clk)) {
		dev_err(dev, "failed to get peripheral clock\n");
		return PTR_ERR(hlcdc->periph_clk);
	}

	hlcdc->sys_clk = devm_clk_get(dev, "sys_clk");
	if (IS_ERR(hlcdc->sys_clk)) {
		dev_err(dev, "failed to get system clock\n");
		return PTR_ERR(hlcdc->sys_clk);
	}

	hlcdc->slow_clk = devm_clk_get(dev, "slow_clk");
	if (IS_ERR(hlcdc->slow_clk)) {
		dev_err(dev, "failed to get slow clock\n");
		return PTR_ERR(hlcdc->slow_clk);
	}

	hlcdc->regmap = devm_regmap_init(dev, NULL, hregmap,
					 &atmel_hlcdc_regmap_config);
	if (IS_ERR(hlcdc->regmap))
		return PTR_ERR(hlcdc->regmap);

	dev_set_drvdata(dev, hlcdc);

	return devm_mfd_add_devices(dev, -1, atmel_hlcdc_cells,
				    ARRAY_SIZE(atmel_hlcdc_cells),
				    NULL, 0, NULL);
}

static const struct of_device_id atmel_hlcdc_match[] = {
	{ .compatible = "atmel,at91sam9n12-hlcdc" },
	{ .compatible = "atmel,at91sam9x5-hlcdc" },
	{ .compatible = "atmel,sama5d2-hlcdc" },
	{ .compatible = "atmel,sama5d3-hlcdc" },
	{ .compatible = "atmel,sama5d4-hlcdc" },
	{ .compatible = "microchip,sam9x60-hlcdc" },
	{ .compatible = "microchip,sam9x75-xlcdc" },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, atmel_hlcdc_match);

static struct platform_driver atmel_hlcdc_driver = {
	.probe = atmel_hlcdc_probe,
	.driver = {
		.name = "atmel-hlcdc",
		.of_match_table = atmel_hlcdc_match,
	},
};
module_platform_driver(atmel_hlcdc_driver);

MODULE_ALIAS("platform:atmel-hlcdc");
MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
MODULE_DESCRIPTION("Atmel HLCDC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
caab277b	1	// SPDX-License-Identifier: GPL-2.0-only
2c86e9fb BB	2	/*
	3	* Copyright (C) 2014 Free Electrons
	4	* Copyright (C) 2014 Atmel
	5	*
	6	* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
2c86e9fb BB	7	*/
	8
	9	#include <linux/clk.h>
ea31c0cf	10	#include <linux/iopoll.h>
2c86e9fb BB	11	#include <linux/mfd/atmel-hlcdc.h>
	12	#include <linux/mfd/core.h>
	13	#include <linux/module.h>
ac316725	14	#include <linux/mod_devicetable.h>
2c86e9fb BB	15	#include <linux/platform_device.h>
	16	#include <linux/regmap.h>
	17
	18	#define ATMEL_HLCDC_REG_MAX (0x4000 - 0x4)
	19
ea31c0cf BB	20	struct atmel_hlcdc_regmap {
ea31c0cf BB	21	void __iomem *regs;
4b1ca3a4	22	struct device *dev;
ea31c0cf BB	23	};
ea31c0cf BB	24
2c86e9fb BB	25	static const struct mfd_cell atmel_hlcdc_cells[] = {
	26	{
	27	.name = "atmel-hlcdc-pwm",
	28	.of_compatible = "atmel,hlcdc-pwm",
	29	},
	30	{
	31	.name = "atmel-hlcdc-dc",
	32	.of_compatible = "atmel,hlcdc-display-controller",
	33	},
	34	};
	35
ea31c0cf BB	36	static int regmap_atmel_hlcdc_reg_write(void *context, unsigned int reg,
	37	unsigned int val)
	38	{
	39	struct atmel_hlcdc_regmap *hregmap = context;
	40
	41	if (reg <= ATMEL_HLCDC_DIS) {
	42	u32 status;
10f91676	43	int ret;
ea31c0cf	44
10f91676 CB	45	ret = readl_poll_timeout_atomic(hregmap->regs + ATMEL_HLCDC_SR,
	46	status,
	47	!(status & ATMEL_HLCDC_SIP),
	48	1, 100);
	49	if (ret) {
	50	dev_err(hregmap->dev,
	51	"Timeout! Clock domain synchronization is in progress!\n");
	52	return ret;
	53	}
ea31c0cf BB	54	}
	55
	56	writel(val, hregmap->regs + reg);
	57
	58	return 0;
	59	}
	60
	61	static int regmap_atmel_hlcdc_reg_read(void *context, unsigned int reg,
	62	unsigned int *val)
	63	{
	64	struct atmel_hlcdc_regmap *hregmap = context;
	65
	66	*val = readl(hregmap->regs + reg);
	67
	68	return 0;
	69	}
	70
2c86e9fb BB	71	static const struct regmap_config atmel_hlcdc_regmap_config = {
	72	.reg_bits = 32,
	73	.val_bits = 32,
	74	.reg_stride = 4,
	75	.max_register = ATMEL_HLCDC_REG_MAX,
ea31c0cf BB	76	.reg_write = regmap_atmel_hlcdc_reg_write,
	77	.reg_read = regmap_atmel_hlcdc_reg_read,
	78	.fast_io = true,
2c86e9fb BB	79	};
	80
	81	static int atmel_hlcdc_probe(struct platform_device *pdev)
	82	{
ea31c0cf	83	struct atmel_hlcdc_regmap *hregmap;
2c86e9fb BB	84	struct device *dev = &pdev->dev;
2c86e9fb BB	85	struct atmel_hlcdc *hlcdc;
ea31c0cf BB	86
	87	hregmap = devm_kzalloc(dev, sizeof(*hregmap), GFP_KERNEL);
	88	if (!hregmap)
	89	return -ENOMEM;
2c86e9fb BB	90
	91	hlcdc = devm_kzalloc(dev, sizeof(*hlcdc), GFP_KERNEL);
	92	if (!hlcdc)
	93	return -ENOMEM;
	94
8e950a60	95	hregmap->regs = devm_platform_ioremap_resource(pdev, 0);
ea31c0cf BB	96	if (IS_ERR(hregmap->regs))
ea31c0cf BB	97	return PTR_ERR(hregmap->regs);
2c86e9fb	98
4b1ca3a4 CB	99	hregmap->dev = &pdev->dev;
4b1ca3a4 CB	100
2c86e9fb BB	101	hlcdc->irq = platform_get_irq(pdev, 0);
	102	if (hlcdc->irq < 0)
	103	return hlcdc->irq;
	104
	105	hlcdc->periph_clk = devm_clk_get(dev, "periph_clk");
	106	if (IS_ERR(hlcdc->periph_clk)) {
	107	dev_err(dev, "failed to get peripheral clock\n");
	108	return PTR_ERR(hlcdc->periph_clk);
	109	}
	110
	111	hlcdc->sys_clk = devm_clk_get(dev, "sys_clk");
	112	if (IS_ERR(hlcdc->sys_clk)) {
	113	dev_err(dev, "failed to get system clock\n");
	114	return PTR_ERR(hlcdc->sys_clk);
	115	}
	116
	117	hlcdc->slow_clk = devm_clk_get(dev, "slow_clk");
	118	if (IS_ERR(hlcdc->slow_clk)) {
	119	dev_err(dev, "failed to get slow clock\n");
	120	return PTR_ERR(hlcdc->slow_clk);
	121	}
	122
ea31c0cf BB	123	hlcdc->regmap = devm_regmap_init(dev, NULL, hregmap,
ea31c0cf BB	124	&atmel_hlcdc_regmap_config);
2c86e9fb BB	125	if (IS_ERR(hlcdc->regmap))
	126	return PTR_ERR(hlcdc->regmap);
	127
	128	dev_set_drvdata(dev, hlcdc);
	129
f32fb9a5 LD	130	return devm_mfd_add_devices(dev, -1, atmel_hlcdc_cells,
	131	ARRAY_SIZE(atmel_hlcdc_cells),
	132	NULL, 0, NULL);
2c86e9fb BB	133	}
	134
	135	static const struct of_device_id atmel_hlcdc_match[] = {
d9c93f5d BB	136	{ .compatible = "atmel,at91sam9n12-hlcdc" },
	137	{ .compatible = "atmel,at91sam9x5-hlcdc" },
	138	{ .compatible = "atmel,sama5d2-hlcdc" },
2c86e9fb	139	{ .compatible = "atmel,sama5d3-hlcdc" },
d9c93f5d	140	{ .compatible = "atmel,sama5d4-hlcdc" },
1e8c1585	141	{ .compatible = "microchip,sam9x60-hlcdc" },
ad3a3c6e	142	{ .compatible = "microchip,sam9x75-xlcdc" },
2c86e9fb BB	143	{ /* sentinel */ },
2c86e9fb BB	144	};
a0aef1f5	145	MODULE_DEVICE_TABLE(of, atmel_hlcdc_match);
2c86e9fb BB	146
	147	static struct platform_driver atmel_hlcdc_driver = {
	148	.probe = atmel_hlcdc_probe,
2c86e9fb BB	149	.driver = {
	150	.name = "atmel-hlcdc",
	151	.of_match_table = atmel_hlcdc_match,
	152	},
	153	};
	154	module_platform_driver(atmel_hlcdc_driver);
	155
	156	MODULE_ALIAS("platform:atmel-hlcdc");
	157	MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
	158	MODULE_DESCRIPTION("Atmel HLCDC driver");
	159	MODULE_LICENSE("GPL v2");