[linux-2.6-block.git] / drivers / mfd / asic3.c

/*
 * driver/mfd/asic3.c
 *
 * Compaq ASIC3 support.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Copyright 2001 Compaq Computer Corporation.
 * Copyright 2004-2005 Phil Blundell
 * Copyright 2007-2008 OpenedHand Ltd.
 *
 * Authors: Phil Blundell <pb@handhelds.org>,
 *	    Samuel Ortiz <sameo@openedhand.com>
 *
 */

#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>

#include <linux/mfd/asic3.h>

struct asic3 {
	void __iomem *mapping;
	unsigned int bus_shift;
	unsigned int irq_nr;
	unsigned int irq_base;
	spinlock_t lock;
	u16 irq_bothedge[4];
	struct gpio_chip gpio;
	struct device *dev;
};

static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);

static inline void asic3_write_register(struct asic3 *asic,
				 unsigned int reg, u32 value)
{
	iowrite16(value, asic->mapping +
		  (reg >> asic->bus_shift));
}

static inline u32 asic3_read_register(struct asic3 *asic,
			       unsigned int reg)
{
	return ioread16(asic->mapping +
			(reg >> asic->bus_shift));
}

/* IRQs */
#define MAX_ASIC_ISR_LOOPS    20
#define ASIC3_GPIO_Base_INCR \
	(ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)

static void asic3_irq_flip_edge(struct asic3 *asic,
				u32 base, int bit)
{
	u16 edge;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	edge = asic3_read_register(asic,
				   base + ASIC3_GPIO_EdgeTrigger);
	edge ^= bit;
	asic3_write_register(asic,
			     base + ASIC3_GPIO_EdgeTrigger, edge);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	int iter, i;
	unsigned long flags;
	struct asic3 *asic;

	desc->chip->ack(irq);

	asic = desc->handler_data;

	for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
		u32 status;
		int bank;

		spin_lock_irqsave(&asic->lock, flags);
		status = asic3_read_register(asic,
					     ASIC3_OFFSET(INTR, PIntStat));
		spin_unlock_irqrestore(&asic->lock, flags);

		/* Check all ten register bits */
		if ((status & 0x3ff) == 0)
			break;

		/* Handle GPIO IRQs */
		for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
			if (status & (1 << bank)) {
				unsigned long base, istat;

				base = ASIC3_GPIO_A_Base
				       + bank * ASIC3_GPIO_Base_INCR;

				spin_lock_irqsave(&asic->lock, flags);
				istat = asic3_read_register(asic,
							    base +
							    ASIC3_GPIO_IntStatus);
				/* Clearing IntStatus */
				asic3_write_register(asic,
						     base +
						     ASIC3_GPIO_IntStatus, 0);
				spin_unlock_irqrestore(&asic->lock, flags);

				for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
					int bit = (1 << i);
					unsigned int irqnr;

					if (!(istat & bit))
						continue;

					irqnr = asic->irq_base +
						(ASIC3_GPIOS_PER_BANK * bank)
						+ i;
					desc = irq_desc + irqnr;
					desc->handle_irq(irqnr, desc);
					if (asic->irq_bothedge[bank] & bit)
						asic3_irq_flip_edge(asic, base,
								    bit);
				}
			}
		}

		/* Handle remaining IRQs in the status register */
		for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
			/* They start at bit 4 and go up */
			if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
				desc = irq_desc +  + i;
				desc->handle_irq(asic->irq_base + i,
						 desc);
			}
		}
	}

	if (iter >= MAX_ASIC_ISR_LOOPS)
		printk(KERN_ERR "%s: interrupt processing overrun\n",
		       __func__);
}

static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
{
	int n;

	n = (irq - asic->irq_base) >> 4;

	return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base));
}

static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
{
	return (irq - asic->irq_base) & 0xf;
}

static void asic3_mask_gpio_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 val, bank, index;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
	val |= 1 << index;
	asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_mask_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	int regval;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	regval = asic3_read_register(asic,
				     ASIC3_INTR_Base +
				     ASIC3_INTR_IntMask);

	regval &= ~(ASIC3_INTMASK_MASK0 <<
		    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));

	asic3_write_register(asic,
			     ASIC3_INTR_Base +
			     ASIC3_INTR_IntMask,
			     regval);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_unmask_gpio_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 val, bank, index;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
	val &= ~(1 << index);
	asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_unmask_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	int regval;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	regval = asic3_read_register(asic,
				     ASIC3_INTR_Base +
				     ASIC3_INTR_IntMask);

	regval |= (ASIC3_INTMASK_MASK0 <<
		   (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));

	asic3_write_register(asic,
			     ASIC3_INTR_Base +
			     ASIC3_INTR_IntMask,
			     regval);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 bank, index;
	u16 trigger, level, edge, bit;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);
	bit = 1<<index;

	spin_lock_irqsave(&asic->lock, flags);
	level = asic3_read_register(asic,
				    bank + ASIC3_GPIO_LevelTrigger);
	edge = asic3_read_register(asic,
				   bank + ASIC3_GPIO_EdgeTrigger);
	trigger = asic3_read_register(asic,
				      bank + ASIC3_GPIO_TriggerType);
	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;

	if (type == IRQT_RISING) {
		trigger |= bit;
		edge |= bit;
	} else if (type == IRQT_FALLING) {
		trigger |= bit;
		edge &= ~bit;
	} else if (type == IRQT_BOTHEDGE) {
		trigger |= bit;
		if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
			edge &= ~bit;
		else
			edge |= bit;
		asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
	} else if (type == IRQT_LOW) {
		trigger &= ~bit;
		level &= ~bit;
	} else if (type == IRQT_HIGH) {
		trigger &= ~bit;
		level |= bit;
	} else {
		/*
		 * if type == IRQT_NOEDGE, we should mask interrupts, but
		 * be careful to not unmask them if mask was also called.
		 * Probably need internal state for mask.
		 */
		printk(KERN_NOTICE "asic3: irq type not changed.\n");
	}
	asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger,
			     level);
	asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger,
			     edge);
	asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType,
			     trigger);
	spin_unlock_irqrestore(&asic->lock, flags);
	return 0;
}

static struct irq_chip asic3_gpio_irq_chip = {
	.name		= "ASIC3-GPIO",
	.ack		= asic3_mask_gpio_irq,
	.mask		= asic3_mask_gpio_irq,
	.unmask		= asic3_unmask_gpio_irq,
	.set_type	= asic3_gpio_irq_type,
};

static struct irq_chip asic3_irq_chip = {
	.name		= "ASIC3",
	.ack		= asic3_mask_irq,
	.mask		= asic3_mask_irq,
	.unmask		= asic3_unmask_irq,
};

static int asic3_irq_probe(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	unsigned long clksel = 0;
	unsigned int irq, irq_base;

	asic->irq_nr = platform_get_irq(pdev, 0);
	if (asic->irq_nr < 0)
		return asic->irq_nr;

	/* turn on clock to IRQ controller */
	clksel |= CLOCK_SEL_CX;
	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
			     clksel);

	irq_base = asic->irq_base;

	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
		if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
			set_irq_chip(irq, &asic3_gpio_irq_chip);
		else
			set_irq_chip(irq, &asic3_irq_chip);

		set_irq_chip_data(irq, asic);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask),
			     ASIC3_INTMASK_GINTMASK);

	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
	set_irq_type(asic->irq_nr, IRQT_RISING);
	set_irq_data(asic->irq_nr, asic);

	return 0;
}

static void asic3_irq_remove(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	unsigned int irq, irq_base;

	irq_base = asic->irq_base;

	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
		set_irq_flags(irq, 0);
		set_irq_handler(irq, NULL);
		set_irq_chip(irq, NULL);
		set_irq_chip_data(irq, NULL);
	}
	set_irq_chained_handler(asic->irq_nr, NULL);
}

/* GPIOs */
static int asic3_gpio_direction(struct gpio_chip *chip,
				unsigned offset, int out)
{
	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
	unsigned int gpio_base;
	unsigned long flags;
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_Base) {
		printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
		       gpio_base, offset);
		return -EINVAL;
	}

	spin_lock_irqsave(&asic->lock, flags);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_Direction);

	/* Input is 0, Output is 1 */
	if (out)
		out_reg |= mask;
	else
		out_reg &= ~mask;

	asic3_write_register(asic, gpio_base + ASIC3_GPIO_Direction, out_reg);

	spin_unlock_irqrestore(&asic->lock, flags);

	return 0;

}

static int asic3_gpio_direction_input(struct gpio_chip *chip,
				      unsigned offset)
{
	return asic3_gpio_direction(chip, offset, 0);
}

static int asic3_gpio_direction_output(struct gpio_chip *chip,
				       unsigned offset, int value)
{
	return asic3_gpio_direction(chip, offset, 1);
}

static int asic3_gpio_get(struct gpio_chip *chip,
			  unsigned offset)
{
	unsigned int gpio_base;
	u32 mask = ASIC3_GPIO_TO_MASK(offset);
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_Base) {
		printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
		       gpio_base, offset);
		return -EINVAL;
	}

	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_Status) & mask;
}

static void asic3_gpio_set(struct gpio_chip *chip,
			   unsigned offset, int value)
{
	u32 mask, out_reg;
	unsigned int gpio_base;
	unsigned long flags;
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_Base) {
		printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
		       gpio_base, offset);
		return;
	}

	mask = ASIC3_GPIO_TO_MASK(offset);

	spin_lock_irqsave(&asic->lock, flags);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_Out);

	if (value)
		out_reg |= mask;
	else
		out_reg &= ~mask;

	asic3_write_register(asic, gpio_base + ASIC3_GPIO_Out, out_reg);

	spin_unlock_irqrestore(&asic->lock, flags);

	return;
}

static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base,
				 unsigned int function)
{
	return asic3_read_register(asic, base + function);
}

static void asic3_set_gpio(struct asic3 *asic, unsigned int base,
			   unsigned int function, u32 bits, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	val |= (asic3_read_register(asic, base + function) & ~bits);

	asic3_write_register(asic, base + function, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

#define asic3_set_gpio_a(asic, fn, bits, val) \
	asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val)
#define asic3_set_gpio_b(asic, fn, bits, val) \
	asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val)
#define asic3_set_gpio_c(asic, fn, bits, val) \
	asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val)
#define asic3_set_gpio_d(asic, fn, bits, val) \
	asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val)

#define asic3_set_gpio_banks(asic, fn, bits, pdata, field) 		  \
	do {								  \
	     asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \
	     asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \
	     asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \
	     asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \
	} while (0)


static int asic3_gpio_probe(struct platform_device *pdev)
{
	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	struct asic3 *asic = platform_get_drvdata(pdev);

	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff);

	asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff);
	asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff);
	asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff);
	asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff);

	if (pdata) {
		asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init);
		asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir);
		asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata,
				     sleep_mask);
		asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out);
		asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata,
				     batt_fault_out);
		asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata,
				     sleep_conf);
		asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata,
				     alt_function);
	}

	return gpiochip_add(&asic->gpio);
}

static int asic3_gpio_remove(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);

	return gpiochip_remove(&asic->gpio);
}


/* Core */
static int asic3_probe(struct platform_device *pdev)
{
	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	struct asic3 *asic;
	struct resource *mem;
	unsigned long clksel;
	int ret = 0;

	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
	if (asic == NULL) {
		printk(KERN_ERR "kzalloc failed\n");
		return -ENOMEM;
	}

	spin_lock_init(&asic->lock);
	platform_set_drvdata(pdev, asic);
	asic->dev = &pdev->dev;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		ret = -ENOMEM;
		printk(KERN_ERR "asic3: no MEM resource\n");
		goto out_free;
	}


	asic->mapping = ioremap(mem->start, PAGE_SIZE);
	if (!asic->mapping) {
		ret = -ENOMEM;
		printk(KERN_ERR "asic3: couldn't ioremap\n");
		goto out_free;
	}

	asic->irq_base = pdata->irq_base;

	if (pdata && pdata->bus_shift)
		asic->bus_shift = 2 - pdata->bus_shift;
	else
		asic->bus_shift = 0;

	clksel = 0;
	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);

	ret = asic3_irq_probe(pdev);
	if (ret < 0) {
		printk(KERN_ERR "asic3: couldn't probe IRQs\n");
		goto out_unmap;
	}

	asic->gpio.base = pdata->gpio_base;
	asic->gpio.ngpio = ASIC3_NUM_GPIOS;
	asic->gpio.get = asic3_gpio_get;
	asic->gpio.set = asic3_gpio_set;
	asic->gpio.direction_input = asic3_gpio_direction_input;
	asic->gpio.direction_output = asic3_gpio_direction_output;

	ret = asic3_gpio_probe(pdev);
	if (ret < 0) {
		printk(KERN_ERR "GPIO probe failed\n");
		goto out_irq;
	}

	printk(KERN_INFO "ASIC3 Core driver\n");

	return 0;

 out_irq:
	asic3_irq_remove(pdev);

 out_unmap:
	iounmap(asic->mapping);

 out_free:
	kfree(asic);

	return ret;
}

static int asic3_remove(struct platform_device *pdev)
{
	int ret;
	struct asic3 *asic = platform_get_drvdata(pdev);

	ret = asic3_gpio_remove(pdev);
	if (ret < 0)
		return ret;
	asic3_irq_remove(pdev);

	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);

	iounmap(asic->mapping);

	kfree(asic);

	return 0;
}

static void asic3_shutdown(struct platform_device *pdev)
{
}

static struct platform_driver asic3_device_driver = {
	.driver		= {
		.name	= "asic3",
	},
	.probe		= asic3_probe,
	.remove		= __devexit_p(asic3_remove),
	.shutdown	= asic3_shutdown,
};

static int __init asic3_init(void)
{
	int retval = 0;
	retval = platform_driver_register(&asic3_device_driver);
	return retval;
}

subsys_initcall(asic3_init);
Commit	Line	Data
fa9ff4b1 SO	1	/*
	2	* driver/mfd/asic3.c
	3	*
	4	* Compaq ASIC3 support.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Copyright 2001 Compaq Computer Corporation.
	11	* Copyright 2004-2005 Phil Blundell
6f2384c4	12	* Copyright 2007-2008 OpenedHand Ltd.
fa9ff4b1 SO	13	*
	14	* Authors: Phil Blundell <pb@handhelds.org>,
	15	* Samuel Ortiz <sameo@openedhand.com>
	16	*
	17	*/
	18
	19	#include <linux/version.h>
	20	#include <linux/kernel.h>
	21	#include <linux/irq.h>
6f2384c4	22	#include <linux/gpio.h>
fa9ff4b1 SO	23	#include <linux/io.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/platform_device.h>
	26
	27	#include <linux/mfd/asic3.h>
	28
6f2384c4 SO	29	struct asic3 {
	30	void __iomem *mapping;
	31	unsigned int bus_shift;
	32	unsigned int irq_nr;
	33	unsigned int irq_base;
	34	spinlock_t lock;
	35	u16 irq_bothedge[4];
	36	struct gpio_chip gpio;
	37	struct device *dev;
	38	};
	39
	40	static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
	41
fa9ff4b1 SO	42	static inline void asic3_write_register(struct asic3 *asic,
	43	unsigned int reg, u32 value)
	44	{
b32661e0	45	iowrite16(value, asic->mapping +
fa9ff4b1 SO	46	(reg >> asic->bus_shift));
	47	}
	48
	49	static inline u32 asic3_read_register(struct asic3 *asic,
	50	unsigned int reg)
	51	{
b32661e0	52	return ioread16(asic->mapping +
fa9ff4b1 SO	53	(reg >> asic->bus_shift));
	54	}
	55
	56	/* IRQs */
	57	#define MAX_ASIC_ISR_LOOPS 20
	58	#define ASIC3_GPIO_Base_INCR \
	59	(ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)
	60
	61	static void asic3_irq_flip_edge(struct asic3 *asic,
	62	u32 base, int bit)
	63	{
	64	u16 edge;
	65	unsigned long flags;
	66
	67	spin_lock_irqsave(&asic->lock, flags);
	68	edge = asic3_read_register(asic,
	69	base + ASIC3_GPIO_EdgeTrigger);
	70	edge ^= bit;
	71	asic3_write_register(asic,
	72	base + ASIC3_GPIO_EdgeTrigger, edge);
	73	spin_unlock_irqrestore(&asic->lock, flags);
	74	}
	75
	76	static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
	77	{
	78	int iter, i;
	79	unsigned long flags;
	80	struct asic3 *asic;
	81
	82	desc->chip->ack(irq);
	83
	84	asic = desc->handler_data;
	85
	86	for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
	87	u32 status;
	88	int bank;
	89
	90	spin_lock_irqsave(&asic->lock, flags);
	91	status = asic3_read_register(asic,
	92	ASIC3_OFFSET(INTR, PIntStat));
	93	spin_unlock_irqrestore(&asic->lock, flags);
	94
	95	/* Check all ten register bits */
	96	if ((status & 0x3ff) == 0)
	97	break;
	98
	99	/* Handle GPIO IRQs */
	100	for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
	101	if (status & (1 << bank)) {
	102	unsigned long base, istat;
	103
	104	base = ASIC3_GPIO_A_Base
	105	+ bank * ASIC3_GPIO_Base_INCR;
	106
	107	spin_lock_irqsave(&asic->lock, flags);
	108	istat = asic3_read_register(asic,
	109	base +
	110	ASIC3_GPIO_IntStatus);
	111	/* Clearing IntStatus */
	112	asic3_write_register(asic,
	113	base +
	114	ASIC3_GPIO_IntStatus, 0);
	115	spin_unlock_irqrestore(&asic->lock, flags);
	116
117	for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
118	int bit = (1 << i);
119	unsigned int irqnr;
120
121	if (!(istat & bit))
122	continue;
123
124	irqnr = asic->irq_base +
125	(ASIC3_GPIOS_PER_BANK * bank)
126	+ i;
127	desc = irq_desc + irqnr;
128	desc->handle_irq(irqnr, desc);
129	if (asic->irq_bothedge[bank] & bit)
130	asic3_irq_flip_edge(asic, base,
131	bit);
132	}
133	}
134	}
135
136	/* Handle remaining IRQs in the status register */
137	for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
138	/* They start at bit 4 and go up */
139	if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
140	desc = irq_desc + + i;
141	desc->handle_irq(asic->irq_base + i,
142	desc);
143	}
144	}
145	}
146
147	if (iter >= MAX_ASIC_ISR_LOOPS)
148	printk(KERN_ERR "%s: interrupt processing overrun\n",
145980a0	149	__func__);
fa9ff4b1 SO	150	}
	151
	152	static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
	153	{
	154	int n;
	155
	156	n = (irq - asic->irq_base) >> 4;
	157
	158	return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base));
	159	}
	160
	161	static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
	162	{
	163	return (irq - asic->irq_base) & 0xf;
	164	}
	165
	166	static void asic3_mask_gpio_irq(unsigned int irq)
	167	{
	168	struct asic3 *asic = get_irq_chip_data(irq);
	169	u32 val, bank, index;
	170	unsigned long flags;
	171
	172	bank = asic3_irq_to_bank(asic, irq);
	173	index = asic3_irq_to_index(asic, irq);
	174
	175	spin_lock_irqsave(&asic->lock, flags);
	176	val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
	177	val \|= 1 << index;
	178	asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
	179	spin_unlock_irqrestore(&asic->lock, flags);
	180	}
	181
	182	static void asic3_mask_irq(unsigned int irq)
	183	{
	184	struct asic3 *asic = get_irq_chip_data(irq);
	185	int regval;
	186	unsigned long flags;
	187
	188	spin_lock_irqsave(&asic->lock, flags);
	189	regval = asic3_read_register(asic,
	190	ASIC3_INTR_Base +
	191	ASIC3_INTR_IntMask);
	192
	193	regval &= ~(ASIC3_INTMASK_MASK0 <<
	194	(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
	195
	196	asic3_write_register(asic,
	197	ASIC3_INTR_Base +
	198	ASIC3_INTR_IntMask,
	199	regval);
	200	spin_unlock_irqrestore(&asic->lock, flags);
	201	}
	202
	203	static void asic3_unmask_gpio_irq(unsigned int irq)
	204	{
	205	struct asic3 *asic = get_irq_chip_data(irq);
	206	u32 val, bank, index;
	207	unsigned long flags;
	208
	209	bank = asic3_irq_to_bank(asic, irq);
	210	index = asic3_irq_to_index(asic, irq);
	211
	212	spin_lock_irqsave(&asic->lock, flags);
	213	val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
214	val &= ~(1 << index);
215	asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
216	spin_unlock_irqrestore(&asic->lock, flags);
217	}
218
219	static void asic3_unmask_irq(unsigned int irq)
220	{
221	struct asic3 *asic = get_irq_chip_data(irq);
222	int regval;
223	unsigned long flags;
224
225	spin_lock_irqsave(&asic->lock, flags);
226	regval = asic3_read_register(asic,
227	ASIC3_INTR_Base +
228	ASIC3_INTR_IntMask);
229
230	regval \|= (ASIC3_INTMASK_MASK0 <<
231	(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
232
233	asic3_write_register(asic,
234	ASIC3_INTR_Base +
235	ASIC3_INTR_IntMask,
236	regval);
237	spin_unlock_irqrestore(&asic->lock, flags);
238	}
239
240	static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
241	{
242	struct asic3 *asic = get_irq_chip_data(irq);
243	u32 bank, index;
244	u16 trigger, level, edge, bit;
245	unsigned long flags;
246
247	bank = asic3_irq_to_bank(asic, irq);
248	index = asic3_irq_to_index(asic, irq);
249	bit = 1<<index;
250
251	spin_lock_irqsave(&asic->lock, flags);
252	level = asic3_read_register(asic,
253	bank + ASIC3_GPIO_LevelTrigger);
254	edge = asic3_read_register(asic,
255	bank + ASIC3_GPIO_EdgeTrigger);
256	trigger = asic3_read_register(asic,
257	bank + ASIC3_GPIO_TriggerType);
258	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
259
260	if (type == IRQT_RISING) {
261	trigger \|= bit;
262	edge \|= bit;
263	} else if (type == IRQT_FALLING) {
264	trigger \|= bit;
265	edge &= ~bit;
266	} else if (type == IRQT_BOTHEDGE) {
267	trigger \|= bit;
6f2384c4	268	if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
fa9ff4b1 SO	269	edge &= ~bit;
	270	else
	271	edge \|= bit;
	272	asic->irq_bothedge[(irq - asic->irq_base) >> 4] \|= bit;
	273	} else if (type == IRQT_LOW) {
	274	trigger &= ~bit;
	275	level &= ~bit;
	276	} else if (type == IRQT_HIGH) {
	277	trigger &= ~bit;
	278	level \|= bit;
	279	} else {
	280	/*
	281	* if type == IRQT_NOEDGE, we should mask interrupts, but
	282	* be careful to not unmask them if mask was also called.
	283	* Probably need internal state for mask.
	284	*/
	285	printk(KERN_NOTICE "asic3: irq type not changed.\n");
	286	}
	287	asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger,
	288	level);
	289	asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger,
	290	edge);
	291	asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType,
	292	trigger);
	293	spin_unlock_irqrestore(&asic->lock, flags);
	294	return 0;
	295	}
	296
	297	static struct irq_chip asic3_gpio_irq_chip = {
	298	.name = "ASIC3-GPIO",
	299	.ack = asic3_mask_gpio_irq,
	300	.mask = asic3_mask_gpio_irq,
	301	.unmask = asic3_unmask_gpio_irq,
	302	.set_type = asic3_gpio_irq_type,
	303	};
	304
	305	static struct irq_chip asic3_irq_chip = {
	306	.name = "ASIC3",
	307	.ack = asic3_mask_irq,
	308	.mask = asic3_mask_irq,
	309	.unmask = asic3_unmask_irq,
	310	};
	311
	312	static int asic3_irq_probe(struct platform_device *pdev)
	313	{
	314	struct asic3 *asic = platform_get_drvdata(pdev);
	315	unsigned long clksel = 0;
	316	unsigned int irq, irq_base;
	317
	318	asic->irq_nr = platform_get_irq(pdev, 0);
	319	if (asic->irq_nr < 0)
	320	return asic->irq_nr;
	321
	322	/* turn on clock to IRQ controller */
	323	clksel \|= CLOCK_SEL_CX;
	324	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
	325	clksel);
	326
	327	irq_base = asic->irq_base;
	328
	329	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
	330	if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
	331	set_irq_chip(irq, &asic3_gpio_irq_chip);
	332	else
333	set_irq_chip(irq, &asic3_irq_chip);
334
335	set_irq_chip_data(irq, asic);
336	set_irq_handler(irq, handle_level_irq);
337	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
338	}
339
340	asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask),
341	ASIC3_INTMASK_GINTMASK);
342
343	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
344	set_irq_type(asic->irq_nr, IRQT_RISING);
345	set_irq_data(asic->irq_nr, asic);
346
347	return 0;
348	}
349
350	static void asic3_irq_remove(struct platform_device *pdev)
351	{
352	struct asic3 *asic = platform_get_drvdata(pdev);
353	unsigned int irq, irq_base;
354
355	irq_base = asic->irq_base;
356
357	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
358	set_irq_flags(irq, 0);
359	set_irq_handler(irq, NULL);
360	set_irq_chip(irq, NULL);
361	set_irq_chip_data(irq, NULL);
362	}
363	set_irq_chained_handler(asic->irq_nr, NULL);
364	}
365
366	/* GPIOs */
6f2384c4 SO	367	static int asic3_gpio_direction(struct gpio_chip *chip,
	368	unsigned offset, int out)
	369	{
	370	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
	371	unsigned int gpio_base;
	372	unsigned long flags;
	373	struct asic3 *asic;
	374
	375	asic = container_of(chip, struct asic3, gpio);
	376	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	377
	378	if (gpio_base > ASIC3_GPIO_D_Base) {
	379	printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
	380	gpio_base, offset);
	381	return -EINVAL;
	382	}
	383
	384	spin_lock_irqsave(&asic->lock, flags);
	385
	386	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_Direction);
	387
	388	/* Input is 0, Output is 1 */
	389	if (out)
	390	out_reg \|= mask;
	391	else
	392	out_reg &= ~mask;
	393
	394	asic3_write_register(asic, gpio_base + ASIC3_GPIO_Direction, out_reg);
	395
	396	spin_unlock_irqrestore(&asic->lock, flags);
	397
	398	return 0;
	399
	400	}
	401
	402	static int asic3_gpio_direction_input(struct gpio_chip *chip,
	403	unsigned offset)
	404	{
	405	return asic3_gpio_direction(chip, offset, 0);
	406	}
	407
	408	static int asic3_gpio_direction_output(struct gpio_chip *chip,
	409	unsigned offset, int value)
	410	{
	411	return asic3_gpio_direction(chip, offset, 1);
	412	}
	413
	414	static int asic3_gpio_get(struct gpio_chip *chip,
	415	unsigned offset)
	416	{
	417	unsigned int gpio_base;
	418	u32 mask = ASIC3_GPIO_TO_MASK(offset);
	419	struct asic3 *asic;
	420
	421	asic = container_of(chip, struct asic3, gpio);
	422	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	423
	424	if (gpio_base > ASIC3_GPIO_D_Base) {
	425	printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
	426	gpio_base, offset);
	427	return -EINVAL;
	428	}
	429
	430	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_Status) & mask;
431	}
432
433	static void asic3_gpio_set(struct gpio_chip *chip,
434	unsigned offset, int value)
435	{
436	u32 mask, out_reg;
437	unsigned int gpio_base;
438	unsigned long flags;
439	struct asic3 *asic;
440
441	asic = container_of(chip, struct asic3, gpio);
442	gpio_base = ASIC3_GPIO_TO_BASE(offset);
443
444	if (gpio_base > ASIC3_GPIO_D_Base) {
445	printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
446	gpio_base, offset);
447	return;
448	}
449
450	mask = ASIC3_GPIO_TO_MASK(offset);
451
452	spin_lock_irqsave(&asic->lock, flags);
453
454	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_Out);
455
456	if (value)
457	out_reg \|= mask;
458	else
459	out_reg &= ~mask;
460
461	asic3_write_register(asic, gpio_base + ASIC3_GPIO_Out, out_reg);
462
463	spin_unlock_irqrestore(&asic->lock, flags);
464
465	return;
466	}
467
fa9ff4b1 SO	468	static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base,
	469	unsigned int function)
	470	{
	471	return asic3_read_register(asic, base + function);
	472	}
	473
	474	static void asic3_set_gpio(struct asic3 *asic, unsigned int base,
	475	unsigned int function, u32 bits, u32 val)
	476	{
	477	unsigned long flags;
	478
	479	spin_lock_irqsave(&asic->lock, flags);
	480	val \|= (asic3_read_register(asic, base + function) & ~bits);
	481
	482	asic3_write_register(asic, base + function, val);
	483	spin_unlock_irqrestore(&asic->lock, flags);
	484	}
	485
fa9ff4b1 SO	486	#define asic3_set_gpio_a(asic, fn, bits, val) \
	487	asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val)
	488	#define asic3_set_gpio_b(asic, fn, bits, val) \
	489	asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val)
	490	#define asic3_set_gpio_c(asic, fn, bits, val) \
	491	asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val)
	492	#define asic3_set_gpio_d(asic, fn, bits, val) \
	493	asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val)
	494
	495	#define asic3_set_gpio_banks(asic, fn, bits, pdata, field) \
	496	do { \
	497	asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \
	498	asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \
	499	asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \
	500	asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \
	501	} while (0)
	502
fa9ff4b1 SO	503
	504	static int asic3_gpio_probe(struct platform_device *pdev)
	505	{
	506	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	507	struct asic3 *asic = platform_get_drvdata(pdev);
	508
	509	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff);
	510	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff);
	511	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff);
	512	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff);
	513
	514	asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff);
	515	asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff);
	516	asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff);
	517	asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff);
	518
	519	if (pdata) {
	520	asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init);
	521	asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir);
	522	asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata,
	523	sleep_mask);
	524	asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out);
	525	asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata,
	526	batt_fault_out);
	527	asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata,
	528	sleep_conf);
	529	asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata,
	530	alt_function);
	531	}
	532
6f2384c4	533	return gpiochip_add(&asic->gpio);
fa9ff4b1 SO	534	}
fa9ff4b1 SO	535
6f2384c4	536	static int asic3_gpio_remove(struct platform_device *pdev)
fa9ff4b1	537	{
6f2384c4 SO	538	struct asic3 *asic = platform_get_drvdata(pdev);
	539
	540	return gpiochip_remove(&asic->gpio);
fa9ff4b1 SO	541	}
	542
	543
	544	/* Core */
	545	static int asic3_probe(struct platform_device *pdev)
	546	{
	547	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	548	struct asic3 *asic;
	549	struct resource *mem;
	550	unsigned long clksel;
6f2384c4	551	int ret = 0;
fa9ff4b1 SO	552
fa9ff4b1 SO	553	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
6f2384c4 SO	554	if (asic == NULL) {
6f2384c4 SO	555	printk(KERN_ERR "kzalloc failed\n");
fa9ff4b1	556	return -ENOMEM;
6f2384c4	557	}
fa9ff4b1 SO	558
	559	spin_lock_init(&asic->lock);
	560	platform_set_drvdata(pdev, asic);
	561	asic->dev = &pdev->dev;
	562
	563	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	564	if (!mem) {
	565	ret = -ENOMEM;
	566	printk(KERN_ERR "asic3: no MEM resource\n");
6f2384c4	567	goto out_free;
fa9ff4b1 SO	568	}
fa9ff4b1 SO	569
6f2384c4	570
fa9ff4b1 SO	571	asic->mapping = ioremap(mem->start, PAGE_SIZE);
	572	if (!asic->mapping) {
	573	ret = -ENOMEM;
	574	printk(KERN_ERR "asic3: couldn't ioremap\n");
6f2384c4	575	goto out_free;
fa9ff4b1 SO	576	}
	577
	578	asic->irq_base = pdata->irq_base;
	579
	580	if (pdata && pdata->bus_shift)
	581	asic->bus_shift = 2 - pdata->bus_shift;
	582	else
	583	asic->bus_shift = 0;
	584
	585	clksel = 0;
	586	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
	587
	588	ret = asic3_irq_probe(pdev);
	589	if (ret < 0) {
	590	printk(KERN_ERR "asic3: couldn't probe IRQs\n");
6f2384c4 SO	591	goto out_unmap;
	592	}
	593
	594	asic->gpio.base = pdata->gpio_base;
	595	asic->gpio.ngpio = ASIC3_NUM_GPIOS;
	596	asic->gpio.get = asic3_gpio_get;
	597	asic->gpio.set = asic3_gpio_set;
	598	asic->gpio.direction_input = asic3_gpio_direction_input;
	599	asic->gpio.direction_output = asic3_gpio_direction_output;
	600
	601	ret = asic3_gpio_probe(pdev);
	602	if (ret < 0) {
	603	printk(KERN_ERR "GPIO probe failed\n");
	604	goto out_irq;
fa9ff4b1	605	}
fa9ff4b1	606
fa9ff4b1 SO	607	printk(KERN_INFO "ASIC3 Core driver\n");
	608
	609	return 0;
	610
6f2384c4 SO	611	out_irq:
	612	asic3_irq_remove(pdev);
	613
	614	out_unmap:
fa9ff4b1	615	iounmap(asic->mapping);
6f2384c4 SO	616
6f2384c4 SO	617	out_free:
fa9ff4b1 SO	618	kfree(asic);
	619
	620	return ret;
	621	}
	622
	623	static int asic3_remove(struct platform_device *pdev)
	624	{
6f2384c4	625	int ret;
fa9ff4b1 SO	626	struct asic3 *asic = platform_get_drvdata(pdev);
fa9ff4b1 SO	627
6f2384c4 SO	628	ret = asic3_gpio_remove(pdev);
	629	if (ret < 0)
	630	return ret;
fa9ff4b1 SO	631	asic3_irq_remove(pdev);
	632
	633	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
	634
	635	iounmap(asic->mapping);
	636
	637	kfree(asic);
	638
	639	return 0;
	640	}
	641
	642	static void asic3_shutdown(struct platform_device *pdev)
	643	{
	644	}
	645
	646	static struct platform_driver asic3_device_driver = {
	647	.driver = {
	648	.name = "asic3",
	649	},
	650	.probe = asic3_probe,
	651	.remove = __devexit_p(asic3_remove),
	652	.shutdown = asic3_shutdown,
	653	};
	654
	655	static int __init asic3_init(void)
	656	{
	657	int retval = 0;
	658	retval = platform_driver_register(&asic3_device_driver);
	659	return retval;
	660	}
	661
	662	subsys_initcall(asic3_init);