Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
fa9ff4b1 SO |
2 | /* |
3 | * driver/mfd/asic3.c | |
4 | * | |
5 | * Compaq ASIC3 support. | |
6 | * | |
fa9ff4b1 SO |
7 | * Copyright 2001 Compaq Computer Corporation. |
8 | * Copyright 2004-2005 Phil Blundell | |
6f2384c4 | 9 | * Copyright 2007-2008 OpenedHand Ltd. |
fa9ff4b1 SO |
10 | * |
11 | * Authors: Phil Blundell <pb@handhelds.org>, | |
12 | * Samuel Ortiz <sameo@openedhand.com> | |
fa9ff4b1 SO |
13 | */ |
14 | ||
fa9ff4b1 | 15 | #include <linux/kernel.h> |
9461f65a | 16 | #include <linux/delay.h> |
fa9ff4b1 | 17 | #include <linux/irq.h> |
5cd690a3 | 18 | #include <linux/gpio/driver.h> |
5d4a357d | 19 | #include <linux/export.h> |
fa9ff4b1 | 20 | #include <linux/io.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
fa9ff4b1 SO |
22 | #include <linux/spinlock.h> |
23 | #include <linux/platform_device.h> | |
24 | ||
25 | #include <linux/mfd/asic3.h> | |
9461f65a PZ |
26 | #include <linux/mfd/core.h> |
27 | #include <linux/mfd/ds1wm.h> | |
09f05ce8 | 28 | #include <linux/mfd/tmio.h> |
fa9ff4b1 | 29 | |
4eb1d7fc RJ |
30 | #include <linux/mmc/host.h> |
31 | ||
e956a2a8 PZ |
32 | enum { |
33 | ASIC3_CLOCK_SPI, | |
34 | ASIC3_CLOCK_OWM, | |
35 | ASIC3_CLOCK_PWM0, | |
36 | ASIC3_CLOCK_PWM1, | |
37 | ASIC3_CLOCK_LED0, | |
38 | ASIC3_CLOCK_LED1, | |
39 | ASIC3_CLOCK_LED2, | |
40 | ASIC3_CLOCK_SD_HOST, | |
41 | ASIC3_CLOCK_SD_BUS, | |
42 | ASIC3_CLOCK_SMBUS, | |
43 | ASIC3_CLOCK_EX0, | |
44 | ASIC3_CLOCK_EX1, | |
45 | }; | |
46 | ||
47 | struct asic3_clk { | |
48 | int enabled; | |
49 | unsigned int cdex; | |
50 | unsigned long rate; | |
51 | }; | |
52 | ||
53 | #define INIT_CDEX(_name, _rate) \ | |
54 | [ASIC3_CLOCK_##_name] = { \ | |
55 | .cdex = CLOCK_CDEX_##_name, \ | |
56 | .rate = _rate, \ | |
57 | } | |
58 | ||
59f2ad2e | 59 | static struct asic3_clk asic3_clk_init[] __initdata = { |
e956a2a8 PZ |
60 | INIT_CDEX(SPI, 0), |
61 | INIT_CDEX(OWM, 5000000), | |
62 | INIT_CDEX(PWM0, 0), | |
63 | INIT_CDEX(PWM1, 0), | |
64 | INIT_CDEX(LED0, 0), | |
65 | INIT_CDEX(LED1, 0), | |
66 | INIT_CDEX(LED2, 0), | |
67 | INIT_CDEX(SD_HOST, 24576000), | |
68 | INIT_CDEX(SD_BUS, 12288000), | |
69 | INIT_CDEX(SMBUS, 0), | |
70 | INIT_CDEX(EX0, 32768), | |
71 | INIT_CDEX(EX1, 24576000), | |
72 | }; | |
73 | ||
6f2384c4 SO |
74 | struct asic3 { |
75 | void __iomem *mapping; | |
76 | unsigned int bus_shift; | |
77 | unsigned int irq_nr; | |
78 | unsigned int irq_base; | |
93ad4471 | 79 | raw_spinlock_t lock; |
6f2384c4 SO |
80 | u16 irq_bothedge[4]; |
81 | struct gpio_chip gpio; | |
82 | struct device *dev; | |
64e8867b | 83 | void __iomem *tmio_cnf; |
e956a2a8 PZ |
84 | |
85 | struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)]; | |
6f2384c4 SO |
86 | }; |
87 | ||
88 | static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset); | |
89 | ||
13ca4f66 | 90 | void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value) |
fa9ff4b1 | 91 | { |
b32661e0 | 92 | iowrite16(value, asic->mapping + |
fa9ff4b1 SO |
93 | (reg >> asic->bus_shift)); |
94 | } | |
13ca4f66 | 95 | EXPORT_SYMBOL_GPL(asic3_write_register); |
fa9ff4b1 | 96 | |
13ca4f66 | 97 | u32 asic3_read_register(struct asic3 *asic, unsigned int reg) |
fa9ff4b1 | 98 | { |
b32661e0 | 99 | return ioread16(asic->mapping + |
fa9ff4b1 SO |
100 | (reg >> asic->bus_shift)); |
101 | } | |
13ca4f66 | 102 | EXPORT_SYMBOL_GPL(asic3_read_register); |
fa9ff4b1 | 103 | |
59f2ad2e | 104 | static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) |
6483c1b5 PZ |
105 | { |
106 | unsigned long flags; | |
107 | u32 val; | |
108 | ||
93ad4471 | 109 | raw_spin_lock_irqsave(&asic->lock, flags); |
6483c1b5 PZ |
110 | val = asic3_read_register(asic, reg); |
111 | if (set) | |
112 | val |= bits; | |
113 | else | |
114 | val &= ~bits; | |
115 | asic3_write_register(asic, reg, val); | |
93ad4471 | 116 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
6483c1b5 PZ |
117 | } |
118 | ||
fa9ff4b1 SO |
119 | /* IRQs */ |
120 | #define MAX_ASIC_ISR_LOOPS 20 | |
3b8139f8 SO |
121 | #define ASIC3_GPIO_BASE_INCR \ |
122 | (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE) | |
fa9ff4b1 SO |
123 | |
124 | static void asic3_irq_flip_edge(struct asic3 *asic, | |
125 | u32 base, int bit) | |
126 | { | |
127 | u16 edge; | |
128 | unsigned long flags; | |
129 | ||
93ad4471 | 130 | raw_spin_lock_irqsave(&asic->lock, flags); |
fa9ff4b1 | 131 | edge = asic3_read_register(asic, |
3b8139f8 | 132 | base + ASIC3_GPIO_EDGE_TRIGGER); |
fa9ff4b1 SO |
133 | edge ^= bit; |
134 | asic3_write_register(asic, | |
3b8139f8 | 135 | base + ASIC3_GPIO_EDGE_TRIGGER, edge); |
93ad4471 | 136 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
fa9ff4b1 SO |
137 | } |
138 | ||
bd0b9ac4 | 139 | static void asic3_irq_demux(struct irq_desc *desc) |
fa9ff4b1 | 140 | { |
52a7d607 TG |
141 | struct asic3 *asic = irq_desc_get_handler_data(desc); |
142 | struct irq_data *data = irq_desc_get_irq_data(desc); | |
fa9ff4b1 SO |
143 | int iter, i; |
144 | unsigned long flags; | |
fa9ff4b1 | 145 | |
a09aee8b | 146 | data->chip->irq_ack(data); |
fa9ff4b1 SO |
147 | |
148 | for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) { | |
149 | u32 status; | |
150 | int bank; | |
151 | ||
93ad4471 | 152 | raw_spin_lock_irqsave(&asic->lock, flags); |
fa9ff4b1 | 153 | status = asic3_read_register(asic, |
3b8139f8 | 154 | ASIC3_OFFSET(INTR, P_INT_STAT)); |
93ad4471 | 155 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
fa9ff4b1 SO |
156 | |
157 | /* Check all ten register bits */ | |
158 | if ((status & 0x3ff) == 0) | |
159 | break; | |
160 | ||
161 | /* Handle GPIO IRQs */ | |
162 | for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) { | |
163 | if (status & (1 << bank)) { | |
164 | unsigned long base, istat; | |
165 | ||
3b8139f8 SO |
166 | base = ASIC3_GPIO_A_BASE |
167 | + bank * ASIC3_GPIO_BASE_INCR; | |
93ad4471 | 168 | raw_spin_lock_irqsave(&asic->lock, flags); |
fa9ff4b1 SO |
169 | istat = asic3_read_register(asic, |
170 | base + | |
3b8139f8 | 171 | ASIC3_GPIO_INT_STATUS); |
fa9ff4b1 SO |
172 | /* Clearing IntStatus */ |
173 | asic3_write_register(asic, | |
174 | base + | |
3b8139f8 | 175 | ASIC3_GPIO_INT_STATUS, 0); |
93ad4471 | 176 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
fa9ff4b1 SO |
177 | |
178 | for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) { | |
179 | int bit = (1 << i); | |
180 | unsigned int irqnr; | |
181 | ||
182 | if (!(istat & bit)) | |
183 | continue; | |
184 | ||
185 | irqnr = asic->irq_base + | |
186 | (ASIC3_GPIOS_PER_BANK * bank) | |
187 | + i; | |
52a7d607 | 188 | generic_handle_irq(irqnr); |
fa9ff4b1 SO |
189 | if (asic->irq_bothedge[bank] & bit) |
190 | asic3_irq_flip_edge(asic, base, | |
191 | bit); | |
192 | } | |
193 | } | |
194 | } | |
195 | ||
196 | /* Handle remaining IRQs in the status register */ | |
197 | for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) { | |
198 | /* They start at bit 4 and go up */ | |
52a7d607 TG |
199 | if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) |
200 | generic_handle_irq(asic->irq_base + i); | |
fa9ff4b1 SO |
201 | } |
202 | } | |
203 | ||
204 | if (iter >= MAX_ASIC_ISR_LOOPS) | |
24f4f2ee | 205 | dev_err(asic->dev, "interrupt processing overrun\n"); |
fa9ff4b1 SO |
206 | } |
207 | ||
208 | static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) | |
209 | { | |
210 | int n; | |
211 | ||
212 | n = (irq - asic->irq_base) >> 4; | |
213 | ||
3b8139f8 | 214 | return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)); |
fa9ff4b1 SO |
215 | } |
216 | ||
217 | static inline int asic3_irq_to_index(struct asic3 *asic, int irq) | |
218 | { | |
219 | return (irq - asic->irq_base) & 0xf; | |
220 | } | |
221 | ||
0f76aaeb | 222 | static void asic3_mask_gpio_irq(struct irq_data *data) |
fa9ff4b1 | 223 | { |
0f76aaeb | 224 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
225 | u32 val, bank, index; |
226 | unsigned long flags; | |
227 | ||
0f76aaeb MB |
228 | bank = asic3_irq_to_bank(asic, data->irq); |
229 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 | 230 | |
93ad4471 | 231 | raw_spin_lock_irqsave(&asic->lock, flags); |
3b8139f8 | 232 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
fa9ff4b1 | 233 | val |= 1 << index; |
3b8139f8 | 234 | asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); |
93ad4471 | 235 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
fa9ff4b1 SO |
236 | } |
237 | ||
0f76aaeb | 238 | static void asic3_mask_irq(struct irq_data *data) |
fa9ff4b1 | 239 | { |
0f76aaeb | 240 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
241 | int regval; |
242 | unsigned long flags; | |
243 | ||
93ad4471 | 244 | raw_spin_lock_irqsave(&asic->lock, flags); |
fa9ff4b1 | 245 | regval = asic3_read_register(asic, |
3b8139f8 SO |
246 | ASIC3_INTR_BASE + |
247 | ASIC3_INTR_INT_MASK); | |
fa9ff4b1 SO |
248 | |
249 | regval &= ~(ASIC3_INTMASK_MASK0 << | |
0f76aaeb | 250 | (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); |
fa9ff4b1 SO |
251 | |
252 | asic3_write_register(asic, | |
3b8139f8 SO |
253 | ASIC3_INTR_BASE + |
254 | ASIC3_INTR_INT_MASK, | |
fa9ff4b1 | 255 | regval); |
93ad4471 | 256 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
fa9ff4b1 SO |
257 | } |
258 | ||
0f76aaeb | 259 | static void asic3_unmask_gpio_irq(struct irq_data *data) |
fa9ff4b1 | 260 | { |
0f76aaeb | 261 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
262 | u32 val, bank, index; |
263 | unsigned long flags; | |
264 | ||
0f76aaeb MB |
265 | bank = asic3_irq_to_bank(asic, data->irq); |
266 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 | 267 | |
93ad4471 | 268 | raw_spin_lock_irqsave(&asic->lock, flags); |
3b8139f8 | 269 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
fa9ff4b1 | 270 | val &= ~(1 << index); |
3b8139f8 | 271 | asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); |
93ad4471 | 272 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
fa9ff4b1 SO |
273 | } |
274 | ||
0f76aaeb | 275 | static void asic3_unmask_irq(struct irq_data *data) |
fa9ff4b1 | 276 | { |
0f76aaeb | 277 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
278 | int regval; |
279 | unsigned long flags; | |
280 | ||
93ad4471 | 281 | raw_spin_lock_irqsave(&asic->lock, flags); |
fa9ff4b1 | 282 | regval = asic3_read_register(asic, |
3b8139f8 SO |
283 | ASIC3_INTR_BASE + |
284 | ASIC3_INTR_INT_MASK); | |
fa9ff4b1 SO |
285 | |
286 | regval |= (ASIC3_INTMASK_MASK0 << | |
0f76aaeb | 287 | (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); |
fa9ff4b1 SO |
288 | |
289 | asic3_write_register(asic, | |
3b8139f8 SO |
290 | ASIC3_INTR_BASE + |
291 | ASIC3_INTR_INT_MASK, | |
fa9ff4b1 | 292 | regval); |
93ad4471 | 293 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
fa9ff4b1 SO |
294 | } |
295 | ||
0f76aaeb | 296 | static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type) |
fa9ff4b1 | 297 | { |
0f76aaeb | 298 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
fa9ff4b1 SO |
299 | u32 bank, index; |
300 | u16 trigger, level, edge, bit; | |
301 | unsigned long flags; | |
302 | ||
0f76aaeb MB |
303 | bank = asic3_irq_to_bank(asic, data->irq); |
304 | index = asic3_irq_to_index(asic, data->irq); | |
fa9ff4b1 SO |
305 | bit = 1<<index; |
306 | ||
93ad4471 | 307 | raw_spin_lock_irqsave(&asic->lock, flags); |
fa9ff4b1 | 308 | level = asic3_read_register(asic, |
3b8139f8 | 309 | bank + ASIC3_GPIO_LEVEL_TRIGGER); |
fa9ff4b1 | 310 | edge = asic3_read_register(asic, |
3b8139f8 | 311 | bank + ASIC3_GPIO_EDGE_TRIGGER); |
fa9ff4b1 | 312 | trigger = asic3_read_register(asic, |
3b8139f8 | 313 | bank + ASIC3_GPIO_TRIGGER_TYPE); |
0f76aaeb | 314 | asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit; |
fa9ff4b1 | 315 | |
6cab4860 | 316 | if (type == IRQ_TYPE_EDGE_RISING) { |
fa9ff4b1 SO |
317 | trigger |= bit; |
318 | edge |= bit; | |
6cab4860 | 319 | } else if (type == IRQ_TYPE_EDGE_FALLING) { |
fa9ff4b1 SO |
320 | trigger |= bit; |
321 | edge &= ~bit; | |
6cab4860 | 322 | } else if (type == IRQ_TYPE_EDGE_BOTH) { |
fa9ff4b1 | 323 | trigger |= bit; |
0f76aaeb | 324 | if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base)) |
fa9ff4b1 SO |
325 | edge &= ~bit; |
326 | else | |
327 | edge |= bit; | |
0f76aaeb | 328 | asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit; |
6cab4860 | 329 | } else if (type == IRQ_TYPE_LEVEL_LOW) { |
fa9ff4b1 SO |
330 | trigger &= ~bit; |
331 | level &= ~bit; | |
6cab4860 | 332 | } else if (type == IRQ_TYPE_LEVEL_HIGH) { |
fa9ff4b1 SO |
333 | trigger &= ~bit; |
334 | level |= bit; | |
335 | } else { | |
336 | /* | |
6cab4860 | 337 | * if type == IRQ_TYPE_NONE, we should mask interrupts, but |
fa9ff4b1 SO |
338 | * be careful to not unmask them if mask was also called. |
339 | * Probably need internal state for mask. | |
340 | */ | |
24f4f2ee | 341 | dev_notice(asic->dev, "irq type not changed\n"); |
fa9ff4b1 | 342 | } |
3b8139f8 | 343 | asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, |
fa9ff4b1 | 344 | level); |
3b8139f8 | 345 | asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, |
fa9ff4b1 | 346 | edge); |
3b8139f8 | 347 | asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, |
fa9ff4b1 | 348 | trigger); |
93ad4471 | 349 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
fa9ff4b1 SO |
350 | return 0; |
351 | } | |
352 | ||
2fe372fc PP |
353 | static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on) |
354 | { | |
355 | struct asic3 *asic = irq_data_get_irq_chip_data(data); | |
356 | u32 bank, index; | |
357 | u16 bit; | |
358 | ||
359 | bank = asic3_irq_to_bank(asic, data->irq); | |
360 | index = asic3_irq_to_index(asic, data->irq); | |
361 | bit = 1<<index; | |
362 | ||
363 | asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on); | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
fa9ff4b1 SO |
368 | static struct irq_chip asic3_gpio_irq_chip = { |
369 | .name = "ASIC3-GPIO", | |
0f76aaeb MB |
370 | .irq_ack = asic3_mask_gpio_irq, |
371 | .irq_mask = asic3_mask_gpio_irq, | |
372 | .irq_unmask = asic3_unmask_gpio_irq, | |
373 | .irq_set_type = asic3_gpio_irq_type, | |
2fe372fc | 374 | .irq_set_wake = asic3_gpio_irq_set_wake, |
fa9ff4b1 SO |
375 | }; |
376 | ||
377 | static struct irq_chip asic3_irq_chip = { | |
378 | .name = "ASIC3", | |
0f76aaeb MB |
379 | .irq_ack = asic3_mask_irq, |
380 | .irq_mask = asic3_mask_irq, | |
381 | .irq_unmask = asic3_unmask_irq, | |
fa9ff4b1 SO |
382 | }; |
383 | ||
065032f6 | 384 | static int __init asic3_irq_probe(struct platform_device *pdev) |
fa9ff4b1 SO |
385 | { |
386 | struct asic3 *asic = platform_get_drvdata(pdev); | |
387 | unsigned long clksel = 0; | |
388 | unsigned int irq, irq_base; | |
c491b2ff | 389 | int ret; |
fa9ff4b1 | 390 | |
c491b2ff RK |
391 | ret = platform_get_irq(pdev, 0); |
392 | if (ret < 0) | |
393 | return ret; | |
394 | asic->irq_nr = ret; | |
fa9ff4b1 SO |
395 | |
396 | /* turn on clock to IRQ controller */ | |
397 | clksel |= CLOCK_SEL_CX; | |
398 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), | |
399 | clksel); | |
400 | ||
401 | irq_base = asic->irq_base; | |
402 | ||
403 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | |
404 | if (irq < asic->irq_base + ASIC3_NUM_GPIOS) | |
d5bb1221 | 405 | irq_set_chip(irq, &asic3_gpio_irq_chip); |
fa9ff4b1 | 406 | else |
d5bb1221 | 407 | irq_set_chip(irq, &asic3_irq_chip); |
fa9ff4b1 | 408 | |
d5bb1221 TG |
409 | irq_set_chip_data(irq, asic); |
410 | irq_set_handler(irq, handle_level_irq); | |
9bd09f34 | 411 | irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
fa9ff4b1 SO |
412 | } |
413 | ||
3b8139f8 | 414 | asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK), |
fa9ff4b1 SO |
415 | ASIC3_INTMASK_GINTMASK); |
416 | ||
c30e3047 | 417 | irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic); |
d5bb1221 | 418 | irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); |
fa9ff4b1 SO |
419 | |
420 | return 0; | |
421 | } | |
422 | ||
423 | static void asic3_irq_remove(struct platform_device *pdev) | |
424 | { | |
425 | struct asic3 *asic = platform_get_drvdata(pdev); | |
426 | unsigned int irq, irq_base; | |
427 | ||
428 | irq_base = asic->irq_base; | |
429 | ||
430 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | |
9bd09f34 | 431 | irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
d6f7ce9f | 432 | irq_set_chip_and_handler(irq, NULL, NULL); |
d5bb1221 | 433 | irq_set_chip_data(irq, NULL); |
fa9ff4b1 | 434 | } |
d5bb1221 | 435 | irq_set_chained_handler(asic->irq_nr, NULL); |
fa9ff4b1 SO |
436 | } |
437 | ||
438 | /* GPIOs */ | |
6f2384c4 SO |
439 | static int asic3_gpio_direction(struct gpio_chip *chip, |
440 | unsigned offset, int out) | |
441 | { | |
442 | u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg; | |
443 | unsigned int gpio_base; | |
444 | unsigned long flags; | |
445 | struct asic3 *asic; | |
446 | ||
082cc468 | 447 | asic = gpiochip_get_data(chip); |
6f2384c4 SO |
448 | gpio_base = ASIC3_GPIO_TO_BASE(offset); |
449 | ||
3b8139f8 | 450 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
451 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
452 | gpio_base, offset); | |
6f2384c4 SO |
453 | return -EINVAL; |
454 | } | |
455 | ||
93ad4471 | 456 | raw_spin_lock_irqsave(&asic->lock, flags); |
6f2384c4 | 457 | |
3b8139f8 | 458 | out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); |
6f2384c4 SO |
459 | |
460 | /* Input is 0, Output is 1 */ | |
461 | if (out) | |
462 | out_reg |= mask; | |
463 | else | |
464 | out_reg &= ~mask; | |
465 | ||
3b8139f8 | 466 | asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg); |
6f2384c4 | 467 | |
93ad4471 | 468 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
6f2384c4 SO |
469 | |
470 | return 0; | |
471 | ||
472 | } | |
473 | ||
474 | static int asic3_gpio_direction_input(struct gpio_chip *chip, | |
475 | unsigned offset) | |
476 | { | |
477 | return asic3_gpio_direction(chip, offset, 0); | |
478 | } | |
479 | ||
480 | static int asic3_gpio_direction_output(struct gpio_chip *chip, | |
481 | unsigned offset, int value) | |
482 | { | |
483 | return asic3_gpio_direction(chip, offset, 1); | |
484 | } | |
485 | ||
486 | static int asic3_gpio_get(struct gpio_chip *chip, | |
487 | unsigned offset) | |
488 | { | |
489 | unsigned int gpio_base; | |
490 | u32 mask = ASIC3_GPIO_TO_MASK(offset); | |
491 | struct asic3 *asic; | |
492 | ||
082cc468 | 493 | asic = gpiochip_get_data(chip); |
6f2384c4 SO |
494 | gpio_base = ASIC3_GPIO_TO_BASE(offset); |
495 | ||
3b8139f8 | 496 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
497 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
498 | gpio_base, offset); | |
6f2384c4 SO |
499 | return -EINVAL; |
500 | } | |
501 | ||
f8e3a514 LW |
502 | return !!(asic3_read_register(asic, |
503 | gpio_base + ASIC3_GPIO_STATUS) & mask); | |
6f2384c4 SO |
504 | } |
505 | ||
506 | static void asic3_gpio_set(struct gpio_chip *chip, | |
507 | unsigned offset, int value) | |
508 | { | |
509 | u32 mask, out_reg; | |
510 | unsigned int gpio_base; | |
511 | unsigned long flags; | |
512 | struct asic3 *asic; | |
513 | ||
082cc468 | 514 | asic = gpiochip_get_data(chip); |
6f2384c4 SO |
515 | gpio_base = ASIC3_GPIO_TO_BASE(offset); |
516 | ||
3b8139f8 | 517 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
518 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
519 | gpio_base, offset); | |
6f2384c4 SO |
520 | return; |
521 | } | |
522 | ||
523 | mask = ASIC3_GPIO_TO_MASK(offset); | |
524 | ||
93ad4471 | 525 | raw_spin_lock_irqsave(&asic->lock, flags); |
6f2384c4 | 526 | |
3b8139f8 | 527 | out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); |
6f2384c4 SO |
528 | |
529 | if (value) | |
530 | out_reg |= mask; | |
531 | else | |
532 | out_reg &= ~mask; | |
533 | ||
3b8139f8 | 534 | asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg); |
6f2384c4 | 535 | |
93ad4471 | 536 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
6f2384c4 SO |
537 | } |
538 | ||
450b1151 PP |
539 | static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
540 | { | |
082cc468 | 541 | struct asic3 *asic = gpiochip_get_data(chip); |
02269ab1 | 542 | |
12693f6c | 543 | return asic->irq_base + offset; |
450b1151 PP |
544 | } |
545 | ||
065032f6 PZ |
546 | static __init int asic3_gpio_probe(struct platform_device *pdev, |
547 | u16 *gpio_config, int num) | |
fa9ff4b1 | 548 | { |
fa9ff4b1 | 549 | struct asic3 *asic = platform_get_drvdata(pdev); |
3b26bf17 SO |
550 | u16 alt_reg[ASIC3_NUM_GPIO_BANKS]; |
551 | u16 out_reg[ASIC3_NUM_GPIO_BANKS]; | |
552 | u16 dir_reg[ASIC3_NUM_GPIO_BANKS]; | |
553 | int i; | |
fa9ff4b1 | 554 | |
59f0cb0f RK |
555 | memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); |
556 | memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); | |
557 | memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); | |
3b26bf17 SO |
558 | |
559 | /* Enable all GPIOs */ | |
3b8139f8 SO |
560 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); |
561 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); | |
562 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); | |
563 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); | |
fa9ff4b1 | 564 | |
3b26bf17 SO |
565 | for (i = 0; i < num; i++) { |
566 | u8 alt, pin, dir, init, bank_num, bit_num; | |
567 | u16 config = gpio_config[i]; | |
568 | ||
569 | pin = ASIC3_CONFIG_GPIO_PIN(config); | |
570 | alt = ASIC3_CONFIG_GPIO_ALT(config); | |
571 | dir = ASIC3_CONFIG_GPIO_DIR(config); | |
572 | init = ASIC3_CONFIG_GPIO_INIT(config); | |
573 | ||
574 | bank_num = ASIC3_GPIO_TO_BANK(pin); | |
575 | bit_num = ASIC3_GPIO_TO_BIT(pin); | |
576 | ||
577 | alt_reg[bank_num] |= (alt << bit_num); | |
578 | out_reg[bank_num] |= (init << bit_num); | |
579 | dir_reg[bank_num] |= (dir << bit_num); | |
580 | } | |
581 | ||
582 | for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) { | |
583 | asic3_write_register(asic, | |
584 | ASIC3_BANK_TO_BASE(i) + | |
3b8139f8 | 585 | ASIC3_GPIO_DIRECTION, |
3b26bf17 SO |
586 | dir_reg[i]); |
587 | asic3_write_register(asic, | |
3b8139f8 | 588 | ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT, |
3b26bf17 SO |
589 | out_reg[i]); |
590 | asic3_write_register(asic, | |
591 | ASIC3_BANK_TO_BASE(i) + | |
3b8139f8 | 592 | ASIC3_GPIO_ALT_FUNCTION, |
3b26bf17 | 593 | alt_reg[i]); |
fa9ff4b1 SO |
594 | } |
595 | ||
082cc468 | 596 | return gpiochip_add_data(&asic->gpio, asic); |
fa9ff4b1 SO |
597 | } |
598 | ||
2598f6ec | 599 | static void asic3_gpio_remove(struct platform_device *pdev) |
fa9ff4b1 | 600 | { |
6f2384c4 SO |
601 | struct asic3 *asic = platform_get_drvdata(pdev); |
602 | ||
88d5e520 | 603 | gpiochip_remove(&asic->gpio); |
fa9ff4b1 SO |
604 | } |
605 | ||
c29a8127 | 606 | static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) |
e956a2a8 PZ |
607 | { |
608 | unsigned long flags; | |
609 | u32 cdex; | |
610 | ||
93ad4471 | 611 | raw_spin_lock_irqsave(&asic->lock, flags); |
e956a2a8 PZ |
612 | if (clk->enabled++ == 0) { |
613 | cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); | |
614 | cdex |= clk->cdex; | |
615 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); | |
616 | } | |
93ad4471 | 617 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
e956a2a8 PZ |
618 | } |
619 | ||
620 | static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk) | |
621 | { | |
622 | unsigned long flags; | |
623 | u32 cdex; | |
624 | ||
625 | WARN_ON(clk->enabled == 0); | |
626 | ||
93ad4471 | 627 | raw_spin_lock_irqsave(&asic->lock, flags); |
e956a2a8 PZ |
628 | if (--clk->enabled == 0) { |
629 | cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); | |
630 | cdex &= ~clk->cdex; | |
631 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); | |
632 | } | |
93ad4471 | 633 | raw_spin_unlock_irqrestore(&asic->lock, flags); |
e956a2a8 | 634 | } |
fa9ff4b1 | 635 | |
9461f65a PZ |
636 | /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */ |
637 | static struct ds1wm_driver_data ds1wm_pdata = { | |
638 | .active_high = 1, | |
f607e7fc | 639 | .reset_recover_delay = 1, |
9461f65a PZ |
640 | }; |
641 | ||
642 | static struct resource ds1wm_resources[] = { | |
643 | { | |
644 | .start = ASIC3_OWM_BASE, | |
645 | .end = ASIC3_OWM_BASE + 0x13, | |
646 | .flags = IORESOURCE_MEM, | |
647 | }, | |
648 | { | |
649 | .start = ASIC3_IRQ_OWM, | |
fe421425 | 650 | .end = ASIC3_IRQ_OWM, |
9461f65a PZ |
651 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
652 | }, | |
653 | }; | |
654 | ||
655 | static int ds1wm_enable(struct platform_device *pdev) | |
656 | { | |
657 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
658 | ||
659 | /* Turn on external clocks and the OWM clock */ | |
660 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
661 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
662 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); | |
d43c4290 | 663 | usleep_range(1000, 5000); |
9461f65a PZ |
664 | |
665 | /* Reset and enable DS1WM */ | |
666 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), | |
667 | ASIC3_EXTCF_OWM_RESET, 1); | |
d43c4290 | 668 | usleep_range(1000, 5000); |
9461f65a PZ |
669 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), |
670 | ASIC3_EXTCF_OWM_RESET, 0); | |
d43c4290 | 671 | usleep_range(1000, 5000); |
9461f65a PZ |
672 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), |
673 | ASIC3_EXTCF_OWM_EN, 1); | |
d43c4290 | 674 | usleep_range(1000, 5000); |
9461f65a PZ |
675 | |
676 | return 0; | |
677 | } | |
678 | ||
679 | static int ds1wm_disable(struct platform_device *pdev) | |
680 | { | |
681 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
682 | ||
683 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
684 | ASIC3_EXTCF_OWM_EN, 0); | |
685 | ||
686 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); | |
687 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
688 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
689 | ||
690 | return 0; | |
691 | } | |
692 | ||
5ac98553 | 693 | static const struct mfd_cell asic3_cell_ds1wm = { |
9461f65a PZ |
694 | .name = "ds1wm", |
695 | .enable = ds1wm_enable, | |
696 | .disable = ds1wm_disable, | |
121ea573 SO |
697 | .platform_data = &ds1wm_pdata, |
698 | .pdata_size = sizeof(ds1wm_pdata), | |
9461f65a PZ |
699 | .num_resources = ARRAY_SIZE(ds1wm_resources), |
700 | .resources = ds1wm_resources, | |
701 | }; | |
702 | ||
64e8867b IM |
703 | static void asic3_mmc_pwr(struct platform_device *pdev, int state) |
704 | { | |
705 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
706 | ||
707 | tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state); | |
708 | } | |
709 | ||
710 | static void asic3_mmc_clk_div(struct platform_device *pdev, int state) | |
711 | { | |
712 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
713 | ||
714 | tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state); | |
715 | } | |
716 | ||
09f05ce8 | 717 | static struct tmio_mmc_data asic3_mmc_data = { |
64e8867b | 718 | .hclk = 24576000, |
4eb1d7fc | 719 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, |
64e8867b IM |
720 | .set_pwr = asic3_mmc_pwr, |
721 | .set_clk_div = asic3_mmc_clk_div, | |
09f05ce8 PZ |
722 | }; |
723 | ||
724 | static struct resource asic3_mmc_resources[] = { | |
c5db56fe ZL |
725 | DEFINE_RES_MEM(ASIC3_SD_CTRL_BASE, 0x400), |
726 | DEFINE_RES_IRQ(0) | |
09f05ce8 PZ |
727 | }; |
728 | ||
729 | static int asic3_mmc_enable(struct platform_device *pdev) | |
730 | { | |
731 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
732 | ||
733 | /* Not sure if it must be done bit by bit, but leaving as-is */ | |
734 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
735 | ASIC3_SDHWCTRL_LEVCD, 1); | |
736 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
737 | ASIC3_SDHWCTRL_LEVWP, 1); | |
738 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
739 | ASIC3_SDHWCTRL_SUSPEND, 0); | |
740 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
741 | ASIC3_SDHWCTRL_PCLR, 0); | |
742 | ||
743 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
744 | /* CLK32 used for card detection and for interruption detection | |
745 | * when HCLK is stopped. | |
746 | */ | |
747 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
d43c4290 | 748 | usleep_range(1000, 5000); |
09f05ce8 PZ |
749 | |
750 | /* HCLK 24.576 MHz, BCLK 12.288 MHz: */ | |
751 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), | |
752 | CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL); | |
753 | ||
754 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); | |
755 | asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); | |
d43c4290 | 756 | usleep_range(1000, 5000); |
09f05ce8 PZ |
757 | |
758 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
759 | ASIC3_EXTCF_SD_MEM_ENABLE, 1); | |
760 | ||
761 | /* Enable SD card slot 3.3V power supply */ | |
762 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
763 | ASIC3_SDHWCTRL_SDPWR, 1); | |
764 | ||
64e8867b IM |
765 | /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */ |
766 | tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift, | |
767 | ASIC3_SD_CTRL_BASE >> 1); | |
768 | ||
09f05ce8 PZ |
769 | return 0; |
770 | } | |
771 | ||
772 | static int asic3_mmc_disable(struct platform_device *pdev) | |
773 | { | |
774 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
775 | ||
776 | /* Put in suspend mode */ | |
777 | asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), | |
778 | ASIC3_SDHWCTRL_SUSPEND, 1); | |
779 | ||
780 | /* Disable clocks */ | |
781 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); | |
782 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); | |
783 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); | |
784 | asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); | |
785 | return 0; | |
786 | } | |
787 | ||
5ac98553 | 788 | static const struct mfd_cell asic3_cell_mmc = { |
09f05ce8 PZ |
789 | .name = "tmio-mmc", |
790 | .enable = asic3_mmc_enable, | |
791 | .disable = asic3_mmc_disable, | |
3c6e3653 PP |
792 | .suspend = asic3_mmc_disable, |
793 | .resume = asic3_mmc_enable, | |
ec71974f SO |
794 | .platform_data = &asic3_mmc_data, |
795 | .pdata_size = sizeof(asic3_mmc_data), | |
09f05ce8 PZ |
796 | .num_resources = ARRAY_SIZE(asic3_mmc_resources), |
797 | .resources = asic3_mmc_resources, | |
798 | }; | |
799 | ||
13ca4f66 PP |
800 | static const int clock_ledn[ASIC3_NUM_LEDS] = { |
801 | [0] = ASIC3_CLOCK_LED0, | |
802 | [1] = ASIC3_CLOCK_LED1, | |
803 | [2] = ASIC3_CLOCK_LED2, | |
804 | }; | |
805 | ||
806 | static int asic3_leds_enable(struct platform_device *pdev) | |
807 | { | |
808 | const struct mfd_cell *cell = mfd_get_cell(pdev); | |
809 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
810 | ||
811 | asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]); | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
816 | static int asic3_leds_disable(struct platform_device *pdev) | |
817 | { | |
818 | const struct mfd_cell *cell = mfd_get_cell(pdev); | |
819 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
820 | ||
821 | asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
e0b13b5b PP |
826 | static int asic3_leds_suspend(struct platform_device *pdev) |
827 | { | |
828 | const struct mfd_cell *cell = mfd_get_cell(pdev); | |
829 | struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); | |
830 | ||
831 | while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0) | |
d43c4290 | 832 | usleep_range(1000, 5000); |
e0b13b5b PP |
833 | |
834 | asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
13ca4f66 PP |
839 | static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = { |
840 | [0] = { | |
841 | .name = "leds-asic3", | |
842 | .id = 0, | |
843 | .enable = asic3_leds_enable, | |
844 | .disable = asic3_leds_disable, | |
e0b13b5b PP |
845 | .suspend = asic3_leds_suspend, |
846 | .resume = asic3_leds_enable, | |
13ca4f66 PP |
847 | }, |
848 | [1] = { | |
849 | .name = "leds-asic3", | |
850 | .id = 1, | |
851 | .enable = asic3_leds_enable, | |
852 | .disable = asic3_leds_disable, | |
e0b13b5b PP |
853 | .suspend = asic3_leds_suspend, |
854 | .resume = asic3_leds_enable, | |
13ca4f66 PP |
855 | }, |
856 | [2] = { | |
857 | .name = "leds-asic3", | |
858 | .id = 2, | |
859 | .enable = asic3_leds_enable, | |
860 | .disable = asic3_leds_disable, | |
e0b13b5b PP |
861 | .suspend = asic3_leds_suspend, |
862 | .resume = asic3_leds_enable, | |
13ca4f66 PP |
863 | }, |
864 | }; | |
865 | ||
9461f65a | 866 | static int __init asic3_mfd_probe(struct platform_device *pdev, |
13ca4f66 | 867 | struct asic3_platform_data *pdata, |
9461f65a PZ |
868 | struct resource *mem) |
869 | { | |
870 | struct asic3 *asic = platform_get_drvdata(pdev); | |
09f05ce8 PZ |
871 | struct resource *mem_sdio; |
872 | int irq, ret; | |
873 | ||
874 | mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
875 | if (!mem_sdio) | |
876 | dev_dbg(asic->dev, "no SDIO MEM resource\n"); | |
877 | ||
878 | irq = platform_get_irq(pdev, 1); | |
879 | if (irq < 0) | |
880 | dev_dbg(asic->dev, "no SDIO IRQ resource\n"); | |
9461f65a PZ |
881 | |
882 | /* DS1WM */ | |
883 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), | |
884 | ASIC3_EXTCF_OWM_SMB, 0); | |
885 | ||
886 | ds1wm_resources[0].start >>= asic->bus_shift; | |
887 | ds1wm_resources[0].end >>= asic->bus_shift; | |
888 | ||
09f05ce8 | 889 | /* MMC */ |
44b61a9f | 890 | if (mem_sdio) { |
d43c4290 LJ |
891 | asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> |
892 | asic->bus_shift) + mem_sdio->start, | |
74e32d1b | 893 | ASIC3_SD_CONFIG_SIZE >> asic->bus_shift); |
44b61a9f SK |
894 | if (!asic->tmio_cnf) { |
895 | ret = -ENOMEM; | |
896 | dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n"); | |
897 | goto out; | |
898 | } | |
64e8867b | 899 | } |
09f05ce8 PZ |
900 | asic3_mmc_resources[0].start >>= asic->bus_shift; |
901 | asic3_mmc_resources[0].end >>= asic->bus_shift; | |
09f05ce8 | 902 | |
4f304245 PP |
903 | if (pdata->clock_rate) { |
904 | ds1wm_pdata.clock_rate = pdata->clock_rate; | |
905 | ret = mfd_add_devices(&pdev->dev, pdev->id, | |
0848c94f | 906 | &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL); |
4f304245 | 907 | if (ret < 0) |
e84ee1a7 | 908 | goto out_unmap; |
4f304245 | 909 | } |
09f05ce8 | 910 | |
13ca4f66 | 911 | if (mem_sdio && (irq >= 0)) { |
09f05ce8 | 912 | ret = mfd_add_devices(&pdev->dev, pdev->id, |
0848c94f | 913 | &asic3_cell_mmc, 1, mem_sdio, irq, NULL); |
13ca4f66 | 914 | if (ret < 0) |
e84ee1a7 | 915 | goto out_unmap; |
13ca4f66 PP |
916 | } |
917 | ||
b2f0fa82 | 918 | ret = 0; |
13ca4f66 PP |
919 | if (pdata->leds) { |
920 | int i; | |
921 | ||
922 | for (i = 0; i < ASIC3_NUM_LEDS; ++i) { | |
923 | asic3_cell_leds[i].platform_data = &pdata->leds[i]; | |
924 | asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]); | |
925 | } | |
926 | ret = mfd_add_devices(&pdev->dev, 0, | |
0848c94f | 927 | asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL); |
13ca4f66 | 928 | } |
e84ee1a7 | 929 | return ret; |
9461f65a | 930 | |
e84ee1a7 ML |
931 | out_unmap: |
932 | if (asic->tmio_cnf) | |
933 | iounmap(asic->tmio_cnf); | |
934 | out: | |
9461f65a PZ |
935 | return ret; |
936 | } | |
937 | ||
938 | static void asic3_mfd_remove(struct platform_device *pdev) | |
939 | { | |
64e8867b IM |
940 | struct asic3 *asic = platform_get_drvdata(pdev); |
941 | ||
9461f65a | 942 | mfd_remove_devices(&pdev->dev); |
64e8867b | 943 | iounmap(asic->tmio_cnf); |
9461f65a PZ |
944 | } |
945 | ||
fa9ff4b1 | 946 | /* Core */ |
065032f6 | 947 | static int __init asic3_probe(struct platform_device *pdev) |
fa9ff4b1 | 948 | { |
334a41ce | 949 | struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev); |
fa9ff4b1 SO |
950 | struct asic3 *asic; |
951 | struct resource *mem; | |
952 | unsigned long clksel; | |
6f2384c4 | 953 | int ret = 0; |
fa9ff4b1 | 954 | |
1cee87fd LJ |
955 | asic = devm_kzalloc(&pdev->dev, |
956 | sizeof(struct asic3), GFP_KERNEL); | |
d43c4290 | 957 | if (!asic) |
fa9ff4b1 SO |
958 | return -ENOMEM; |
959 | ||
93ad4471 | 960 | raw_spin_lock_init(&asic->lock); |
fa9ff4b1 SO |
961 | platform_set_drvdata(pdev, asic); |
962 | asic->dev = &pdev->dev; | |
963 | ||
964 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
965 | if (!mem) { | |
24f4f2ee | 966 | dev_err(asic->dev, "no MEM resource\n"); |
1cee87fd | 967 | return -ENOMEM; |
fa9ff4b1 SO |
968 | } |
969 | ||
be584bd5 | 970 | asic->mapping = ioremap(mem->start, resource_size(mem)); |
fa9ff4b1 | 971 | if (!asic->mapping) { |
24f4f2ee | 972 | dev_err(asic->dev, "Couldn't ioremap\n"); |
1cee87fd | 973 | return -ENOMEM; |
fa9ff4b1 SO |
974 | } |
975 | ||
976 | asic->irq_base = pdata->irq_base; | |
977 | ||
99cdb0c8 | 978 | /* calculate bus shift from mem resource */ |
be584bd5 | 979 | asic->bus_shift = 2 - (resource_size(mem) >> 12); |
fa9ff4b1 SO |
980 | |
981 | clksel = 0; | |
982 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); | |
983 | ||
984 | ret = asic3_irq_probe(pdev); | |
985 | if (ret < 0) { | |
24f4f2ee | 986 | dev_err(asic->dev, "Couldn't probe IRQs\n"); |
6f2384c4 SO |
987 | goto out_unmap; |
988 | } | |
989 | ||
d8e4a88b | 990 | asic->gpio.label = "asic3"; |
6f2384c4 SO |
991 | asic->gpio.base = pdata->gpio_base; |
992 | asic->gpio.ngpio = ASIC3_NUM_GPIOS; | |
993 | asic->gpio.get = asic3_gpio_get; | |
994 | asic->gpio.set = asic3_gpio_set; | |
995 | asic->gpio.direction_input = asic3_gpio_direction_input; | |
996 | asic->gpio.direction_output = asic3_gpio_direction_output; | |
450b1151 | 997 | asic->gpio.to_irq = asic3_gpio_to_irq; |
6f2384c4 | 998 | |
3b26bf17 SO |
999 | ret = asic3_gpio_probe(pdev, |
1000 | pdata->gpio_config, | |
1001 | pdata->gpio_config_num); | |
6f2384c4 | 1002 | if (ret < 0) { |
24f4f2ee | 1003 | dev_err(asic->dev, "GPIO probe failed\n"); |
6f2384c4 | 1004 | goto out_irq; |
fa9ff4b1 | 1005 | } |
fa9ff4b1 | 1006 | |
e956a2a8 PZ |
1007 | /* Making a per-device copy is only needed for the |
1008 | * theoretical case of multiple ASIC3s on one board: | |
1009 | */ | |
1010 | memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); | |
1011 | ||
13ca4f66 | 1012 | asic3_mfd_probe(pdev, pdata, mem); |
9461f65a | 1013 | |
f22a9c6f PP |
1014 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), |
1015 | (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1); | |
1016 | ||
24f4f2ee | 1017 | dev_info(asic->dev, "ASIC3 Core driver\n"); |
fa9ff4b1 SO |
1018 | |
1019 | return 0; | |
1020 | ||
6f2384c4 SO |
1021 | out_irq: |
1022 | asic3_irq_remove(pdev); | |
1023 | ||
1024 | out_unmap: | |
fa9ff4b1 | 1025 | iounmap(asic->mapping); |
6f2384c4 | 1026 | |
fa9ff4b1 SO |
1027 | return ret; |
1028 | } | |
1029 | ||
4740f73f | 1030 | static int asic3_remove(struct platform_device *pdev) |
fa9ff4b1 SO |
1031 | { |
1032 | struct asic3 *asic = platform_get_drvdata(pdev); | |
1033 | ||
f22a9c6f PP |
1034 | asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), |
1035 | (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0); | |
1036 | ||
9461f65a PZ |
1037 | asic3_mfd_remove(pdev); |
1038 | ||
2598f6ec UKK |
1039 | asic3_gpio_remove(pdev); |
1040 | ||
fa9ff4b1 SO |
1041 | asic3_irq_remove(pdev); |
1042 | ||
1043 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); | |
1044 | ||
1045 | iounmap(asic->mapping); | |
1046 | ||
fa9ff4b1 SO |
1047 | return 0; |
1048 | } | |
1049 | ||
1050 | static void asic3_shutdown(struct platform_device *pdev) | |
1051 | { | |
1052 | } | |
1053 | ||
1054 | static struct platform_driver asic3_device_driver = { | |
1055 | .driver = { | |
1056 | .name = "asic3", | |
1057 | }, | |
84449216 | 1058 | .remove = asic3_remove, |
fa9ff4b1 SO |
1059 | .shutdown = asic3_shutdown, |
1060 | }; | |
1061 | ||
1062 | static int __init asic3_init(void) | |
1063 | { | |
1064 | int retval = 0; | |
d43c4290 | 1065 | |
065032f6 | 1066 | retval = platform_driver_probe(&asic3_device_driver, asic3_probe); |
d43c4290 | 1067 | |
fa9ff4b1 SO |
1068 | return retval; |
1069 | } | |
1070 | ||
1071 | subsys_initcall(asic3_init); |