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9787f5e2 | 1 | /* |
0a589167 PG |
2 | * Altera Arria10 DevKit System Resource MFD Driver |
3 | * | |
4 | * Author: Thor Thayer <tthayer@opensource.altera.com> | |
5 | * | |
9787f5e2 TT |
6 | * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | * | |
20 | * SPI access for Altera Arria10 MAX5 System Resource Chip | |
21 | * | |
22 | * Adapted from DA9052 | |
23 | */ | |
24 | ||
25 | #include <linux/mfd/altera-a10sr.h> | |
26 | #include <linux/mfd/core.h> | |
0a589167 | 27 | #include <linux/init.h> |
9787f5e2 TT |
28 | #include <linux/of.h> |
29 | #include <linux/spi/spi.h> | |
30 | ||
31 | static const struct mfd_cell altr_a10sr_subdev_info[] = { | |
32 | { | |
33 | .name = "altr_a10sr_gpio", | |
34 | .of_compatible = "altr,a10sr-gpio", | |
35 | }, | |
dd47e972 TT |
36 | { |
37 | .name = "altr_a10sr_reset", | |
38 | .of_compatible = "altr,a10sr-reset", | |
39 | }, | |
9787f5e2 TT |
40 | }; |
41 | ||
42 | static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg) | |
43 | { | |
44 | switch (reg) { | |
45 | case ALTR_A10SR_VERSION_READ: | |
46 | case ALTR_A10SR_LED_REG: | |
47 | case ALTR_A10SR_PBDSW_REG: | |
48 | case ALTR_A10SR_PBDSW_IRQ_REG: | |
49 | case ALTR_A10SR_PWR_GOOD1_REG: | |
50 | case ALTR_A10SR_PWR_GOOD2_REG: | |
51 | case ALTR_A10SR_PWR_GOOD3_REG: | |
52 | case ALTR_A10SR_FMCAB_REG: | |
53 | case ALTR_A10SR_HPS_RST_REG: | |
54 | case ALTR_A10SR_USB_QSPI_REG: | |
55 | case ALTR_A10SR_SFPA_REG: | |
56 | case ALTR_A10SR_SFPB_REG: | |
57 | case ALTR_A10SR_I2C_M_REG: | |
58 | case ALTR_A10SR_WARM_RST_REG: | |
59 | case ALTR_A10SR_WR_KEY_REG: | |
60 | case ALTR_A10SR_PMBUS_REG: | |
61 | return true; | |
62 | default: | |
63 | return false; | |
64 | } | |
65 | } | |
66 | ||
67 | static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg) | |
68 | { | |
69 | switch (reg) { | |
70 | case ALTR_A10SR_LED_REG: | |
71 | case ALTR_A10SR_PBDSW_IRQ_REG: | |
72 | case ALTR_A10SR_FMCAB_REG: | |
73 | case ALTR_A10SR_HPS_RST_REG: | |
74 | case ALTR_A10SR_USB_QSPI_REG: | |
75 | case ALTR_A10SR_SFPA_REG: | |
76 | case ALTR_A10SR_SFPB_REG: | |
77 | case ALTR_A10SR_WARM_RST_REG: | |
78 | case ALTR_A10SR_WR_KEY_REG: | |
79 | case ALTR_A10SR_PMBUS_REG: | |
80 | return true; | |
81 | default: | |
82 | return false; | |
83 | } | |
84 | } | |
85 | ||
86 | static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg) | |
87 | { | |
88 | switch (reg) { | |
89 | case ALTR_A10SR_PBDSW_REG: | |
90 | case ALTR_A10SR_PBDSW_IRQ_REG: | |
91 | case ALTR_A10SR_PWR_GOOD1_REG: | |
92 | case ALTR_A10SR_PWR_GOOD2_REG: | |
93 | case ALTR_A10SR_PWR_GOOD3_REG: | |
94 | case ALTR_A10SR_HPS_RST_REG: | |
95 | case ALTR_A10SR_I2C_M_REG: | |
96 | case ALTR_A10SR_WARM_RST_REG: | |
97 | case ALTR_A10SR_WR_KEY_REG: | |
98 | case ALTR_A10SR_PMBUS_REG: | |
99 | return true; | |
100 | default: | |
101 | return false; | |
102 | } | |
103 | } | |
104 | ||
7f70495a | 105 | static const struct regmap_config altr_a10sr_regmap_config = { |
9787f5e2 TT |
106 | .reg_bits = 8, |
107 | .val_bits = 8, | |
108 | ||
109 | .cache_type = REGCACHE_NONE, | |
110 | ||
111 | .use_single_rw = true, | |
112 | .read_flag_mask = 1, | |
113 | .write_flag_mask = 0, | |
114 | ||
115 | .max_register = ALTR_A10SR_WR_KEY_REG, | |
116 | .readable_reg = altr_a10sr_reg_readable, | |
117 | .writeable_reg = altr_a10sr_reg_writeable, | |
118 | .volatile_reg = altr_a10sr_reg_volatile, | |
119 | ||
120 | }; | |
121 | ||
122 | static int altr_a10sr_spi_probe(struct spi_device *spi) | |
123 | { | |
124 | int ret; | |
125 | struct altr_a10sr *a10sr; | |
126 | ||
127 | a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr), | |
128 | GFP_KERNEL); | |
129 | if (!a10sr) | |
130 | return -ENOMEM; | |
131 | ||
132 | spi->mode = SPI_MODE_3; | |
133 | spi->bits_per_word = 8; | |
134 | spi_setup(spi); | |
135 | ||
136 | a10sr->dev = &spi->dev; | |
137 | ||
138 | spi_set_drvdata(spi, a10sr); | |
139 | ||
140 | a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config); | |
141 | if (IS_ERR(a10sr->regmap)) { | |
142 | ret = PTR_ERR(a10sr->regmap); | |
143 | dev_err(&spi->dev, "Failed to allocate register map: %d\n", | |
144 | ret); | |
145 | return ret; | |
146 | } | |
147 | ||
148 | ret = devm_mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO, | |
149 | altr_a10sr_subdev_info, | |
150 | ARRAY_SIZE(altr_a10sr_subdev_info), | |
151 | NULL, 0, NULL); | |
152 | if (ret) | |
153 | dev_err(a10sr->dev, "Failed to register sub-devices: %d\n", | |
154 | ret); | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
159 | static const struct of_device_id altr_a10sr_spi_of_match[] = { | |
160 | { .compatible = "altr,a10sr" }, | |
161 | { }, | |
162 | }; | |
9787f5e2 TT |
163 | |
164 | static struct spi_driver altr_a10sr_spi_driver = { | |
165 | .probe = altr_a10sr_spi_probe, | |
166 | .driver = { | |
167 | .name = "altr_a10sr", | |
168 | .of_match_table = of_match_ptr(altr_a10sr_spi_of_match), | |
169 | }, | |
170 | }; | |
0a589167 | 171 | builtin_driver(altr_a10sr_spi_driver, spi_register_driver) |