Commit | Line | Data |
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dae2db30 AM |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * Author: Arun R Murthy <arun.murthy@stericsson.com> | |
6321992c | 6 | * Author: Daniel Willerud <daniel.willerud@stericsson.com> |
586f3318 | 7 | * Author: Johan Palsson <johan.palsson@stericsson.com> |
dae2db30 AM |
8 | */ |
9 | #include <linux/init.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/device.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/delay.h> | |
5f8aaef4 | 15 | #include <linux/pm_runtime.h> |
dae2db30 AM |
16 | #include <linux/platform_device.h> |
17 | #include <linux/completion.h> | |
18 | #include <linux/regulator/consumer.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/slab.h> | |
6321992c | 21 | #include <linux/list.h> |
dae2db30 | 22 | #include <linux/mfd/abx500.h> |
ee66e653 LW |
23 | #include <linux/mfd/abx500/ab8500.h> |
24 | #include <linux/mfd/abx500/ab8500-gpadc.h> | |
dae2db30 AM |
25 | |
26 | /* | |
27 | * GPADC register offsets | |
28 | * Bank : 0x0A | |
29 | */ | |
30 | #define AB8500_GPADC_CTRL1_REG 0x00 | |
31 | #define AB8500_GPADC_CTRL2_REG 0x01 | |
32 | #define AB8500_GPADC_CTRL3_REG 0x02 | |
33 | #define AB8500_GPADC_AUTO_TIMER_REG 0x03 | |
34 | #define AB8500_GPADC_STAT_REG 0x04 | |
35 | #define AB8500_GPADC_MANDATAL_REG 0x05 | |
36 | #define AB8500_GPADC_MANDATAH_REG 0x06 | |
37 | #define AB8500_GPADC_AUTODATAL_REG 0x07 | |
38 | #define AB8500_GPADC_AUTODATAH_REG 0x08 | |
39 | #define AB8500_GPADC_MUX_CTRL_REG 0x09 | |
e4bffe8d LJ |
40 | #define AB8540_GPADC_MANDATA2L_REG 0x09 |
41 | #define AB8540_GPADC_MANDATA2H_REG 0x0A | |
42 | #define AB8540_GPADC_APEAAX_REG 0x10 | |
43 | #define AB8540_GPADC_APEAAT_REG 0x11 | |
44 | #define AB8540_GPADC_APEAAM_REG 0x12 | |
45 | #define AB8540_GPADC_APEAAH_REG 0x13 | |
46 | #define AB8540_GPADC_APEAAL_REG 0x14 | |
dae2db30 | 47 | |
586f3318 JP |
48 | /* |
49 | * OTP register offsets | |
50 | * Bank : 0x15 | |
51 | */ | |
52 | #define AB8500_GPADC_CAL_1 0x0F | |
53 | #define AB8500_GPADC_CAL_2 0x10 | |
54 | #define AB8500_GPADC_CAL_3 0x11 | |
55 | #define AB8500_GPADC_CAL_4 0x12 | |
56 | #define AB8500_GPADC_CAL_5 0x13 | |
57 | #define AB8500_GPADC_CAL_6 0x14 | |
58 | #define AB8500_GPADC_CAL_7 0x15 | |
e4bffe8d LJ |
59 | /* New calibration for 8540 */ |
60 | #define AB8540_GPADC_OTP4_REG_7 0x38 | |
61 | #define AB8540_GPADC_OTP4_REG_6 0x39 | |
62 | #define AB8540_GPADC_OTP4_REG_5 0x3A | |
586f3318 | 63 | |
dae2db30 AM |
64 | /* gpadc constants */ |
65 | #define EN_VINTCORE12 0x04 | |
66 | #define EN_VTVOUT 0x02 | |
67 | #define EN_GPADC 0x01 | |
68 | #define DIS_GPADC 0x00 | |
73482346 LJ |
69 | #define AVG_1 0x00 |
70 | #define AVG_4 0x20 | |
71 | #define AVG_8 0x40 | |
72 | #define AVG_16 0x60 | |
dae2db30 | 73 | #define ADC_SW_CONV 0x04 |
4aad5a91 | 74 | #define EN_ICHAR 0x80 |
ed139416 | 75 | #define BTEMP_PULL_UP 0x08 |
dae2db30 AM |
76 | #define EN_BUF 0x40 |
77 | #define DIS_ZERO 0x00 | |
78 | #define GPADC_BUSY 0x01 | |
73482346 LJ |
79 | #define EN_FALLING 0x10 |
80 | #define EN_TRIG_EDGE 0x02 | |
e4bffe8d | 81 | #define EN_VBIAS_XTAL_TEMP 0x02 |
dae2db30 | 82 | |
586f3318 JP |
83 | /* GPADC constants from AB8500 spec, UM0836 */ |
84 | #define ADC_RESOLUTION 1024 | |
85 | #define ADC_CH_BTEMP_MIN 0 | |
86 | #define ADC_CH_BTEMP_MAX 1350 | |
87 | #define ADC_CH_DIETEMP_MIN 0 | |
88 | #define ADC_CH_DIETEMP_MAX 1350 | |
89 | #define ADC_CH_CHG_V_MIN 0 | |
90 | #define ADC_CH_CHG_V_MAX 20030 | |
91 | #define ADC_CH_ACCDET2_MIN 0 | |
92 | #define ADC_CH_ACCDET2_MAX 2500 | |
93 | #define ADC_CH_VBAT_MIN 2300 | |
94 | #define ADC_CH_VBAT_MAX 4800 | |
95 | #define ADC_CH_CHG_I_MIN 0 | |
96 | #define ADC_CH_CHG_I_MAX 1500 | |
97 | #define ADC_CH_BKBAT_MIN 0 | |
98 | #define ADC_CH_BKBAT_MAX 3200 | |
99 | ||
e4bffe8d LJ |
100 | /* GPADC constants from AB8540 spec */ |
101 | #define ADC_CH_IBAT_MIN (-6000) /* mA range measured by ADC for ibat*/ | |
102 | #define ADC_CH_IBAT_MAX 6000 | |
103 | #define ADC_CH_IBAT_MIN_V (-60) /* mV range measured by ADC for ibat*/ | |
104 | #define ADC_CH_IBAT_MAX_V 60 | |
105 | #define IBAT_VDROP_L (-56) /* mV */ | |
106 | #define IBAT_VDROP_H 56 | |
107 | ||
586f3318 | 108 | /* This is used to not lose precision when dividing to get gain and offset */ |
e4bffe8d LJ |
109 | #define CALIB_SCALE 1000 |
110 | /* | |
111 | * Number of bits shift used to not lose precision | |
112 | * when dividing to get ibat gain. | |
113 | */ | |
114 | #define CALIB_SHIFT_IBAT 20 | |
586f3318 | 115 | |
5f8aaef4 LJ |
116 | /* Time in ms before disabling regulator */ |
117 | #define GPADC_AUDOSUSPEND_DELAY 1 | |
118 | ||
f825ebe5 LJ |
119 | #define CONVERSION_TIME 500 /* ms */ |
120 | ||
586f3318 JP |
121 | enum cal_channels { |
122 | ADC_INPUT_VMAIN = 0, | |
123 | ADC_INPUT_BTEMP, | |
124 | ADC_INPUT_VBAT, | |
e4bffe8d | 125 | ADC_INPUT_IBAT, |
586f3318 JP |
126 | NBR_CAL_INPUTS, |
127 | }; | |
128 | ||
129 | /** | |
130 | * struct adc_cal_data - Table for storing gain and offset for the calibrated | |
131 | * ADC channels | |
132 | * @gain: Gain of the ADC channel | |
133 | * @offset: Offset of the ADC channel | |
134 | */ | |
135 | struct adc_cal_data { | |
e4bffe8d LJ |
136 | s64 gain; |
137 | s64 offset; | |
bc6b4132 LJ |
138 | u16 otp_calib_hi; |
139 | u16 otp_calib_lo; | |
586f3318 JP |
140 | }; |
141 | ||
dae2db30 | 142 | /** |
586f3318 | 143 | * struct ab8500_gpadc - AB8500 GPADC device information |
dae2db30 | 144 | * @dev: pointer to the struct device |
6321992c DW |
145 | * @node: a list of AB8500 GPADCs, hence prepared for |
146 | reentrance | |
20bf4283 | 147 | * @parent: pointer to the struct ab8500 |
dae2db30 AM |
148 | * @ab8500_gpadc_complete: pointer to the struct completion, to indicate |
149 | * the completion of gpadc conversion | |
150 | * @ab8500_gpadc_lock: structure of type mutex | |
151 | * @regu: pointer to the struct regulator | |
73482346 LJ |
152 | * @irq_sw: interrupt number that is used by gpadc for Sw |
153 | * conversion | |
154 | * @irq_hw: interrupt number that is used by gpadc for Hw | |
155 | * conversion | |
586f3318 | 156 | * @cal_data array of ADC calibration data structs |
dae2db30 | 157 | */ |
6321992c | 158 | struct ab8500_gpadc { |
dae2db30 | 159 | struct device *dev; |
6321992c | 160 | struct list_head node; |
20bf4283 | 161 | struct ab8500 *parent; |
dae2db30 AM |
162 | struct completion ab8500_gpadc_complete; |
163 | struct mutex ab8500_gpadc_lock; | |
164 | struct regulator *regu; | |
73482346 LJ |
165 | int irq_sw; |
166 | int irq_hw; | |
586f3318 | 167 | struct adc_cal_data cal_data[NBR_CAL_INPUTS]; |
6321992c DW |
168 | }; |
169 | ||
170 | static LIST_HEAD(ab8500_gpadc_list); | |
171 | ||
172 | /** | |
173 | * ab8500_gpadc_get() - returns a reference to the primary AB8500 GPADC | |
174 | * (i.e. the first GPADC in the instance list) | |
175 | */ | |
176 | struct ab8500_gpadc *ab8500_gpadc_get(char *name) | |
177 | { | |
178 | struct ab8500_gpadc *gpadc; | |
179 | ||
180 | list_for_each_entry(gpadc, &ab8500_gpadc_list, node) { | |
181 | if (!strcmp(name, dev_name(gpadc->dev))) | |
182 | return gpadc; | |
183 | } | |
184 | ||
185 | return ERR_PTR(-ENOENT); | |
186 | } | |
187 | EXPORT_SYMBOL(ab8500_gpadc_get); | |
dae2db30 | 188 | |
bd4a40b5 KK |
189 | /** |
190 | * ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage | |
191 | */ | |
192 | int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, u8 channel, | |
586f3318 JP |
193 | int ad_value) |
194 | { | |
195 | int res; | |
196 | ||
bd4a40b5 | 197 | switch (channel) { |
586f3318 JP |
198 | case MAIN_CHARGER_V: |
199 | /* For some reason we don't have calibrated data */ | |
200 | if (!gpadc->cal_data[ADC_INPUT_VMAIN].gain) { | |
201 | res = ADC_CH_CHG_V_MIN + (ADC_CH_CHG_V_MAX - | |
202 | ADC_CH_CHG_V_MIN) * ad_value / | |
203 | ADC_RESOLUTION; | |
204 | break; | |
205 | } | |
206 | /* Here we can use the calibrated data */ | |
207 | res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VMAIN].gain + | |
208 | gpadc->cal_data[ADC_INPUT_VMAIN].offset) / CALIB_SCALE; | |
209 | break; | |
210 | ||
e4bffe8d | 211 | case XTAL_TEMP: |
586f3318 JP |
212 | case BAT_CTRL: |
213 | case BTEMP_BALL: | |
214 | case ACC_DETECT1: | |
215 | case ADC_AUX1: | |
216 | case ADC_AUX2: | |
217 | /* For some reason we don't have calibrated data */ | |
218 | if (!gpadc->cal_data[ADC_INPUT_BTEMP].gain) { | |
219 | res = ADC_CH_BTEMP_MIN + (ADC_CH_BTEMP_MAX - | |
220 | ADC_CH_BTEMP_MIN) * ad_value / | |
221 | ADC_RESOLUTION; | |
222 | break; | |
223 | } | |
224 | /* Here we can use the calibrated data */ | |
225 | res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_BTEMP].gain + | |
226 | gpadc->cal_data[ADC_INPUT_BTEMP].offset) / CALIB_SCALE; | |
227 | break; | |
228 | ||
229 | case MAIN_BAT_V: | |
e4bffe8d | 230 | case VBAT_TRUE_MEAS: |
586f3318 JP |
231 | /* For some reason we don't have calibrated data */ |
232 | if (!gpadc->cal_data[ADC_INPUT_VBAT].gain) { | |
233 | res = ADC_CH_VBAT_MIN + (ADC_CH_VBAT_MAX - | |
234 | ADC_CH_VBAT_MIN) * ad_value / | |
235 | ADC_RESOLUTION; | |
236 | break; | |
237 | } | |
238 | /* Here we can use the calibrated data */ | |
239 | res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VBAT].gain + | |
240 | gpadc->cal_data[ADC_INPUT_VBAT].offset) / CALIB_SCALE; | |
241 | break; | |
242 | ||
243 | case DIE_TEMP: | |
244 | res = ADC_CH_DIETEMP_MIN + | |
245 | (ADC_CH_DIETEMP_MAX - ADC_CH_DIETEMP_MIN) * ad_value / | |
246 | ADC_RESOLUTION; | |
247 | break; | |
248 | ||
249 | case ACC_DETECT2: | |
250 | res = ADC_CH_ACCDET2_MIN + | |
251 | (ADC_CH_ACCDET2_MAX - ADC_CH_ACCDET2_MIN) * ad_value / | |
252 | ADC_RESOLUTION; | |
253 | break; | |
254 | ||
255 | case VBUS_V: | |
256 | res = ADC_CH_CHG_V_MIN + | |
257 | (ADC_CH_CHG_V_MAX - ADC_CH_CHG_V_MIN) * ad_value / | |
258 | ADC_RESOLUTION; | |
259 | break; | |
260 | ||
261 | case MAIN_CHARGER_C: | |
262 | case USB_CHARGER_C: | |
263 | res = ADC_CH_CHG_I_MIN + | |
264 | (ADC_CH_CHG_I_MAX - ADC_CH_CHG_I_MIN) * ad_value / | |
265 | ADC_RESOLUTION; | |
266 | break; | |
267 | ||
268 | case BK_BAT_V: | |
269 | res = ADC_CH_BKBAT_MIN + | |
270 | (ADC_CH_BKBAT_MAX - ADC_CH_BKBAT_MIN) * ad_value / | |
271 | ADC_RESOLUTION; | |
272 | break; | |
273 | ||
e4bffe8d LJ |
274 | case IBAT_VIRTUAL_CHANNEL: |
275 | /* For some reason we don't have calibrated data */ | |
276 | if (!gpadc->cal_data[ADC_INPUT_IBAT].gain) { | |
277 | res = ADC_CH_IBAT_MIN + (ADC_CH_IBAT_MAX - | |
278 | ADC_CH_IBAT_MIN) * ad_value / | |
279 | ADC_RESOLUTION; | |
280 | break; | |
281 | } | |
282 | /* Here we can use the calibrated data */ | |
283 | res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_IBAT].gain + | |
284 | gpadc->cal_data[ADC_INPUT_IBAT].offset) | |
285 | >> CALIB_SHIFT_IBAT; | |
286 | break; | |
287 | ||
586f3318 JP |
288 | default: |
289 | dev_err(gpadc->dev, | |
290 | "unknown channel, not possible to convert\n"); | |
291 | res = -EINVAL; | |
292 | break; | |
293 | ||
294 | } | |
295 | return res; | |
296 | } | |
bd4a40b5 | 297 | EXPORT_SYMBOL(ab8500_gpadc_ad_to_voltage); |
586f3318 | 298 | |
dae2db30 | 299 | /** |
73482346 | 300 | * ab8500_gpadc_sw_hw_convert() - gpadc conversion |
bd4a40b5 | 301 | * @channel: analog channel to be converted to digital data |
73482346 LJ |
302 | * @avg_sample: number of ADC sample to average |
303 | * @trig_egde: selected ADC trig edge | |
304 | * @trig_timer: selected ADC trigger delay timer | |
305 | * @conv_type: selected conversion type (HW or SW conversion) | |
dae2db30 AM |
306 | * |
307 | * This function converts the selected analog i/p to digital | |
586f3318 | 308 | * data. |
dae2db30 | 309 | */ |
73482346 LJ |
310 | int ab8500_gpadc_sw_hw_convert(struct ab8500_gpadc *gpadc, u8 channel, |
311 | u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type) | |
bd4a40b5 KK |
312 | { |
313 | int ad_value; | |
314 | int voltage; | |
315 | ||
73482346 LJ |
316 | ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample, |
317 | trig_edge, trig_timer, conv_type); | |
318 | /* On failure retry a second time */ | |
d89cc5aa | 319 | if (ad_value < 0) |
73482346 LJ |
320 | ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample, |
321 | trig_edge, trig_timer, conv_type); | |
322 | if (ad_value < 0) { | |
323 | dev_err(gpadc->dev, "GPADC raw value failed ch: %d\n", | |
324 | channel); | |
bd4a40b5 KK |
325 | return ad_value; |
326 | } | |
327 | ||
328 | voltage = ab8500_gpadc_ad_to_voltage(gpadc, channel, ad_value); | |
bd4a40b5 KK |
329 | if (voltage < 0) |
330 | dev_err(gpadc->dev, "GPADC to voltage conversion failed ch:" | |
331 | " %d AD: 0x%x\n", channel, ad_value); | |
332 | ||
333 | return voltage; | |
334 | } | |
335 | EXPORT_SYMBOL(ab8500_gpadc_convert); | |
336 | ||
337 | /** | |
338 | * ab8500_gpadc_read_raw() - gpadc read | |
339 | * @channel: analog channel to be read | |
73482346 LJ |
340 | * @avg_sample: number of ADC sample to average |
341 | * @trig_edge: selected trig edge | |
342 | * @trig_timer: selected ADC trigger delay timer | |
343 | * @conv_type: selected conversion type (HW or SW conversion) | |
bd4a40b5 | 344 | * |
73482346 LJ |
345 | * This function obtains the raw ADC value for an hardware conversion, |
346 | * this then needs to be converted by calling ab8500_gpadc_ad_to_voltage() | |
bd4a40b5 | 347 | */ |
73482346 LJ |
348 | int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel, |
349 | u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type) | |
e4bffe8d LJ |
350 | { |
351 | int raw_data; | |
352 | raw_data = ab8500_gpadc_double_read_raw(gpadc, channel, | |
353 | avg_sample, trig_edge, trig_timer, conv_type, NULL); | |
354 | return raw_data; | |
355 | } | |
356 | ||
357 | int ab8500_gpadc_double_read_raw(struct ab8500_gpadc *gpadc, u8 channel, | |
358 | u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type, | |
359 | int *ibat) | |
dae2db30 AM |
360 | { |
361 | int ret; | |
dae2db30 | 362 | int looplimit = 0; |
e4bffe8d | 363 | u8 val, low_data, high_data, low_data2, high_data2; |
dae2db30 | 364 | |
6321992c | 365 | if (!gpadc) |
dae2db30 AM |
366 | return -ENODEV; |
367 | ||
c0eda9ae LJ |
368 | /* check if convertion is supported */ |
369 | if ((gpadc->irq_sw < 0) && (conv_type == ADC_SW)) | |
370 | return -ENOTSUPP; | |
371 | if ((gpadc->irq_hw < 0) && (conv_type == ADC_HW)) | |
372 | return -ENOTSUPP; | |
373 | ||
6321992c | 374 | mutex_lock(&gpadc->ab8500_gpadc_lock); |
dae2db30 | 375 | /* Enable VTVout LDO this is required for GPADC */ |
5f8aaef4 | 376 | pm_runtime_get_sync(gpadc->dev); |
dae2db30 AM |
377 | |
378 | /* Check if ADC is not busy, lock and proceed */ | |
379 | do { | |
6321992c DW |
380 | ret = abx500_get_register_interruptible(gpadc->dev, |
381 | AB8500_GPADC, AB8500_GPADC_STAT_REG, &val); | |
dae2db30 AM |
382 | if (ret < 0) |
383 | goto out; | |
384 | if (!(val & GPADC_BUSY)) | |
385 | break; | |
386 | msleep(10); | |
387 | } while (++looplimit < 10); | |
388 | if (looplimit >= 10 && (val & GPADC_BUSY)) { | |
6321992c | 389 | dev_err(gpadc->dev, "gpadc_conversion: GPADC busy"); |
dae2db30 AM |
390 | ret = -EINVAL; |
391 | goto out; | |
392 | } | |
393 | ||
394 | /* Enable GPADC */ | |
6321992c DW |
395 | ret = abx500_mask_and_set_register_interruptible(gpadc->dev, |
396 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, EN_GPADC, EN_GPADC); | |
dae2db30 | 397 | if (ret < 0) { |
6321992c | 398 | dev_err(gpadc->dev, "gpadc_conversion: enable gpadc failed\n"); |
dae2db30 AM |
399 | goto out; |
400 | } | |
c9c9513f | 401 | |
73482346 LJ |
402 | /* Select the channel source and set average samples */ |
403 | switch (avg_sample) { | |
404 | case SAMPLE_1: | |
405 | val = channel | AVG_1; | |
406 | break; | |
407 | case SAMPLE_4: | |
408 | val = channel | AVG_4; | |
409 | break; | |
410 | case SAMPLE_8: | |
411 | val = channel | AVG_8; | |
412 | break; | |
413 | default: | |
414 | val = channel | AVG_16; | |
415 | break; | |
73482346 LJ |
416 | } |
417 | ||
418 | if (conv_type == ADC_HW) | |
419 | ret = abx500_set_register_interruptible(gpadc->dev, | |
420 | AB8500_GPADC, AB8500_GPADC_CTRL3_REG, val); | |
421 | else | |
422 | ret = abx500_set_register_interruptible(gpadc->dev, | |
423 | AB8500_GPADC, AB8500_GPADC_CTRL2_REG, val); | |
dae2db30 | 424 | if (ret < 0) { |
6321992c | 425 | dev_err(gpadc->dev, |
dae2db30 AM |
426 | "gpadc_conversion: set avg samples failed\n"); |
427 | goto out; | |
428 | } | |
c9c9513f | 429 | |
4aad5a91 KK |
430 | /* |
431 | * Enable ADC, buffering, select rising edge and enable ADC path | |
c9c9513f KK |
432 | * charging current sense if it needed, ABB 3.0 needs some special |
433 | * treatment too. | |
4aad5a91 | 434 | */ |
73482346 LJ |
435 | if ((conv_type == ADC_HW) && (trig_edge)) { |
436 | ret = abx500_mask_and_set_register_interruptible(gpadc->dev, | |
437 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
438 | EN_FALLING, EN_FALLING); | |
73482346 | 439 | } |
e4bffe8d | 440 | |
bd4a40b5 | 441 | switch (channel) { |
4aad5a91 KK |
442 | case MAIN_CHARGER_C: |
443 | case USB_CHARGER_C: | |
73482346 | 444 | if (conv_type == ADC_HW) |
c9c9513f KK |
445 | ret = abx500_mask_and_set_register_interruptible( |
446 | gpadc->dev, | |
447 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
73482346 LJ |
448 | EN_BUF | EN_ICHAR | EN_TRIG_EDGE, |
449 | EN_BUF | EN_ICHAR | EN_TRIG_EDGE); | |
450 | else | |
451 | ret = abx500_mask_and_set_register_interruptible( | |
452 | gpadc->dev, | |
453 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
454 | EN_BUF | EN_ICHAR, | |
455 | EN_BUF | EN_ICHAR); | |
456 | break; | |
e4bffe8d LJ |
457 | |
458 | case XTAL_TEMP: | |
459 | if (conv_type == ADC_HW) | |
460 | ret = abx500_mask_and_set_register_interruptible( | |
461 | gpadc->dev, | |
462 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
463 | EN_BUF | EN_TRIG_EDGE, | |
464 | EN_BUF | EN_TRIG_EDGE); | |
465 | else | |
466 | ret = abx500_mask_and_set_register_interruptible( | |
467 | gpadc->dev, | |
468 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
469 | EN_BUF , | |
470 | EN_BUF); | |
471 | break; | |
472 | ||
473 | case VBAT_TRUE_MEAS: | |
474 | if (conv_type == ADC_HW) | |
475 | ret = abx500_mask_and_set_register_interruptible( | |
476 | gpadc->dev, | |
477 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
478 | EN_BUF | EN_TRIG_EDGE, | |
479 | EN_BUF | EN_TRIG_EDGE); | |
480 | else | |
481 | ret = abx500_mask_and_set_register_interruptible( | |
482 | gpadc->dev, | |
483 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
484 | EN_BUF , | |
485 | EN_BUF); | |
486 | break; | |
487 | ||
488 | case BAT_CTRL_AND_IBAT: | |
489 | case VBAT_MEAS_AND_IBAT: | |
490 | case VBAT_TRUE_MEAS_AND_IBAT: | |
491 | case BAT_TEMP_AND_IBAT: | |
492 | if (conv_type == ADC_HW) | |
493 | ret = abx500_mask_and_set_register_interruptible( | |
494 | gpadc->dev, | |
495 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
496 | EN_TRIG_EDGE, | |
497 | EN_TRIG_EDGE); | |
498 | else | |
499 | ret = abx500_mask_and_set_register_interruptible( | |
500 | gpadc->dev, | |
501 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
502 | EN_BUF, | |
503 | 0); | |
504 | break; | |
505 | ||
73482346 LJ |
506 | case BTEMP_BALL: |
507 | if (!is_ab8500_2p0_or_earlier(gpadc->parent)) { | |
508 | if (conv_type == ADC_HW) | |
509 | /* Turn on btemp pull-up on ABB 3.0 */ | |
510 | ret = abx500_mask_and_set_register_interruptible | |
511 | (gpadc->dev, | |
512 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
513 | EN_BUF | BTEMP_PULL_UP | EN_TRIG_EDGE, | |
514 | EN_BUF | BTEMP_PULL_UP | EN_TRIG_EDGE); | |
515 | else | |
516 | ret = abx500_mask_and_set_register_interruptible | |
517 | (gpadc->dev, | |
518 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
519 | EN_BUF | BTEMP_PULL_UP, | |
520 | EN_BUF | BTEMP_PULL_UP); | |
c9c9513f KK |
521 | |
522 | /* | |
523 | * Delay might be needed for ABB8500 cut 3.0, if not, remove | |
5a4432b9 | 524 | * when hardware will be available |
c9c9513f | 525 | */ |
d0b32fa1 | 526 | usleep_range(1000, 1000); |
c9c9513f KK |
527 | break; |
528 | } | |
529 | /* Intentional fallthrough */ | |
4aad5a91 | 530 | default: |
73482346 LJ |
531 | if (conv_type == ADC_HW) |
532 | ret = abx500_mask_and_set_register_interruptible( | |
533 | gpadc->dev, | |
534 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
535 | EN_BUF | EN_TRIG_EDGE, | |
536 | EN_BUF | EN_TRIG_EDGE); | |
537 | else | |
538 | ret = abx500_mask_and_set_register_interruptible( | |
539 | gpadc->dev, | |
540 | AB8500_GPADC, | |
541 | AB8500_GPADC_CTRL1_REG, EN_BUF, EN_BUF); | |
4aad5a91 KK |
542 | break; |
543 | } | |
dae2db30 | 544 | if (ret < 0) { |
6321992c | 545 | dev_err(gpadc->dev, |
dae2db30 AM |
546 | "gpadc_conversion: select falling edge failed\n"); |
547 | goto out; | |
548 | } | |
c9c9513f | 549 | |
73482346 LJ |
550 | /* Set trigger delay timer */ |
551 | if (conv_type == ADC_HW) { | |
552 | ret = abx500_set_register_interruptible(gpadc->dev, | |
553 | AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG, trig_timer); | |
554 | if (ret < 0) { | |
555 | dev_err(gpadc->dev, | |
556 | "gpadc_conversion: trig timer failed\n"); | |
557 | goto out; | |
558 | } | |
559 | } | |
560 | ||
561 | /* Start SW conversion */ | |
562 | if (conv_type == ADC_SW) { | |
563 | ret = abx500_mask_and_set_register_interruptible(gpadc->dev, | |
564 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
565 | ADC_SW_CONV, ADC_SW_CONV); | |
566 | if (ret < 0) { | |
567 | dev_err(gpadc->dev, | |
568 | "gpadc_conversion: start s/w conv failed\n"); | |
569 | goto out; | |
570 | } | |
dae2db30 | 571 | } |
73482346 | 572 | |
dae2db30 | 573 | /* wait for completion of conversion */ |
73482346 LJ |
574 | if (conv_type == ADC_HW) { |
575 | if (!wait_for_completion_timeout(&gpadc->ab8500_gpadc_complete, | |
e4bffe8d LJ |
576 | 2 * HZ)) { |
577 | dev_err(gpadc->dev, | |
578 | "timeout didn't receive hw GPADC conv interrupt\n"); | |
579 | ret = -EINVAL; | |
580 | goto out; | |
73482346 LJ |
581 | } |
582 | } else { | |
583 | if (!wait_for_completion_timeout(&gpadc->ab8500_gpadc_complete, | |
e4bffe8d LJ |
584 | msecs_to_jiffies(CONVERSION_TIME))) { |
585 | dev_err(gpadc->dev, | |
586 | "timeout didn't receive sw GPADC conv interrupt\n"); | |
587 | ret = -EINVAL; | |
588 | goto out; | |
73482346 | 589 | } |
dae2db30 AM |
590 | } |
591 | ||
592 | /* Read the converted RAW data */ | |
73482346 LJ |
593 | if (conv_type == ADC_HW) { |
594 | ret = abx500_get_register_interruptible(gpadc->dev, | |
595 | AB8500_GPADC, AB8500_GPADC_AUTODATAL_REG, &low_data); | |
596 | if (ret < 0) { | |
597 | dev_err(gpadc->dev, | |
598 | "gpadc_conversion: read hw low data failed\n"); | |
599 | goto out; | |
600 | } | |
dae2db30 | 601 | |
73482346 LJ |
602 | ret = abx500_get_register_interruptible(gpadc->dev, |
603 | AB8500_GPADC, AB8500_GPADC_AUTODATAH_REG, &high_data); | |
604 | if (ret < 0) { | |
605 | dev_err(gpadc->dev, | |
606 | "gpadc_conversion: read hw high data failed\n"); | |
607 | goto out; | |
608 | } | |
609 | } else { | |
610 | ret = abx500_get_register_interruptible(gpadc->dev, | |
611 | AB8500_GPADC, AB8500_GPADC_MANDATAL_REG, &low_data); | |
612 | if (ret < 0) { | |
613 | dev_err(gpadc->dev, | |
614 | "gpadc_conversion: read sw low data failed\n"); | |
615 | goto out; | |
616 | } | |
617 | ||
618 | ret = abx500_get_register_interruptible(gpadc->dev, | |
619 | AB8500_GPADC, AB8500_GPADC_MANDATAH_REG, &high_data); | |
620 | if (ret < 0) { | |
621 | dev_err(gpadc->dev, | |
622 | "gpadc_conversion: read sw high data failed\n"); | |
623 | goto out; | |
624 | } | |
dae2db30 | 625 | } |
e4bffe8d LJ |
626 | /* Check if double convertion is required */ |
627 | if ((channel == BAT_CTRL_AND_IBAT) || | |
628 | (channel == VBAT_MEAS_AND_IBAT) || | |
629 | (channel == VBAT_TRUE_MEAS_AND_IBAT) || | |
630 | (channel == BAT_TEMP_AND_IBAT)) { | |
631 | ||
632 | if (conv_type == ADC_HW) { | |
633 | /* not supported */ | |
634 | ret = -ENOTSUPP; | |
635 | dev_err(gpadc->dev, | |
636 | "gpadc_conversion: only SW double conversion supported\n"); | |
637 | goto out; | |
638 | } else { | |
639 | /* Read the converted RAW data 2 */ | |
640 | ret = abx500_get_register_interruptible(gpadc->dev, | |
641 | AB8500_GPADC, AB8540_GPADC_MANDATA2L_REG, | |
642 | &low_data2); | |
643 | if (ret < 0) { | |
644 | dev_err(gpadc->dev, | |
645 | "gpadc_conversion: read sw low data 2 failed\n"); | |
646 | goto out; | |
647 | } | |
648 | ||
649 | ret = abx500_get_register_interruptible(gpadc->dev, | |
650 | AB8500_GPADC, AB8540_GPADC_MANDATA2H_REG, | |
651 | &high_data2); | |
652 | if (ret < 0) { | |
653 | dev_err(gpadc->dev, | |
654 | "gpadc_conversion: read sw high data 2 failed\n"); | |
655 | goto out; | |
656 | } | |
657 | if (ibat != NULL) { | |
658 | *ibat = (high_data2 << 8) | low_data2; | |
659 | } else { | |
660 | dev_warn(gpadc->dev, | |
661 | "gpadc_conversion: ibat not stored\n"); | |
662 | } | |
663 | ||
664 | } | |
665 | } | |
dae2db30 | 666 | |
dae2db30 | 667 | /* Disable GPADC */ |
6321992c | 668 | ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC, |
dae2db30 AM |
669 | AB8500_GPADC_CTRL1_REG, DIS_GPADC); |
670 | if (ret < 0) { | |
6321992c | 671 | dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n"); |
dae2db30 AM |
672 | goto out; |
673 | } | |
5f8aaef4 | 674 | |
73482346 | 675 | /* Disable VTVout LDO this is required for GPADC */ |
5f8aaef4 LJ |
676 | pm_runtime_mark_last_busy(gpadc->dev); |
677 | pm_runtime_put_autosuspend(gpadc->dev); | |
678 | ||
6321992c | 679 | mutex_unlock(&gpadc->ab8500_gpadc_lock); |
bd4a40b5 KK |
680 | |
681 | return (high_data << 8) | low_data; | |
dae2db30 AM |
682 | |
683 | out: | |
684 | /* | |
685 | * It has shown to be needed to turn off the GPADC if an error occurs, | |
686 | * otherwise we might have problem when waiting for the busy bit in the | |
687 | * GPADC status register to go low. In V1.1 there wait_for_completion | |
688 | * seems to timeout when waiting for an interrupt.. Not seen in V2.0 | |
689 | */ | |
6321992c | 690 | (void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC, |
dae2db30 | 691 | AB8500_GPADC_CTRL1_REG, DIS_GPADC); |
5f8aaef4 | 692 | pm_runtime_put(gpadc->dev); |
6321992c DW |
693 | mutex_unlock(&gpadc->ab8500_gpadc_lock); |
694 | dev_err(gpadc->dev, | |
bd4a40b5 | 695 | "gpadc_conversion: Failed to AD convert channel %d\n", channel); |
dae2db30 AM |
696 | return ret; |
697 | } | |
bd4a40b5 | 698 | EXPORT_SYMBOL(ab8500_gpadc_read_raw); |
dae2db30 AM |
699 | |
700 | /** | |
73482346 | 701 | * ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion |
dae2db30 AM |
702 | * @irq: irq number |
703 | * @data: pointer to the data passed during request irq | |
704 | * | |
73482346 | 705 | * This is a interrupt service routine for gpadc conversion completion. |
dae2db30 AM |
706 | * Notifies the gpadc completion is completed and the converted raw value |
707 | * can be read from the registers. | |
708 | * Returns IRQ status(IRQ_HANDLED) | |
709 | */ | |
73482346 | 710 | static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *_gpadc) |
dae2db30 | 711 | { |
6321992c | 712 | struct ab8500_gpadc *gpadc = _gpadc; |
dae2db30 AM |
713 | |
714 | complete(&gpadc->ab8500_gpadc_complete); | |
715 | ||
716 | return IRQ_HANDLED; | |
717 | } | |
718 | ||
586f3318 JP |
719 | static int otp_cal_regs[] = { |
720 | AB8500_GPADC_CAL_1, | |
721 | AB8500_GPADC_CAL_2, | |
722 | AB8500_GPADC_CAL_3, | |
723 | AB8500_GPADC_CAL_4, | |
724 | AB8500_GPADC_CAL_5, | |
725 | AB8500_GPADC_CAL_6, | |
726 | AB8500_GPADC_CAL_7, | |
727 | }; | |
728 | ||
e4bffe8d LJ |
729 | static int otp4_cal_regs[] = { |
730 | AB8540_GPADC_OTP4_REG_7, | |
731 | AB8540_GPADC_OTP4_REG_6, | |
732 | AB8540_GPADC_OTP4_REG_5, | |
733 | }; | |
734 | ||
586f3318 JP |
735 | static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc) |
736 | { | |
737 | int i; | |
738 | int ret[ARRAY_SIZE(otp_cal_regs)]; | |
739 | u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)]; | |
e4bffe8d LJ |
740 | int ret_otp4[ARRAY_SIZE(otp4_cal_regs)]; |
741 | u8 gpadc_otp4[ARRAY_SIZE(otp4_cal_regs)]; | |
586f3318 JP |
742 | int vmain_high, vmain_low; |
743 | int btemp_high, btemp_low; | |
744 | int vbat_high, vbat_low; | |
e4bffe8d LJ |
745 | int ibat_high, ibat_low; |
746 | s64 V_gain, V_offset, V2A_gain, V2A_offset; | |
747 | struct ab8500 *ab8500; | |
748 | ||
749 | ab8500 = gpadc->parent; | |
586f3318 JP |
750 | |
751 | /* First we read all OTP registers and store the error code */ | |
752 | for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) { | |
753 | ret[i] = abx500_get_register_interruptible(gpadc->dev, | |
754 | AB8500_OTP_EMUL, otp_cal_regs[i], &gpadc_cal[i]); | |
755 | if (ret[i] < 0) | |
756 | dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n", | |
757 | __func__, otp_cal_regs[i]); | |
758 | } | |
759 | ||
760 | /* | |
761 | * The ADC calibration data is stored in OTP registers. | |
762 | * The layout of the calibration data is outlined below and a more | |
763 | * detailed description can be found in UM0836 | |
764 | * | |
765 | * vm_h/l = vmain_high/low | |
766 | * bt_h/l = btemp_high/low | |
767 | * vb_h/l = vbat_high/low | |
768 | * | |
e4bffe8d | 769 | * Data bits 8500/9540: |
586f3318 JP |
770 | * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
771 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
772 | * | | vm_h9 | vm_h8 | |
773 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
774 | * | | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2 | |
775 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
776 | * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9 | |
777 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
778 | * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1 | |
779 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
780 | * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8 | |
781 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
782 | * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0 | |
783 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
784 | * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 | | |
785 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
786 | * | |
e4bffe8d LJ |
787 | * Data bits 8540: |
788 | * OTP2 | |
789 | * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
790 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
791 | * | | |
792 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
793 | * | vm_h9 | vm_h8 | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2 | |
794 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
795 | * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9 | |
796 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
797 | * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1 | |
798 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
799 | * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8 | |
800 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
801 | * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0 | |
802 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
803 | * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 | | |
804 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
805 | * | |
806 | * Data bits 8540: | |
807 | * OTP4 | |
808 | * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
809 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
810 | * | | ib_h9 | ib_h8 | ib_h7 | |
811 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
812 | * | ib_h6 | ib_h5 | ib_h4 | ib_h3 | ib_h2 | ib_h1 | ib_h0 | ib_l5 | |
813 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
814 | * | ib_l4 | ib_l3 | ib_l2 | ib_l1 | ib_l0 | | |
815 | * | |
586f3318 JP |
816 | * |
817 | * Ideal output ADC codes corresponding to injected input voltages | |
818 | * during manufacturing is: | |
819 | * | |
820 | * vmain_high: Vin = 19500mV / ADC ideal code = 997 | |
821 | * vmain_low: Vin = 315mV / ADC ideal code = 16 | |
822 | * btemp_high: Vin = 1300mV / ADC ideal code = 985 | |
823 | * btemp_low: Vin = 21mV / ADC ideal code = 16 | |
824 | * vbat_high: Vin = 4700mV / ADC ideal code = 982 | |
825 | * vbat_low: Vin = 2380mV / ADC ideal code = 33 | |
826 | */ | |
827 | ||
e4bffe8d LJ |
828 | if (is_ab8540(ab8500)) { |
829 | /* Calculate gain and offset for VMAIN if all reads succeeded*/ | |
830 | if (!(ret[1] < 0 || ret[2] < 0)) { | |
831 | vmain_high = (((gpadc_cal[1] & 0xFF) << 2) | | |
832 | ((gpadc_cal[2] & 0xC0) >> 6)); | |
833 | vmain_low = ((gpadc_cal[2] & 0x3E) >> 1); | |
bc6b4132 LJ |
834 | |
835 | gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi = | |
836 | (u16)vmain_high; | |
837 | gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo = | |
838 | (u16)vmain_low; | |
839 | ||
e4bffe8d LJ |
840 | gpadc->cal_data[ADC_INPUT_VMAIN].gain = CALIB_SCALE * |
841 | (19500 - 315) / (vmain_high - vmain_low); | |
842 | gpadc->cal_data[ADC_INPUT_VMAIN].offset = CALIB_SCALE * | |
843 | 19500 - (CALIB_SCALE * (19500 - 315) / | |
844 | (vmain_high - vmain_low)) * vmain_high; | |
845 | } else { | |
846 | gpadc->cal_data[ADC_INPUT_VMAIN].gain = 0; | |
847 | } | |
586f3318 | 848 | |
e4bffe8d LJ |
849 | /* Read IBAT calibration Data */ |
850 | for (i = 0; i < ARRAY_SIZE(otp4_cal_regs); i++) { | |
851 | ret_otp4[i] = abx500_get_register_interruptible( | |
852 | gpadc->dev, AB8500_OTP_EMUL, | |
853 | otp4_cal_regs[i], &gpadc_otp4[i]); | |
854 | if (ret_otp4[i] < 0) | |
855 | dev_err(gpadc->dev, | |
856 | "%s: read otp4 reg 0x%02x failed\n", | |
857 | __func__, otp4_cal_regs[i]); | |
858 | } | |
586f3318 | 859 | |
e4bffe8d LJ |
860 | /* Calculate gain and offset for IBAT if all reads succeeded */ |
861 | if (!(ret_otp4[0] < 0 || ret_otp4[1] < 0 || ret_otp4[2] < 0)) { | |
862 | ibat_high = (((gpadc_otp4[0] & 0x07) << 7) | | |
863 | ((gpadc_otp4[1] & 0xFE) >> 1)); | |
864 | ibat_low = (((gpadc_otp4[1] & 0x01) << 5) | | |
865 | ((gpadc_otp4[2] & 0xF8) >> 3)); | |
866 | ||
bc6b4132 LJ |
867 | gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_hi = |
868 | (u16)ibat_high; | |
869 | gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_lo = | |
870 | (u16)ibat_low; | |
871 | ||
e4bffe8d LJ |
872 | V_gain = ((IBAT_VDROP_H - IBAT_VDROP_L) |
873 | << CALIB_SHIFT_IBAT) / (ibat_high - ibat_low); | |
874 | ||
875 | V_offset = (IBAT_VDROP_H << CALIB_SHIFT_IBAT) - | |
876 | (((IBAT_VDROP_H - IBAT_VDROP_L) << | |
877 | CALIB_SHIFT_IBAT) / (ibat_high - ibat_low)) | |
878 | * ibat_high; | |
879 | /* | |
880 | * Result obtained is in mV (at a scale factor), | |
881 | * we need to calculate gain and offset to get mA | |
882 | */ | |
883 | V2A_gain = (ADC_CH_IBAT_MAX - ADC_CH_IBAT_MIN)/ | |
884 | (ADC_CH_IBAT_MAX_V - ADC_CH_IBAT_MIN_V); | |
885 | V2A_offset = ((ADC_CH_IBAT_MAX_V * ADC_CH_IBAT_MIN - | |
886 | ADC_CH_IBAT_MAX * ADC_CH_IBAT_MIN_V) | |
887 | << CALIB_SHIFT_IBAT) | |
888 | / (ADC_CH_IBAT_MAX_V - ADC_CH_IBAT_MIN_V); | |
889 | ||
890 | gpadc->cal_data[ADC_INPUT_IBAT].gain = V_gain * V2A_gain; | |
891 | gpadc->cal_data[ADC_INPUT_IBAT].offset = V_offset * | |
892 | V2A_gain + V2A_offset; | |
893 | } else { | |
894 | gpadc->cal_data[ADC_INPUT_IBAT].gain = 0; | |
895 | } | |
586f3318 | 896 | |
e4bffe8d LJ |
897 | dev_dbg(gpadc->dev, "IBAT gain %llu offset %llu\n", |
898 | gpadc->cal_data[ADC_INPUT_IBAT].gain, | |
899 | gpadc->cal_data[ADC_INPUT_IBAT].offset); | |
586f3318 | 900 | } else { |
e4bffe8d LJ |
901 | /* Calculate gain and offset for VMAIN if all reads succeeded */ |
902 | if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) { | |
903 | vmain_high = (((gpadc_cal[0] & 0x03) << 8) | | |
904 | ((gpadc_cal[1] & 0x3F) << 2) | | |
905 | ((gpadc_cal[2] & 0xC0) >> 6)); | |
906 | vmain_low = ((gpadc_cal[2] & 0x3E) >> 1); | |
907 | ||
bc6b4132 LJ |
908 | gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi = |
909 | (u16)vmain_high; | |
910 | gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo = | |
911 | (u16)vmain_low; | |
912 | ||
e4bffe8d LJ |
913 | gpadc->cal_data[ADC_INPUT_VMAIN].gain = CALIB_SCALE * |
914 | (19500 - 315) / (vmain_high - vmain_low); | |
915 | ||
916 | gpadc->cal_data[ADC_INPUT_VMAIN].offset = CALIB_SCALE * | |
917 | 19500 - (CALIB_SCALE * (19500 - 315) / | |
918 | (vmain_high - vmain_low)) * vmain_high; | |
919 | } else { | |
920 | gpadc->cal_data[ADC_INPUT_VMAIN].gain = 0; | |
921 | } | |
586f3318 | 922 | } |
bc6b4132 | 923 | |
586f3318 JP |
924 | /* Calculate gain and offset for BTEMP if all reads succeeded */ |
925 | if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) { | |
926 | btemp_high = (((gpadc_cal[2] & 0x01) << 9) | | |
e4bffe8d | 927 | (gpadc_cal[3] << 1) | ((gpadc_cal[4] & 0x80) >> 7)); |
586f3318 JP |
928 | btemp_low = ((gpadc_cal[4] & 0x7C) >> 2); |
929 | ||
bc6b4132 LJ |
930 | gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_hi = (u16)btemp_high; |
931 | gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_lo = (u16)btemp_low; | |
932 | ||
586f3318 JP |
933 | gpadc->cal_data[ADC_INPUT_BTEMP].gain = |
934 | CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low); | |
586f3318 | 935 | gpadc->cal_data[ADC_INPUT_BTEMP].offset = CALIB_SCALE * 1300 - |
e4bffe8d LJ |
936 | (CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low)) |
937 | * btemp_high; | |
586f3318 JP |
938 | } else { |
939 | gpadc->cal_data[ADC_INPUT_BTEMP].gain = 0; | |
940 | } | |
941 | ||
942 | /* Calculate gain and offset for VBAT if all reads succeeded */ | |
943 | if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) { | |
944 | vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]); | |
945 | vbat_low = ((gpadc_cal[6] & 0xFC) >> 2); | |
946 | ||
bc6b4132 LJ |
947 | gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_hi = (u16)vbat_high; |
948 | gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_lo = (u16)vbat_low; | |
949 | ||
586f3318 JP |
950 | gpadc->cal_data[ADC_INPUT_VBAT].gain = CALIB_SCALE * |
951 | (4700 - 2380) / (vbat_high - vbat_low); | |
586f3318 JP |
952 | gpadc->cal_data[ADC_INPUT_VBAT].offset = CALIB_SCALE * 4700 - |
953 | (CALIB_SCALE * (4700 - 2380) / | |
954 | (vbat_high - vbat_low)) * vbat_high; | |
955 | } else { | |
956 | gpadc->cal_data[ADC_INPUT_VBAT].gain = 0; | |
957 | } | |
958 | ||
959 | dev_dbg(gpadc->dev, "VMAIN gain %llu offset %llu\n", | |
960 | gpadc->cal_data[ADC_INPUT_VMAIN].gain, | |
961 | gpadc->cal_data[ADC_INPUT_VMAIN].offset); | |
962 | ||
963 | dev_dbg(gpadc->dev, "BTEMP gain %llu offset %llu\n", | |
964 | gpadc->cal_data[ADC_INPUT_BTEMP].gain, | |
965 | gpadc->cal_data[ADC_INPUT_BTEMP].offset); | |
966 | ||
967 | dev_dbg(gpadc->dev, "VBAT gain %llu offset %llu\n", | |
968 | gpadc->cal_data[ADC_INPUT_VBAT].gain, | |
969 | gpadc->cal_data[ADC_INPUT_VBAT].offset); | |
970 | } | |
971 | ||
5f8aaef4 LJ |
972 | static int ab8500_gpadc_runtime_suspend(struct device *dev) |
973 | { | |
974 | struct ab8500_gpadc *gpadc = dev_get_drvdata(dev); | |
975 | ||
976 | regulator_disable(gpadc->regu); | |
977 | return 0; | |
978 | } | |
979 | ||
980 | static int ab8500_gpadc_runtime_resume(struct device *dev) | |
981 | { | |
982 | struct ab8500_gpadc *gpadc = dev_get_drvdata(dev); | |
983 | ||
984 | regulator_enable(gpadc->regu); | |
985 | return 0; | |
986 | } | |
987 | ||
988 | static int ab8500_gpadc_runtime_idle(struct device *dev) | |
989 | { | |
5f8aaef4 LJ |
990 | pm_runtime_suspend(dev); |
991 | return 0; | |
992 | } | |
993 | ||
774c50ab DW |
994 | static int ab8500_gpadc_suspend(struct device *dev) |
995 | { | |
996 | struct ab8500_gpadc *gpadc = dev_get_drvdata(dev); | |
997 | ||
998 | mutex_lock(&gpadc->ab8500_gpadc_lock); | |
999 | ||
1000 | pm_runtime_get_sync(dev); | |
1001 | ||
1002 | regulator_disable(gpadc->regu); | |
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | static int ab8500_gpadc_resume(struct device *dev) | |
1007 | { | |
1008 | struct ab8500_gpadc *gpadc = dev_get_drvdata(dev); | |
1009 | ||
1010 | regulator_enable(gpadc->regu); | |
1011 | ||
1012 | pm_runtime_mark_last_busy(gpadc->dev); | |
1013 | pm_runtime_put_autosuspend(gpadc->dev); | |
1014 | ||
1015 | mutex_unlock(&gpadc->ab8500_gpadc_lock); | |
1016 | return 0; | |
1017 | } | |
1018 | ||
f791be49 | 1019 | static int ab8500_gpadc_probe(struct platform_device *pdev) |
dae2db30 AM |
1020 | { |
1021 | int ret = 0; | |
1022 | struct ab8500_gpadc *gpadc; | |
1023 | ||
1024 | gpadc = kzalloc(sizeof(struct ab8500_gpadc), GFP_KERNEL); | |
1025 | if (!gpadc) { | |
1026 | dev_err(&pdev->dev, "Error: No memory\n"); | |
1027 | return -ENOMEM; | |
1028 | } | |
1029 | ||
73482346 | 1030 | gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END"); |
c0eda9ae LJ |
1031 | if (gpadc->irq_sw < 0) |
1032 | dev_err(gpadc->dev, "failed to get platform sw_conv_end irq\n"); | |
73482346 LJ |
1033 | |
1034 | gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END"); | |
c0eda9ae LJ |
1035 | if (gpadc->irq_hw < 0) |
1036 | dev_err(gpadc->dev, "failed to get platform hw_conv_end irq\n"); | |
dae2db30 AM |
1037 | |
1038 | gpadc->dev = &pdev->dev; | |
20bf4283 | 1039 | gpadc->parent = dev_get_drvdata(pdev->dev.parent); |
6321992c | 1040 | mutex_init(&gpadc->ab8500_gpadc_lock); |
dae2db30 AM |
1041 | |
1042 | /* Initialize completion used to notify completion of conversion */ | |
1043 | init_completion(&gpadc->ab8500_gpadc_complete); | |
1044 | ||
73482346 | 1045 | /* Register interrupts */ |
c0eda9ae LJ |
1046 | if (gpadc->irq_sw >= 0) { |
1047 | ret = request_threaded_irq(gpadc->irq_sw, NULL, | |
1048 | ab8500_bm_gpadcconvend_handler, | |
1049 | IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-sw", | |
1050 | gpadc); | |
1051 | if (ret < 0) { | |
1052 | dev_err(gpadc->dev, | |
1053 | "Failed to register interrupt irq: %d\n", | |
1054 | gpadc->irq_sw); | |
1055 | goto fail; | |
1056 | } | |
73482346 | 1057 | } |
c0eda9ae LJ |
1058 | |
1059 | if (gpadc->irq_hw >= 0) { | |
1060 | ret = request_threaded_irq(gpadc->irq_hw, NULL, | |
1061 | ab8500_bm_gpadcconvend_handler, | |
1062 | IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-hw", | |
1063 | gpadc); | |
1064 | if (ret < 0) { | |
1065 | dev_err(gpadc->dev, | |
1066 | "Failed to register interrupt irq: %d\n", | |
1067 | gpadc->irq_hw); | |
1068 | goto fail_irq; | |
1069 | } | |
dae2db30 AM |
1070 | } |
1071 | ||
1072 | /* VTVout LDO used to power up ab8500-GPADC */ | |
1073 | gpadc->regu = regulator_get(&pdev->dev, "vddadc"); | |
1074 | if (IS_ERR(gpadc->regu)) { | |
1075 | ret = PTR_ERR(gpadc->regu); | |
1076 | dev_err(gpadc->dev, "failed to get vtvout LDO\n"); | |
633e0fa5 | 1077 | goto fail_irq; |
dae2db30 | 1078 | } |
5f8aaef4 LJ |
1079 | |
1080 | platform_set_drvdata(pdev, gpadc); | |
1081 | ||
1082 | regulator_enable(gpadc->regu); | |
1083 | ||
1084 | pm_runtime_set_autosuspend_delay(gpadc->dev, GPADC_AUDOSUSPEND_DELAY); | |
1085 | pm_runtime_use_autosuspend(gpadc->dev); | |
1086 | pm_runtime_set_active(gpadc->dev); | |
1087 | pm_runtime_enable(gpadc->dev); | |
1088 | ||
586f3318 | 1089 | ab8500_gpadc_read_calibration_data(gpadc); |
6321992c | 1090 | list_add_tail(&gpadc->node, &ab8500_gpadc_list); |
dae2db30 | 1091 | dev_dbg(gpadc->dev, "probe success\n"); |
c0eda9ae | 1092 | |
dae2db30 | 1093 | return 0; |
c0eda9ae | 1094 | |
633e0fa5 | 1095 | fail_irq: |
73482346 LJ |
1096 | free_irq(gpadc->irq_sw, gpadc); |
1097 | free_irq(gpadc->irq_hw, gpadc); | |
dae2db30 AM |
1098 | fail: |
1099 | kfree(gpadc); | |
1100 | gpadc = NULL; | |
1101 | return ret; | |
1102 | } | |
1103 | ||
4740f73f | 1104 | static int ab8500_gpadc_remove(struct platform_device *pdev) |
dae2db30 AM |
1105 | { |
1106 | struct ab8500_gpadc *gpadc = platform_get_drvdata(pdev); | |
1107 | ||
6321992c DW |
1108 | /* remove this gpadc entry from the list */ |
1109 | list_del(&gpadc->node); | |
dae2db30 | 1110 | /* remove interrupt - completion of Sw ADC conversion */ |
c0eda9ae LJ |
1111 | if (gpadc->irq_sw >= 0) |
1112 | free_irq(gpadc->irq_sw, gpadc); | |
1113 | if (gpadc->irq_hw >= 0) | |
1114 | free_irq(gpadc->irq_hw, gpadc); | |
5f8aaef4 LJ |
1115 | |
1116 | pm_runtime_get_sync(gpadc->dev); | |
1117 | pm_runtime_disable(gpadc->dev); | |
1118 | ||
1119 | regulator_disable(gpadc->regu); | |
1120 | ||
1121 | pm_runtime_set_suspended(gpadc->dev); | |
1122 | ||
1123 | pm_runtime_put_noidle(gpadc->dev); | |
1124 | ||
dae2db30 AM |
1125 | kfree(gpadc); |
1126 | gpadc = NULL; | |
1127 | return 0; | |
1128 | } | |
1129 | ||
5f8aaef4 LJ |
1130 | static const struct dev_pm_ops ab8500_gpadc_pm_ops = { |
1131 | SET_RUNTIME_PM_OPS(ab8500_gpadc_runtime_suspend, | |
1132 | ab8500_gpadc_runtime_resume, | |
1133 | ab8500_gpadc_runtime_idle) | |
774c50ab DW |
1134 | SET_SYSTEM_SLEEP_PM_OPS(ab8500_gpadc_suspend, |
1135 | ab8500_gpadc_resume) | |
1136 | ||
5f8aaef4 LJ |
1137 | }; |
1138 | ||
dae2db30 AM |
1139 | static struct platform_driver ab8500_gpadc_driver = { |
1140 | .probe = ab8500_gpadc_probe, | |
84449216 | 1141 | .remove = ab8500_gpadc_remove, |
dae2db30 AM |
1142 | .driver = { |
1143 | .name = "ab8500-gpadc", | |
1144 | .owner = THIS_MODULE, | |
5f8aaef4 | 1145 | .pm = &ab8500_gpadc_pm_ops, |
dae2db30 AM |
1146 | }, |
1147 | }; | |
1148 | ||
1149 | static int __init ab8500_gpadc_init(void) | |
1150 | { | |
1151 | return platform_driver_register(&ab8500_gpadc_driver); | |
1152 | } | |
1153 | ||
1154 | static void __exit ab8500_gpadc_exit(void) | |
1155 | { | |
1156 | platform_driver_unregister(&ab8500_gpadc_driver); | |
1157 | } | |
1158 | ||
bc6b4132 LJ |
1159 | /** |
1160 | * ab8540_gpadc_get_otp() - returns OTP values | |
1161 | * | |
1162 | */ | |
1163 | void ab8540_gpadc_get_otp(struct ab8500_gpadc *gpadc, | |
1164 | u16 *vmain_l, u16 *vmain_h, u16 *btemp_l, u16 *btemp_h, | |
1165 | u16 *vbat_l, u16 *vbat_h, u16 *ibat_l, u16 *ibat_h) | |
1166 | { | |
1167 | *vmain_l = gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_lo; | |
1168 | *vmain_h = gpadc->cal_data[ADC_INPUT_VMAIN].otp_calib_hi; | |
1169 | *btemp_l = gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_lo; | |
1170 | *btemp_h = gpadc->cal_data[ADC_INPUT_BTEMP].otp_calib_hi; | |
1171 | *vbat_l = gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_lo; | |
1172 | *vbat_h = gpadc->cal_data[ADC_INPUT_VBAT].otp_calib_hi; | |
1173 | *ibat_l = gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_lo; | |
1174 | *ibat_h = gpadc->cal_data[ADC_INPUT_IBAT].otp_calib_hi; | |
1175 | return ; | |
1176 | } | |
1177 | ||
dae2db30 AM |
1178 | subsys_initcall_sync(ab8500_gpadc_init); |
1179 | module_exit(ab8500_gpadc_exit); | |
1180 | ||
1181 | MODULE_LICENSE("GPL v2"); | |
73482346 LJ |
1182 | MODULE_AUTHOR("Arun R Murthy, Daniel Willerud, Johan Palsson," |
1183 | "M'boumba Cedric Madianga"); | |
dae2db30 AM |
1184 | MODULE_ALIAS("platform:ab8500_gpadc"); |
1185 | MODULE_DESCRIPTION("AB8500 GPADC driver"); |