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mfd: ab8500-sysctrl: Add new reset function
[linux-2.6-block.git] / drivers / mfd / ab8500-gpadc.c
CommitLineData
dae2db30
AM		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Arun R Murthy <arun.murthy@stericsson.com>
6321992c 6 * Author: Daniel Willerud <daniel.willerud@stericsson.com>
586f3318 7 * Author: Johan Palsson <johan.palsson@stericsson.com>
dae2db30
AM		 8 */
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/device.h>
12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
14#include <linux/delay.h>
5f8aaef4 15#include <linux/pm_runtime.h>
dae2db30
AM		 16#include <linux/platform_device.h>
17#include <linux/completion.h>
18#include <linux/regulator/consumer.h>
19#include <linux/err.h>
20#include <linux/slab.h>
6321992c 21#include <linux/list.h>
dae2db30 22#include <linux/mfd/abx500.h>
ee66e653
LW		 23#include <linux/mfd/abx500/ab8500.h>
24#include <linux/mfd/abx500/ab8500-gpadc.h>
dae2db30
AM		 25
26/*
27 * GPADC register offsets
28 * Bank : 0x0A
29 */
30#define AB8500_GPADC_CTRL1_REG 0x00
31#define AB8500_GPADC_CTRL2_REG 0x01
32#define AB8500_GPADC_CTRL3_REG 0x02
33#define AB8500_GPADC_AUTO_TIMER_REG 0x03
34#define AB8500_GPADC_STAT_REG 0x04
35#define AB8500_GPADC_MANDATAL_REG 0x05
36#define AB8500_GPADC_MANDATAH_REG 0x06
37#define AB8500_GPADC_AUTODATAL_REG 0x07
38#define AB8500_GPADC_AUTODATAH_REG 0x08
39#define AB8500_GPADC_MUX_CTRL_REG 0x09
40
586f3318
JP		 41/*
42 * OTP register offsets
43 * Bank : 0x15
44 */
45#define AB8500_GPADC_CAL_1 0x0F
46#define AB8500_GPADC_CAL_2 0x10
47#define AB8500_GPADC_CAL_3 0x11
48#define AB8500_GPADC_CAL_4 0x12
49#define AB8500_GPADC_CAL_5 0x13
50#define AB8500_GPADC_CAL_6 0x14
51#define AB8500_GPADC_CAL_7 0x15
52
dae2db30
AM		 53/* gpadc constants */
54#define EN_VINTCORE12 0x04
55#define EN_VTVOUT 0x02
56#define EN_GPADC 0x01
57#define DIS_GPADC 0x00
73482346
LJ		 58#define AVG_1 0x00
59#define AVG_4 0x20
60#define AVG_8 0x40
61#define AVG_16 0x60
dae2db30 62#define ADC_SW_CONV 0x04
4aad5a91 63#define EN_ICHAR 0x80
ed139416 64#define BTEMP_PULL_UP 0x08
dae2db30
AM		 65#define EN_BUF 0x40
66#define DIS_ZERO 0x00
67#define GPADC_BUSY 0x01
73482346
LJ		 68#define EN_FALLING 0x10
69#define EN_TRIG_EDGE 0x02
dae2db30 70
586f3318
JP		 71/* GPADC constants from AB8500 spec, UM0836 */
72#define ADC_RESOLUTION 1024
73#define ADC_CH_BTEMP_MIN 0
74#define ADC_CH_BTEMP_MAX 1350
75#define ADC_CH_DIETEMP_MIN 0
76#define ADC_CH_DIETEMP_MAX 1350
77#define ADC_CH_CHG_V_MIN 0
78#define ADC_CH_CHG_V_MAX 20030
79#define ADC_CH_ACCDET2_MIN 0
80#define ADC_CH_ACCDET2_MAX 2500
81#define ADC_CH_VBAT_MIN 2300
82#define ADC_CH_VBAT_MAX 4800
83#define ADC_CH_CHG_I_MIN 0
84#define ADC_CH_CHG_I_MAX 1500
85#define ADC_CH_BKBAT_MIN 0
86#define ADC_CH_BKBAT_MAX 3200
87
88/* This is used to not lose precision when dividing to get gain and offset */
89#define CALIB_SCALE 1000
90
5f8aaef4
LJ		 91/* Time in ms before disabling regulator */
92#define GPADC_AUDOSUSPEND_DELAY 1
93
f825ebe5
LJ		 94#define CONVERSION_TIME 500 /* ms */
95
586f3318
JP		 96enum cal_channels {
97 ADC_INPUT_VMAIN = 0,
98 ADC_INPUT_BTEMP,
99 ADC_INPUT_VBAT,
100 NBR_CAL_INPUTS,
101};
102
103/**
104 * struct adc_cal_data - Table for storing gain and offset for the calibrated
105 * ADC channels
106 * @gain: Gain of the ADC channel
107 * @offset: Offset of the ADC channel
108 */
109struct adc_cal_data {
110 u64 gain;
111 u64 offset;
112};
113
dae2db30 114/**
586f3318 115 * struct ab8500_gpadc - AB8500 GPADC device information
dae2db30 116 * @dev: pointer to the struct device
6321992c
DW		 117 * @node: a list of AB8500 GPADCs, hence prepared for
118 reentrance
20bf4283 119 * @parent: pointer to the struct ab8500
dae2db30
AM		 120 * @ab8500_gpadc_complete: pointer to the struct completion, to indicate
121 * the completion of gpadc conversion
122 * @ab8500_gpadc_lock: structure of type mutex
123 * @regu: pointer to the struct regulator
73482346
LJ		 124 * @irq_sw: interrupt number that is used by gpadc for Sw
125 * conversion
126 * @irq_hw: interrupt number that is used by gpadc for Hw
127 * conversion
586f3318 128 * @cal_data array of ADC calibration data structs
dae2db30 129 */
6321992c 130struct ab8500_gpadc {
dae2db30 131 struct device *dev;
6321992c 132 struct list_head node;
20bf4283 133 struct ab8500 *parent;
dae2db30
AM		 134 struct completion ab8500_gpadc_complete;
135 struct mutex ab8500_gpadc_lock;
136 struct regulator *regu;
73482346
LJ		 137 int irq_sw;
138 int irq_hw;
586f3318 139 struct adc_cal_data cal_data[NBR_CAL_INPUTS];
6321992c
DW		 140};
141
142static LIST_HEAD(ab8500_gpadc_list);
143
144/**
145 * ab8500_gpadc_get() - returns a reference to the primary AB8500 GPADC
146 * (i.e. the first GPADC in the instance list)
147 */
148struct ab8500_gpadc *ab8500_gpadc_get(char *name)
149{
150 struct ab8500_gpadc *gpadc;
151
152 list_for_each_entry(gpadc, &ab8500_gpadc_list, node) {
153 if (!strcmp(name, dev_name(gpadc->dev)))
154 return gpadc;
155 }
156
157 return ERR_PTR(-ENOENT);
158}
159EXPORT_SYMBOL(ab8500_gpadc_get);
dae2db30 160
bd4a40b5
KK		 161/**
162 * ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage
163 */
164int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, u8 channel,
586f3318
JP		 165 int ad_value)
166{
167 int res;
168
bd4a40b5 169 switch (channel) {
586f3318
JP		 170 case MAIN_CHARGER_V:
171 /* For some reason we don't have calibrated data */
172 if (!gpadc->cal_data[ADC_INPUT_VMAIN].gain) {
173 res = ADC_CH_CHG_V_MIN + (ADC_CH_CHG_V_MAX -
174 ADC_CH_CHG_V_MIN) * ad_value /
175 ADC_RESOLUTION;
176 break;
177 }
178 /* Here we can use the calibrated data */
179 res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VMAIN].gain +
180 gpadc->cal_data[ADC_INPUT_VMAIN].offset) / CALIB_SCALE;
181 break;
182
183 case BAT_CTRL:
184 case BTEMP_BALL:
185 case ACC_DETECT1:
186 case ADC_AUX1:
187 case ADC_AUX2:
188 /* For some reason we don't have calibrated data */
189 if (!gpadc->cal_data[ADC_INPUT_BTEMP].gain) {
190 res = ADC_CH_BTEMP_MIN + (ADC_CH_BTEMP_MAX -
191 ADC_CH_BTEMP_MIN) * ad_value /
192 ADC_RESOLUTION;
193 break;
194 }
195 /* Here we can use the calibrated data */
196 res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_BTEMP].gain +
197 gpadc->cal_data[ADC_INPUT_BTEMP].offset) / CALIB_SCALE;
198 break;
199
200 case MAIN_BAT_V:
201 /* For some reason we don't have calibrated data */
202 if (!gpadc->cal_data[ADC_INPUT_VBAT].gain) {
203 res = ADC_CH_VBAT_MIN + (ADC_CH_VBAT_MAX -
204 ADC_CH_VBAT_MIN) * ad_value /
205 ADC_RESOLUTION;
206 break;
207 }
208 /* Here we can use the calibrated data */
209 res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VBAT].gain +
210 gpadc->cal_data[ADC_INPUT_VBAT].offset) / CALIB_SCALE;
211 break;
212
213 case DIE_TEMP:
214 res = ADC_CH_DIETEMP_MIN +
215 (ADC_CH_DIETEMP_MAX - ADC_CH_DIETEMP_MIN) * ad_value /
216 ADC_RESOLUTION;
217 break;
218
219 case ACC_DETECT2:
220 res = ADC_CH_ACCDET2_MIN +
221 (ADC_CH_ACCDET2_MAX - ADC_CH_ACCDET2_MIN) * ad_value /
222 ADC_RESOLUTION;
223 break;
224
225 case VBUS_V:
226 res = ADC_CH_CHG_V_MIN +
227 (ADC_CH_CHG_V_MAX - ADC_CH_CHG_V_MIN) * ad_value /
228 ADC_RESOLUTION;
229 break;
230
231 case MAIN_CHARGER_C:
232 case USB_CHARGER_C:
233 res = ADC_CH_CHG_I_MIN +
234 (ADC_CH_CHG_I_MAX - ADC_CH_CHG_I_MIN) * ad_value /
235 ADC_RESOLUTION;
236 break;
237
238 case BK_BAT_V:
239 res = ADC_CH_BKBAT_MIN +
240 (ADC_CH_BKBAT_MAX - ADC_CH_BKBAT_MIN) * ad_value /
241 ADC_RESOLUTION;
242 break;
243
244 default:
245 dev_err(gpadc->dev,
246 "unknown channel, not possible to convert\n");
247 res = -EINVAL;
248 break;
249
250 }
251 return res;
252}
bd4a40b5 253EXPORT_SYMBOL(ab8500_gpadc_ad_to_voltage);
586f3318 254
dae2db30 255/**
73482346 256 * ab8500_gpadc_sw_hw_convert() - gpadc conversion
bd4a40b5 257 * @channel: analog channel to be converted to digital data
73482346
LJ		 258 * @avg_sample: number of ADC sample to average
259 * @trig_egde: selected ADC trig edge
260 * @trig_timer: selected ADC trigger delay timer
261 * @conv_type: selected conversion type (HW or SW conversion)
dae2db30
AM		 262 *
263 * This function converts the selected analog i/p to digital
586f3318 264 * data.
dae2db30 265 */
73482346
LJ		 266int ab8500_gpadc_sw_hw_convert(struct ab8500_gpadc *gpadc, u8 channel,
267 u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type)
bd4a40b5
KK		 268{
269 int ad_value;
270 int voltage;
271
73482346
LJ		 272 ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample,
273 trig_edge, trig_timer, conv_type);
274/* On failure retry a second time */
d89cc5aa 275 if (ad_value < 0)
73482346
LJ		 276 ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample,
277 trig_edge, trig_timer, conv_type);
278if (ad_value < 0) {
279 dev_err(gpadc->dev, "GPADC raw value failed ch: %d\n",
280 channel);
bd4a40b5
KK		 281 return ad_value;
282 }
283
284 voltage = ab8500_gpadc_ad_to_voltage(gpadc, channel, ad_value);
bd4a40b5
KK		 285 if (voltage < 0)
286 dev_err(gpadc->dev, "GPADC to voltage conversion failed ch:"
287 " %d AD: 0x%x\n", channel, ad_value);
288
289 return voltage;
290}
291EXPORT_SYMBOL(ab8500_gpadc_convert);
292
293/**
294 * ab8500_gpadc_read_raw() - gpadc read
295 * @channel: analog channel to be read
73482346
LJ		 296 * @avg_sample: number of ADC sample to average
297 * @trig_edge: selected trig edge
298 * @trig_timer: selected ADC trigger delay timer
299 * @conv_type: selected conversion type (HW or SW conversion)
bd4a40b5 300 *
73482346
LJ		 301 * This function obtains the raw ADC value for an hardware conversion,
302 * this then needs to be converted by calling ab8500_gpadc_ad_to_voltage()
bd4a40b5 303 */
73482346
LJ		 304int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
305 u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type)
dae2db30
AM		 306{
307 int ret;
dae2db30
AM		 308 int looplimit = 0;
309 u8 val, low_data, high_data;
310
6321992c 311 if (!gpadc)
dae2db30
AM		 312 return -ENODEV;
313
c0eda9ae
LJ		 314 /* check if convertion is supported */
315 if ((gpadc->irq_sw < 0) && (conv_type == ADC_SW))
316 return -ENOTSUPP;
317 if ((gpadc->irq_hw < 0) && (conv_type == ADC_HW))
318 return -ENOTSUPP;
319
6321992c 320 mutex_lock(&gpadc->ab8500_gpadc_lock);
dae2db30 321 /* Enable VTVout LDO this is required for GPADC */
5f8aaef4 322 pm_runtime_get_sync(gpadc->dev);
dae2db30
AM		 323
324 /* Check if ADC is not busy, lock and proceed */
325 do {
6321992c
DW		 326 ret = abx500_get_register_interruptible(gpadc->dev,
327 AB8500_GPADC, AB8500_GPADC_STAT_REG, &val);
dae2db30
AM		 328 if (ret < 0)
329 goto out;
330 if (!(val & GPADC_BUSY))
331 break;
332 msleep(10);
333 } while (++looplimit < 10);
334 if (looplimit >= 10 && (val & GPADC_BUSY)) {
6321992c 335 dev_err(gpadc->dev, "gpadc_conversion: GPADC busy");
dae2db30
AM		 336 ret = -EINVAL;
337 goto out;
338 }
339
340 /* Enable GPADC */
6321992c
DW		 341 ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
342 AB8500_GPADC, AB8500_GPADC_CTRL1_REG, EN_GPADC, EN_GPADC);
dae2db30 343 if (ret < 0) {
6321992c 344 dev_err(gpadc->dev, "gpadc_conversion: enable gpadc failed\n");
dae2db30
AM		 345 goto out;
346 }
c9c9513f 347
73482346
LJ		 348 /* Select the channel source and set average samples */
349 switch (avg_sample) {
350 case SAMPLE_1:
351 val = channel | AVG_1;
352 break;
353 case SAMPLE_4:
354 val = channel | AVG_4;
355 break;
356 case SAMPLE_8:
357 val = channel | AVG_8;
358 break;
359 default:
360 val = channel | AVG_16;
361 break;
362
363 }
364
365 if (conv_type == ADC_HW)
366 ret = abx500_set_register_interruptible(gpadc->dev,
367 AB8500_GPADC, AB8500_GPADC_CTRL3_REG, val);
368 else
369 ret = abx500_set_register_interruptible(gpadc->dev,
370 AB8500_GPADC, AB8500_GPADC_CTRL2_REG, val);
dae2db30 371 if (ret < 0) {
6321992c 372 dev_err(gpadc->dev,
dae2db30
AM		 373 "gpadc_conversion: set avg samples failed\n");
374 goto out;
375 }
c9c9513f 376
4aad5a91
KK		 377 /*
378 * Enable ADC, buffering, select rising edge and enable ADC path
c9c9513f
KK		 379 * charging current sense if it needed, ABB 3.0 needs some special
380 * treatment too.
4aad5a91 381 */
73482346
LJ		 382 if ((conv_type == ADC_HW) && (trig_edge)) {
383 ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
384 AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
385 EN_FALLING, EN_FALLING);
386
387 }
bd4a40b5 388 switch (channel) {
4aad5a91
KK		 389 case MAIN_CHARGER_C:
390 case USB_CHARGER_C:
73482346 391 if (conv_type == ADC_HW)
c9c9513f
KK		 392 ret = abx500_mask_and_set_register_interruptible(
393 gpadc->dev,
394 AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
73482346
LJ		 395 EN_BUF | EN_ICHAR | EN_TRIG_EDGE,
396 EN_BUF | EN_ICHAR | EN_TRIG_EDGE);
397 else
398 ret = abx500_mask_and_set_register_interruptible(
399 gpadc->dev,
400 AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
401 EN_BUF | EN_ICHAR,
402 EN_BUF | EN_ICHAR);
403 break;
404 case BTEMP_BALL:
405 if (!is_ab8500_2p0_or_earlier(gpadc->parent)) {
406 if (conv_type == ADC_HW)
407 /* Turn on btemp pull-up on ABB 3.0 */
408 ret = abx500_mask_and_set_register_interruptible
409 (gpadc->dev,
410 AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
411 EN_BUF | BTEMP_PULL_UP | EN_TRIG_EDGE,
412 EN_BUF | BTEMP_PULL_UP | EN_TRIG_EDGE);
413 else
414 ret = abx500_mask_and_set_register_interruptible
415 (gpadc->dev,
416 AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
417 EN_BUF | BTEMP_PULL_UP,
418 EN_BUF | BTEMP_PULL_UP);
c9c9513f
KK		 419
420 /*
421 * Delay might be needed for ABB8500 cut 3.0, if not, remove
5a4432b9 422 * when hardware will be available
c9c9513f 423 */
d0b32fa1 424 usleep_range(1000, 1000);
c9c9513f
KK		 425 break;
426 }
427 /* Intentional fallthrough */
4aad5a91 428 default:
73482346
LJ		 429 if (conv_type == ADC_HW)
430 ret = abx500_mask_and_set_register_interruptible(
431 gpadc->dev,
432 AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
433 EN_BUF | EN_TRIG_EDGE,
434 EN_BUF | EN_TRIG_EDGE);
435 else
436 ret = abx500_mask_and_set_register_interruptible(
437 gpadc->dev,
438 AB8500_GPADC,
439 AB8500_GPADC_CTRL1_REG, EN_BUF, EN_BUF);
4aad5a91
KK		 440 break;
441 }
dae2db30 442 if (ret < 0) {
6321992c 443 dev_err(gpadc->dev,
dae2db30
AM		 444 "gpadc_conversion: select falling edge failed\n");
445 goto out;
446 }
c9c9513f 447
73482346
LJ		 448 /* Set trigger delay timer */
449 if (conv_type == ADC_HW) {
450 ret = abx500_set_register_interruptible(gpadc->dev,
451 AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG, trig_timer);
452 if (ret < 0) {
453 dev_err(gpadc->dev,
454 "gpadc_conversion: trig timer failed\n");
455 goto out;
456 }
457 }
458
459 /* Start SW conversion */
460 if (conv_type == ADC_SW) {
461 ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
462 AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
463 ADC_SW_CONV, ADC_SW_CONV);
464 if (ret < 0) {
465 dev_err(gpadc->dev,
466 "gpadc_conversion: start s/w conv failed\n");
467 goto out;
468 }
dae2db30 469 }
73482346 470
dae2db30 471 /* wait for completion of conversion */
73482346
LJ		 472 if (conv_type == ADC_HW) {
473 if (!wait_for_completion_timeout(&gpadc->ab8500_gpadc_complete,
474 2*HZ)) {
475 dev_err(gpadc->dev,
476 "timeout didn't receive"
477 " hw GPADC conv interrupt\n");
478 ret = -EINVAL;
479 goto out;
480 }
481 } else {
482 if (!wait_for_completion_timeout(&gpadc->ab8500_gpadc_complete,
483 msecs_to_jiffies(CONVERSION_TIME))) {
484 dev_err(gpadc->dev,
485 "timeout didn't receive"
486 " sw GPADC conv interrupt\n");
487 ret = -EINVAL;
488 goto out;
489 }
dae2db30
AM		 490 }
491
492 /* Read the converted RAW data */
73482346
LJ		 493 if (conv_type == ADC_HW) {
494 ret = abx500_get_register_interruptible(gpadc->dev,
495 AB8500_GPADC, AB8500_GPADC_AUTODATAL_REG, &low_data);
496 if (ret < 0) {
497 dev_err(gpadc->dev,
498 "gpadc_conversion: read hw low data failed\n");
499 goto out;
500 }
dae2db30 501
73482346
LJ		 502 ret = abx500_get_register_interruptible(gpadc->dev,
503 AB8500_GPADC, AB8500_GPADC_AUTODATAH_REG, &high_data);
504 if (ret < 0) {
505 dev_err(gpadc->dev,
506 "gpadc_conversion: read hw high data failed\n");
507 goto out;
508 }
509 } else {
510 ret = abx500_get_register_interruptible(gpadc->dev,
511 AB8500_GPADC, AB8500_GPADC_MANDATAL_REG, &low_data);
512 if (ret < 0) {
513 dev_err(gpadc->dev,
514 "gpadc_conversion: read sw low data failed\n");
515 goto out;
516 }
517
518 ret = abx500_get_register_interruptible(gpadc->dev,
519 AB8500_GPADC, AB8500_GPADC_MANDATAH_REG, &high_data);
520 if (ret < 0) {
521 dev_err(gpadc->dev,
522 "gpadc_conversion: read sw high data failed\n");
523 goto out;
524 }
dae2db30
AM		 525 }
526
dae2db30 527 /* Disable GPADC */
6321992c 528 ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
dae2db30
AM		 529 AB8500_GPADC_CTRL1_REG, DIS_GPADC);
530 if (ret < 0) {
6321992c 531 dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n");
dae2db30
AM		 532 goto out;
533 }
5f8aaef4 534
73482346 535 /* Disable VTVout LDO this is required for GPADC */
5f8aaef4
LJ		 536 pm_runtime_mark_last_busy(gpadc->dev);
537 pm_runtime_put_autosuspend(gpadc->dev);
538
6321992c 539 mutex_unlock(&gpadc->ab8500_gpadc_lock);
bd4a40b5
KK		 540
541 return (high_data << 8) | low_data;
dae2db30
AM		 542
543out:
544 /*
545 * It has shown to be needed to turn off the GPADC if an error occurs,
546 * otherwise we might have problem when waiting for the busy bit in the
547 * GPADC status register to go low. In V1.1 there wait_for_completion
548 * seems to timeout when waiting for an interrupt.. Not seen in V2.0
549 */
6321992c 550 (void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
dae2db30 551 AB8500_GPADC_CTRL1_REG, DIS_GPADC);
5f8aaef4 552 pm_runtime_put(gpadc->dev);
6321992c
DW		 553 mutex_unlock(&gpadc->ab8500_gpadc_lock);
554 dev_err(gpadc->dev,
bd4a40b5 555 "gpadc_conversion: Failed to AD convert channel %d\n", channel);
dae2db30
AM		 556 return ret;
557}
bd4a40b5 558EXPORT_SYMBOL(ab8500_gpadc_read_raw);
dae2db30
AM		 559
560/**
73482346 561 * ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion
dae2db30
AM		 562 * @irq: irq number
563 * @data: pointer to the data passed during request irq
564 *
73482346 565 * This is a interrupt service routine for gpadc conversion completion.
dae2db30
AM		 566 * Notifies the gpadc completion is completed and the converted raw value
567 * can be read from the registers.
568 * Returns IRQ status(IRQ_HANDLED)
569 */
73482346 570static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *_gpadc)
dae2db30 571{
6321992c 572 struct ab8500_gpadc *gpadc = _gpadc;
dae2db30
AM		 573
574 complete(&gpadc->ab8500_gpadc_complete);
575
576 return IRQ_HANDLED;
577}
578
586f3318
JP		 579static int otp_cal_regs[] = {
580 AB8500_GPADC_CAL_1,
581 AB8500_GPADC_CAL_2,
582 AB8500_GPADC_CAL_3,
583 AB8500_GPADC_CAL_4,
584 AB8500_GPADC_CAL_5,
585 AB8500_GPADC_CAL_6,
586 AB8500_GPADC_CAL_7,
587};
588
589static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc)
590{
591 int i;
592 int ret[ARRAY_SIZE(otp_cal_regs)];
593 u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)];
594
595 int vmain_high, vmain_low;
596 int btemp_high, btemp_low;
597 int vbat_high, vbat_low;
598
599 /* First we read all OTP registers and store the error code */
600 for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) {
601 ret[i] = abx500_get_register_interruptible(gpadc->dev,
602 AB8500_OTP_EMUL, otp_cal_regs[i], &gpadc_cal[i]);
603 if (ret[i] < 0)
604 dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n",
605 __func__, otp_cal_regs[i]);
606 }
607
608 /*
609 * The ADC calibration data is stored in OTP registers.
610 * The layout of the calibration data is outlined below and a more
611 * detailed description can be found in UM0836
612 *
613 * vm_h/l = vmain_high/low
614 * bt_h/l = btemp_high/low
615 * vb_h/l = vbat_high/low
616 *
617 * Data bits:
618 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
619 * |.......|.......|.......|.......|.......|.......|.......|.......
620 * | | vm_h9 | vm_h8
621 * |.......|.......|.......|.......|.......|.......|.......|.......
622 * | | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
623 * |.......|.......|.......|.......|.......|.......|.......|.......
624 * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
625 * |.......|.......|.......|.......|.......|.......|.......|.......
626 * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
627 * |.......|.......|.......|.......|.......|.......|.......|.......
628 * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
629 * |.......|.......|.......|.......|.......|.......|.......|.......
630 * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
631 * |.......|.......|.......|.......|.......|.......|.......|.......
632 * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
633 * |.......|.......|.......|.......|.......|.......|.......|.......
634 *
635 *
636 * Ideal output ADC codes corresponding to injected input voltages
637 * during manufacturing is:
638 *
639 * vmain_high: Vin = 19500mV / ADC ideal code = 997
640 * vmain_low: Vin = 315mV / ADC ideal code = 16
641 * btemp_high: Vin = 1300mV / ADC ideal code = 985
642 * btemp_low: Vin = 21mV / ADC ideal code = 16
643 * vbat_high: Vin = 4700mV / ADC ideal code = 982
644 * vbat_low: Vin = 2380mV / ADC ideal code = 33
645 */
646
647 /* Calculate gain and offset for VMAIN if all reads succeeded */
648 if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) {
649 vmain_high = (((gpadc_cal[0] & 0x03) << 8) |
650 ((gpadc_cal[1] & 0x3F) << 2) |
651 ((gpadc_cal[2] & 0xC0) >> 6));
652
653 vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
654
655 gpadc->cal_data[ADC_INPUT_VMAIN].gain = CALIB_SCALE *
656 (19500 - 315) / (vmain_high - vmain_low);
657
658 gpadc->cal_data[ADC_INPUT_VMAIN].offset = CALIB_SCALE * 19500 -
659 (CALIB_SCALE * (19500 - 315) /
660 (vmain_high - vmain_low)) * vmain_high;
661 } else {
662 gpadc->cal_data[ADC_INPUT_VMAIN].gain = 0;
663 }
664
665 /* Calculate gain and offset for BTEMP if all reads succeeded */
666 if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) {
667 btemp_high = (((gpadc_cal[2] & 0x01) << 9) |
668 (gpadc_cal[3] << 1) |
669 ((gpadc_cal[4] & 0x80) >> 7));
670
671 btemp_low = ((gpadc_cal[4] & 0x7C) >> 2);
672
673 gpadc->cal_data[ADC_INPUT_BTEMP].gain =
674 CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low);
675
676 gpadc->cal_data[ADC_INPUT_BTEMP].offset = CALIB_SCALE * 1300 -
677 (CALIB_SCALE * (1300 - 21) /
678 (btemp_high - btemp_low)) * btemp_high;
679 } else {
680 gpadc->cal_data[ADC_INPUT_BTEMP].gain = 0;
681 }
682
683 /* Calculate gain and offset for VBAT if all reads succeeded */
684 if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) {
685 vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]);
686 vbat_low = ((gpadc_cal[6] & 0xFC) >> 2);
687
688 gpadc->cal_data[ADC_INPUT_VBAT].gain = CALIB_SCALE *
689 (4700 - 2380) / (vbat_high - vbat_low);
690
691 gpadc->cal_data[ADC_INPUT_VBAT].offset = CALIB_SCALE * 4700 -
692 (CALIB_SCALE * (4700 - 2380) /
693 (vbat_high - vbat_low)) * vbat_high;
694 } else {
695 gpadc->cal_data[ADC_INPUT_VBAT].gain = 0;
696 }
697
698 dev_dbg(gpadc->dev, "VMAIN gain %llu offset %llu\n",
699 gpadc->cal_data[ADC_INPUT_VMAIN].gain,
700 gpadc->cal_data[ADC_INPUT_VMAIN].offset);
701
702 dev_dbg(gpadc->dev, "BTEMP gain %llu offset %llu\n",
703 gpadc->cal_data[ADC_INPUT_BTEMP].gain,
704 gpadc->cal_data[ADC_INPUT_BTEMP].offset);
705
706 dev_dbg(gpadc->dev, "VBAT gain %llu offset %llu\n",
707 gpadc->cal_data[ADC_INPUT_VBAT].gain,
708 gpadc->cal_data[ADC_INPUT_VBAT].offset);
709}
710
5f8aaef4
LJ		 711static int ab8500_gpadc_runtime_suspend(struct device *dev)
712{
713 struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
714
715 regulator_disable(gpadc->regu);
716 return 0;
717}
718
719static int ab8500_gpadc_runtime_resume(struct device *dev)
720{
721 struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
722
723 regulator_enable(gpadc->regu);
724 return 0;
725}
726
727static int ab8500_gpadc_runtime_idle(struct device *dev)
728{
5f8aaef4
LJ		 729 pm_runtime_suspend(dev);
730 return 0;
731}
732
774c50ab
DW		 733static int ab8500_gpadc_suspend(struct device *dev)
734{
735 struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
736
737 mutex_lock(&gpadc->ab8500_gpadc_lock);
738
739 pm_runtime_get_sync(dev);
740
741 regulator_disable(gpadc->regu);
742 return 0;
743}
744
745static int ab8500_gpadc_resume(struct device *dev)
746{
747 struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
748
749 regulator_enable(gpadc->regu);
750
751 pm_runtime_mark_last_busy(gpadc->dev);
752 pm_runtime_put_autosuspend(gpadc->dev);
753
754 mutex_unlock(&gpadc->ab8500_gpadc_lock);
755 return 0;
756}
757
f791be49 758static int ab8500_gpadc_probe(struct platform_device *pdev)
dae2db30
AM		 759{
760 int ret = 0;
761 struct ab8500_gpadc *gpadc;
762
763 gpadc = kzalloc(sizeof(struct ab8500_gpadc), GFP_KERNEL);
764 if (!gpadc) {
765 dev_err(&pdev->dev, "Error: No memory\n");
766 return -ENOMEM;
767 }
768
73482346 769 gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END");
c0eda9ae
LJ		 770 if (gpadc->irq_sw < 0)
771 dev_err(gpadc->dev, "failed to get platform sw_conv_end irq\n");
73482346
LJ		 772
773 gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END");
c0eda9ae
LJ		 774 if (gpadc->irq_hw < 0)
775 dev_err(gpadc->dev, "failed to get platform hw_conv_end irq\n");
dae2db30
AM		 776
777 gpadc->dev = &pdev->dev;
20bf4283 778 gpadc->parent = dev_get_drvdata(pdev->dev.parent);
6321992c 779 mutex_init(&gpadc->ab8500_gpadc_lock);
dae2db30
AM		 780
781 /* Initialize completion used to notify completion of conversion */
782 init_completion(&gpadc->ab8500_gpadc_complete);
783
73482346 784 /* Register interrupts */
c0eda9ae
LJ		 785 if (gpadc->irq_sw >= 0) {
786 ret = request_threaded_irq(gpadc->irq_sw, NULL,
787 ab8500_bm_gpadcconvend_handler,
788 IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-sw",
789 gpadc);
790 if (ret < 0) {
791 dev_err(gpadc->dev,
792 "Failed to register interrupt irq: %d\n",
793 gpadc->irq_sw);
794 goto fail;
795 }
73482346 796 }
c0eda9ae
LJ		 797
798 if (gpadc->irq_hw >= 0) {
799 ret = request_threaded_irq(gpadc->irq_hw, NULL,
800 ab8500_bm_gpadcconvend_handler,
801 IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-hw",
802 gpadc);
803 if (ret < 0) {
804 dev_err(gpadc->dev,
805 "Failed to register interrupt irq: %d\n",
806 gpadc->irq_hw);
807 goto fail_irq;
808 }
dae2db30
AM		 809 }
810
811 /* VTVout LDO used to power up ab8500-GPADC */
812 gpadc->regu = regulator_get(&pdev->dev, "vddadc");
813 if (IS_ERR(gpadc->regu)) {
814 ret = PTR_ERR(gpadc->regu);
815 dev_err(gpadc->dev, "failed to get vtvout LDO\n");
633e0fa5 816 goto fail_irq;
dae2db30 817 }
5f8aaef4
LJ		 818
819 platform_set_drvdata(pdev, gpadc);
820
821 regulator_enable(gpadc->regu);
822
823 pm_runtime_set_autosuspend_delay(gpadc->dev, GPADC_AUDOSUSPEND_DELAY);
824 pm_runtime_use_autosuspend(gpadc->dev);
825 pm_runtime_set_active(gpadc->dev);
826 pm_runtime_enable(gpadc->dev);
827
586f3318 828 ab8500_gpadc_read_calibration_data(gpadc);
6321992c 829 list_add_tail(&gpadc->node, &ab8500_gpadc_list);
dae2db30 830 dev_dbg(gpadc->dev, "probe success\n");
c0eda9ae 831
dae2db30 832 return 0;
c0eda9ae 833
633e0fa5 834fail_irq:
73482346
LJ		 835 free_irq(gpadc->irq_sw, gpadc);
836 free_irq(gpadc->irq_hw, gpadc);
dae2db30
AM		 837fail:
838 kfree(gpadc);
839 gpadc = NULL;
840 return ret;
841}
842
4740f73f 843static int ab8500_gpadc_remove(struct platform_device *pdev)
dae2db30
AM		 844{
845 struct ab8500_gpadc *gpadc = platform_get_drvdata(pdev);
846
6321992c
DW		 847 /* remove this gpadc entry from the list */
848 list_del(&gpadc->node);
dae2db30 849 /* remove interrupt - completion of Sw ADC conversion */
c0eda9ae
LJ		 850 if (gpadc->irq_sw >= 0)
851 free_irq(gpadc->irq_sw, gpadc);
852 if (gpadc->irq_hw >= 0)
853 free_irq(gpadc->irq_hw, gpadc);
5f8aaef4
LJ		 854
855 pm_runtime_get_sync(gpadc->dev);
856 pm_runtime_disable(gpadc->dev);
857
858 regulator_disable(gpadc->regu);
859
860 pm_runtime_set_suspended(gpadc->dev);
861
862 pm_runtime_put_noidle(gpadc->dev);
863
dae2db30
AM		 864 kfree(gpadc);
865 gpadc = NULL;
866 return 0;
867}
868
5f8aaef4
LJ		 869static const struct dev_pm_ops ab8500_gpadc_pm_ops = {
870 SET_RUNTIME_PM_OPS(ab8500_gpadc_runtime_suspend,
871 ab8500_gpadc_runtime_resume,
872 ab8500_gpadc_runtime_idle)
774c50ab
DW		 873 SET_SYSTEM_SLEEP_PM_OPS(ab8500_gpadc_suspend,
874 ab8500_gpadc_resume)
875
5f8aaef4
LJ		 876};
877
dae2db30
AM		 878static struct platform_driver ab8500_gpadc_driver = {
879 .probe = ab8500_gpadc_probe,
84449216 880 .remove = ab8500_gpadc_remove,
dae2db30
AM		 881 .driver = {
882 .name = "ab8500-gpadc",
883 .owner = THIS_MODULE,
5f8aaef4 884 .pm = &ab8500_gpadc_pm_ops,
dae2db30
AM		 885 },
886};
887
888static int __init ab8500_gpadc_init(void)
889{
890 return platform_driver_register(&ab8500_gpadc_driver);
891}
892
893static void __exit ab8500_gpadc_exit(void)
894{
895 platform_driver_unregister(&ab8500_gpadc_driver);
896}
897
898subsys_initcall_sync(ab8500_gpadc_init);
899module_exit(ab8500_gpadc_exit);
900
901MODULE_LICENSE("GPL v2");
73482346
LJ		 902MODULE_AUTHOR("Arun R Murthy, Daniel Willerud, Johan Palsson,"
903 "M'boumba Cedric Madianga");
dae2db30
AM		 904MODULE_ALIAS("platform:ab8500_gpadc");
905MODULE_DESCRIPTION("AB8500 GPADC driver");
Linux 6.x block layer and io_uring tree(s)