[linux-2.6-block.git] / drivers / mfd / 88pm800.c

/*
 * Base driver for Marvell 88PM800
 *
 * Copyright (C) 2012 Marvell International Ltd.
 * Haojian Zhuang <haojian.zhuang@marvell.com>
 * Joseph(Yossi) Hanin <yhanin@marvell.com>
 * Qiao Zhou <zhouqiao@marvell.com>
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License. See the file "COPYING" in the main directory of this
 * archive for more details.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/88pm80x.h>
#include <linux/slab.h>

/* Interrupt Registers */
#define PM800_INT_STATUS1		(0x05)
#define PM800_ONKEY_INT_STS1		(1 << 0)
#define PM800_EXTON_INT_STS1		(1 << 1)
#define PM800_CHG_INT_STS1			(1 << 2)
#define PM800_BAT_INT_STS1			(1 << 3)
#define PM800_RTC_INT_STS1			(1 << 4)
#define PM800_CLASSD_OC_INT_STS1	(1 << 5)

#define PM800_INT_STATUS2		(0x06)
#define PM800_VBAT_INT_STS2		(1 << 0)
#define PM800_VSYS_INT_STS2		(1 << 1)
#define PM800_VCHG_INT_STS2		(1 << 2)
#define PM800_TINT_INT_STS2		(1 << 3)
#define PM800_GPADC0_INT_STS2	(1 << 4)
#define PM800_TBAT_INT_STS2		(1 << 5)
#define PM800_GPADC2_INT_STS2	(1 << 6)
#define PM800_GPADC3_INT_STS2	(1 << 7)

#define PM800_INT_STATUS3		(0x07)

#define PM800_INT_STATUS4		(0x08)
#define PM800_GPIO0_INT_STS4		(1 << 0)
#define PM800_GPIO1_INT_STS4		(1 << 1)
#define PM800_GPIO2_INT_STS4		(1 << 2)
#define PM800_GPIO3_INT_STS4		(1 << 3)
#define PM800_GPIO4_INT_STS4		(1 << 4)

#define PM800_INT_ENA_1		(0x09)
#define PM800_ONKEY_INT_ENA1		(1 << 0)
#define PM800_EXTON_INT_ENA1		(1 << 1)
#define PM800_CHG_INT_ENA1			(1 << 2)
#define PM800_BAT_INT_ENA1			(1 << 3)
#define PM800_RTC_INT_ENA1			(1 << 4)
#define PM800_CLASSD_OC_INT_ENA1	(1 << 5)

#define PM800_INT_ENA_2		(0x0A)
#define PM800_VBAT_INT_ENA2		(1 << 0)
#define PM800_VSYS_INT_ENA2		(1 << 1)
#define PM800_VCHG_INT_ENA2		(1 << 2)
#define PM800_TINT_INT_ENA2		(1 << 3)

#define PM800_INT_ENA_3		(0x0B)
#define PM800_GPADC0_INT_ENA3		(1 << 0)
#define PM800_GPADC1_INT_ENA3		(1 << 1)
#define PM800_GPADC2_INT_ENA3		(1 << 2)
#define PM800_GPADC3_INT_ENA3		(1 << 3)
#define PM800_GPADC4_INT_ENA3		(1 << 4)

#define PM800_INT_ENA_4		(0x0C)
#define PM800_GPIO0_INT_ENA4		(1 << 0)
#define PM800_GPIO1_INT_ENA4		(1 << 1)
#define PM800_GPIO2_INT_ENA4		(1 << 2)
#define PM800_GPIO3_INT_ENA4		(1 << 3)
#define PM800_GPIO4_INT_ENA4		(1 << 4)

/* number of INT_ENA & INT_STATUS regs */
#define PM800_INT_REG_NUM			(4)

/* Interrupt Number in 88PM800 */
enum {
	PM800_IRQ_ONKEY,	/*EN1b0 *//*0 */
	PM800_IRQ_EXTON,	/*EN1b1 */
	PM800_IRQ_CHG,		/*EN1b2 */
	PM800_IRQ_BAT,		/*EN1b3 */
	PM800_IRQ_RTC,		/*EN1b4 */
	PM800_IRQ_CLASSD,	/*EN1b5 *//*5 */
	PM800_IRQ_VBAT,		/*EN2b0 */
	PM800_IRQ_VSYS,		/*EN2b1 */
	PM800_IRQ_VCHG,		/*EN2b2 */
	PM800_IRQ_TINT,		/*EN2b3 */
	PM800_IRQ_GPADC0,	/*EN3b0 *//*10 */
	PM800_IRQ_GPADC1,	/*EN3b1 */
	PM800_IRQ_GPADC2,	/*EN3b2 */
	PM800_IRQ_GPADC3,	/*EN3b3 */
	PM800_IRQ_GPADC4,	/*EN3b4 */
	PM800_IRQ_GPIO0,	/*EN4b0 *//*15 */
	PM800_IRQ_GPIO1,	/*EN4b1 */
	PM800_IRQ_GPIO2,	/*EN4b2 */
	PM800_IRQ_GPIO3,	/*EN4b3 */
	PM800_IRQ_GPIO4,	/*EN4b4 *//*19 */
	PM800_MAX_IRQ,
};

/* PM800: generation identification number */
#define PM800_CHIP_GEN_ID_NUM	0x3

static const struct i2c_device_id pm80x_id_table[] = {
	{"88PM800", 0},
	{} /* NULL terminated */
};
MODULE_DEVICE_TABLE(i2c, pm80x_id_table);

static struct resource rtc_resources[] = {
	{
	 .name = "88pm80x-rtc",
	 .start = PM800_IRQ_RTC,
	 .end = PM800_IRQ_RTC,
	 .flags = IORESOURCE_IRQ,
	 },
};

static struct mfd_cell rtc_devs[] = {
	{
	 .name = "88pm80x-rtc",
	 .num_resources = ARRAY_SIZE(rtc_resources),
	 .resources = &rtc_resources[0],
	 .id = -1,
	 },
};

static struct resource onkey_resources[] = {
	{
	 .name = "88pm80x-onkey",
	 .start = PM800_IRQ_ONKEY,
	 .end = PM800_IRQ_ONKEY,
	 .flags = IORESOURCE_IRQ,
	 },
};

static struct mfd_cell onkey_devs[] = {
	{
	 .name = "88pm80x-onkey",
	 .num_resources = 1,
	 .resources = &onkey_resources[0],
	 .id = -1,
	 },
};

static const struct regmap_irq pm800_irqs[] = {
	/* INT0 */
	[PM800_IRQ_ONKEY] = {
		.mask = PM800_ONKEY_INT_ENA1,
	},
	[PM800_IRQ_EXTON] = {
		.mask = PM800_EXTON_INT_ENA1,
	},
	[PM800_IRQ_CHG] = {
		.mask = PM800_CHG_INT_ENA1,
	},
	[PM800_IRQ_BAT] = {
		.mask = PM800_BAT_INT_ENA1,
	},
	[PM800_IRQ_RTC] = {
		.mask = PM800_RTC_INT_ENA1,
	},
	[PM800_IRQ_CLASSD] = {
		.mask = PM800_CLASSD_OC_INT_ENA1,
	},
	/* INT1 */
	[PM800_IRQ_VBAT] = {
		.reg_offset = 1,
		.mask = PM800_VBAT_INT_ENA2,
	},
	[PM800_IRQ_VSYS] = {
		.reg_offset = 1,
		.mask = PM800_VSYS_INT_ENA2,
	},
	[PM800_IRQ_VCHG] = {
		.reg_offset = 1,
		.mask = PM800_VCHG_INT_ENA2,
	},
	[PM800_IRQ_TINT] = {
		.reg_offset = 1,
		.mask = PM800_TINT_INT_ENA2,
	},
	/* INT2 */
	[PM800_IRQ_GPADC0] = {
		.reg_offset = 2,
		.mask = PM800_GPADC0_INT_ENA3,
	},
	[PM800_IRQ_GPADC1] = {
		.reg_offset = 2,
		.mask = PM800_GPADC1_INT_ENA3,
	},
	[PM800_IRQ_GPADC2] = {
		.reg_offset = 2,
		.mask = PM800_GPADC2_INT_ENA3,
	},
	[PM800_IRQ_GPADC3] = {
		.reg_offset = 2,
		.mask = PM800_GPADC3_INT_ENA3,
	},
	[PM800_IRQ_GPADC4] = {
		.reg_offset = 2,
		.mask = PM800_GPADC4_INT_ENA3,
	},
	/* INT3 */
	[PM800_IRQ_GPIO0] = {
		.reg_offset = 3,
		.mask = PM800_GPIO0_INT_ENA4,
	},
	[PM800_IRQ_GPIO1] = {
		.reg_offset = 3,
		.mask = PM800_GPIO1_INT_ENA4,
	},
	[PM800_IRQ_GPIO2] = {
		.reg_offset = 3,
		.mask = PM800_GPIO2_INT_ENA4,
	},
	[PM800_IRQ_GPIO3] = {
		.reg_offset = 3,
		.mask = PM800_GPIO3_INT_ENA4,
	},
	[PM800_IRQ_GPIO4] = {
		.reg_offset = 3,
		.mask = PM800_GPIO4_INT_ENA4,
	},
};

static int device_gpadc_init(struct pm80x_chip *chip,
				       struct pm80x_platform_data *pdata)
{
	struct pm80x_subchip *subchip = chip->subchip;
	struct regmap *map = subchip->regmap_gpadc;
	int data = 0, mask = 0, ret = 0;

	if (!map) {
		dev_warn(chip->dev,
			 "Warning: gpadc regmap is not available!\n");
		return -EINVAL;
	}
	/*
	 * initialize GPADC without activating it turn on GPADC
	 * measurments
	 */
	ret = regmap_update_bits(map,
				 PM800_GPADC_MISC_CONFIG2,
				 PM800_GPADC_MISC_GPFSM_EN,
				 PM800_GPADC_MISC_GPFSM_EN);
	if (ret < 0)
		goto out;
	/*
	 * This function configures the ADC as requires for
	 * CP implementation.CP does not "own" the ADC configuration
	 * registers and relies on AP.
	 * Reason: enable automatic ADC measurements needed
	 * for CP to get VBAT and RF temperature readings.
	 */
	ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
				 PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
	if (ret < 0)
		goto out;
	ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
				 (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
				 (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
	if (ret < 0)
		goto out;

	/*
	 * the defult of PM800 is GPADC operates at 100Ks/s rate
	 * and Number of GPADC slots with active current bias prior
	 * to GPADC sampling = 1 slot for all GPADCs set for
	 * Temprature mesurmants
	 */
	mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
		PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);

	if (pdata && (pdata->batt_det == 0))
		data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
			PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
	else
		data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
			PM800_GPADC_GP_BIAS_EN3);

	ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
	if (ret < 0)
		goto out;

	dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
	return 0;

out:
	dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
	return ret;
}

static int device_onkey_init(struct pm80x_chip *chip,
				struct pm80x_platform_data *pdata)
{
	int ret;

	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
			      ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
			      NULL);
	if (ret) {
		dev_err(chip->dev, "Failed to add onkey subdev\n");
		return ret;
	}

	return 0;
}

static int device_rtc_init(struct pm80x_chip *chip,
				struct pm80x_platform_data *pdata)
{
	int ret;

	rtc_devs[0].platform_data = pdata->rtc;
	rtc_devs[0].pdata_size =
			pdata->rtc ? sizeof(struct pm80x_rtc_pdata) : 0;
	ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
			      ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
	if (ret) {
		dev_err(chip->dev, "Failed to add rtc subdev\n");
		return ret;
	}

	return 0;
}

static int device_irq_init_800(struct pm80x_chip *chip)
{
	struct regmap *map = chip->regmap;
	unsigned long flags = IRQF_ONESHOT;
	int data, mask, ret = -EINVAL;

	if (!map || !chip->irq) {
		dev_err(chip->dev, "incorrect parameters\n");
		return -EINVAL;
	}

	/*
	 * irq_mode defines the way of clearing interrupt. it's read-clear by
	 * default.
	 */
	mask =
	    PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
	    PM800_WAKEUP2_INT_MASK;

	data = PM800_WAKEUP2_INT_CLEAR;
	ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);

	if (ret < 0)
		goto out;

	ret =
	    regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
				chip->regmap_irq_chip, &chip->irq_data);

out:
	return ret;
}

static void device_irq_exit_800(struct pm80x_chip *chip)
{
	regmap_del_irq_chip(chip->irq, chip->irq_data);
}

static struct regmap_irq_chip pm800_irq_chip = {
	.name = "88pm800",
	.irqs = pm800_irqs,
	.num_irqs = ARRAY_SIZE(pm800_irqs),

	.num_regs = 4,
	.status_base = PM800_INT_STATUS1,
	.mask_base = PM800_INT_ENA_1,
	.ack_base = PM800_INT_STATUS1,
	.mask_invert = 1,
};

static int pm800_pages_init(struct pm80x_chip *chip)
{
	struct pm80x_subchip *subchip;
	struct i2c_client *client = chip->client;

	int ret = 0;

	subchip = chip->subchip;
	if (!subchip || !subchip->power_page_addr || !subchip->gpadc_page_addr)
		return -ENODEV;

	/* PM800 block power page */
	subchip->power_page = i2c_new_dummy(client->adapter,
					    subchip->power_page_addr);
	if (subchip->power_page == NULL) {
		ret = -ENODEV;
		goto out;
	}

	subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
						     &pm80x_regmap_config);
	if (IS_ERR(subchip->regmap_power)) {
		ret = PTR_ERR(subchip->regmap_power);
		dev_err(chip->dev,
			"Failed to allocate regmap_power: %d\n", ret);
		goto out;
	}

	i2c_set_clientdata(subchip->power_page, chip);

	/* PM800 block GPADC */
	subchip->gpadc_page = i2c_new_dummy(client->adapter,
					    subchip->gpadc_page_addr);
	if (subchip->gpadc_page == NULL) {
		ret = -ENODEV;
		goto out;
	}

	subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
						     &pm80x_regmap_config);
	if (IS_ERR(subchip->regmap_gpadc)) {
		ret = PTR_ERR(subchip->regmap_gpadc);
		dev_err(chip->dev,
			"Failed to allocate regmap_gpadc: %d\n", ret);
		goto out;
	}
	i2c_set_clientdata(subchip->gpadc_page, chip);

out:
	return ret;
}

static void pm800_pages_exit(struct pm80x_chip *chip)
{
	struct pm80x_subchip *subchip;

	subchip = chip->subchip;

	if (subchip && subchip->power_page)
		i2c_unregister_device(subchip->power_page);

	if (subchip && subchip->gpadc_page)
		i2c_unregister_device(subchip->gpadc_page);
}

static int device_800_init(struct pm80x_chip *chip,
				     struct pm80x_platform_data *pdata)
{
	int ret;
	unsigned int val;

	/*
	 * alarm wake up bit will be clear in device_irq_init(),
	 * read before that
	 */
	ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
	if (ret < 0) {
		dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
		goto out;
	}
	if (val & PM800_ALARM_WAKEUP) {
		if (pdata && pdata->rtc)
			pdata->rtc->rtc_wakeup = 1;
	}

	ret = device_gpadc_init(chip, pdata);
	if (ret < 0) {
		dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
		goto out;
	}

	chip->regmap_irq_chip = &pm800_irq_chip;

	ret = device_irq_init_800(chip);
	if (ret < 0) {
		dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
		goto out;
	}

	ret = device_onkey_init(chip, pdata);
	if (ret) {
		dev_err(chip->dev, "Failed to add onkey subdev\n");
		goto out_dev;
	}

	ret = device_rtc_init(chip, pdata);
	if (ret) {
		dev_err(chip->dev, "Failed to add rtc subdev\n");
		goto out;
	}

	return 0;
out_dev:
	mfd_remove_devices(chip->dev);
	device_irq_exit_800(chip);
out:
	return ret;
}

static int pm800_probe(struct i2c_client *client,
				 const struct i2c_device_id *id)
{
	int ret = 0;
	struct pm80x_chip *chip;
	struct pm80x_platform_data *pdata = client->dev.platform_data;
	struct pm80x_subchip *subchip;

	ret = pm80x_init(client);
	if (ret) {
		dev_err(&client->dev, "pm800_init fail\n");
		goto out_init;
	}

	chip = i2c_get_clientdata(client);

	/* init subchip for PM800 */
	subchip =
	    devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
			 GFP_KERNEL);
	if (!subchip) {
		ret = -ENOMEM;
		goto err_subchip_alloc;
	}

	/* pm800 has 2 addtional pages to support power and gpadc. */
	subchip->power_page_addr = client->addr + 1;
	subchip->gpadc_page_addr = client->addr + 2;
	chip->subchip = subchip;

	ret = pm800_pages_init(chip);
	if (ret) {
		dev_err(&client->dev, "pm800_pages_init failed!\n");
		goto err_page_init;
	}

	ret = device_800_init(chip, pdata);
	if (ret) {
		dev_err(chip->dev, "Failed to initialize 88pm800 devices\n");
		goto err_device_init;
	}

	if (pdata->plat_config)
		pdata->plat_config(chip, pdata);

	return 0;

err_device_init:
	pm800_pages_exit(chip);
err_page_init:
err_subchip_alloc:
	pm80x_deinit();
out_init:
	return ret;
}

static int pm800_remove(struct i2c_client *client)
{
	struct pm80x_chip *chip = i2c_get_clientdata(client);

	mfd_remove_devices(chip->dev);
	device_irq_exit_800(chip);

	pm800_pages_exit(chip);
	pm80x_deinit();

	return 0;
}

static struct i2c_driver pm800_driver = {
	.driver = {
		.name = "88PM800",
		.owner = THIS_MODULE,
		.pm = &pm80x_pm_ops,
		},
	.probe = pm800_probe,
	.remove = pm800_remove,
	.id_table = pm80x_id_table,
};

static int __init pm800_i2c_init(void)
{
	return i2c_add_driver(&pm800_driver);
}
subsys_initcall(pm800_i2c_init);

static void __exit pm800_i2c_exit(void)
{
	i2c_del_driver(&pm800_driver);
}
module_exit(pm800_i2c_exit);

MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
70c6cce0 QZ	1	/*
	2	* Base driver for Marvell 88PM800
	3	*
	4	* Copyright (C) 2012 Marvell International Ltd.
	5	* Haojian Zhuang <haojian.zhuang@marvell.com>
	6	* Joseph(Yossi) Hanin <yhanin@marvell.com>
	7	* Qiao Zhou <zhouqiao@marvell.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General
	10	* Public License. See the file "COPYING" in the main directory of this
	11	* archive for more details.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
52705344	25	#include <linux/err.h>
70c6cce0 QZ	26	#include <linux/i2c.h>
	27	#include <linux/mfd/core.h>
	28	#include <linux/mfd/88pm80x.h>
	29	#include <linux/slab.h>
	30
70c6cce0 QZ	31	/* Interrupt Registers */
	32	#define PM800_INT_STATUS1 (0x05)
	33	#define PM800_ONKEY_INT_STS1 (1 << 0)
	34	#define PM800_EXTON_INT_STS1 (1 << 1)
	35	#define PM800_CHG_INT_STS1 (1 << 2)
	36	#define PM800_BAT_INT_STS1 (1 << 3)
	37	#define PM800_RTC_INT_STS1 (1 << 4)
	38	#define PM800_CLASSD_OC_INT_STS1 (1 << 5)
	39
	40	#define PM800_INT_STATUS2 (0x06)
	41	#define PM800_VBAT_INT_STS2 (1 << 0)
	42	#define PM800_VSYS_INT_STS2 (1 << 1)
	43	#define PM800_VCHG_INT_STS2 (1 << 2)
	44	#define PM800_TINT_INT_STS2 (1 << 3)
	45	#define PM800_GPADC0_INT_STS2 (1 << 4)
	46	#define PM800_TBAT_INT_STS2 (1 << 5)
	47	#define PM800_GPADC2_INT_STS2 (1 << 6)
	48	#define PM800_GPADC3_INT_STS2 (1 << 7)
	49
	50	#define PM800_INT_STATUS3 (0x07)
	51
	52	#define PM800_INT_STATUS4 (0x08)
	53	#define PM800_GPIO0_INT_STS4 (1 << 0)
	54	#define PM800_GPIO1_INT_STS4 (1 << 1)
	55	#define PM800_GPIO2_INT_STS4 (1 << 2)
	56	#define PM800_GPIO3_INT_STS4 (1 << 3)
	57	#define PM800_GPIO4_INT_STS4 (1 << 4)
	58
	59	#define PM800_INT_ENA_1 (0x09)
	60	#define PM800_ONKEY_INT_ENA1 (1 << 0)
	61	#define PM800_EXTON_INT_ENA1 (1 << 1)
	62	#define PM800_CHG_INT_ENA1 (1 << 2)
	63	#define PM800_BAT_INT_ENA1 (1 << 3)
	64	#define PM800_RTC_INT_ENA1 (1 << 4)
	65	#define PM800_CLASSD_OC_INT_ENA1 (1 << 5)
	66
	67	#define PM800_INT_ENA_2 (0x0A)
	68	#define PM800_VBAT_INT_ENA2 (1 << 0)
	69	#define PM800_VSYS_INT_ENA2 (1 << 1)
	70	#define PM800_VCHG_INT_ENA2 (1 << 2)
	71	#define PM800_TINT_INT_ENA2 (1 << 3)
	72
	73	#define PM800_INT_ENA_3 (0x0B)
	74	#define PM800_GPADC0_INT_ENA3 (1 << 0)
	75	#define PM800_GPADC1_INT_ENA3 (1 << 1)
	76	#define PM800_GPADC2_INT_ENA3 (1 << 2)
	77	#define PM800_GPADC3_INT_ENA3 (1 << 3)
	78	#define PM800_GPADC4_INT_ENA3 (1 << 4)
	79
	80	#define PM800_INT_ENA_4 (0x0C)
	81	#define PM800_GPIO0_INT_ENA4 (1 << 0)
	82	#define PM800_GPIO1_INT_ENA4 (1 << 1)
	83	#define PM800_GPIO2_INT_ENA4 (1 << 2)
	84	#define PM800_GPIO3_INT_ENA4 (1 << 3)
	85	#define PM800_GPIO4_INT_ENA4 (1 << 4)
	86
	87	/* number of INT_ENA & INT_STATUS regs */
	88	#define PM800_INT_REG_NUM (4)
	89
	90	/* Interrupt Number in 88PM800 */
	91	enum {
	92	PM800_IRQ_ONKEY, /EN1b0 //0 /
	93	PM800_IRQ_EXTON, /EN1b1 /
	94	PM800_IRQ_CHG, /EN1b2 /
95	PM800_IRQ_BAT, /EN1b3 /
96	PM800_IRQ_RTC, /EN1b4 /
97	PM800_IRQ_CLASSD, /EN1b5 //5 /
98	PM800_IRQ_VBAT, /EN2b0 /
99	PM800_IRQ_VSYS, /EN2b1 /
100	PM800_IRQ_VCHG, /EN2b2 /
101	PM800_IRQ_TINT, /EN2b3 /
102	PM800_IRQ_GPADC0, /EN3b0 //10 /
103	PM800_IRQ_GPADC1, /EN3b1 /
104	PM800_IRQ_GPADC2, /EN3b2 /
105	PM800_IRQ_GPADC3, /EN3b3 /
106	PM800_IRQ_GPADC4, /EN3b4 /
107	PM800_IRQ_GPIO0, /EN4b0 //15 /
108	PM800_IRQ_GPIO1, /EN4b1 /
109	PM800_IRQ_GPIO2, /EN4b2 /
110	PM800_IRQ_GPIO3, /EN4b3 /
111	PM800_IRQ_GPIO4, /EN4b4 //19 /
112	PM800_MAX_IRQ,
113	};
114
03dcc544 CX	115	/* PM800: generation identification number */
03dcc544 CX	116	#define PM800_CHIP_GEN_ID_NUM 0x3
70c6cce0 QZ	117
70c6cce0 QZ	118	static const struct i2c_device_id pm80x_id_table[] = {
03dcc544	119	{"88PM800", 0},
31b3ffbd	120	{} /* NULL terminated */
70c6cce0 QZ	121	};
	122	MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
	123
	124	static struct resource rtc_resources[] = {
	125	{
	126	.name = "88pm80x-rtc",
	127	.start = PM800_IRQ_RTC,
	128	.end = PM800_IRQ_RTC,
	129	.flags = IORESOURCE_IRQ,
	130	},
	131	};
	132
	133	static struct mfd_cell rtc_devs[] = {
	134	{
	135	.name = "88pm80x-rtc",
	136	.num_resources = ARRAY_SIZE(rtc_resources),
	137	.resources = &rtc_resources[0],
	138	.id = -1,
	139	},
	140	};
	141
	142	static struct resource onkey_resources[] = {
	143	{
	144	.name = "88pm80x-onkey",
	145	.start = PM800_IRQ_ONKEY,
	146	.end = PM800_IRQ_ONKEY,
	147	.flags = IORESOURCE_IRQ,
	148	},
	149	};
	150
	151	static struct mfd_cell onkey_devs[] = {
	152	{
	153	.name = "88pm80x-onkey",
	154	.num_resources = 1,
	155	.resources = &onkey_resources[0],
	156	.id = -1,
	157	},
	158	};
	159
	160	static const struct regmap_irq pm800_irqs[] = {
	161	/* INT0 */
	162	[PM800_IRQ_ONKEY] = {
	163	.mask = PM800_ONKEY_INT_ENA1,
	164	},
	165	[PM800_IRQ_EXTON] = {
	166	.mask = PM800_EXTON_INT_ENA1,
	167	},
	168	[PM800_IRQ_CHG] = {
	169	.mask = PM800_CHG_INT_ENA1,
	170	},
	171	[PM800_IRQ_BAT] = {
	172	.mask = PM800_BAT_INT_ENA1,
	173	},
	174	[PM800_IRQ_RTC] = {
	175	.mask = PM800_RTC_INT_ENA1,
	176	},
	177	[PM800_IRQ_CLASSD] = {
	178	.mask = PM800_CLASSD_OC_INT_ENA1,
	179	},
	180	/* INT1 */
	181	[PM800_IRQ_VBAT] = {
	182	.reg_offset = 1,
	183	.mask = PM800_VBAT_INT_ENA2,
	184	},
185	[PM800_IRQ_VSYS] = {
186	.reg_offset = 1,
187	.mask = PM800_VSYS_INT_ENA2,
188	},
189	[PM800_IRQ_VCHG] = {
190	.reg_offset = 1,
191	.mask = PM800_VCHG_INT_ENA2,
192	},
193	[PM800_IRQ_TINT] = {
194	.reg_offset = 1,
195	.mask = PM800_TINT_INT_ENA2,
196	},
197	/* INT2 */
198	[PM800_IRQ_GPADC0] = {
199	.reg_offset = 2,
200	.mask = PM800_GPADC0_INT_ENA3,
201	},
202	[PM800_IRQ_GPADC1] = {
203	.reg_offset = 2,
204	.mask = PM800_GPADC1_INT_ENA3,
205	},
206	[PM800_IRQ_GPADC2] = {
207	.reg_offset = 2,
208	.mask = PM800_GPADC2_INT_ENA3,
209	},
210	[PM800_IRQ_GPADC3] = {
211	.reg_offset = 2,
212	.mask = PM800_GPADC3_INT_ENA3,
213	},
214	[PM800_IRQ_GPADC4] = {
215	.reg_offset = 2,
216	.mask = PM800_GPADC4_INT_ENA3,
217	},
218	/* INT3 */
219	[PM800_IRQ_GPIO0] = {
220	.reg_offset = 3,
221	.mask = PM800_GPIO0_INT_ENA4,
222	},
223	[PM800_IRQ_GPIO1] = {
224	.reg_offset = 3,
225	.mask = PM800_GPIO1_INT_ENA4,
226	},
227	[PM800_IRQ_GPIO2] = {
228	.reg_offset = 3,
229	.mask = PM800_GPIO2_INT_ENA4,
230	},
231	[PM800_IRQ_GPIO3] = {
232	.reg_offset = 3,
233	.mask = PM800_GPIO3_INT_ENA4,
234	},
235	[PM800_IRQ_GPIO4] = {
236	.reg_offset = 3,
237	.mask = PM800_GPIO4_INT_ENA4,
238	},
239	};
240
f791be49	241	static int device_gpadc_init(struct pm80x_chip *chip,
70c6cce0 QZ	242	struct pm80x_platform_data *pdata)
	243	{
	244	struct pm80x_subchip *subchip = chip->subchip;
	245	struct regmap *map = subchip->regmap_gpadc;
	246	int data = 0, mask = 0, ret = 0;
	247
	248	if (!map) {
	249	dev_warn(chip->dev,
	250	"Warning: gpadc regmap is not available!\n");
	251	return -EINVAL;
	252	}
	253	/*
	254	* initialize GPADC without activating it turn on GPADC
	255	* measurments
	256	*/
	257	ret = regmap_update_bits(map,
	258	PM800_GPADC_MISC_CONFIG2,
	259	PM800_GPADC_MISC_GPFSM_EN,
	260	PM800_GPADC_MISC_GPFSM_EN);
	261	if (ret < 0)
	262	goto out;
	263	/*
	264	* This function configures the ADC as requires for
	265	* CP implementation.CP does not "own" the ADC configuration
	266	* registers and relies on AP.
	267	* Reason: enable automatic ADC measurements needed
	268	* for CP to get VBAT and RF temperature readings.
	269	*/
	270	ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
	271	PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
	272	if (ret < 0)
	273	goto out;
	274	ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
	275	(PM800_MEAS_EN2_RFTMP \| PM800_MEAS_GP0_EN),
	276	(PM800_MEAS_EN2_RFTMP \| PM800_MEAS_GP0_EN));
	277	if (ret < 0)
	278	goto out;
	279
	280	/*
	281	* the defult of PM800 is GPADC operates at 100Ks/s rate
	282	* and Number of GPADC slots with active current bias prior
	283	* to GPADC sampling = 1 slot for all GPADCs set for
	284	* Temprature mesurmants
	285	*/
	286	mask = (PM800_GPADC_GP_BIAS_EN0 \| PM800_GPADC_GP_BIAS_EN1 \|
	287	PM800_GPADC_GP_BIAS_EN2 \| PM800_GPADC_GP_BIAS_EN3);
	288
	289	if (pdata && (pdata->batt_det == 0))
	290	data = (PM800_GPADC_GP_BIAS_EN0 \| PM800_GPADC_GP_BIAS_EN1 \|
	291	PM800_GPADC_GP_BIAS_EN2 \| PM800_GPADC_GP_BIAS_EN3);
	292	else
	293	data = (PM800_GPADC_GP_BIAS_EN0 \| PM800_GPADC_GP_BIAS_EN2 \|
	294	PM800_GPADC_GP_BIAS_EN3);
	295
	296	ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
	297	if (ret < 0)
	298	goto out;
	299
	300	dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
	301	return 0;
	302
	303	out:
	304	dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
	305	return ret;
306	}
307
3a3ece54 CX	308	static int device_onkey_init(struct pm80x_chip *chip,
	309	struct pm80x_platform_data *pdata)
	310	{
	311	int ret;
	312
	313	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
	314	ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
	315	NULL);
	316	if (ret) {
	317	dev_err(chip->dev, "Failed to add onkey subdev\n");
	318	return ret;
	319	}
	320
	321	return 0;
	322	}
	323
	324	static int device_rtc_init(struct pm80x_chip *chip,
	325	struct pm80x_platform_data *pdata)
	326	{
	327	int ret;
	328
	329	rtc_devs[0].platform_data = pdata->rtc;
	330	rtc_devs[0].pdata_size =
	331	pdata->rtc ? sizeof(struct pm80x_rtc_pdata) : 0;
	332	ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
	333	ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
	334	if (ret) {
	335	dev_err(chip->dev, "Failed to add rtc subdev\n");
	336	return ret;
	337	}
	338
	339	return 0;
	340	}
	341
f791be49	342	static int device_irq_init_800(struct pm80x_chip *chip)
70c6cce0 QZ	343	{
70c6cce0 QZ	344	struct regmap *map = chip->regmap;
1ef5677e	345	unsigned long flags = IRQF_ONESHOT;
70c6cce0 QZ	346	int data, mask, ret = -EINVAL;
	347
	348	if (!map \|\| !chip->irq) {
	349	dev_err(chip->dev, "incorrect parameters\n");
	350	return -EINVAL;
	351	}
	352
	353	/*
	354	* irq_mode defines the way of clearing interrupt. it's read-clear by
	355	* default.
	356	*/
	357	mask =
	358	PM800_WAKEUP2_INV_INT \| PM800_WAKEUP2_INT_CLEAR \|
	359	PM800_WAKEUP2_INT_MASK;
	360
	361	data = PM800_WAKEUP2_INT_CLEAR;
	362	ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
	363
	364	if (ret < 0)
	365	goto out;
	366
	367	ret =
	368	regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
	369	chip->regmap_irq_chip, &chip->irq_data);
	370
	371	out:
	372	return ret;
	373	}
	374
	375	static void device_irq_exit_800(struct pm80x_chip *chip)
	376	{
	377	regmap_del_irq_chip(chip->irq, chip->irq_data);
	378	}
	379
	380	static struct regmap_irq_chip pm800_irq_chip = {
	381	.name = "88pm800",
	382	.irqs = pm800_irqs,
	383	.num_irqs = ARRAY_SIZE(pm800_irqs),
	384
	385	.num_regs = 4,
	386	.status_base = PM800_INT_STATUS1,
	387	.mask_base = PM800_INT_ENA_1,
	388	.ack_base = PM800_INT_STATUS1,
cb5c5800	389	.mask_invert = 1,
70c6cce0 QZ	390	};
	391
	392	static int pm800_pages_init(struct pm80x_chip *chip)
	393	{
	394	struct pm80x_subchip *subchip;
	395	struct i2c_client *client = chip->client;
	396
52705344 CX	397	int ret = 0;
52705344 CX	398
70c6cce0	399	subchip = chip->subchip;
52705344 CX	400	if (!subchip \|\| !subchip->power_page_addr \|\| !subchip->gpadc_page_addr)
	401	return -ENODEV;
	402
	403	/* PM800 block power page */
	404	subchip->power_page = i2c_new_dummy(client->adapter,
	405	subchip->power_page_addr);
	406	if (subchip->power_page == NULL) {
	407	ret = -ENODEV;
	408	goto out;
	409	}
70c6cce0	410
52705344 CX	411	subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
	412	&pm80x_regmap_config);
	413	if (IS_ERR(subchip->regmap_power)) {
	414	ret = PTR_ERR(subchip->regmap_power);
	415	dev_err(chip->dev,
	416	"Failed to allocate regmap_power: %d\n", ret);
	417	goto out;
	418	}
	419
	420	i2c_set_clientdata(subchip->power_page, chip);
	421
	422	/* PM800 block GPADC */
	423	subchip->gpadc_page = i2c_new_dummy(client->adapter,
	424	subchip->gpadc_page_addr);
	425	if (subchip->gpadc_page == NULL) {
	426	ret = -ENODEV;
	427	goto out;
	428	}
	429
	430	subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
	431	&pm80x_regmap_config);
	432	if (IS_ERR(subchip->regmap_gpadc)) {
	433	ret = PTR_ERR(subchip->regmap_gpadc);
	434	dev_err(chip->dev,
	435	"Failed to allocate regmap_gpadc: %d\n", ret);
	436	goto out;
	437	}
	438	i2c_set_clientdata(subchip->gpadc_page, chip);
	439
	440	out:
	441	return ret;
70c6cce0 QZ	442	}
	443
	444	static void pm800_pages_exit(struct pm80x_chip *chip)
	445	{
	446	struct pm80x_subchip *subchip;
	447
70c6cce0	448	subchip = chip->subchip;
52705344 CX	449
52705344 CX	450	if (subchip && subchip->power_page)
70c6cce0	451	i2c_unregister_device(subchip->power_page);
52705344 CX	452
52705344 CX	453	if (subchip && subchip->gpadc_page)
70c6cce0	454	i2c_unregister_device(subchip->gpadc_page);
70c6cce0 QZ	455	}
70c6cce0 QZ	456
f791be49	457	static int device_800_init(struct pm80x_chip *chip,
70c6cce0 QZ	458	struct pm80x_platform_data *pdata)
70c6cce0 QZ	459	{
03dcc544	460	int ret;
46b65a8f	461	unsigned int val;
70c6cce0	462
70c6cce0 QZ	463	/*
	464	* alarm wake up bit will be clear in device_irq_init(),
	465	* read before that
	466	*/
46b65a8f	467	ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
70c6cce0 QZ	468	if (ret < 0) {
	469	dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
	470	goto out;
	471	}
46b65a8f	472	if (val & PM800_ALARM_WAKEUP) {
70c6cce0 QZ	473	if (pdata && pdata->rtc)
	474	pdata->rtc->rtc_wakeup = 1;
	475	}
	476
	477	ret = device_gpadc_init(chip, pdata);
	478	if (ret < 0) {
	479	dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
	480	goto out;
	481	}
	482
	483	chip->regmap_irq_chip = &pm800_irq_chip;
	484
	485	ret = device_irq_init_800(chip);
	486	if (ret < 0) {
	487	dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
	488	goto out;
	489	}
	490
3a3ece54 CX	491	ret = device_onkey_init(chip, pdata);
3a3ece54 CX	492	if (ret) {
70c6cce0 QZ	493	dev_err(chip->dev, "Failed to add onkey subdev\n");
70c6cce0 QZ	494	goto out_dev;
3a3ece54 CX	495	}
	496
	497	ret = device_rtc_init(chip, pdata);
	498	if (ret) {
	499	dev_err(chip->dev, "Failed to add rtc subdev\n");
	500	goto out;
70c6cce0 QZ	501	}
	502
	503	return 0;
	504	out_dev:
	505	mfd_remove_devices(chip->dev);
	506	device_irq_exit_800(chip);
	507	out:
	508	return ret;
	509	}
	510
f791be49	511	static int pm800_probe(struct i2c_client *client,
70c6cce0 QZ	512	const struct i2c_device_id *id)
	513	{
	514	int ret = 0;
	515	struct pm80x_chip *chip;
	516	struct pm80x_platform_data *pdata = client->dev.platform_data;
	517	struct pm80x_subchip *subchip;
	518
03dcc544	519	ret = pm80x_init(client);
70c6cce0 QZ	520	if (ret) {
	521	dev_err(&client->dev, "pm800_init fail\n");
	522	goto out_init;
	523	}
	524
	525	chip = i2c_get_clientdata(client);
	526
	527	/* init subchip for PM800 */
	528	subchip =
	529	devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
	530	GFP_KERNEL);
	531	if (!subchip) {
	532	ret = -ENOMEM;
	533	goto err_subchip_alloc;
	534	}
	535
c750d8e0 CX	536	/* pm800 has 2 addtional pages to support power and gpadc. */
	537	subchip->power_page_addr = client->addr + 1;
	538	subchip->gpadc_page_addr = client->addr + 2;
70c6cce0 QZ	539	chip->subchip = subchip;
70c6cce0 QZ	540
70c6cce0 QZ	541	ret = pm800_pages_init(chip);
	542	if (ret) {
	543	dev_err(&client->dev, "pm800_pages_init failed!\n");
	544	goto err_page_init;
	545	}
	546
618fa575 YZ	547	ret = device_800_init(chip, pdata);
618fa575 YZ	548	if (ret) {
03dcc544	549	dev_err(chip->dev, "Failed to initialize 88pm800 devices\n");
618fa575 YZ	550	goto err_device_init;
	551	}
	552
70c6cce0 QZ	553	if (pdata->plat_config)
	554	pdata->plat_config(chip, pdata);
	555
618fa575 YZ	556	return 0;
	557
	558	err_device_init:
	559	pm800_pages_exit(chip);
70c6cce0	560	err_page_init:
70c6cce0	561	err_subchip_alloc:
306df798	562	pm80x_deinit();
70c6cce0 QZ	563	out_init:
	564	return ret;
	565	}
	566
4740f73f	567	static int pm800_remove(struct i2c_client *client)
70c6cce0 QZ	568	{
	569	struct pm80x_chip *chip = i2c_get_clientdata(client);
	570
	571	mfd_remove_devices(chip->dev);
	572	device_irq_exit_800(chip);
	573
	574	pm800_pages_exit(chip);
306df798	575	pm80x_deinit();
70c6cce0 QZ	576
	577	return 0;
	578	}
	579
	580	static struct i2c_driver pm800_driver = {
	581	.driver = {
46223a19	582	.name = "88PM800",
70c6cce0 QZ	583	.owner = THIS_MODULE,
	584	.pm = &pm80x_pm_ops,
	585	},
	586	.probe = pm800_probe,
84449216	587	.remove = pm800_remove,
70c6cce0 QZ	588	.id_table = pm80x_id_table,
	589	};
	590
	591	static int __init pm800_i2c_init(void)
	592	{
	593	return i2c_add_driver(&pm800_driver);
	594	}
	595	subsys_initcall(pm800_i2c_init);
	596
	597	static void __exit pm800_i2c_exit(void)
	598	{
	599	i2c_del_driver(&pm800_driver);
	600	}
	601	module_exit(pm800_i2c_exit);
	602
	603	MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
	604	MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
	605	MODULE_LICENSE("GPL");