[linux-2.6-block.git] / drivers / memstick / host / rtsx_pci_ms.c

// SPDX-License-Identifier: GPL-2.0-or-later
/* Realtek PCI-Express Memstick Card Interface driver
 *
 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
 *
 * Author:
 *   Wei WANG <wei_wang@realsil.com.cn>
 */

#include <linux/module.h>
#include <linux/highmem.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/memstick.h>
#include <linux/rtsx_pci.h>
#include <asm/unaligned.h>

struct realtek_pci_ms {
	struct platform_device	*pdev;
	struct rtsx_pcr		*pcr;
	struct memstick_host	*msh;
	struct memstick_request	*req;

	struct mutex		host_mutex;
	struct work_struct	handle_req;

	u8			ssc_depth;
	unsigned int		clock;
	unsigned char           ifmode;
	bool			eject;
};

static inline struct device *ms_dev(struct realtek_pci_ms *host)
{
	return &(host->pdev->dev);
}

static inline void ms_clear_error(struct realtek_pci_ms *host)
{
	rtsx_pci_write_register(host->pcr, CARD_STOP,
			MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
}

#ifdef DEBUG

static void ms_print_debug_regs(struct realtek_pci_ms *host)
{
	struct rtsx_pcr *pcr = host->pcr;
	u16 i;
	u8 *ptr;

	/* Print MS host internal registers */
	rtsx_pci_init_cmd(pcr);
	for (i = 0xFD40; i <= 0xFD44; i++)
		rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
	for (i = 0xFD52; i <= 0xFD69; i++)
		rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
	rtsx_pci_send_cmd(pcr, 100);

	ptr = rtsx_pci_get_cmd_data(pcr);
	for (i = 0xFD40; i <= 0xFD44; i++)
		dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
	for (i = 0xFD52; i <= 0xFD69; i++)
		dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
}

#else

#define ms_print_debug_regs(host)

#endif

static int ms_power_on(struct realtek_pci_ms *host)
{
	struct rtsx_pcr *pcr = host->pcr;
	int err;

	rtsx_pci_init_cmd(pcr);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, MS_MOD_SEL);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
			CARD_SHARE_MASK, CARD_SHARE_48_MS);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
			MS_CLK_EN, MS_CLK_EN);
	err = rtsx_pci_send_cmd(pcr, 100);
	if (err < 0)
		return err;

	err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_MS_CARD);
	if (err < 0)
		return err;

	err = rtsx_pci_card_power_on(pcr, RTSX_MS_CARD);
	if (err < 0)
		return err;

	/* Wait ms power stable */
	msleep(150);

	err = rtsx_pci_write_register(pcr, CARD_OE,
			MS_OUTPUT_EN, MS_OUTPUT_EN);
	if (err < 0)
		return err;

	return 0;
}

static int ms_power_off(struct realtek_pci_ms *host)
{
	struct rtsx_pcr *pcr = host->pcr;
	int err;

	rtsx_pci_init_cmd(pcr);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);

	err = rtsx_pci_send_cmd(pcr, 100);
	if (err < 0)
		return err;

	err = rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
	if (err < 0)
		return err;

	return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
}

static int ms_transfer_data(struct realtek_pci_ms *host, unsigned char data_dir,
		u8 tpc, u8 cfg, struct scatterlist *sg)
{
	struct rtsx_pcr *pcr = host->pcr;
	int err;
	unsigned int length = sg->length;
	u16 sec_cnt = (u16)(length / 512);
	u8 val, trans_mode, dma_dir;
	struct memstick_dev *card = host->msh->card;
	bool pro_card = card->id.type == MEMSTICK_TYPE_PRO;

	dev_dbg(ms_dev(host), "%s: tpc = 0x%02x, data_dir = %s, length = %d\n",
			__func__, tpc, (data_dir == READ) ? "READ" : "WRITE",
			length);

	if (data_dir == READ) {
		dma_dir = DMA_DIR_FROM_CARD;
		trans_mode = pro_card ? MS_TM_AUTO_READ : MS_TM_NORMAL_READ;
	} else {
		dma_dir = DMA_DIR_TO_CARD;
		trans_mode = pro_card ? MS_TM_AUTO_WRITE : MS_TM_NORMAL_WRITE;
	}

	rtsx_pci_init_cmd(pcr);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
	if (pro_card) {
		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_SECTOR_CNT_H,
				0xFF, (u8)(sec_cnt >> 8));
		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_SECTOR_CNT_L,
				0xFF, (u8)sec_cnt);
	}
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
			DMA_DONE_INT, DMA_DONE_INT);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(length >> 24));
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(length >> 16));
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(length >> 8));
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)length);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
			0x03 | DMA_PACK_SIZE_MASK, dma_dir | DMA_EN | DMA_512);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
			0x01, RING_BUFFER);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
			0xFF, MS_TRANSFER_START | trans_mode);
	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
			MS_TRANSFER_END, MS_TRANSFER_END);

	rtsx_pci_send_cmd_no_wait(pcr);

	err = rtsx_pci_transfer_data(pcr, sg, 1, data_dir == READ, 10000);
	if (err < 0) {
		ms_clear_error(host);
		return err;
	}

	rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
	if (pro_card) {
		if (val & (MS_INT_CMDNK | MS_INT_ERR |
				MS_CRC16_ERR | MS_RDY_TIMEOUT))
			return -EIO;
	} else {
		if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT))
			return -EIO;
	}

	return 0;
}

static int ms_write_bytes(struct realtek_pci_ms *host, u8 tpc,
		u8 cfg, u8 cnt, u8 *data, u8 *int_reg)
{
	struct rtsx_pcr *pcr = host->pcr;
	int err, i;

	dev_dbg(ms_dev(host), "%s: tpc = 0x%02x\n", __func__, tpc);

	if (!data)
		return -EINVAL;

	rtsx_pci_init_cmd(pcr);

	for (i = 0; i < cnt; i++)
		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
				PPBUF_BASE2 + i, 0xFF, data[i]);
	if (cnt % 2)
		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
				PPBUF_BASE2 + i, 0xFF, 0xFF);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
			0x01, PINGPONG_BUFFER);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
			0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
			MS_TRANSFER_END, MS_TRANSFER_END);
	if (int_reg)
		rtsx_pci_add_cmd(pcr, READ_REG_CMD, MS_TRANS_CFG, 0, 0);

	err = rtsx_pci_send_cmd(pcr, 5000);
	if (err < 0) {
		u8 val;

		rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
		dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val);

		if (int_reg)
			*int_reg = val & 0x0F;

		ms_print_debug_regs(host);

		ms_clear_error(host);

		if (!(tpc & 0x08)) {
			if (val & MS_CRC16_ERR)
				return -EIO;
		} else {
			if (!(val & 0x80)) {
				if (val & (MS_INT_ERR | MS_INT_CMDNK))
					return -EIO;
			}
		}

		return -ETIMEDOUT;
	}

	if (int_reg) {
		u8 *ptr = rtsx_pci_get_cmd_data(pcr) + 1;
		*int_reg = *ptr & 0x0F;
	}

	return 0;
}

static int ms_read_bytes(struct realtek_pci_ms *host, u8 tpc,
		u8 cfg, u8 cnt, u8 *data, u8 *int_reg)
{
	struct rtsx_pcr *pcr = host->pcr;
	int err, i;
	u8 *ptr;

	dev_dbg(ms_dev(host), "%s: tpc = 0x%02x\n", __func__, tpc);

	if (!data)
		return -EINVAL;

	rtsx_pci_init_cmd(pcr);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
			0x01, PINGPONG_BUFFER);

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
			0xFF, MS_TRANSFER_START | MS_TM_READ_BYTES);
	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
			MS_TRANSFER_END, MS_TRANSFER_END);
	for (i = 0; i < cnt - 1; i++)
		rtsx_pci_add_cmd(pcr, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
	if (cnt % 2)
		rtsx_pci_add_cmd(pcr, READ_REG_CMD, PPBUF_BASE2 + cnt, 0, 0);
	else
		rtsx_pci_add_cmd(pcr, READ_REG_CMD,
				PPBUF_BASE2 + cnt - 1, 0, 0);
	if (int_reg)
		rtsx_pci_add_cmd(pcr, READ_REG_CMD, MS_TRANS_CFG, 0, 0);

	err = rtsx_pci_send_cmd(pcr, 5000);
	if (err < 0) {
		u8 val;

		rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
		dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val);

		if (int_reg)
			*int_reg = val & 0x0F;

		ms_print_debug_regs(host);

		ms_clear_error(host);

		if (!(tpc & 0x08)) {
			if (val & MS_CRC16_ERR)
				return -EIO;
		} else {
			if (!(val & 0x80)) {
				if (val & (MS_INT_ERR | MS_INT_CMDNK))
					return -EIO;
			}
		}

		return -ETIMEDOUT;
	}

	ptr = rtsx_pci_get_cmd_data(pcr) + 1;
	for (i = 0; i < cnt; i++)
		data[i] = *ptr++;

	if (int_reg)
		*int_reg = *ptr & 0x0F;

	return 0;
}

static int rtsx_pci_ms_issue_cmd(struct realtek_pci_ms *host)
{
	struct memstick_request *req = host->req;
	int err = 0;
	u8 cfg = 0, int_reg;

	dev_dbg(ms_dev(host), "%s\n", __func__);

	if (req->need_card_int) {
		if (host->ifmode != MEMSTICK_SERIAL)
			cfg = WAIT_INT;
	}

	if (req->long_data) {
		err = ms_transfer_data(host, req->data_dir,
				req->tpc, cfg, &(req->sg));
	} else {
		if (req->data_dir == READ) {
			err = ms_read_bytes(host, req->tpc, cfg,
					req->data_len, req->data, &int_reg);
		} else {
			err = ms_write_bytes(host, req->tpc, cfg,
					req->data_len, req->data, &int_reg);
		}
	}
	if (err < 0)
		return err;

	if (req->need_card_int && (host->ifmode == MEMSTICK_SERIAL)) {
		err = ms_read_bytes(host, MS_TPC_GET_INT,
				NO_WAIT_INT, 1, &int_reg, NULL);
		if (err < 0)
			return err;
	}

	if (req->need_card_int) {
		dev_dbg(ms_dev(host), "int_reg: 0x%02x\n", int_reg);

		if (int_reg & MS_INT_CMDNK)
			req->int_reg |= MEMSTICK_INT_CMDNAK;
		if (int_reg & MS_INT_BREQ)
			req->int_reg |= MEMSTICK_INT_BREQ;
		if (int_reg & MS_INT_ERR)
			req->int_reg |= MEMSTICK_INT_ERR;
		if (int_reg & MS_INT_CED)
			req->int_reg |= MEMSTICK_INT_CED;
	}

	return 0;
}

static void rtsx_pci_ms_handle_req(struct work_struct *work)
{
	struct realtek_pci_ms *host = container_of(work,
			struct realtek_pci_ms, handle_req);
	struct rtsx_pcr *pcr = host->pcr;
	struct memstick_host *msh = host->msh;
	int rc;

	mutex_lock(&pcr->pcr_mutex);

	rtsx_pci_start_run(pcr);

	rtsx_pci_switch_clock(host->pcr, host->clock, host->ssc_depth,
			false, true, false);
	rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, MS_MOD_SEL);
	rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
			CARD_SHARE_MASK, CARD_SHARE_48_MS);

	if (!host->req) {
		do {
			rc = memstick_next_req(msh, &host->req);
			dev_dbg(ms_dev(host), "next req %d\n", rc);

			if (!rc)
				host->req->error = rtsx_pci_ms_issue_cmd(host);
		} while (!rc);
	}

	mutex_unlock(&pcr->pcr_mutex);
}

static void rtsx_pci_ms_request(struct memstick_host *msh)
{
	struct realtek_pci_ms *host = memstick_priv(msh);

	dev_dbg(ms_dev(host), "--> %s\n", __func__);

	if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_MS_CARD))
		return;

	schedule_work(&host->handle_req);
}

static int rtsx_pci_ms_set_param(struct memstick_host *msh,
		enum memstick_param param, int value)
{
	struct realtek_pci_ms *host = memstick_priv(msh);
	struct rtsx_pcr *pcr = host->pcr;
	unsigned int clock = 0;
	u8 ssc_depth = 0;
	int err;

	dev_dbg(ms_dev(host), "%s: param = %d, value = %d\n",
			__func__, param, value);

	err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_MS_CARD);
	if (err)
		return err;

	switch (param) {
	case MEMSTICK_POWER:
		if (value == MEMSTICK_POWER_ON)
			err = ms_power_on(host);
		else if (value == MEMSTICK_POWER_OFF)
			err = ms_power_off(host);
		else
			return -EINVAL;
		break;

	case MEMSTICK_INTERFACE:
		if (value == MEMSTICK_SERIAL) {
			clock = 19000000;
			ssc_depth = RTSX_SSC_DEPTH_500K;

			err = rtsx_pci_write_register(pcr, MS_CFG, 0x58,
					MS_BUS_WIDTH_1 | PUSH_TIME_DEFAULT);
			if (err < 0)
				return err;
		} else if (value == MEMSTICK_PAR4) {
			clock = 39000000;
			ssc_depth = RTSX_SSC_DEPTH_1M;

			err = rtsx_pci_write_register(pcr, MS_CFG,
					0x58, MS_BUS_WIDTH_4 | PUSH_TIME_ODD);
			if (err < 0)
				return err;
		} else {
			return -EINVAL;
		}

		err = rtsx_pci_switch_clock(pcr, clock,
				ssc_depth, false, true, false);
		if (err < 0)
			return err;

		host->ssc_depth = ssc_depth;
		host->clock = clock;
		host->ifmode = value;
		break;
	}

	return 0;
}

#ifdef CONFIG_PM

static int rtsx_pci_ms_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct realtek_pci_ms *host = platform_get_drvdata(pdev);
	struct memstick_host *msh = host->msh;

	dev_dbg(ms_dev(host), "--> %s\n", __func__);

	memstick_suspend_host(msh);
	return 0;
}

static int rtsx_pci_ms_resume(struct platform_device *pdev)
{
	struct realtek_pci_ms *host = platform_get_drvdata(pdev);
	struct memstick_host *msh = host->msh;

	dev_dbg(ms_dev(host), "--> %s\n", __func__);

	memstick_resume_host(msh);
	return 0;
}

#else /* CONFIG_PM */

#define rtsx_pci_ms_suspend NULL
#define rtsx_pci_ms_resume NULL

#endif /* CONFIG_PM */

static void rtsx_pci_ms_card_event(struct platform_device *pdev)
{
	struct realtek_pci_ms *host = platform_get_drvdata(pdev);

	memstick_detect_change(host->msh);
}

static int rtsx_pci_ms_drv_probe(struct platform_device *pdev)
{
	struct memstick_host *msh;
	struct realtek_pci_ms *host;
	struct rtsx_pcr *pcr;
	struct pcr_handle *handle = pdev->dev.platform_data;
	int rc;

	if (!handle)
		return -ENXIO;

	pcr = handle->pcr;
	if (!pcr)
		return -ENXIO;

	dev_dbg(&(pdev->dev),
			": Realtek PCI-E Memstick controller found\n");

	msh = memstick_alloc_host(sizeof(*host), &pdev->dev);
	if (!msh)
		return -ENOMEM;

	host = memstick_priv(msh);
	host->pcr = pcr;
	host->msh = msh;
	host->pdev = pdev;
	platform_set_drvdata(pdev, host);
	pcr->slots[RTSX_MS_CARD].p_dev = pdev;
	pcr->slots[RTSX_MS_CARD].card_event = rtsx_pci_ms_card_event;

	mutex_init(&host->host_mutex);

	INIT_WORK(&host->handle_req, rtsx_pci_ms_handle_req);
	msh->request = rtsx_pci_ms_request;
	msh->set_param = rtsx_pci_ms_set_param;
	msh->caps = MEMSTICK_CAP_PAR4;

	rc = memstick_add_host(msh);
	if (rc) {
		memstick_free_host(msh);
		return rc;
	}

	return 0;
}

static int rtsx_pci_ms_drv_remove(struct platform_device *pdev)
{
	struct realtek_pci_ms *host = platform_get_drvdata(pdev);
	struct rtsx_pcr *pcr;
	struct memstick_host *msh;
	int rc;

	pcr = host->pcr;
	pcr->slots[RTSX_MS_CARD].p_dev = NULL;
	pcr->slots[RTSX_MS_CARD].card_event = NULL;
	msh = host->msh;
	host->eject = true;
	cancel_work_sync(&host->handle_req);

	mutex_lock(&host->host_mutex);
	if (host->req) {
		dev_dbg(&(pdev->dev),
			"%s: Controller removed during transfer\n",
			dev_name(&msh->dev));

		rtsx_pci_complete_unfinished_transfer(pcr);

		host->req->error = -ENOMEDIUM;
		do {
			rc = memstick_next_req(msh, &host->req);
			if (!rc)
				host->req->error = -ENOMEDIUM;
		} while (!rc);
	}
	mutex_unlock(&host->host_mutex);

	memstick_remove_host(msh);
	memstick_free_host(msh);

	dev_dbg(&(pdev->dev),
		": Realtek PCI-E Memstick controller has been removed\n");

	return 0;
}

static struct platform_device_id rtsx_pci_ms_ids[] = {
	{
		.name = DRV_NAME_RTSX_PCI_MS,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, rtsx_pci_ms_ids);

static struct platform_driver rtsx_pci_ms_driver = {
	.probe		= rtsx_pci_ms_drv_probe,
	.remove		= rtsx_pci_ms_drv_remove,
	.id_table       = rtsx_pci_ms_ids,
	.suspend	= rtsx_pci_ms_suspend,
	.resume		= rtsx_pci_ms_resume,
	.driver		= {
		.name	= DRV_NAME_RTSX_PCI_MS,
	},
};
module_platform_driver(rtsx_pci_ms_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
MODULE_DESCRIPTION("Realtek PCI-E Memstick Card Host Driver");
Commit	Line	Data
aaf4989b	1	// SPDX-License-Identifier: GPL-2.0-or-later
b902dd4e WW	2	/* Realtek PCI-Express Memstick Card Interface driver
b902dd4e WW	3	*
62282180	4	* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
b902dd4e	5	*
b902dd4e WW	6	* Author:
b902dd4e WW	7	* Wei WANG <wei_wang@realsil.com.cn>
b902dd4e WW	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/highmem.h>
	12	#include <linux/delay.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/memstick.h>
e455b69d	15	#include <linux/rtsx_pci.h>
b902dd4e WW	16	#include <asm/unaligned.h>
	17
	18	struct realtek_pci_ms {
	19	struct platform_device *pdev;
	20	struct rtsx_pcr *pcr;
	21	struct memstick_host *msh;
	22	struct memstick_request *req;
	23
	24	struct mutex host_mutex;
	25	struct work_struct handle_req;
	26
	27	u8 ssc_depth;
	28	unsigned int clock;
	29	unsigned char ifmode;
	30	bool eject;
	31	};
	32
	33	static inline struct device ms_dev(struct realtek_pci_ms host)
	34	{
	35	return &(host->pdev->dev);
	36	}
	37
	38	static inline void ms_clear_error(struct realtek_pci_ms *host)
	39	{
	40	rtsx_pci_write_register(host->pcr, CARD_STOP,
	41	MS_STOP \| MS_CLR_ERR, MS_STOP \| MS_CLR_ERR);
	42	}
	43
	44	#ifdef DEBUG
	45
	46	static void ms_print_debug_regs(struct realtek_pci_ms *host)
	47	{
	48	struct rtsx_pcr *pcr = host->pcr;
	49	u16 i;
	50	u8 *ptr;
	51
	52	/* Print MS host internal registers */
	53	rtsx_pci_init_cmd(pcr);
	54	for (i = 0xFD40; i <= 0xFD44; i++)
	55	rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
	56	for (i = 0xFD52; i <= 0xFD69; i++)
	57	rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
	58	rtsx_pci_send_cmd(pcr, 100);
	59
	60	ptr = rtsx_pci_get_cmd_data(pcr);
	61	for (i = 0xFD40; i <= 0xFD44; i++)
	62	dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
	63	for (i = 0xFD52; i <= 0xFD69; i++)
	64	dev_dbg(ms_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
	65	}
	66
	67	#else
	68
	69	#define ms_print_debug_regs(host)
	70
	71	#endif
	72
	73	static int ms_power_on(struct realtek_pci_ms *host)
	74	{
	75	struct rtsx_pcr *pcr = host->pcr;
	76	int err;
	77
	78	rtsx_pci_init_cmd(pcr);
	79	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, MS_MOD_SEL);
80	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
81	CARD_SHARE_MASK, CARD_SHARE_48_MS);
82	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
83	MS_CLK_EN, MS_CLK_EN);
84	err = rtsx_pci_send_cmd(pcr, 100);
85	if (err < 0)
86	return err;
87
88	err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_MS_CARD);
89	if (err < 0)
90	return err;
91
92	err = rtsx_pci_card_power_on(pcr, RTSX_MS_CARD);
93	if (err < 0)
94	return err;
95
96	/* Wait ms power stable */
97	msleep(150);
98
99	err = rtsx_pci_write_register(pcr, CARD_OE,
100	MS_OUTPUT_EN, MS_OUTPUT_EN);
101	if (err < 0)
102	return err;
103
104	return 0;
105	}
106
107	static int ms_power_off(struct realtek_pci_ms *host)
108	{
109	struct rtsx_pcr *pcr = host->pcr;
110	int err;
111
112	rtsx_pci_init_cmd(pcr);
113
114	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
115	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
116
117	err = rtsx_pci_send_cmd(pcr, 100);
118	if (err < 0)
119	return err;
120
121	err = rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
122	if (err < 0)
123	return err;
124
125	return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
126	}
127
128	static int ms_transfer_data(struct realtek_pci_ms *host, unsigned char data_dir,
129	u8 tpc, u8 cfg, struct scatterlist *sg)
130	{
131	struct rtsx_pcr *pcr = host->pcr;
132	int err;
133	unsigned int length = sg->length;
134	u16 sec_cnt = (u16)(length / 512);
135	u8 val, trans_mode, dma_dir;
63509bea MC	136	struct memstick_dev *card = host->msh->card;
63509bea MC	137	bool pro_card = card->id.type == MEMSTICK_TYPE_PRO;
b902dd4e WW	138
	139	dev_dbg(ms_dev(host), "%s: tpc = 0x%02x, data_dir = %s, length = %d\n",
	140	__func__, tpc, (data_dir == READ) ? "READ" : "WRITE",
	141	length);
	142
	143	if (data_dir == READ) {
	144	dma_dir = DMA_DIR_FROM_CARD;
63509bea	145	trans_mode = pro_card ? MS_TM_AUTO_READ : MS_TM_NORMAL_READ;
b902dd4e WW	146	} else {
b902dd4e WW	147	dma_dir = DMA_DIR_TO_CARD;
63509bea	148	trans_mode = pro_card ? MS_TM_AUTO_WRITE : MS_TM_NORMAL_WRITE;
b902dd4e WW	149	}
	150
	151	rtsx_pci_init_cmd(pcr);
	152
	153	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
63509bea MC	154	if (pro_card) {
	155	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_SECTOR_CNT_H,
	156	0xFF, (u8)(sec_cnt >> 8));
	157	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_SECTOR_CNT_L,
	158	0xFF, (u8)sec_cnt);
	159	}
b902dd4e WW	160	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
	161
	162	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
	163	DMA_DONE_INT, DMA_DONE_INT);
	164	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(length >> 24));
	165	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(length >> 16));
	166	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(length >> 8));
	167	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)length);
	168	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
	169	0x03 \| DMA_PACK_SIZE_MASK, dma_dir \| DMA_EN \| DMA_512);
	170	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
	171	0x01, RING_BUFFER);
	172
	173	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
	174	0xFF, MS_TRANSFER_START \| trans_mode);
	175	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
	176	MS_TRANSFER_END, MS_TRANSFER_END);
	177
	178	rtsx_pci_send_cmd_no_wait(pcr);
	179
	180	err = rtsx_pci_transfer_data(pcr, sg, 1, data_dir == READ, 10000);
	181	if (err < 0) {
	182	ms_clear_error(host);
	183	return err;
	184	}
	185
	186	rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
63509bea MC	187	if (pro_card) {
	188	if (val & (MS_INT_CMDNK \| MS_INT_ERR \|
	189	MS_CRC16_ERR \| MS_RDY_TIMEOUT))
	190	return -EIO;
	191	} else {
	192	if (val & (MS_CRC16_ERR \| MS_RDY_TIMEOUT))
	193	return -EIO;
	194	}
b902dd4e WW	195
	196	return 0;
	197	}
	198
	199	static int ms_write_bytes(struct realtek_pci_ms *host, u8 tpc,
	200	u8 cfg, u8 cnt, u8 data, u8 int_reg)
	201	{
	202	struct rtsx_pcr *pcr = host->pcr;
	203	int err, i;
	204
	205	dev_dbg(ms_dev(host), "%s: tpc = 0x%02x\n", __func__, tpc);
	206
	207	if (!data)
	208	return -EINVAL;
	209
	210	rtsx_pci_init_cmd(pcr);
	211
	212	for (i = 0; i < cnt; i++)
	213	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
	214	PPBUF_BASE2 + i, 0xFF, data[i]);
	215	if (cnt % 2)
	216	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
	217	PPBUF_BASE2 + i, 0xFF, 0xFF);
	218
	219	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
	220	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
	221	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
	222	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
	223	0x01, PINGPONG_BUFFER);
	224
	225	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
	226	0xFF, MS_TRANSFER_START \| MS_TM_WRITE_BYTES);
	227	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
	228	MS_TRANSFER_END, MS_TRANSFER_END);
	229	if (int_reg)
	230	rtsx_pci_add_cmd(pcr, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
	231
	232	err = rtsx_pci_send_cmd(pcr, 5000);
	233	if (err < 0) {
	234	u8 val;
	235
	236	rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
	237	dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val);
	238
	239	if (int_reg)
	240	*int_reg = val & 0x0F;
	241
	242	ms_print_debug_regs(host);
	243
	244	ms_clear_error(host);
	245
	246	if (!(tpc & 0x08)) {
	247	if (val & MS_CRC16_ERR)
	248	return -EIO;
	249	} else {
	250	if (!(val & 0x80)) {
	251	if (val & (MS_INT_ERR \| MS_INT_CMDNK))
	252	return -EIO;
	253	}
	254	}
	255
	256	return -ETIMEDOUT;
	257	}
	258
259	if (int_reg) {
260	u8 *ptr = rtsx_pci_get_cmd_data(pcr) + 1;
261	int_reg = ptr & 0x0F;
262	}
263
264	return 0;
265	}
266
267	static int ms_read_bytes(struct realtek_pci_ms *host, u8 tpc,
268	u8 cfg, u8 cnt, u8 data, u8 int_reg)
269	{
270	struct rtsx_pcr *pcr = host->pcr;
271	int err, i;
272	u8 *ptr;
273
274	dev_dbg(ms_dev(host), "%s: tpc = 0x%02x\n", __func__, tpc);
275
276	if (!data)
277	return -EINVAL;
278
279	rtsx_pci_init_cmd(pcr);
280
281	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
282	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
283	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
284	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
285	0x01, PINGPONG_BUFFER);
286
287	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
288	0xFF, MS_TRANSFER_START \| MS_TM_READ_BYTES);
289	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
290	MS_TRANSFER_END, MS_TRANSFER_END);
291	for (i = 0; i < cnt - 1; i++)
292	rtsx_pci_add_cmd(pcr, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
293	if (cnt % 2)
294	rtsx_pci_add_cmd(pcr, READ_REG_CMD, PPBUF_BASE2 + cnt, 0, 0);
295	else
296	rtsx_pci_add_cmd(pcr, READ_REG_CMD,
297	PPBUF_BASE2 + cnt - 1, 0, 0);
298	if (int_reg)
299	rtsx_pci_add_cmd(pcr, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
300
301	err = rtsx_pci_send_cmd(pcr, 5000);
302	if (err < 0) {
303	u8 val;
304
305	rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
306	dev_dbg(ms_dev(host), "MS_TRANS_CFG: 0x%02x\n", val);
307
308	if (int_reg)
309	*int_reg = val & 0x0F;
310
311	ms_print_debug_regs(host);
312
313	ms_clear_error(host);
314
315	if (!(tpc & 0x08)) {
316	if (val & MS_CRC16_ERR)
317	return -EIO;
318	} else {
319	if (!(val & 0x80)) {
320	if (val & (MS_INT_ERR \| MS_INT_CMDNK))
321	return -EIO;
322	}
323	}
324
325	return -ETIMEDOUT;
326	}
327
328	ptr = rtsx_pci_get_cmd_data(pcr) + 1;
329	for (i = 0; i < cnt; i++)
330	data[i] = *ptr++;
331
332	if (int_reg)
333	int_reg = ptr & 0x0F;
334
335	return 0;
336	}
337
338	static int rtsx_pci_ms_issue_cmd(struct realtek_pci_ms *host)
339	{
340	struct memstick_request *req = host->req;
341	int err = 0;
342	u8 cfg = 0, int_reg;
343
344	dev_dbg(ms_dev(host), "%s\n", __func__);
345
346	if (req->need_card_int) {
347	if (host->ifmode != MEMSTICK_SERIAL)
348	cfg = WAIT_INT;
349	}
350
351	if (req->long_data) {
352	err = ms_transfer_data(host, req->data_dir,
353	req->tpc, cfg, &(req->sg));
354	} else {
355	if (req->data_dir == READ) {
356	err = ms_read_bytes(host, req->tpc, cfg,
357	req->data_len, req->data, &int_reg);
358	} else {
359	err = ms_write_bytes(host, req->tpc, cfg,
360	req->data_len, req->data, &int_reg);
361	}
362	}
363	if (err < 0)
364	return err;
365
366	if (req->need_card_int && (host->ifmode == MEMSTICK_SERIAL)) {
367	err = ms_read_bytes(host, MS_TPC_GET_INT,
368	NO_WAIT_INT, 1, &int_reg, NULL);
369	if (err < 0)
370	return err;
371	}
372
373	if (req->need_card_int) {
374	dev_dbg(ms_dev(host), "int_reg: 0x%02x\n", int_reg);
375
376	if (int_reg & MS_INT_CMDNK)
377	req->int_reg \|= MEMSTICK_INT_CMDNAK;
378	if (int_reg & MS_INT_BREQ)
379	req->int_reg \|= MEMSTICK_INT_BREQ;
380	if (int_reg & MS_INT_ERR)
381	req->int_reg \|= MEMSTICK_INT_ERR;
382	if (int_reg & MS_INT_CED)
383	req->int_reg \|= MEMSTICK_INT_CED;
384	}
385
386	return 0;
387	}
388
389	static void rtsx_pci_ms_handle_req(struct work_struct *work)
390	{
391	struct realtek_pci_ms *host = container_of(work,
392	struct realtek_pci_ms, handle_req);
393	struct rtsx_pcr *pcr = host->pcr;
394	struct memstick_host *msh = host->msh;
395	int rc;
396
397	mutex_lock(&pcr->pcr_mutex);
398
399	rtsx_pci_start_run(pcr);
400
401	rtsx_pci_switch_clock(host->pcr, host->clock, host->ssc_depth,
402	false, true, false);
403	rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, MS_MOD_SEL);
404	rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
405	CARD_SHARE_MASK, CARD_SHARE_48_MS);
406
407	if (!host->req) {
408	do {
409	rc = memstick_next_req(msh, &host->req);
410	dev_dbg(ms_dev(host), "next req %d\n", rc);
411
412	if (!rc)
413	host->req->error = rtsx_pci_ms_issue_cmd(host);
414	} while (!rc);
415	}
416
417	mutex_unlock(&pcr->pcr_mutex);
418	}
419
420	static void rtsx_pci_ms_request(struct memstick_host *msh)
421	{
422	struct realtek_pci_ms *host = memstick_priv(msh);
423
424	dev_dbg(ms_dev(host), "--> %s\n", __func__);
425
c3481955 WW	426	if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_MS_CARD))
	427	return;
	428
b902dd4e WW	429	schedule_work(&host->handle_req);
	430	}
	431
	432	static int rtsx_pci_ms_set_param(struct memstick_host *msh,
	433	enum memstick_param param, int value)
	434	{
	435	struct realtek_pci_ms *host = memstick_priv(msh);
	436	struct rtsx_pcr *pcr = host->pcr;
	437	unsigned int clock = 0;
	438	u8 ssc_depth = 0;
	439	int err;
	440
	441	dev_dbg(ms_dev(host), "%s: param = %d, value = %d\n",
	442	__func__, param, value);
	443
c3481955 WW	444	err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_MS_CARD);
	445	if (err)
	446	return err;
	447
b902dd4e WW	448	switch (param) {
	449	case MEMSTICK_POWER:
	450	if (value == MEMSTICK_POWER_ON)
	451	err = ms_power_on(host);
	452	else if (value == MEMSTICK_POWER_OFF)
	453	err = ms_power_off(host);
	454	else
	455	return -EINVAL;
	456	break;
	457
	458	case MEMSTICK_INTERFACE:
	459	if (value == MEMSTICK_SERIAL) {
	460	clock = 19000000;
	461	ssc_depth = RTSX_SSC_DEPTH_500K;
	462
63509bea MC	463	err = rtsx_pci_write_register(pcr, MS_CFG, 0x58,
63509bea MC	464	MS_BUS_WIDTH_1 \| PUSH_TIME_DEFAULT);
b902dd4e WW	465	if (err < 0)
	466	return err;
	467	} else if (value == MEMSTICK_PAR4) {
	468	clock = 39000000;
	469	ssc_depth = RTSX_SSC_DEPTH_1M;
	470
	471	err = rtsx_pci_write_register(pcr, MS_CFG,
	472	0x58, MS_BUS_WIDTH_4 \| PUSH_TIME_ODD);
	473	if (err < 0)
	474	return err;
	475	} else {
	476	return -EINVAL;
	477	}
	478
	479	err = rtsx_pci_switch_clock(pcr, clock,
	480	ssc_depth, false, true, false);
	481	if (err < 0)
	482	return err;
	483
	484	host->ssc_depth = ssc_depth;
	485	host->clock = clock;
	486	host->ifmode = value;
	487	break;
	488	}
	489
	490	return 0;
	491	}
	492
	493	#ifdef CONFIG_PM
	494
	495	static int rtsx_pci_ms_suspend(struct platform_device *pdev, pm_message_t state)
	496	{
	497	struct realtek_pci_ms *host = platform_get_drvdata(pdev);
	498	struct memstick_host *msh = host->msh;
	499
	500	dev_dbg(ms_dev(host), "--> %s\n", __func__);
	501
	502	memstick_suspend_host(msh);
	503	return 0;
	504	}
	505
	506	static int rtsx_pci_ms_resume(struct platform_device *pdev)
	507	{
	508	struct realtek_pci_ms *host = platform_get_drvdata(pdev);
	509	struct memstick_host *msh = host->msh;
	510
	511	dev_dbg(ms_dev(host), "--> %s\n", __func__);
	512
	513	memstick_resume_host(msh);
	514	return 0;
	515	}
	516
	517	#else /* CONFIG_PM */
	518
	519	#define rtsx_pci_ms_suspend NULL
	520	#define rtsx_pci_ms_resume NULL
	521
	522	#endif /* CONFIG_PM */
	523
	524	static void rtsx_pci_ms_card_event(struct platform_device *pdev)
	525	{
	526	struct realtek_pci_ms *host = platform_get_drvdata(pdev);
	527
	528	memstick_detect_change(host->msh);
529	}
530
531	static int rtsx_pci_ms_drv_probe(struct platform_device *pdev)
532	{
533	struct memstick_host *msh;
534	struct realtek_pci_ms *host;
535	struct rtsx_pcr *pcr;
536	struct pcr_handle *handle = pdev->dev.platform_data;
537	int rc;
538
539	if (!handle)
540	return -ENXIO;
541
542	pcr = handle->pcr;
543	if (!pcr)
544	return -ENXIO;
545
546	dev_dbg(&(pdev->dev),
547	": Realtek PCI-E Memstick controller found\n");
548
549	msh = memstick_alloc_host(sizeof(*host), &pdev->dev);
550	if (!msh)
551	return -ENOMEM;
552
553	host = memstick_priv(msh);
554	host->pcr = pcr;
555	host->msh = msh;
556	host->pdev = pdev;
557	platform_set_drvdata(pdev, host);
558	pcr->slots[RTSX_MS_CARD].p_dev = pdev;
559	pcr->slots[RTSX_MS_CARD].card_event = rtsx_pci_ms_card_event;
560
561	mutex_init(&host->host_mutex);
562
563	INIT_WORK(&host->handle_req, rtsx_pci_ms_handle_req);
564	msh->request = rtsx_pci_ms_request;
565	msh->set_param = rtsx_pci_ms_set_param;
566	msh->caps = MEMSTICK_CAP_PAR4;
567
568	rc = memstick_add_host(msh);
569	if (rc) {
570	memstick_free_host(msh);
571	return rc;
572	}
573
574	return 0;
575	}
576
577	static int rtsx_pci_ms_drv_remove(struct platform_device *pdev)
578	{
579	struct realtek_pci_ms *host = platform_get_drvdata(pdev);
580	struct rtsx_pcr *pcr;
581	struct memstick_host *msh;
582	int rc;
583
b902dd4e WW	584	pcr = host->pcr;
	585	pcr->slots[RTSX_MS_CARD].p_dev = NULL;
	586	pcr->slots[RTSX_MS_CARD].card_event = NULL;
	587	msh = host->msh;
	588	host->eject = true;
b6226b45	589	cancel_work_sync(&host->handle_req);
b902dd4e WW	590
	591	mutex_lock(&host->host_mutex);
	592	if (host->req) {
	593	dev_dbg(&(pdev->dev),
	594	"%s: Controller removed during transfer\n",
	595	dev_name(&msh->dev));
	596
	597	rtsx_pci_complete_unfinished_transfer(pcr);
	598
	599	host->req->error = -ENOMEDIUM;
	600	do {
	601	rc = memstick_next_req(msh, &host->req);
	602	if (!rc)
	603	host->req->error = -ENOMEDIUM;
	604	} while (!rc);
	605	}
	606	mutex_unlock(&host->host_mutex);
	607
	608	memstick_remove_host(msh);
	609	memstick_free_host(msh);
	610
b902dd4e WW	611	dev_dbg(&(pdev->dev),
	612	": Realtek PCI-E Memstick controller has been removed\n");
	613
	614	return 0;
	615	}
	616
	617	static struct platform_device_id rtsx_pci_ms_ids[] = {
	618	{
	619	.name = DRV_NAME_RTSX_PCI_MS,
	620	}, {
	621	/* sentinel */
	622	}
	623	};
	624	MODULE_DEVICE_TABLE(platform, rtsx_pci_ms_ids);
	625
	626	static struct platform_driver rtsx_pci_ms_driver = {
	627	.probe = rtsx_pci_ms_drv_probe,
	628	.remove = rtsx_pci_ms_drv_remove,
	629	.id_table = rtsx_pci_ms_ids,
	630	.suspend = rtsx_pci_ms_suspend,
	631	.resume = rtsx_pci_ms_resume,
	632	.driver = {
b902dd4e WW	633	.name = DRV_NAME_RTSX_PCI_MS,
	634	},
	635	};
	636	module_platform_driver(rtsx_pci_ms_driver);
	637
	638	MODULE_LICENSE("GPL");
	639	MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
	640	MODULE_DESCRIPTION("Realtek PCI-E Memstick Card Host Driver");