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60fdd931 AD |
1 | /* |
2 | * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader | |
3 | * | |
4 | * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/spinlock.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/pci.h> | |
d3597ea2 | 15 | #include <linux/dma-mapping.h> |
60fdd931 AD |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
18 | #include <linux/memstick.h> | |
19 | ||
20 | #define DRIVER_NAME "jmb38x_ms" | |
21 | ||
22 | static int no_dma; | |
23 | module_param(no_dma, bool, 0644); | |
24 | ||
25 | enum { | |
26 | DMA_ADDRESS = 0x00, | |
27 | BLOCK = 0x04, | |
28 | DMA_CONTROL = 0x08, | |
29 | TPC_P0 = 0x0c, | |
30 | TPC_P1 = 0x10, | |
31 | TPC = 0x14, | |
32 | HOST_CONTROL = 0x18, | |
33 | DATA = 0x1c, | |
34 | STATUS = 0x20, | |
35 | INT_STATUS = 0x24, | |
36 | INT_STATUS_ENABLE = 0x28, | |
37 | INT_SIGNAL_ENABLE = 0x2c, | |
38 | TIMER = 0x30, | |
39 | TIMER_CONTROL = 0x34, | |
40 | PAD_OUTPUT_ENABLE = 0x38, | |
41 | PAD_PU_PD = 0x3c, | |
42 | CLOCK_DELAY = 0x40, | |
43 | ADMA_ADDRESS = 0x44, | |
44 | CLOCK_CONTROL = 0x48, | |
45 | LED_CONTROL = 0x4c, | |
46 | VERSION = 0x50 | |
47 | }; | |
48 | ||
49 | struct jmb38x_ms_host { | |
50 | struct jmb38x_ms *chip; | |
51 | void __iomem *addr; | |
52 | spinlock_t lock; | |
53 | int id; | |
54 | char host_id[DEVICE_ID_SIZE]; | |
55 | int irq; | |
56 | unsigned int block_pos; | |
57 | unsigned long timeout_jiffies; | |
58 | struct timer_list timer; | |
59 | struct memstick_request *req; | |
60fdd931 AD |
60 | unsigned char cmd_flags; |
61 | unsigned char io_pos; | |
62 | unsigned int io_word[2]; | |
63 | }; | |
64 | ||
65 | struct jmb38x_ms { | |
66 | struct pci_dev *pdev; | |
67 | int host_cnt; | |
68 | struct memstick_host *hosts[]; | |
69 | }; | |
70 | ||
71 | #define BLOCK_COUNT_MASK 0xffff0000 | |
72 | #define BLOCK_SIZE_MASK 0x00000fff | |
73 | ||
74 | #define DMA_CONTROL_ENABLE 0x00000001 | |
75 | ||
76 | #define TPC_DATA_SEL 0x00008000 | |
77 | #define TPC_DIR 0x00004000 | |
78 | #define TPC_WAIT_INT 0x00002000 | |
79 | #define TPC_GET_INT 0x00000800 | |
80 | #define TPC_CODE_SZ_MASK 0x00000700 | |
81 | #define TPC_DATA_SZ_MASK 0x00000007 | |
82 | ||
83 | #define HOST_CONTROL_RESET_REQ 0x00008000 | |
84 | #define HOST_CONTROL_REI 0x00004000 | |
85 | #define HOST_CONTROL_LED 0x00000400 | |
86 | #define HOST_CONTROL_FAST_CLK 0x00000200 | |
87 | #define HOST_CONTROL_RESET 0x00000100 | |
88 | #define HOST_CONTROL_POWER_EN 0x00000080 | |
89 | #define HOST_CONTROL_CLOCK_EN 0x00000040 | |
90 | #define HOST_CONTROL_IF_SHIFT 4 | |
91 | ||
92 | #define HOST_CONTROL_IF_SERIAL 0x0 | |
93 | #define HOST_CONTROL_IF_PAR4 0x1 | |
94 | #define HOST_CONTROL_IF_PAR8 0x3 | |
95 | ||
ead70773 AD |
96 | #define STATUS_BUSY 0x00080000 |
97 | #define STATUS_MS_DAT7 0x00040000 | |
98 | #define STATUS_MS_DAT6 0x00020000 | |
99 | #define STATUS_MS_DAT5 0x00010000 | |
100 | #define STATUS_MS_DAT4 0x00008000 | |
101 | #define STATUS_MS_DAT3 0x00004000 | |
102 | #define STATUS_MS_DAT2 0x00002000 | |
103 | #define STATUS_MS_DAT1 0x00001000 | |
104 | #define STATUS_MS_DAT0 0x00000800 | |
60fdd931 AD |
105 | #define STATUS_HAS_MEDIA 0x00000400 |
106 | #define STATUS_FIFO_EMPTY 0x00000200 | |
107 | #define STATUS_FIFO_FULL 0x00000100 | |
ead70773 AD |
108 | #define STATUS_MS_CED 0x00000080 |
109 | #define STATUS_MS_ERR 0x00000040 | |
110 | #define STATUS_MS_BRQ 0x00000020 | |
111 | #define STATUS_MS_CNK 0x00000001 | |
60fdd931 AD |
112 | |
113 | #define INT_STATUS_TPC_ERR 0x00080000 | |
114 | #define INT_STATUS_CRC_ERR 0x00040000 | |
115 | #define INT_STATUS_TIMER_TO 0x00020000 | |
116 | #define INT_STATUS_HSK_TO 0x00010000 | |
117 | #define INT_STATUS_ANY_ERR 0x00008000 | |
118 | #define INT_STATUS_FIFO_WRDY 0x00000080 | |
119 | #define INT_STATUS_FIFO_RRDY 0x00000040 | |
120 | #define INT_STATUS_MEDIA_OUT 0x00000010 | |
121 | #define INT_STATUS_MEDIA_IN 0x00000008 | |
122 | #define INT_STATUS_DMA_BOUNDARY 0x00000004 | |
123 | #define INT_STATUS_EOTRAN 0x00000002 | |
124 | #define INT_STATUS_EOTPC 0x00000001 | |
125 | ||
126 | #define INT_STATUS_ALL 0x000f801f | |
127 | ||
128 | #define PAD_OUTPUT_ENABLE_MS 0x0F3F | |
129 | ||
130 | #define PAD_PU_PD_OFF 0x7FFF0000 | |
131 | #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000 | |
132 | #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000 | |
133 | ||
cf821e8f AD |
134 | #define CLOCK_CONTROL_40MHZ 0x00000001 |
135 | #define CLOCK_CONTROL_50MHZ 0x00000002 | |
136 | #define CLOCK_CONTROL_60MHZ 0x00000008 | |
137 | #define CLOCK_CONTROL_62_5MHZ 0x0000000c | |
138 | #define CLOCK_CONTROL_OFF 0x00000000 | |
139 | ||
60fdd931 AD |
140 | enum { |
141 | CMD_READY = 0x01, | |
142 | FIFO_READY = 0x02, | |
143 | REG_DATA = 0x04, | |
ead70773 | 144 | DMA_DATA = 0x08 |
60fdd931 AD |
145 | }; |
146 | ||
147 | static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host, | |
148 | unsigned char *buf, unsigned int length) | |
149 | { | |
150 | unsigned int off = 0; | |
151 | ||
152 | while (host->io_pos && length) { | |
153 | buf[off++] = host->io_word[0] & 0xff; | |
154 | host->io_word[0] >>= 8; | |
155 | length--; | |
156 | host->io_pos--; | |
157 | } | |
158 | ||
159 | if (!length) | |
160 | return off; | |
161 | ||
162 | while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) { | |
163 | if (length < 4) | |
164 | break; | |
165 | *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA); | |
166 | length -= 4; | |
167 | off += 4; | |
168 | } | |
169 | ||
170 | if (length | |
171 | && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) { | |
172 | host->io_word[0] = readl(host->addr + DATA); | |
173 | for (host->io_pos = 4; host->io_pos; --host->io_pos) { | |
174 | buf[off++] = host->io_word[0] & 0xff; | |
175 | host->io_word[0] >>= 8; | |
176 | length--; | |
177 | if (!length) | |
178 | break; | |
179 | } | |
180 | } | |
181 | ||
182 | return off; | |
183 | } | |
184 | ||
185 | static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host, | |
186 | unsigned char *buf, | |
187 | unsigned int length) | |
188 | { | |
189 | unsigned int off = 0; | |
190 | ||
191 | while (host->io_pos > 4 && length) { | |
192 | buf[off++] = host->io_word[0] & 0xff; | |
193 | host->io_word[0] >>= 8; | |
194 | length--; | |
195 | host->io_pos--; | |
196 | } | |
197 | ||
198 | if (!length) | |
199 | return off; | |
200 | ||
201 | while (host->io_pos && length) { | |
202 | buf[off++] = host->io_word[1] & 0xff; | |
203 | host->io_word[1] >>= 8; | |
204 | length--; | |
205 | host->io_pos--; | |
206 | } | |
207 | ||
208 | return off; | |
209 | } | |
210 | ||
211 | static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host, | |
212 | unsigned char *buf, | |
213 | unsigned int length) | |
214 | { | |
215 | unsigned int off = 0; | |
216 | ||
217 | if (host->io_pos) { | |
218 | while (host->io_pos < 4 && length) { | |
219 | host->io_word[0] |= buf[off++] << (host->io_pos * 8); | |
220 | host->io_pos++; | |
221 | length--; | |
222 | } | |
223 | } | |
224 | ||
225 | if (host->io_pos == 4 | |
226 | && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) { | |
227 | writel(host->io_word[0], host->addr + DATA); | |
228 | host->io_pos = 0; | |
229 | host->io_word[0] = 0; | |
230 | } else if (host->io_pos) { | |
231 | return off; | |
232 | } | |
233 | ||
234 | if (!length) | |
235 | return off; | |
236 | ||
237 | while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) { | |
238 | if (length < 4) | |
239 | break; | |
240 | ||
241 | __raw_writel(*(unsigned int *)(buf + off), | |
242 | host->addr + DATA); | |
243 | length -= 4; | |
244 | off += 4; | |
245 | } | |
246 | ||
247 | switch (length) { | |
248 | case 3: | |
249 | host->io_word[0] |= buf[off + 2] << 16; | |
250 | host->io_pos++; | |
251 | case 2: | |
252 | host->io_word[0] |= buf[off + 1] << 8; | |
253 | host->io_pos++; | |
254 | case 1: | |
255 | host->io_word[0] |= buf[off]; | |
256 | host->io_pos++; | |
257 | } | |
258 | ||
259 | off += host->io_pos; | |
260 | ||
261 | return off; | |
262 | } | |
263 | ||
264 | static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host, | |
265 | unsigned char *buf, | |
266 | unsigned int length) | |
267 | { | |
268 | unsigned int off = 0; | |
269 | ||
270 | while (host->io_pos < 4 && length) { | |
271 | host->io_word[0] &= ~(0xff << (host->io_pos * 8)); | |
272 | host->io_word[0] |= buf[off++] << (host->io_pos * 8); | |
273 | host->io_pos++; | |
274 | length--; | |
275 | } | |
276 | ||
277 | if (!length) | |
278 | return off; | |
279 | ||
280 | while (host->io_pos < 8 && length) { | |
281 | host->io_word[1] &= ~(0xff << (host->io_pos * 8)); | |
282 | host->io_word[1] |= buf[off++] << (host->io_pos * 8); | |
283 | host->io_pos++; | |
284 | length--; | |
285 | } | |
286 | ||
287 | return off; | |
288 | } | |
289 | ||
290 | static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host) | |
291 | { | |
292 | unsigned int length; | |
293 | unsigned int off; | |
8195096b | 294 | unsigned int t_size, p_cnt; |
60fdd931 AD |
295 | unsigned char *buf; |
296 | struct page *pg; | |
297 | unsigned long flags = 0; | |
298 | ||
299 | if (host->req->long_data) { | |
300 | length = host->req->sg.length - host->block_pos; | |
301 | off = host->req->sg.offset + host->block_pos; | |
302 | } else { | |
303 | length = host->req->data_len - host->block_pos; | |
304 | off = 0; | |
305 | } | |
306 | ||
307 | while (length) { | |
8195096b AM |
308 | unsigned int uninitialized_var(p_off); |
309 | ||
60fdd931 AD |
310 | if (host->req->long_data) { |
311 | pg = nth_page(sg_page(&host->req->sg), | |
312 | off >> PAGE_SHIFT); | |
313 | p_off = offset_in_page(off); | |
314 | p_cnt = PAGE_SIZE - p_off; | |
315 | p_cnt = min(p_cnt, length); | |
316 | ||
317 | local_irq_save(flags); | |
318 | buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + p_off; | |
319 | } else { | |
320 | buf = host->req->data + host->block_pos; | |
321 | p_cnt = host->req->data_len - host->block_pos; | |
322 | } | |
323 | ||
324 | if (host->req->data_dir == WRITE) | |
325 | t_size = !(host->cmd_flags & REG_DATA) | |
326 | ? jmb38x_ms_write_data(host, buf, p_cnt) | |
327 | : jmb38x_ms_write_reg_data(host, buf, p_cnt); | |
328 | else | |
329 | t_size = !(host->cmd_flags & REG_DATA) | |
330 | ? jmb38x_ms_read_data(host, buf, p_cnt) | |
331 | : jmb38x_ms_read_reg_data(host, buf, p_cnt); | |
332 | ||
333 | if (host->req->long_data) { | |
334 | kunmap_atomic(buf - p_off, KM_BIO_SRC_IRQ); | |
335 | local_irq_restore(flags); | |
336 | } | |
337 | ||
338 | if (!t_size) | |
339 | break; | |
340 | host->block_pos += t_size; | |
341 | length -= t_size; | |
342 | off += t_size; | |
343 | } | |
344 | ||
345 | if (!length && host->req->data_dir == WRITE) { | |
346 | if (host->cmd_flags & REG_DATA) { | |
347 | writel(host->io_word[0], host->addr + TPC_P0); | |
348 | writel(host->io_word[1], host->addr + TPC_P1); | |
349 | } else if (host->io_pos) { | |
350 | writel(host->io_word[0], host->addr + DATA); | |
351 | } | |
352 | } | |
353 | ||
354 | return length; | |
355 | } | |
356 | ||
357 | static int jmb38x_ms_issue_cmd(struct memstick_host *msh) | |
358 | { | |
359 | struct jmb38x_ms_host *host = memstick_priv(msh); | |
360 | unsigned char *data; | |
361 | unsigned int data_len, cmd, t_val; | |
362 | ||
363 | if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) { | |
364 | dev_dbg(msh->cdev.dev, "no media status\n"); | |
365 | host->req->error = -ETIME; | |
366 | return host->req->error; | |
367 | } | |
368 | ||
369 | dev_dbg(msh->cdev.dev, "control %08x\n", | |
370 | readl(host->addr + HOST_CONTROL)); | |
371 | dev_dbg(msh->cdev.dev, "status %08x\n", readl(host->addr + INT_STATUS)); | |
372 | dev_dbg(msh->cdev.dev, "hstatus %08x\n", readl(host->addr + STATUS)); | |
373 | ||
374 | host->cmd_flags = 0; | |
375 | host->block_pos = 0; | |
376 | host->io_pos = 0; | |
377 | host->io_word[0] = 0; | |
378 | host->io_word[1] = 0; | |
379 | ||
380 | cmd = host->req->tpc << 16; | |
381 | cmd |= TPC_DATA_SEL; | |
382 | ||
383 | if (host->req->data_dir == READ) | |
384 | cmd |= TPC_DIR; | |
385 | if (host->req->need_card_int) | |
386 | cmd |= TPC_WAIT_INT; | |
60fdd931 AD |
387 | |
388 | data = host->req->data; | |
389 | ||
ead70773 AD |
390 | if (!no_dma) |
391 | host->cmd_flags |= DMA_DATA; | |
60fdd931 AD |
392 | |
393 | if (host->req->long_data) { | |
394 | data_len = host->req->sg.length; | |
395 | } else { | |
396 | data_len = host->req->data_len; | |
ead70773 | 397 | host->cmd_flags &= ~DMA_DATA; |
60fdd931 AD |
398 | } |
399 | ||
400 | if (data_len <= 8) { | |
401 | cmd &= ~(TPC_DATA_SEL | 0xf); | |
402 | host->cmd_flags |= REG_DATA; | |
403 | cmd |= data_len & 0xf; | |
ead70773 | 404 | host->cmd_flags &= ~DMA_DATA; |
60fdd931 AD |
405 | } |
406 | ||
ead70773 | 407 | if (host->cmd_flags & DMA_DATA) { |
60fdd931 AD |
408 | if (1 != pci_map_sg(host->chip->pdev, &host->req->sg, 1, |
409 | host->req->data_dir == READ | |
410 | ? PCI_DMA_FROMDEVICE | |
411 | : PCI_DMA_TODEVICE)) { | |
412 | host->req->error = -ENOMEM; | |
413 | return host->req->error; | |
414 | } | |
415 | data_len = sg_dma_len(&host->req->sg); | |
416 | writel(sg_dma_address(&host->req->sg), | |
417 | host->addr + DMA_ADDRESS); | |
418 | writel(((1 << 16) & BLOCK_COUNT_MASK) | |
419 | | (data_len & BLOCK_SIZE_MASK), | |
420 | host->addr + BLOCK); | |
421 | writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL); | |
422 | } else if (!(host->cmd_flags & REG_DATA)) { | |
423 | writel(((1 << 16) & BLOCK_COUNT_MASK) | |
424 | | (data_len & BLOCK_SIZE_MASK), | |
425 | host->addr + BLOCK); | |
426 | t_val = readl(host->addr + INT_STATUS_ENABLE); | |
427 | t_val |= host->req->data_dir == READ | |
428 | ? INT_STATUS_FIFO_RRDY | |
429 | : INT_STATUS_FIFO_WRDY; | |
430 | ||
431 | writel(t_val, host->addr + INT_STATUS_ENABLE); | |
432 | writel(t_val, host->addr + INT_SIGNAL_ENABLE); | |
433 | } else { | |
434 | cmd &= ~(TPC_DATA_SEL | 0xf); | |
435 | host->cmd_flags |= REG_DATA; | |
436 | cmd |= data_len & 0xf; | |
437 | ||
438 | if (host->req->data_dir == WRITE) { | |
439 | jmb38x_ms_transfer_data(host); | |
440 | writel(host->io_word[0], host->addr + TPC_P0); | |
441 | writel(host->io_word[1], host->addr + TPC_P1); | |
442 | } | |
443 | } | |
444 | ||
445 | mod_timer(&host->timer, jiffies + host->timeout_jiffies); | |
446 | writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL), | |
447 | host->addr + HOST_CONTROL); | |
448 | host->req->error = 0; | |
449 | ||
450 | writel(cmd, host->addr + TPC); | |
451 | dev_dbg(msh->cdev.dev, "executing TPC %08x, len %x\n", cmd, data_len); | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last) | |
457 | { | |
458 | struct jmb38x_ms_host *host = memstick_priv(msh); | |
459 | unsigned int t_val = 0; | |
460 | int rc; | |
461 | ||
462 | del_timer(&host->timer); | |
463 | ||
464 | dev_dbg(msh->cdev.dev, "c control %08x\n", | |
465 | readl(host->addr + HOST_CONTROL)); | |
466 | dev_dbg(msh->cdev.dev, "c status %08x\n", | |
467 | readl(host->addr + INT_STATUS)); | |
468 | dev_dbg(msh->cdev.dev, "c hstatus %08x\n", readl(host->addr + STATUS)); | |
469 | ||
ead70773 AD |
470 | host->req->int_reg = readl(host->addr + STATUS) & 0xff; |
471 | ||
472 | writel(0, host->addr + BLOCK); | |
473 | writel(0, host->addr + DMA_CONTROL); | |
60fdd931 | 474 | |
ead70773 | 475 | if (host->cmd_flags & DMA_DATA) { |
60fdd931 AD |
476 | pci_unmap_sg(host->chip->pdev, &host->req->sg, 1, |
477 | host->req->data_dir == READ | |
478 | ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); | |
479 | } else { | |
480 | t_val = readl(host->addr + INT_STATUS_ENABLE); | |
481 | if (host->req->data_dir == READ) | |
482 | t_val &= ~INT_STATUS_FIFO_RRDY; | |
483 | else | |
484 | t_val &= ~INT_STATUS_FIFO_WRDY; | |
485 | ||
486 | writel(t_val, host->addr + INT_STATUS_ENABLE); | |
487 | writel(t_val, host->addr + INT_SIGNAL_ENABLE); | |
488 | } | |
489 | ||
490 | writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL), | |
491 | host->addr + HOST_CONTROL); | |
492 | ||
493 | if (!last) { | |
494 | do { | |
495 | rc = memstick_next_req(msh, &host->req); | |
496 | } while (!rc && jmb38x_ms_issue_cmd(msh)); | |
497 | } else { | |
498 | do { | |
499 | rc = memstick_next_req(msh, &host->req); | |
500 | if (!rc) | |
501 | host->req->error = -ETIME; | |
502 | } while (!rc); | |
503 | } | |
504 | } | |
505 | ||
506 | static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id) | |
507 | { | |
508 | struct memstick_host *msh = dev_id; | |
509 | struct jmb38x_ms_host *host = memstick_priv(msh); | |
510 | unsigned int irq_status; | |
511 | ||
512 | spin_lock(&host->lock); | |
513 | irq_status = readl(host->addr + INT_STATUS); | |
514 | dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status); | |
515 | if (irq_status == 0 || irq_status == (~0)) { | |
516 | spin_unlock(&host->lock); | |
517 | return IRQ_NONE; | |
518 | } | |
519 | ||
520 | if (host->req) { | |
521 | if (irq_status & INT_STATUS_ANY_ERR) { | |
522 | if (irq_status & INT_STATUS_CRC_ERR) | |
523 | host->req->error = -EILSEQ; | |
524 | else | |
525 | host->req->error = -ETIME; | |
526 | } else { | |
ead70773 | 527 | if (host->cmd_flags & DMA_DATA) { |
60fdd931 AD |
528 | if (irq_status & INT_STATUS_EOTRAN) |
529 | host->cmd_flags |= FIFO_READY; | |
530 | } else { | |
531 | if (irq_status & (INT_STATUS_FIFO_RRDY | |
532 | | INT_STATUS_FIFO_WRDY)) | |
533 | jmb38x_ms_transfer_data(host); | |
534 | ||
535 | if (irq_status & INT_STATUS_EOTRAN) { | |
536 | jmb38x_ms_transfer_data(host); | |
537 | host->cmd_flags |= FIFO_READY; | |
538 | } | |
539 | } | |
540 | ||
541 | if (irq_status & INT_STATUS_EOTPC) { | |
542 | host->cmd_flags |= CMD_READY; | |
543 | if (host->cmd_flags & REG_DATA) { | |
544 | if (host->req->data_dir == READ) { | |
545 | host->io_word[0] | |
546 | = readl(host->addr | |
547 | + TPC_P0); | |
548 | host->io_word[1] | |
549 | = readl(host->addr | |
550 | + TPC_P1); | |
551 | host->io_pos = 8; | |
552 | ||
553 | jmb38x_ms_transfer_data(host); | |
554 | } | |
555 | host->cmd_flags |= FIFO_READY; | |
556 | } | |
557 | } | |
558 | } | |
559 | } | |
560 | ||
561 | if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) { | |
562 | dev_dbg(&host->chip->pdev->dev, "media changed\n"); | |
563 | memstick_detect_change(msh); | |
564 | } | |
565 | ||
566 | writel(irq_status, host->addr + INT_STATUS); | |
567 | ||
568 | if (host->req | |
569 | && (((host->cmd_flags & CMD_READY) | |
570 | && (host->cmd_flags & FIFO_READY)) | |
571 | || host->req->error)) | |
572 | jmb38x_ms_complete_cmd(msh, 0); | |
573 | ||
574 | spin_unlock(&host->lock); | |
575 | return IRQ_HANDLED; | |
576 | } | |
577 | ||
578 | static void jmb38x_ms_abort(unsigned long data) | |
579 | { | |
580 | struct memstick_host *msh = (struct memstick_host *)data; | |
581 | struct jmb38x_ms_host *host = memstick_priv(msh); | |
582 | unsigned long flags; | |
583 | ||
584 | dev_dbg(&host->chip->pdev->dev, "abort\n"); | |
585 | spin_lock_irqsave(&host->lock, flags); | |
586 | if (host->req) { | |
587 | host->req->error = -ETIME; | |
588 | jmb38x_ms_complete_cmd(msh, 0); | |
589 | } | |
590 | spin_unlock_irqrestore(&host->lock, flags); | |
591 | } | |
592 | ||
593 | static void jmb38x_ms_request(struct memstick_host *msh) | |
594 | { | |
595 | struct jmb38x_ms_host *host = memstick_priv(msh); | |
596 | unsigned long flags; | |
597 | int rc; | |
598 | ||
599 | spin_lock_irqsave(&host->lock, flags); | |
600 | if (host->req) { | |
601 | spin_unlock_irqrestore(&host->lock, flags); | |
602 | BUG(); | |
603 | return; | |
604 | } | |
605 | ||
606 | do { | |
607 | rc = memstick_next_req(msh, &host->req); | |
608 | } while (!rc && jmb38x_ms_issue_cmd(msh)); | |
609 | spin_unlock_irqrestore(&host->lock, flags); | |
610 | } | |
611 | ||
612 | static void jmb38x_ms_reset(struct jmb38x_ms_host *host) | |
613 | { | |
614 | unsigned int host_ctl = readl(host->addr + HOST_CONTROL); | |
615 | ||
cf821e8f | 616 | writel(HOST_CONTROL_RESET_REQ, host->addr + HOST_CONTROL); |
60fdd931 AD |
617 | |
618 | while (HOST_CONTROL_RESET_REQ | |
619 | & (host_ctl = readl(host->addr + HOST_CONTROL))) { | |
cf821e8f AD |
620 | ndelay(20); |
621 | dev_dbg(&host->chip->pdev->dev, "reset %08x\n", host_ctl); | |
60fdd931 AD |
622 | } |
623 | ||
cf821e8f AD |
624 | writel(HOST_CONTROL_RESET, host->addr + HOST_CONTROL); |
625 | mmiowb(); | |
60fdd931 | 626 | writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE); |
cf821e8f | 627 | writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE); |
60fdd931 AD |
628 | } |
629 | ||
630 | static void jmb38x_ms_set_param(struct memstick_host *msh, | |
631 | enum memstick_param param, | |
632 | int value) | |
633 | { | |
634 | struct jmb38x_ms_host *host = memstick_priv(msh); | |
cf821e8f AD |
635 | unsigned int host_ctl = readl(host->addr + HOST_CONTROL); |
636 | unsigned int clock_ctl = CLOCK_CONTROL_40MHZ, clock_delay = 0; | |
60fdd931 AD |
637 | |
638 | switch (param) { | |
639 | case MEMSTICK_POWER: | |
640 | if (value == MEMSTICK_POWER_ON) { | |
641 | jmb38x_ms_reset(host); | |
642 | ||
643 | writel(host->id ? PAD_PU_PD_ON_MS_SOCK1 | |
cf821e8f | 644 | : PAD_PU_PD_ON_MS_SOCK0, |
60fdd931 AD |
645 | host->addr + PAD_PU_PD); |
646 | ||
647 | writel(PAD_OUTPUT_ENABLE_MS, | |
648 | host->addr + PAD_OUTPUT_ENABLE); | |
649 | ||
cf821e8f AD |
650 | host_ctl = 7; |
651 | host_ctl |= HOST_CONTROL_POWER_EN | |
652 | | HOST_CONTROL_CLOCK_EN; | |
653 | writel(host_ctl, host->addr + HOST_CONTROL); | |
60fdd931 AD |
654 | |
655 | dev_dbg(&host->chip->pdev->dev, "power on\n"); | |
656 | } else if (value == MEMSTICK_POWER_OFF) { | |
cf821e8f AD |
657 | host_ctl &= ~(HOST_CONTROL_POWER_EN |
658 | | HOST_CONTROL_CLOCK_EN); | |
659 | writel(host_ctl, host->addr + HOST_CONTROL); | |
60fdd931 AD |
660 | writel(0, host->addr + PAD_OUTPUT_ENABLE); |
661 | writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD); | |
662 | dev_dbg(&host->chip->pdev->dev, "power off\n"); | |
663 | } | |
664 | break; | |
665 | case MEMSTICK_INTERFACE: | |
60fdd931 | 666 | host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT); |
60fdd931 AD |
667 | |
668 | if (value == MEMSTICK_SERIAL) { | |
669 | host_ctl &= ~HOST_CONTROL_FAST_CLK; | |
670 | host_ctl |= HOST_CONTROL_IF_SERIAL | |
671 | << HOST_CONTROL_IF_SHIFT; | |
672 | host_ctl |= HOST_CONTROL_REI; | |
cf821e8f AD |
673 | clock_ctl = CLOCK_CONTROL_40MHZ; |
674 | clock_delay = 0; | |
60fdd931 AD |
675 | } else if (value == MEMSTICK_PAR4) { |
676 | host_ctl |= HOST_CONTROL_FAST_CLK; | |
677 | host_ctl |= HOST_CONTROL_IF_PAR4 | |
678 | << HOST_CONTROL_IF_SHIFT; | |
679 | host_ctl &= ~HOST_CONTROL_REI; | |
cf821e8f AD |
680 | clock_ctl = CLOCK_CONTROL_40MHZ; |
681 | clock_delay = 4; | |
60fdd931 AD |
682 | } else if (value == MEMSTICK_PAR8) { |
683 | host_ctl |= HOST_CONTROL_FAST_CLK; | |
684 | host_ctl |= HOST_CONTROL_IF_PAR8 | |
685 | << HOST_CONTROL_IF_SHIFT; | |
686 | host_ctl &= ~HOST_CONTROL_REI; | |
cf821e8f AD |
687 | clock_ctl = CLOCK_CONTROL_60MHZ; |
688 | clock_delay = 0; | |
60fdd931 AD |
689 | } |
690 | writel(host_ctl, host->addr + HOST_CONTROL); | |
cf821e8f AD |
691 | writel(clock_ctl, host->addr + CLOCK_CONTROL); |
692 | writel(clock_delay, host->addr + CLOCK_DELAY); | |
60fdd931 AD |
693 | break; |
694 | }; | |
60fdd931 AD |
695 | } |
696 | ||
697 | #ifdef CONFIG_PM | |
698 | ||
699 | static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state) | |
700 | { | |
701 | struct jmb38x_ms *jm = pci_get_drvdata(dev); | |
702 | int cnt; | |
703 | ||
704 | for (cnt = 0; cnt < jm->host_cnt; ++cnt) { | |
705 | if (!jm->hosts[cnt]) | |
706 | break; | |
707 | memstick_suspend_host(jm->hosts[cnt]); | |
708 | } | |
709 | ||
710 | pci_save_state(dev); | |
711 | pci_enable_wake(dev, pci_choose_state(dev, state), 0); | |
712 | pci_disable_device(dev); | |
713 | pci_set_power_state(dev, pci_choose_state(dev, state)); | |
714 | return 0; | |
715 | } | |
716 | ||
717 | static int jmb38x_ms_resume(struct pci_dev *dev) | |
718 | { | |
719 | struct jmb38x_ms *jm = pci_get_drvdata(dev); | |
720 | int rc; | |
721 | ||
722 | pci_set_power_state(dev, PCI_D0); | |
723 | pci_restore_state(dev); | |
724 | rc = pci_enable_device(dev); | |
725 | if (rc) | |
726 | return rc; | |
727 | pci_set_master(dev); | |
728 | ||
729 | pci_read_config_dword(dev, 0xac, &rc); | |
730 | pci_write_config_dword(dev, 0xac, rc | 0x00470000); | |
731 | ||
732 | for (rc = 0; rc < jm->host_cnt; ++rc) { | |
733 | if (!jm->hosts[rc]) | |
734 | break; | |
735 | memstick_resume_host(jm->hosts[rc]); | |
736 | memstick_detect_change(jm->hosts[rc]); | |
737 | } | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
742 | #else | |
743 | ||
744 | #define jmb38x_ms_suspend NULL | |
745 | #define jmb38x_ms_resume NULL | |
746 | ||
747 | #endif /* CONFIG_PM */ | |
748 | ||
749 | static int jmb38x_ms_count_slots(struct pci_dev *pdev) | |
750 | { | |
751 | int cnt, rc = 0; | |
752 | ||
753 | for (cnt = 0; cnt < PCI_ROM_RESOURCE; ++cnt) { | |
754 | if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt))) | |
755 | break; | |
756 | ||
757 | if (256 != pci_resource_len(pdev, cnt)) | |
758 | break; | |
759 | ||
760 | ++rc; | |
761 | } | |
762 | return rc; | |
763 | } | |
764 | ||
765 | static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt) | |
766 | { | |
767 | struct memstick_host *msh; | |
768 | struct jmb38x_ms_host *host; | |
769 | ||
770 | msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host), | |
771 | &jm->pdev->dev); | |
772 | if (!msh) | |
773 | return NULL; | |
774 | ||
775 | host = memstick_priv(msh); | |
776 | host->chip = jm; | |
777 | host->addr = ioremap(pci_resource_start(jm->pdev, cnt), | |
778 | pci_resource_len(jm->pdev, cnt)); | |
779 | if (!host->addr) | |
780 | goto err_out_free; | |
781 | ||
782 | spin_lock_init(&host->lock); | |
783 | host->id = cnt; | |
784 | snprintf(host->host_id, DEVICE_ID_SIZE, DRIVER_NAME ":slot%d", | |
785 | host->id); | |
786 | host->irq = jm->pdev->irq; | |
ead70773 | 787 | host->timeout_jiffies = msecs_to_jiffies(1000); |
60fdd931 AD |
788 | msh->request = jmb38x_ms_request; |
789 | msh->set_param = jmb38x_ms_set_param; | |
ead70773 | 790 | |
60fdd931 AD |
791 | msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8; |
792 | ||
793 | setup_timer(&host->timer, jmb38x_ms_abort, (unsigned long)msh); | |
794 | ||
795 | if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id, | |
796 | msh)) | |
797 | return msh; | |
798 | ||
799 | iounmap(host->addr); | |
800 | err_out_free: | |
801 | kfree(msh); | |
802 | return NULL; | |
803 | } | |
804 | ||
805 | static void jmb38x_ms_free_host(struct memstick_host *msh) | |
806 | { | |
807 | struct jmb38x_ms_host *host = memstick_priv(msh); | |
808 | ||
809 | free_irq(host->irq, msh); | |
810 | iounmap(host->addr); | |
811 | memstick_free_host(msh); | |
812 | } | |
813 | ||
814 | static int jmb38x_ms_probe(struct pci_dev *pdev, | |
815 | const struct pci_device_id *dev_id) | |
816 | { | |
817 | struct jmb38x_ms *jm; | |
818 | int pci_dev_busy = 0; | |
819 | int rc, cnt; | |
820 | ||
821 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
822 | if (rc) | |
823 | return rc; | |
824 | ||
825 | rc = pci_enable_device(pdev); | |
826 | if (rc) | |
827 | return rc; | |
828 | ||
829 | pci_set_master(pdev); | |
830 | ||
831 | rc = pci_request_regions(pdev, DRIVER_NAME); | |
832 | if (rc) { | |
833 | pci_dev_busy = 1; | |
834 | goto err_out; | |
835 | } | |
836 | ||
837 | pci_read_config_dword(pdev, 0xac, &rc); | |
838 | pci_write_config_dword(pdev, 0xac, rc | 0x00470000); | |
839 | ||
840 | cnt = jmb38x_ms_count_slots(pdev); | |
841 | if (!cnt) { | |
842 | rc = -ENODEV; | |
843 | pci_dev_busy = 1; | |
844 | goto err_out; | |
845 | } | |
846 | ||
847 | jm = kzalloc(sizeof(struct jmb38x_ms) | |
848 | + cnt * sizeof(struct memstick_host *), GFP_KERNEL); | |
849 | if (!jm) { | |
850 | rc = -ENOMEM; | |
851 | goto err_out_int; | |
852 | } | |
853 | ||
854 | jm->pdev = pdev; | |
855 | jm->host_cnt = cnt; | |
856 | pci_set_drvdata(pdev, jm); | |
857 | ||
858 | for (cnt = 0; cnt < jm->host_cnt; ++cnt) { | |
859 | jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt); | |
860 | if (!jm->hosts[cnt]) | |
861 | break; | |
862 | ||
863 | rc = memstick_add_host(jm->hosts[cnt]); | |
864 | ||
865 | if (rc) { | |
866 | jmb38x_ms_free_host(jm->hosts[cnt]); | |
867 | jm->hosts[cnt] = NULL; | |
868 | break; | |
869 | } | |
870 | } | |
871 | ||
872 | if (cnt) | |
873 | return 0; | |
874 | ||
875 | rc = -ENODEV; | |
876 | ||
877 | pci_set_drvdata(pdev, NULL); | |
878 | kfree(jm); | |
879 | err_out_int: | |
880 | pci_release_regions(pdev); | |
881 | err_out: | |
882 | if (!pci_dev_busy) | |
883 | pci_disable_device(pdev); | |
884 | return rc; | |
885 | } | |
886 | ||
887 | static void jmb38x_ms_remove(struct pci_dev *dev) | |
888 | { | |
889 | struct jmb38x_ms *jm = pci_get_drvdata(dev); | |
890 | struct jmb38x_ms_host *host; | |
891 | int cnt; | |
892 | unsigned long flags; | |
893 | ||
894 | for (cnt = 0; cnt < jm->host_cnt; ++cnt) { | |
895 | if (!jm->hosts[cnt]) | |
896 | break; | |
897 | ||
898 | host = memstick_priv(jm->hosts[cnt]); | |
899 | ||
900 | writel(0, host->addr + INT_SIGNAL_ENABLE); | |
901 | writel(0, host->addr + INT_STATUS_ENABLE); | |
902 | mmiowb(); | |
903 | dev_dbg(&jm->pdev->dev, "interrupts off\n"); | |
904 | spin_lock_irqsave(&host->lock, flags); | |
905 | if (host->req) { | |
906 | host->req->error = -ETIME; | |
907 | jmb38x_ms_complete_cmd(jm->hosts[cnt], 1); | |
908 | } | |
909 | spin_unlock_irqrestore(&host->lock, flags); | |
910 | ||
911 | memstick_remove_host(jm->hosts[cnt]); | |
912 | dev_dbg(&jm->pdev->dev, "host removed\n"); | |
913 | ||
914 | jmb38x_ms_free_host(jm->hosts[cnt]); | |
915 | } | |
916 | ||
917 | pci_set_drvdata(dev, NULL); | |
918 | pci_release_regions(dev); | |
919 | pci_disable_device(dev); | |
920 | kfree(jm); | |
921 | } | |
922 | ||
923 | static struct pci_device_id jmb38x_ms_id_tbl [] = { | |
924 | { PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS, PCI_ANY_ID, | |
925 | PCI_ANY_ID, 0, 0, 0 }, | |
926 | { } | |
927 | }; | |
928 | ||
929 | static struct pci_driver jmb38x_ms_driver = { | |
930 | .name = DRIVER_NAME, | |
931 | .id_table = jmb38x_ms_id_tbl, | |
932 | .probe = jmb38x_ms_probe, | |
933 | .remove = jmb38x_ms_remove, | |
934 | .suspend = jmb38x_ms_suspend, | |
935 | .resume = jmb38x_ms_resume | |
936 | }; | |
937 | ||
938 | static int __init jmb38x_ms_init(void) | |
939 | { | |
940 | return pci_register_driver(&jmb38x_ms_driver); | |
941 | } | |
942 | ||
943 | static void __exit jmb38x_ms_exit(void) | |
944 | { | |
945 | pci_unregister_driver(&jmb38x_ms_driver); | |
946 | } | |
947 | ||
948 | MODULE_AUTHOR("Alex Dubov"); | |
949 | MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver"); | |
950 | MODULE_LICENSE("GPL"); | |
951 | MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl); | |
952 | ||
953 | module_init(jmb38x_ms_init); | |
954 | module_exit(jmb38x_ms_exit); |