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17c50b70 JE |
1 | /* |
2 | * Memory controller driver for ARM PrimeCell PL172 | |
3 | * PrimeCell MultiPort Memory Controller (PL172) | |
4 | * | |
5 | * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com> | |
6 | * | |
7 | * Based on: | |
8 | * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc. | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
14 | ||
15 | #include <linux/amba/bus.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/of_platform.h> | |
25 | #include <linux/time.h> | |
26 | ||
27 | #define MPMC_STATIC_CFG(n) (0x200 + 0x20 * n) | |
28 | #define MPMC_STATIC_CFG_MW_8BIT 0x0 | |
29 | #define MPMC_STATIC_CFG_MW_16BIT 0x1 | |
30 | #define MPMC_STATIC_CFG_MW_32BIT 0x2 | |
31 | #define MPMC_STATIC_CFG_PM BIT(3) | |
32 | #define MPMC_STATIC_CFG_PC BIT(6) | |
33 | #define MPMC_STATIC_CFG_PB BIT(7) | |
34 | #define MPMC_STATIC_CFG_EW BIT(8) | |
35 | #define MPMC_STATIC_CFG_B BIT(19) | |
36 | #define MPMC_STATIC_CFG_P BIT(20) | |
37 | #define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * n) | |
38 | #define MPMC_STATIC_WAIT_WEN_MAX 0x0f | |
39 | #define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * n) | |
40 | #define MPMC_STATIC_WAIT_OEN_MAX 0x0f | |
41 | #define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * n) | |
42 | #define MPMC_STATIC_WAIT_RD_MAX 0x1f | |
43 | #define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * n) | |
44 | #define MPMC_STATIC_WAIT_PAGE_MAX 0x1f | |
45 | #define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * n) | |
46 | #define MPMC_STATIC_WAIT_WR_MAX 0x1f | |
47 | #define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * n) | |
48 | #define MPMC_STATIC_WAIT_TURN_MAX 0x0f | |
49 | ||
50 | /* Maximum number of static chip selects */ | |
51 | #define PL172_MAX_CS 4 | |
52 | ||
53 | struct pl172_data { | |
54 | void __iomem *base; | |
55 | unsigned long rate; | |
56 | struct clk *clk; | |
57 | }; | |
58 | ||
59 | static int pl172_timing_prop(struct amba_device *adev, | |
60 | const struct device_node *np, const char *name, | |
61 | u32 reg_offset, u32 max, int start) | |
62 | { | |
63 | struct pl172_data *pl172 = amba_get_drvdata(adev); | |
64 | int cycles; | |
65 | u32 val; | |
66 | ||
67 | if (!of_property_read_u32(np, name, &val)) { | |
68 | cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; | |
69 | if (cycles < 0) { | |
70 | cycles = 0; | |
71 | } else if (cycles > max) { | |
72 | dev_err(&adev->dev, "%s timing too tight\n", name); | |
73 | return -EINVAL; | |
74 | } | |
75 | ||
76 | writel(cycles, pl172->base + reg_offset); | |
77 | } | |
78 | ||
79 | dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + | |
80 | readl(pl172->base + reg_offset)); | |
81 | ||
82 | return 0; | |
83 | } | |
84 | ||
85 | static int pl172_setup_static(struct amba_device *adev, | |
86 | struct device_node *np, u32 cs) | |
87 | { | |
88 | struct pl172_data *pl172 = amba_get_drvdata(adev); | |
89 | u32 cfg; | |
90 | int ret; | |
91 | ||
92 | /* MPMC static memory configuration */ | |
93 | if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) { | |
94 | if (cfg == 8) { | |
95 | cfg = MPMC_STATIC_CFG_MW_8BIT; | |
96 | } else if (cfg == 16) { | |
97 | cfg = MPMC_STATIC_CFG_MW_16BIT; | |
98 | } else if (cfg == 32) { | |
99 | cfg = MPMC_STATIC_CFG_MW_32BIT; | |
100 | } else { | |
101 | dev_err(&adev->dev, "invalid memory width cs%u\n", cs); | |
102 | return -EINVAL; | |
103 | } | |
104 | } else { | |
105 | dev_err(&adev->dev, "memory-width property required\n"); | |
106 | return -EINVAL; | |
107 | } | |
108 | ||
109 | if (of_property_read_bool(np, "mpmc,async-page-mode")) | |
110 | cfg |= MPMC_STATIC_CFG_PM; | |
111 | ||
112 | if (of_property_read_bool(np, "mpmc,cs-active-high")) | |
113 | cfg |= MPMC_STATIC_CFG_PC; | |
114 | ||
115 | if (of_property_read_bool(np, "mpmc,byte-lane-low")) | |
116 | cfg |= MPMC_STATIC_CFG_PB; | |
117 | ||
118 | if (of_property_read_bool(np, "mpmc,extended-wait")) | |
119 | cfg |= MPMC_STATIC_CFG_EW; | |
120 | ||
121 | if (of_property_read_bool(np, "mpmc,buffer-enable")) | |
122 | cfg |= MPMC_STATIC_CFG_B; | |
123 | ||
124 | if (of_property_read_bool(np, "mpmc,write-protect")) | |
125 | cfg |= MPMC_STATIC_CFG_P; | |
126 | ||
127 | writel(cfg, pl172->base + MPMC_STATIC_CFG(cs)); | |
128 | dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg); | |
129 | ||
130 | /* MPMC static memory timing */ | |
131 | ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay", | |
132 | MPMC_STATIC_WAIT_WEN(cs), | |
133 | MPMC_STATIC_WAIT_WEN_MAX, 1); | |
134 | if (ret) | |
135 | goto fail; | |
136 | ||
137 | ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay", | |
138 | MPMC_STATIC_WAIT_OEN(cs), | |
139 | MPMC_STATIC_WAIT_OEN_MAX, 0); | |
140 | if (ret) | |
141 | goto fail; | |
142 | ||
143 | ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay", | |
144 | MPMC_STATIC_WAIT_RD(cs), | |
145 | MPMC_STATIC_WAIT_RD_MAX, 1); | |
146 | if (ret) | |
147 | goto fail; | |
148 | ||
149 | ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay", | |
150 | MPMC_STATIC_WAIT_PAGE(cs), | |
151 | MPMC_STATIC_WAIT_PAGE_MAX, 1); | |
152 | if (ret) | |
153 | goto fail; | |
154 | ||
155 | ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay", | |
156 | MPMC_STATIC_WAIT_WR(cs), | |
157 | MPMC_STATIC_WAIT_WR_MAX, 2); | |
158 | if (ret) | |
159 | goto fail; | |
160 | ||
161 | ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay", | |
162 | MPMC_STATIC_WAIT_TURN(cs), | |
163 | MPMC_STATIC_WAIT_TURN_MAX, 1); | |
164 | if (ret) | |
165 | goto fail; | |
166 | ||
167 | return 0; | |
168 | fail: | |
169 | dev_err(&adev->dev, "failed to configure cs%u\n", cs); | |
170 | return ret; | |
171 | } | |
172 | ||
173 | static int pl172_parse_cs_config(struct amba_device *adev, | |
174 | struct device_node *np) | |
175 | { | |
176 | u32 cs; | |
177 | ||
178 | if (!of_property_read_u32(np, "mpmc,cs", &cs)) { | |
179 | if (cs >= PL172_MAX_CS) { | |
180 | dev_err(&adev->dev, "cs%u invalid\n", cs); | |
181 | return -EINVAL; | |
182 | } | |
183 | ||
184 | return pl172_setup_static(adev, np, cs); | |
185 | } | |
186 | ||
187 | dev_err(&adev->dev, "cs property required\n"); | |
188 | ||
189 | return -EINVAL; | |
190 | } | |
191 | ||
192 | static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"}; | |
193 | ||
194 | static int pl172_probe(struct amba_device *adev, const struct amba_id *id) | |
195 | { | |
196 | struct device_node *child_np, *np = adev->dev.of_node; | |
197 | struct device *dev = &adev->dev; | |
198 | static const char *rev = "?"; | |
199 | struct pl172_data *pl172; | |
200 | int ret; | |
201 | ||
202 | if (amba_part(adev) == 0x172) { | |
203 | if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions)) | |
204 | rev = pl172_revisions[amba_rev(adev)]; | |
205 | } | |
206 | ||
207 | dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev); | |
208 | ||
209 | pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL); | |
210 | if (!pl172) | |
211 | return -ENOMEM; | |
212 | ||
213 | pl172->clk = devm_clk_get(dev, "mpmcclk"); | |
214 | if (IS_ERR(pl172->clk)) { | |
215 | dev_err(dev, "no mpmcclk provided clock\n"); | |
216 | return PTR_ERR(pl172->clk); | |
217 | } | |
218 | ||
219 | ret = clk_prepare_enable(pl172->clk); | |
220 | if (ret) { | |
221 | dev_err(dev, "unable to mpmcclk enable clock\n"); | |
222 | return ret; | |
223 | } | |
224 | ||
225 | pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC; | |
226 | if (!pl172->rate) { | |
227 | dev_err(dev, "unable to get mpmcclk clock rate\n"); | |
228 | ret = -EINVAL; | |
229 | goto err_clk_enable; | |
230 | } | |
231 | ||
232 | ret = amba_request_regions(adev, NULL); | |
233 | if (ret) { | |
234 | dev_err(dev, "unable to request AMBA regions\n"); | |
235 | goto err_clk_enable; | |
236 | } | |
237 | ||
238 | pl172->base = devm_ioremap(dev, adev->res.start, | |
239 | resource_size(&adev->res)); | |
240 | if (!pl172->base) { | |
241 | dev_err(dev, "ioremap failed\n"); | |
242 | ret = -ENOMEM; | |
243 | goto err_no_ioremap; | |
244 | } | |
245 | ||
246 | amba_set_drvdata(adev, pl172); | |
247 | ||
248 | /* | |
249 | * Loop through each child node, which represent a chip select, and | |
250 | * configure parameters and timing. If successful; populate devices | |
251 | * under that node. | |
252 | */ | |
253 | for_each_available_child_of_node(np, child_np) { | |
254 | ret = pl172_parse_cs_config(adev, child_np); | |
255 | if (ret) | |
256 | continue; | |
257 | ||
0ff818ef | 258 | of_platform_populate(child_np, NULL, NULL, dev); |
17c50b70 JE |
259 | } |
260 | ||
261 | return 0; | |
262 | ||
263 | err_no_ioremap: | |
264 | amba_release_regions(adev); | |
265 | err_clk_enable: | |
266 | clk_disable_unprepare(pl172->clk); | |
267 | return ret; | |
268 | } | |
269 | ||
270 | static int pl172_remove(struct amba_device *adev) | |
271 | { | |
272 | struct pl172_data *pl172 = amba_get_drvdata(adev); | |
273 | ||
274 | clk_disable_unprepare(pl172->clk); | |
275 | amba_release_regions(adev); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | static const struct amba_id pl172_ids[] = { | |
281 | { | |
282 | .id = 0x07341172, | |
283 | .mask = 0xffffffff, | |
284 | }, | |
285 | { 0, 0 }, | |
286 | }; | |
287 | MODULE_DEVICE_TABLE(amba, pl172_ids); | |
288 | ||
289 | static struct amba_driver pl172_driver = { | |
290 | .drv = { | |
291 | .name = "memory-pl172", | |
292 | }, | |
293 | .probe = pl172_probe, | |
294 | .remove = pl172_remove, | |
295 | .id_table = pl172_ids, | |
296 | }; | |
297 | module_amba_driver(pl172_driver); | |
298 | ||
299 | MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>"); | |
300 | MODULE_DESCRIPTION("PL172 Memory Controller Driver"); | |
301 | MODULE_LICENSE("GPL v2"); |