Commit | Line | Data |
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4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
db97eb7d | 15 | #include <linux/irq.h> |
4bbbc1ad JY |
16 | #include <linux/kernel.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
f37e4580 ID |
20 | #include <linux/ioport.h> |
21 | #include <linux/spinlock.h> | |
fced80c7 | 22 | #include <linux/io.h> |
d2d00862 | 23 | #include <linux/gpio/driver.h> |
db97eb7d | 24 | #include <linux/interrupt.h> |
384258f2 | 25 | #include <linux/irqdomain.h> |
da496873 | 26 | #include <linux/platform_device.h> |
bc6b1e7b | 27 | #include <linux/of.h> |
cdd6928c | 28 | #include <linux/of_address.h> |
bc6b1e7b | 29 | #include <linux/of_device.h> |
b1dc1ca9 | 30 | #include <linux/of_platform.h> |
e639cd5b | 31 | #include <linux/omap-gpmc.h> |
b3f5525c | 32 | #include <linux/pm_runtime.h> |
4bbbc1ad | 33 | |
bc3668ea | 34 | #include <linux/platform_data/mtd-nand-omap2.h> |
e639cd5b | 35 | #include <linux/platform_data/mtd-onenand-omap2.h> |
4bbbc1ad | 36 | |
7f245162 | 37 | #include <asm/mach-types.h> |
72d0f1c3 | 38 | |
4be48fd5 AM |
39 | #define DEVICE_NAME "omap-gpmc" |
40 | ||
fd1dc87d | 41 | /* GPMC register offsets */ |
4bbbc1ad JY |
42 | #define GPMC_REVISION 0x00 |
43 | #define GPMC_SYSCONFIG 0x10 | |
44 | #define GPMC_SYSSTATUS 0x14 | |
45 | #define GPMC_IRQSTATUS 0x18 | |
46 | #define GPMC_IRQENABLE 0x1c | |
47 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
48 | #define GPMC_ERR_ADDRESS 0x44 | |
49 | #define GPMC_ERR_TYPE 0x48 | |
50 | #define GPMC_CONFIG 0x50 | |
51 | #define GPMC_STATUS 0x54 | |
52 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
53 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 54 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
55 | #define GPMC_PREFETCH_STATUS 0x1f0 |
56 | #define GPMC_ECC_CONFIG 0x1f4 | |
57 | #define GPMC_ECC_CONTROL 0x1f8 | |
58 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 59 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 60 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
2fdf0c98 AM |
61 | #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ |
62 | #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ | |
63 | #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ | |
27c9fd60 | 64 | #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ |
65 | #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ | |
66 | #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ | |
4bbbc1ad | 67 | |
2c65e744 YY |
68 | /* GPMC ECC control settings */ |
69 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
70 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
71 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
72 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
73 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
74 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
75 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
76 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
77 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
78 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
79 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
80 | ||
e378d22b RQ |
81 | #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) |
82 | ||
512d73d1 RQ |
83 | #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0) |
84 | ||
559d94b0 AM |
85 | #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) |
86 | #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) | |
87 | #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) | |
88 | #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) | |
89 | #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) | |
90 | #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) | |
91 | ||
948d38e7 | 92 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad | 93 | #define GPMC_CS_SIZE 0x30 |
2fdf0c98 | 94 | #define GPMC_BCH_SIZE 0x10 |
4bbbc1ad | 95 | |
bdd7e033 RQ |
96 | /* |
97 | * The first 1MB of GPMC address space is typically mapped to | |
98 | * the internal ROM. Never allocate the first page, to | |
99 | * facilitate bug detection; even if we didn't boot from ROM. | |
100 | * As GPMC minimum partition size is 16MB we can only start from | |
101 | * there. | |
102 | */ | |
103 | #define GPMC_MEM_START 0x1000000 | |
f37e4580 | 104 | #define GPMC_MEM_END 0x3FFFFFFF |
f37e4580 ID |
105 | |
106 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
107 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
108 | ||
59e9c5ae | 109 | #define CS_NUM_SHIFT 24 |
110 | #define ENABLE_PREFETCH (0x1 << 7) | |
111 | #define DMA_MPU_MODE 2 | |
112 | ||
da496873 AM |
113 | #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) |
114 | #define GPMC_REVISION_MINOR(l) (l & 0xf) | |
115 | ||
116 | #define GPMC_HAS_WR_ACCESS 0x1 | |
117 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | |
aa8d4767 | 118 | #define GPMC_HAS_MUX_AAD 0x4 |
da496873 | 119 | |
9f833156 JH |
120 | #define GPMC_NR_WAITPINS 4 |
121 | ||
e639cd5b TL |
122 | #define GPMC_CS_CONFIG1 0x00 |
123 | #define GPMC_CS_CONFIG2 0x04 | |
124 | #define GPMC_CS_CONFIG3 0x08 | |
125 | #define GPMC_CS_CONFIG4 0x0c | |
126 | #define GPMC_CS_CONFIG5 0x10 | |
127 | #define GPMC_CS_CONFIG6 0x14 | |
128 | #define GPMC_CS_CONFIG7 0x18 | |
129 | #define GPMC_CS_NAND_COMMAND 0x1c | |
130 | #define GPMC_CS_NAND_ADDRESS 0x20 | |
131 | #define GPMC_CS_NAND_DATA 0x24 | |
132 | ||
133 | /* Control Commands */ | |
134 | #define GPMC_CONFIG_RDY_BSY 0x00000001 | |
135 | #define GPMC_CONFIG_DEV_SIZE 0x00000002 | |
136 | #define GPMC_CONFIG_DEV_TYPE 0x00000003 | |
e639cd5b TL |
137 | |
138 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | |
139 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) | |
140 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) | |
141 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | |
142 | #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) | |
143 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) | |
144 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | |
145 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | |
4b613e9b RA |
146 | /** CLKACTIVATIONTIME Max Ticks */ |
147 | #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2 | |
e639cd5b | 148 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) |
4b613e9b RA |
149 | /** ATTACHEDDEVICEPAGELENGTH Max Value */ |
150 | #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2 | |
e639cd5b TL |
151 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) |
152 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | |
2e676901 RA |
153 | #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18) |
154 | /** WAITMONITORINGTIME Max Ticks */ | |
155 | #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2 | |
e639cd5b TL |
156 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) |
157 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | |
158 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | |
4b613e9b RA |
159 | /** DEVICESIZE Max Value */ |
160 | #define GPMC_CONFIG1_DEVICESIZE_MAX 1 | |
e639cd5b TL |
161 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) |
162 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | |
163 | #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) | |
164 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | |
165 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | |
166 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | |
167 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | |
168 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | |
169 | #define GPMC_CONFIG7_CSVALID (1 << 6) | |
170 | ||
9c4f757e SP |
171 | #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f |
172 | #define GPMC_CONFIG7_CSVALID_MASK BIT(6) | |
173 | #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8 | |
174 | #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET) | |
175 | /* All CONFIG7 bits except reserved bits */ | |
176 | #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \ | |
177 | GPMC_CONFIG7_CSVALID_MASK | \ | |
178 | GPMC_CONFIG7_MASKADDRESS_MASK) | |
179 | ||
e639cd5b TL |
180 | #define GPMC_DEVICETYPE_NOR 0 |
181 | #define GPMC_DEVICETYPE_NAND 2 | |
182 | #define GPMC_CONFIG_WRITEPROTECT 0x00000010 | |
183 | #define WR_RD_PIN_MONITORING 0x00600000 | |
184 | ||
e639cd5b TL |
185 | /* ECC commands */ |
186 | #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ | |
187 | #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ | |
188 | #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ | |
189 | ||
b2bac25a | 190 | #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */ |
6b6c32fc | 191 | |
7f2e8c58 RA |
192 | enum gpmc_clk_domain { |
193 | GPMC_CD_FCLK, | |
194 | GPMC_CD_CLK | |
195 | }; | |
196 | ||
9ed7a776 TL |
197 | struct gpmc_cs_data { |
198 | const char *name; | |
199 | ||
200 | #define GPMC_CS_RESERVED (1 << 0) | |
201 | u32 flags; | |
202 | ||
203 | struct resource mem; | |
204 | }; | |
205 | ||
a2d3e7ba RN |
206 | /* Structure to save gpmc cs context */ |
207 | struct gpmc_cs_config { | |
208 | u32 config1; | |
209 | u32 config2; | |
210 | u32 config3; | |
211 | u32 config4; | |
212 | u32 config5; | |
213 | u32 config6; | |
214 | u32 config7; | |
215 | int is_valid; | |
216 | }; | |
217 | ||
218 | /* | |
219 | * Structure to save/restore gpmc context | |
220 | * to support core off on OMAP3 | |
221 | */ | |
222 | struct omap3_gpmc_regs { | |
223 | u32 sysconfig; | |
224 | u32 irqenable; | |
225 | u32 timeout_ctrl; | |
226 | u32 config; | |
227 | u32 prefetch_config1; | |
228 | u32 prefetch_config2; | |
229 | u32 prefetch_control; | |
230 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
231 | }; | |
232 | ||
384258f2 RQ |
233 | struct gpmc_device { |
234 | struct device *dev; | |
235 | int irq; | |
236 | struct irq_chip irq_chip; | |
d2d00862 | 237 | struct gpio_chip gpio_chip; |
b2bac25a | 238 | int nirqs; |
384258f2 RQ |
239 | }; |
240 | ||
241 | static struct irq_domain *gpmc_irq_domain; | |
6b6c32fc | 242 | |
f37e4580 | 243 | static struct resource gpmc_mem_root; |
9ed7a776 | 244 | static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM]; |
87b247c4 | 245 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
6797b4fe | 246 | /* Define chip-selects as reserved by default until probe completes */ |
f34f3716 | 247 | static unsigned int gpmc_cs_num = GPMC_CS_NUM; |
9f833156 | 248 | static unsigned int gpmc_nr_waitpins; |
da496873 AM |
249 | static resource_size_t phys_base, mem_size; |
250 | static unsigned gpmc_capability; | |
fd1dc87d | 251 | static void __iomem *gpmc_base; |
4bbbc1ad | 252 | |
fd1dc87d | 253 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 254 | |
db97eb7d SG |
255 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
256 | ||
4bbbc1ad JY |
257 | static void gpmc_write_reg(int idx, u32 val) |
258 | { | |
edfaf05c | 259 | writel_relaxed(val, gpmc_base + idx); |
4bbbc1ad JY |
260 | } |
261 | ||
262 | static u32 gpmc_read_reg(int idx) | |
263 | { | |
edfaf05c | 264 | return readl_relaxed(gpmc_base + idx); |
4bbbc1ad JY |
265 | } |
266 | ||
267 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
268 | { | |
269 | void __iomem *reg_addr; | |
270 | ||
948d38e7 | 271 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
edfaf05c | 272 | writel_relaxed(val, reg_addr); |
4bbbc1ad JY |
273 | } |
274 | ||
3fc089e7 | 275 | static u32 gpmc_cs_read_reg(int cs, int idx) |
4bbbc1ad | 276 | { |
fd1dc87d PW |
277 | void __iomem *reg_addr; |
278 | ||
948d38e7 | 279 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
edfaf05c | 280 | return readl_relaxed(reg_addr); |
4bbbc1ad JY |
281 | } |
282 | ||
fd1dc87d | 283 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
3fc089e7 | 284 | static unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 285 | { |
fd1dc87d PW |
286 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
287 | ||
fd1dc87d PW |
288 | rate /= 1000; |
289 | rate = 1000000000 / rate; /* In picoseconds */ | |
290 | ||
291 | return rate; | |
4bbbc1ad JY |
292 | } |
293 | ||
7f2e8c58 RA |
294 | /** |
295 | * gpmc_get_clk_period - get period of selected clock domain in ps | |
296 | * @cs Chip Select Region. | |
297 | * @cd Clock Domain. | |
298 | * | |
299 | * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup | |
300 | * prior to calling this function with GPMC_CD_CLK. | |
301 | */ | |
302 | static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) | |
303 | { | |
304 | ||
305 | unsigned long tick_ps = gpmc_get_fclk_period(); | |
306 | u32 l; | |
307 | int div; | |
308 | ||
309 | switch (cd) { | |
310 | case GPMC_CD_CLK: | |
311 | /* get current clk divider */ | |
312 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
313 | div = (l & 0x03) + 1; | |
314 | /* get GPMC_CLK period */ | |
315 | tick_ps *= div; | |
316 | break; | |
317 | case GPMC_CD_FCLK: | |
318 | /* FALL-THROUGH */ | |
319 | default: | |
320 | break; | |
321 | } | |
322 | ||
323 | return tick_ps; | |
324 | ||
325 | } | |
326 | ||
327 | static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, | |
328 | enum gpmc_clk_domain cd) | |
4bbbc1ad JY |
329 | { |
330 | unsigned long tick_ps; | |
331 | ||
332 | /* Calculate in picosecs to yield more exact results */ | |
7f2e8c58 | 333 | tick_ps = gpmc_get_clk_period(cs, cd); |
4bbbc1ad JY |
334 | |
335 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
336 | } | |
337 | ||
7f2e8c58 RA |
338 | static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) |
339 | { | |
340 | return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); | |
341 | } | |
342 | ||
3fc089e7 | 343 | static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
a3551f5b AH |
344 | { |
345 | unsigned long tick_ps; | |
346 | ||
347 | /* Calculate in picosecs to yield more exact results */ | |
348 | tick_ps = gpmc_get_fclk_period(); | |
349 | ||
350 | return (time_ps + tick_ps - 1) / tick_ps; | |
351 | } | |
352 | ||
3950fffd BX |
353 | static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs, |
354 | enum gpmc_clk_domain cd) | |
7f2e8c58 RA |
355 | { |
356 | return ticks * gpmc_get_clk_period(cs, cd) / 1000; | |
357 | } | |
358 | ||
fd1dc87d PW |
359 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
360 | { | |
7f2e8c58 | 361 | return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK); |
fd1dc87d PW |
362 | } |
363 | ||
246da26d AM |
364 | static unsigned int gpmc_ticks_to_ps(unsigned int ticks) |
365 | { | |
366 | return ticks * gpmc_get_fclk_period(); | |
367 | } | |
368 | ||
369 | static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) | |
370 | { | |
371 | unsigned long ticks = gpmc_ps_to_ticks(time_ps); | |
372 | ||
373 | return ticks * gpmc_get_fclk_period(); | |
374 | } | |
375 | ||
559d94b0 AM |
376 | static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) |
377 | { | |
378 | u32 l; | |
379 | ||
380 | l = gpmc_cs_read_reg(cs, reg); | |
381 | if (value) | |
382 | l |= mask; | |
383 | else | |
384 | l &= ~mask; | |
385 | gpmc_cs_write_reg(cs, reg, l); | |
386 | } | |
387 | ||
388 | static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) | |
389 | { | |
390 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, | |
391 | GPMC_CONFIG1_TIME_PARA_GRAN, | |
392 | p->time_para_granularity); | |
393 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, | |
394 | GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); | |
395 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, | |
396 | GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); | |
397 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
398 | GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); | |
399 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
8f50b8e5 | 400 | GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); |
559d94b0 AM |
401 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, |
402 | GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, | |
403 | p->cycle2cyclesamecsen); | |
404 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
405 | GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, | |
406 | p->cycle2cyclediffcsen); | |
407 | } | |
408 | ||
63aa945b | 409 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
563dbb26 RA |
410 | /** |
411 | * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it. | |
412 | * @cs: Chip Select Region | |
413 | * @reg: GPMC_CS_CONFIGn register offset. | |
414 | * @st_bit: Start Bit | |
415 | * @end_bit: End Bit. Must be >= @st_bit. | |
4b613e9b RA |
416 | * @ma:x Maximum parameter value (before optional @shift). |
417 | * If 0, maximum is as high as @st_bit and @end_bit allow. | |
563dbb26 | 418 | * @name: DTS node name, w/o "gpmc," |
7f2e8c58 RA |
419 | * @cd: Clock Domain of timing parameter. |
420 | * @shift: Parameter value left shifts @shift, which is then printed instead of value. | |
563dbb26 RA |
421 | * @raw: Raw Format Option. |
422 | * raw format: gpmc,name = <value> | |
423 | * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/ | |
424 | * Where x ns -- y ns result in the same tick value. | |
4b613e9b | 425 | * When @max is exceeded, "invalid" is printed inside comment. |
563dbb26 | 426 | * @noval: Parameter values equal to 0 are not printed. |
563dbb26 RA |
427 | * @return: Specified timing parameter (after optional @shift). |
428 | * | |
429 | */ | |
7f2e8c58 RA |
430 | static int get_gpmc_timing_reg( |
431 | /* timing specifiers */ | |
4b613e9b | 432 | int cs, int reg, int st_bit, int end_bit, int max, |
7f2e8c58 RA |
433 | const char *name, const enum gpmc_clk_domain cd, |
434 | /* value transform */ | |
435 | int shift, | |
436 | /* format specifiers */ | |
437 | bool raw, bool noval) | |
35ac051e TL |
438 | { |
439 | u32 l; | |
563dbb26 RA |
440 | int nr_bits; |
441 | int mask; | |
4b613e9b | 442 | bool invalid; |
35ac051e TL |
443 | |
444 | l = gpmc_cs_read_reg(cs, reg); | |
445 | nr_bits = end_bit - st_bit + 1; | |
563dbb26 RA |
446 | mask = (1 << nr_bits) - 1; |
447 | l = (l >> st_bit) & mask; | |
4b613e9b RA |
448 | if (!max) |
449 | max = mask; | |
450 | invalid = l > max; | |
35ac051e TL |
451 | if (shift) |
452 | l = (shift << l); | |
453 | if (noval && (l == 0)) | |
454 | return 0; | |
455 | if (!raw) { | |
563dbb26 RA |
456 | /* DTS tick format for timings in ns */ |
457 | unsigned int time_ns; | |
458 | unsigned int time_ns_min = 0; | |
35ac051e | 459 | |
563dbb26 | 460 | if (l) |
7f2e8c58 RA |
461 | time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; |
462 | time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); | |
95c278b2 | 463 | pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", |
4b613e9b RA |
464 | name, time_ns, time_ns_min, time_ns, l, |
465 | invalid ? "; invalid " : " "); | |
35ac051e | 466 | } else { |
563dbb26 | 467 | /* raw format */ |
95c278b2 | 468 | pr_info("gpmc,%s = <%u>;%s\n", name, l, |
4b613e9b | 469 | invalid ? " /* invalid */" : ""); |
35ac051e TL |
470 | } |
471 | ||
472 | return l; | |
473 | } | |
474 | ||
475 | #define GPMC_PRINT_CONFIG(cs, config) \ | |
476 | pr_info("cs%i %s: 0x%08x\n", cs, #config, \ | |
477 | gpmc_cs_read_reg(cs, config)) | |
478 | #define GPMC_GET_RAW(reg, st, end, field) \ | |
4b613e9b RA |
479 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) |
480 | #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \ | |
481 | get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0) | |
35ac051e | 482 | #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ |
4b613e9b RA |
483 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1) |
484 | #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \ | |
485 | get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1) | |
35ac051e | 486 | #define GPMC_GET_TICKS(reg, st, end, field) \ |
4b613e9b | 487 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0) |
7f2e8c58 | 488 | #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \ |
4b613e9b RA |
489 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0) |
490 | #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \ | |
491 | get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0) | |
35ac051e TL |
492 | |
493 | static void gpmc_show_regs(int cs, const char *desc) | |
494 | { | |
495 | pr_info("gpmc cs%i %s:\n", cs, desc); | |
496 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); | |
497 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); | |
498 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); | |
499 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); | |
500 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); | |
501 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); | |
502 | } | |
503 | ||
504 | /* | |
505 | * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available, | |
506 | * see commit c9fb809. | |
507 | */ | |
508 | static void gpmc_cs_show_timings(int cs, const char *desc) | |
509 | { | |
510 | gpmc_show_regs(cs, desc); | |
511 | ||
512 | pr_info("gpmc cs%i access configuration:\n", cs); | |
513 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); | |
514 | GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); | |
4b613e9b RA |
515 | GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13, |
516 | GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); | |
35ac051e TL |
517 | GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); |
518 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); | |
519 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); | |
4b613e9b RA |
520 | GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4, |
521 | GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX, | |
522 | "burst-length"); | |
35ac051e TL |
523 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); |
524 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); | |
525 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); | |
526 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); | |
527 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); | |
528 | ||
529 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); | |
530 | ||
531 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); | |
532 | ||
533 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); | |
534 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); | |
535 | ||
536 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); | |
537 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); | |
538 | ||
539 | pr_info("gpmc cs%i timings configuration:\n", cs); | |
540 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); | |
541 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); | |
542 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); | |
543 | ||
544 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); | |
545 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); | |
546 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); | |
2c92c04b NA |
547 | if (gpmc_capability & GPMC_HAS_MUX_AAD) { |
548 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns"); | |
549 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26, | |
550 | "adv-aad-mux-rd-off-ns"); | |
551 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30, | |
552 | "adv-aad-mux-wr-off-ns"); | |
553 | } | |
35ac051e TL |
554 | |
555 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); | |
556 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); | |
2c92c04b NA |
557 | if (gpmc_capability & GPMC_HAS_MUX_AAD) { |
558 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns"); | |
559 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns"); | |
560 | } | |
35ac051e TL |
561 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); |
562 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); | |
563 | ||
564 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); | |
565 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); | |
566 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); | |
567 | ||
568 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); | |
569 | ||
570 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); | |
571 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); | |
572 | ||
4b613e9b RA |
573 | GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19, |
574 | GPMC_CONFIG1_WAITMONITORINGTIME_MAX, | |
575 | "wait-monitoring-ns", GPMC_CD_CLK); | |
576 | GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26, | |
577 | GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, | |
578 | "clk-activation-ns", GPMC_CD_FCLK); | |
35ac051e TL |
579 | |
580 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); | |
581 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); | |
582 | } | |
4bbbc1ad | 583 | #else |
35ac051e TL |
584 | static inline void gpmc_cs_show_timings(int cs, const char *desc) |
585 | { | |
586 | } | |
4bbbc1ad | 587 | #endif |
35ac051e | 588 | |
7f2e8c58 RA |
589 | /** |
590 | * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region. | |
591 | * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER | |
592 | * prior to calling this function with @cd equal to GPMC_CD_CLK. | |
593 | * | |
594 | * @cs: Chip Select Region. | |
595 | * @reg: GPMC_CS_CONFIGn register offset. | |
596 | * @st_bit: Start Bit | |
597 | * @end_bit: End Bit. Must be >= @st_bit. | |
4b613e9b RA |
598 | * @max: Maximum parameter value. |
599 | * If 0, maximum is as high as @st_bit and @end_bit allow. | |
7f2e8c58 RA |
600 | * @time: Timing parameter in ns. |
601 | * @cd: Timing parameter clock domain. | |
602 | * @name: Timing parameter name. | |
603 | * @return: 0 on success, -1 on error. | |
604 | */ | |
4b613e9b | 605 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, |
7f2e8c58 | 606 | int time, enum gpmc_clk_domain cd, const char *name) |
4bbbc1ad JY |
607 | { |
608 | u32 l; | |
609 | int ticks, mask, nr_bits; | |
610 | ||
611 | if (time == 0) | |
612 | ticks = 0; | |
613 | else | |
7f2e8c58 | 614 | ticks = gpmc_ns_to_clk_ticks(time, cs, cd); |
4bbbc1ad | 615 | nr_bits = end_bit - st_bit + 1; |
80323742 RQ |
616 | mask = (1 << nr_bits) - 1; |
617 | ||
4b613e9b RA |
618 | if (!max) |
619 | max = mask; | |
620 | ||
621 | if (ticks > max) { | |
7f2e8c58 | 622 | pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", |
4b613e9b | 623 | __func__, cs, name, time, ticks, max); |
80323742 | 624 | |
4bbbc1ad | 625 | return -1; |
1c22cc13 | 626 | } |
4bbbc1ad | 627 | |
4bbbc1ad | 628 | l = gpmc_cs_read_reg(cs, reg); |
63aa945b | 629 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
f585070b | 630 | pr_info( |
2affc816 | 631 | "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", |
7f2e8c58 | 632 | cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, |
1c22cc13 | 633 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
634 | #endif |
635 | l &= ~(mask << st_bit); | |
636 | l |= ticks << st_bit; | |
637 | gpmc_cs_write_reg(cs, reg, l); | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
4b613e9b RA |
642 | #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \ |
643 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \ | |
644 | t->field, (cd), #field) < 0) \ | |
4bbbc1ad | 645 | return -1 |
4bbbc1ad | 646 | |
7f2e8c58 | 647 | #define GPMC_SET_ONE(reg, st, end, field) \ |
4b613e9b | 648 | GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK) |
7f2e8c58 | 649 | |
2e676901 RA |
650 | /** |
651 | * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME | |
652 | * WAITMONITORINGTIME will be _at least_ as long as desired, i.e. | |
653 | * read --> don't sample bus too early | |
654 | * write --> data is longer on bus | |
655 | * | |
656 | * Formula: | |
657 | * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns) | |
658 | * / waitmonitoring_ticks) | |
659 | * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by | |
660 | * div <= 0 check. | |
661 | * | |
662 | * @wait_monitoring: WAITMONITORINGTIME in ns. | |
663 | * @return: -1 on failure to scale, else proper divider > 0. | |
664 | */ | |
665 | static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) | |
666 | { | |
667 | ||
668 | int div = gpmc_ns_to_ticks(wait_monitoring); | |
669 | ||
670 | div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; | |
671 | div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX; | |
672 | ||
673 | if (div > 4) | |
674 | return -1; | |
675 | if (div <= 0) | |
676 | div = 1; | |
677 | ||
678 | return div; | |
679 | ||
680 | } | |
681 | ||
682 | /** | |
683 | * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period. | |
684 | * @sync_clk: GPMC_CLK period in ps. | |
685 | * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK. | |
686 | * Else, returns -1. | |
687 | */ | |
1b47ca1a | 688 | int gpmc_calc_divider(unsigned int sync_clk) |
4bbbc1ad | 689 | { |
2e676901 | 690 | int div = gpmc_ps_to_ticks(sync_clk); |
4bbbc1ad | 691 | |
4bbbc1ad JY |
692 | if (div > 4) |
693 | return -1; | |
1c22cc13 | 694 | if (div <= 0) |
4bbbc1ad JY |
695 | div = 1; |
696 | ||
697 | return div; | |
698 | } | |
699 | ||
2e676901 RA |
700 | /** |
701 | * gpmc_cs_set_timings - program timing parameters for Chip Select Region. | |
702 | * @cs: Chip Select Region. | |
703 | * @t: GPMC timing parameters. | |
704 | * @s: GPMC timing settings. | |
705 | * @return: 0 on success, -1 on error. | |
706 | */ | |
707 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, | |
708 | const struct gpmc_settings *s) | |
4bbbc1ad JY |
709 | { |
710 | int div; | |
711 | u32 l; | |
712 | ||
1b47ca1a | 713 | div = gpmc_calc_divider(t->sync_clk); |
4bbbc1ad | 714 | if (div < 0) |
a032d33b | 715 | return div; |
4bbbc1ad | 716 | |
2e676901 RA |
717 | /* |
718 | * See if we need to change the divider for waitmonitoringtime. | |
719 | * | |
720 | * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for | |
721 | * pure asynchronous accesses, i.e. both read and write asynchronous. | |
722 | * However, only do so if WAITMONITORINGTIME is actually used, i.e. | |
723 | * either WAITREADMONITORING or WAITWRITEMONITORING is set. | |
724 | * | |
725 | * This statement must not change div to scale async WAITMONITORINGTIME | |
726 | * to protect mixed synchronous and asynchronous accesses. | |
727 | * | |
728 | * We raise an error later if WAITMONITORINGTIME does not fit. | |
729 | */ | |
730 | if (!s->sync_read && !s->sync_write && | |
731 | (s->wait_on_read || s->wait_on_write) | |
732 | ) { | |
733 | ||
734 | div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); | |
735 | if (div < 0) { | |
736 | pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n", | |
737 | __func__, | |
738 | t->wait_monitoring | |
739 | ); | |
740 | return -1; | |
741 | } | |
742 | } | |
743 | ||
4bbbc1ad JY |
744 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); |
745 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
746 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
747 | ||
748 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
749 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
750 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
2c92c04b NA |
751 | if (gpmc_capability & GPMC_HAS_MUX_AAD) { |
752 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on); | |
753 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off); | |
754 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off); | |
755 | } | |
4bbbc1ad JY |
756 | |
757 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
758 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
2c92c04b NA |
759 | if (gpmc_capability & GPMC_HAS_MUX_AAD) { |
760 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on); | |
761 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off); | |
762 | } | |
4bbbc1ad JY |
763 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); |
764 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
765 | ||
766 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
767 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
768 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
769 | ||
770 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
771 | ||
559d94b0 AM |
772 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); |
773 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); | |
774 | ||
da496873 | 775 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) |
cc26b3b0 | 776 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); |
da496873 | 777 | if (gpmc_capability & GPMC_HAS_WR_ACCESS) |
cc26b3b0 | 778 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); |
cc26b3b0 | 779 | |
1c22cc13 | 780 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); |
7f2e8c58 RA |
781 | l &= ~0x03; |
782 | l |= (div - 1); | |
783 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
784 | ||
4b613e9b RA |
785 | GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19, |
786 | GPMC_CONFIG1_WAITMONITORINGTIME_MAX, | |
787 | wait_monitoring, GPMC_CD_CLK); | |
788 | GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26, | |
789 | GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, | |
790 | clk_activation, GPMC_CD_FCLK); | |
7f2e8c58 | 791 | |
63aa945b | 792 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
f585070b RA |
793 | pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", |
794 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 795 | #endif |
4bbbc1ad | 796 | |
559d94b0 | 797 | gpmc_cs_bool_timings(cs, &t->bool_timings); |
35ac051e | 798 | gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); |
559d94b0 | 799 | |
4bbbc1ad JY |
800 | return 0; |
801 | } | |
802 | ||
4cf27d2e | 803 | static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) |
f37e4580 ID |
804 | { |
805 | u32 l; | |
806 | u32 mask; | |
807 | ||
c71f8e9b JH |
808 | /* |
809 | * Ensure that base address is aligned on a | |
810 | * boundary equal to or greater than size. | |
811 | */ | |
812 | if (base & (size - 1)) | |
813 | return -EINVAL; | |
814 | ||
9c4f757e | 815 | base >>= GPMC_CHUNK_SHIFT; |
f37e4580 | 816 | mask = (1 << GPMC_SECTION_SHIFT) - size; |
9c4f757e SP |
817 | mask >>= GPMC_CHUNK_SHIFT; |
818 | mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET; | |
819 | ||
f37e4580 | 820 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); |
9c4f757e SP |
821 | l &= ~GPMC_CONFIG7_MASK; |
822 | l |= base & GPMC_CONFIG7_BASEADDRESS_MASK; | |
823 | l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK; | |
a2d3e7ba | 824 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 | 825 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
c71f8e9b JH |
826 | |
827 | return 0; | |
f37e4580 ID |
828 | } |
829 | ||
4cf27d2e RQ |
830 | static void gpmc_cs_enable_mem(int cs) |
831 | { | |
832 | u32 l; | |
833 | ||
834 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
835 | l |= GPMC_CONFIG7_CSVALID; | |
836 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); | |
837 | } | |
838 | ||
f37e4580 ID |
839 | static void gpmc_cs_disable_mem(int cs) |
840 | { | |
841 | u32 l; | |
842 | ||
843 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 844 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
845 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
846 | } | |
847 | ||
848 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
849 | { | |
850 | u32 l; | |
851 | u32 mask; | |
852 | ||
853 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
854 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
855 | mask = (l >> 8) & 0x0f; | |
856 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
857 | } | |
858 | ||
859 | static int gpmc_cs_mem_enabled(int cs) | |
860 | { | |
861 | u32 l; | |
862 | ||
863 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 864 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
865 | } |
866 | ||
f5d8edaf | 867 | static void gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 868 | { |
9ed7a776 TL |
869 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
870 | ||
871 | gpmc->flags |= GPMC_CS_RESERVED; | |
f37e4580 ID |
872 | } |
873 | ||
ae9d908a | 874 | static bool gpmc_cs_reserved(int cs) |
f37e4580 | 875 | { |
9ed7a776 TL |
876 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
877 | ||
878 | return gpmc->flags & GPMC_CS_RESERVED; | |
879 | } | |
880 | ||
881 | static void gpmc_cs_set_name(int cs, const char *name) | |
882 | { | |
883 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; | |
884 | ||
885 | gpmc->name = name; | |
886 | } | |
887 | ||
2e25b0ec | 888 | static const char *gpmc_cs_get_name(int cs) |
9ed7a776 TL |
889 | { |
890 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; | |
891 | ||
892 | return gpmc->name; | |
f37e4580 ID |
893 | } |
894 | ||
895 | static unsigned long gpmc_mem_align(unsigned long size) | |
896 | { | |
897 | int order; | |
898 | ||
899 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
900 | order = GPMC_CHUNK_SHIFT - 1; | |
901 | do { | |
902 | size >>= 1; | |
903 | order++; | |
904 | } while (size); | |
905 | size = 1 << order; | |
906 | return size; | |
907 | } | |
908 | ||
909 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
910 | { | |
9ed7a776 TL |
911 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
912 | struct resource *res = &gpmc->mem; | |
f37e4580 ID |
913 | int r; |
914 | ||
915 | size = gpmc_mem_align(size); | |
916 | spin_lock(&gpmc_mem_lock); | |
917 | res->start = base; | |
918 | res->end = base + size - 1; | |
919 | r = request_resource(&gpmc_mem_root, res); | |
920 | spin_unlock(&gpmc_mem_lock); | |
921 | ||
922 | return r; | |
923 | } | |
924 | ||
da496873 AM |
925 | static int gpmc_cs_delete_mem(int cs) |
926 | { | |
9ed7a776 TL |
927 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
928 | struct resource *res = &gpmc->mem; | |
da496873 AM |
929 | int r; |
930 | ||
931 | spin_lock(&gpmc_mem_lock); | |
efe80723 | 932 | r = release_resource(res); |
da496873 AM |
933 | res->start = 0; |
934 | res->end = 0; | |
935 | spin_unlock(&gpmc_mem_lock); | |
936 | ||
937 | return r; | |
938 | } | |
939 | ||
cdd6928c JH |
940 | /** |
941 | * gpmc_cs_remap - remaps a chip-select physical base address | |
942 | * @cs: chip-select to remap | |
943 | * @base: physical base address to re-map chip-select to | |
944 | * | |
945 | * Re-maps a chip-select to a new physical base address specified by | |
946 | * "base". Returns 0 on success and appropriate negative error code | |
947 | * on failure. | |
948 | */ | |
949 | static int gpmc_cs_remap(int cs, u32 base) | |
950 | { | |
951 | int ret; | |
952 | u32 old_base, size; | |
953 | ||
f34f3716 GP |
954 | if (cs > gpmc_cs_num) { |
955 | pr_err("%s: requested chip-select is disabled\n", __func__); | |
cdd6928c | 956 | return -ENODEV; |
f34f3716 | 957 | } |
fb677ef7 TL |
958 | |
959 | /* | |
960 | * Make sure we ignore any device offsets from the GPMC partition | |
961 | * allocated for the chip select and that the new base confirms | |
962 | * to the GPMC 16MB minimum granularity. | |
963 | */ | |
964 | base &= ~(SZ_16M - 1); | |
965 | ||
cdd6928c JH |
966 | gpmc_cs_get_memconf(cs, &old_base, &size); |
967 | if (base == old_base) | |
968 | return 0; | |
4cf27d2e | 969 | |
cdd6928c JH |
970 | ret = gpmc_cs_delete_mem(cs); |
971 | if (ret < 0) | |
972 | return ret; | |
4cf27d2e | 973 | |
cdd6928c | 974 | ret = gpmc_cs_insert_mem(cs, base, size); |
c71f8e9b JH |
975 | if (ret < 0) |
976 | return ret; | |
cdd6928c | 977 | |
4cf27d2e RQ |
978 | ret = gpmc_cs_set_memconf(cs, base, size); |
979 | ||
980 | return ret; | |
cdd6928c JH |
981 | } |
982 | ||
f37e4580 ID |
983 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) |
984 | { | |
9ed7a776 TL |
985 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
986 | struct resource *res = &gpmc->mem; | |
f37e4580 ID |
987 | int r = -1; |
988 | ||
f34f3716 GP |
989 | if (cs > gpmc_cs_num) { |
990 | pr_err("%s: requested chip-select is disabled\n", __func__); | |
f37e4580 | 991 | return -ENODEV; |
f34f3716 | 992 | } |
f37e4580 ID |
993 | size = gpmc_mem_align(size); |
994 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
995 | return -ENOMEM; | |
996 | ||
997 | spin_lock(&gpmc_mem_lock); | |
998 | if (gpmc_cs_reserved(cs)) { | |
999 | r = -EBUSY; | |
1000 | goto out; | |
1001 | } | |
1002 | if (gpmc_cs_mem_enabled(cs)) | |
1003 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
1004 | if (r < 0) | |
1005 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
1006 | size, NULL, NULL); | |
1007 | if (r < 0) | |
1008 | goto out; | |
1009 | ||
4cf27d2e RQ |
1010 | /* Disable CS while changing base address and size mask */ |
1011 | gpmc_cs_disable_mem(cs); | |
1012 | ||
1013 | r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); | |
c71f8e9b JH |
1014 | if (r < 0) { |
1015 | release_resource(res); | |
1016 | goto out; | |
1017 | } | |
1018 | ||
4cf27d2e RQ |
1019 | /* Enable CS */ |
1020 | gpmc_cs_enable_mem(cs); | |
f37e4580 ID |
1021 | *base = res->start; |
1022 | gpmc_cs_set_reserved(cs, 1); | |
1023 | out: | |
1024 | spin_unlock(&gpmc_mem_lock); | |
1025 | return r; | |
1026 | } | |
fd1dc87d | 1027 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
1028 | |
1029 | void gpmc_cs_free(int cs) | |
1030 | { | |
9ed7a776 TL |
1031 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
1032 | struct resource *res = &gpmc->mem; | |
efe80723 | 1033 | |
f37e4580 | 1034 | spin_lock(&gpmc_mem_lock); |
f34f3716 | 1035 | if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
1036 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
1037 | BUG(); | |
1038 | spin_unlock(&gpmc_mem_lock); | |
1039 | return; | |
1040 | } | |
1041 | gpmc_cs_disable_mem(cs); | |
efe80723 TL |
1042 | if (res->flags) |
1043 | release_resource(res); | |
f37e4580 ID |
1044 | gpmc_cs_set_reserved(cs, 0); |
1045 | spin_unlock(&gpmc_mem_lock); | |
1046 | } | |
fd1dc87d | 1047 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 1048 | |
948d38e7 | 1049 | /** |
3a544354 | 1050 | * gpmc_configure - write request to configure gpmc |
948d38e7 SG |
1051 | * @cmd: command type |
1052 | * @wval: value to write | |
1053 | * @return status of the operation | |
1054 | */ | |
3a544354 | 1055 | int gpmc_configure(int cmd, int wval) |
948d38e7 | 1056 | { |
3a544354 | 1057 | u32 regval; |
948d38e7 SG |
1058 | |
1059 | switch (cmd) { | |
948d38e7 SG |
1060 | case GPMC_CONFIG_WP: |
1061 | regval = gpmc_read_reg(GPMC_CONFIG); | |
1062 | if (wval) | |
1063 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
1064 | else | |
1065 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
1066 | gpmc_write_reg(GPMC_CONFIG, regval); | |
1067 | break; | |
1068 | ||
948d38e7 | 1069 | default: |
3a544354 JH |
1070 | pr_err("%s: command not supported\n", __func__); |
1071 | return -EINVAL; | |
948d38e7 SG |
1072 | } |
1073 | ||
3a544354 | 1074 | return 0; |
948d38e7 | 1075 | } |
3a544354 | 1076 | EXPORT_SYMBOL(gpmc_configure); |
948d38e7 | 1077 | |
52bd138d AM |
1078 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
1079 | { | |
2fdf0c98 AM |
1080 | int i; |
1081 | ||
9e694621 | 1082 | reg->gpmc_status = NULL; /* deprecated */ |
52bd138d AM |
1083 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + |
1084 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | |
1085 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | |
1086 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | |
1087 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | |
1088 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | |
1089 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | |
1090 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | |
1091 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | |
1092 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | |
1093 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | |
1094 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | |
1095 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | |
1096 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | |
2fdf0c98 AM |
1097 | |
1098 | for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { | |
1099 | reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + | |
1100 | GPMC_BCH_SIZE * i; | |
1101 | reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + | |
1102 | GPMC_BCH_SIZE * i; | |
1103 | reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + | |
1104 | GPMC_BCH_SIZE * i; | |
1105 | reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + | |
1106 | GPMC_BCH_SIZE * i; | |
27c9fd60 | 1107 | reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + |
1108 | i * GPMC_BCH_SIZE; | |
1109 | reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + | |
1110 | i * GPMC_BCH_SIZE; | |
1111 | reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + | |
1112 | i * GPMC_BCH_SIZE; | |
2fdf0c98 | 1113 | } |
52bd138d AM |
1114 | } |
1115 | ||
512d73d1 RQ |
1116 | static bool gpmc_nand_writebuffer_empty(void) |
1117 | { | |
1118 | if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS) | |
1119 | return true; | |
1120 | ||
1121 | return false; | |
1122 | } | |
1123 | ||
1124 | static struct gpmc_nand_ops nand_ops = { | |
1125 | .nand_writebuffer_empty = gpmc_nand_writebuffer_empty, | |
1126 | }; | |
f47fcad6 RQ |
1127 | |
1128 | /** | |
1129 | * gpmc_omap_get_nand_ops - Get the GPMC NAND interface | |
1130 | * @regs: the GPMC NAND register map exclusive for NAND use. | |
1131 | * @cs: GPMC chip select number on which the NAND sits. The | |
1132 | * register map returned will be specific to this chip select. | |
1133 | * | |
1134 | * Returns NULL on error e.g. invalid cs. | |
1135 | */ | |
1136 | struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs) | |
1137 | { | |
1138 | if (cs >= gpmc_cs_num) | |
1139 | return NULL; | |
1140 | ||
1141 | gpmc_update_nand_reg(reg, cs); | |
1142 | ||
1143 | return &nand_ops; | |
1144 | } | |
1145 | EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops); | |
1146 | ||
6b6c32fc AM |
1147 | int gpmc_get_client_irq(unsigned irq_config) |
1148 | { | |
384258f2 RQ |
1149 | if (!gpmc_irq_domain) { |
1150 | pr_warn("%s called before GPMC IRQ domain available\n", | |
1151 | __func__); | |
6b6c32fc | 1152 | return 0; |
384258f2 | 1153 | } |
6b6c32fc | 1154 | |
b2bac25a RQ |
1155 | /* we restrict this to NAND IRQs only */ |
1156 | if (irq_config >= GPMC_NR_NAND_IRQS) | |
384258f2 | 1157 | return 0; |
6b6c32fc | 1158 | |
384258f2 | 1159 | return irq_create_mapping(gpmc_irq_domain, irq_config); |
6b6c32fc AM |
1160 | } |
1161 | ||
384258f2 | 1162 | static int gpmc_irq_endis(unsigned long hwirq, bool endis) |
6b6c32fc | 1163 | { |
6b6c32fc AM |
1164 | u32 regval; |
1165 | ||
b2bac25a RQ |
1166 | /* bits GPMC_NR_NAND_IRQS to 8 are reserved */ |
1167 | if (hwirq >= GPMC_NR_NAND_IRQS) | |
1168 | hwirq += 8 - GPMC_NR_NAND_IRQS; | |
1169 | ||
384258f2 RQ |
1170 | regval = gpmc_read_reg(GPMC_IRQENABLE); |
1171 | if (endis) | |
1172 | regval |= BIT(hwirq); | |
1173 | else | |
1174 | regval &= ~BIT(hwirq); | |
1175 | gpmc_write_reg(GPMC_IRQENABLE, regval); | |
6b6c32fc AM |
1176 | |
1177 | return 0; | |
1178 | } | |
1179 | ||
1180 | static void gpmc_irq_disable(struct irq_data *p) | |
1181 | { | |
384258f2 | 1182 | gpmc_irq_endis(p->hwirq, false); |
6b6c32fc AM |
1183 | } |
1184 | ||
1185 | static void gpmc_irq_enable(struct irq_data *p) | |
1186 | { | |
384258f2 | 1187 | gpmc_irq_endis(p->hwirq, true); |
6b6c32fc AM |
1188 | } |
1189 | ||
b2bac25a RQ |
1190 | static void gpmc_irq_mask(struct irq_data *d) |
1191 | { | |
1192 | gpmc_irq_endis(d->hwirq, false); | |
1193 | } | |
1194 | ||
1195 | static void gpmc_irq_unmask(struct irq_data *d) | |
1196 | { | |
1197 | gpmc_irq_endis(d->hwirq, true); | |
1198 | } | |
1199 | ||
1200 | static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge) | |
1201 | { | |
1202 | u32 regval; | |
1203 | ||
1204 | /* NAND IRQs polarity is not configurable */ | |
1205 | if (hwirq < GPMC_NR_NAND_IRQS) | |
1206 | return; | |
1207 | ||
1208 | /* WAITPIN starts at BIT 8 */ | |
1209 | hwirq += 8 - GPMC_NR_NAND_IRQS; | |
1210 | ||
1211 | regval = gpmc_read_reg(GPMC_CONFIG); | |
1212 | if (rising_edge) | |
1213 | regval &= ~BIT(hwirq); | |
1214 | else | |
1215 | regval |= BIT(hwirq); | |
1216 | ||
1217 | gpmc_write_reg(GPMC_CONFIG, regval); | |
1218 | } | |
1219 | ||
1220 | static void gpmc_irq_ack(struct irq_data *d) | |
1221 | { | |
1222 | unsigned int hwirq = d->hwirq; | |
1223 | ||
1224 | /* skip reserved bits */ | |
1225 | if (hwirq >= GPMC_NR_NAND_IRQS) | |
1226 | hwirq += 8 - GPMC_NR_NAND_IRQS; | |
1227 | ||
1228 | /* Setting bit to 1 clears (or Acks) the interrupt */ | |
1229 | gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq)); | |
1230 | } | |
1231 | ||
1232 | static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger) | |
1233 | { | |
1234 | /* can't set type for NAND IRQs */ | |
1235 | if (d->hwirq < GPMC_NR_NAND_IRQS) | |
1236 | return -EINVAL; | |
1237 | ||
1238 | /* We can support either rising or falling edge at a time */ | |
1239 | if (trigger == IRQ_TYPE_EDGE_FALLING) | |
1240 | gpmc_irq_edge_config(d->hwirq, false); | |
1241 | else if (trigger == IRQ_TYPE_EDGE_RISING) | |
1242 | gpmc_irq_edge_config(d->hwirq, true); | |
1243 | else | |
1244 | return -EINVAL; | |
6b6c32fc | 1245 | |
b2bac25a RQ |
1246 | return 0; |
1247 | } | |
6b6c32fc | 1248 | |
384258f2 RQ |
1249 | static int gpmc_irq_map(struct irq_domain *d, unsigned int virq, |
1250 | irq_hw_number_t hw) | |
6b6c32fc | 1251 | { |
384258f2 RQ |
1252 | struct gpmc_device *gpmc = d->host_data; |
1253 | ||
1254 | irq_set_chip_data(virq, gpmc); | |
b2bac25a RQ |
1255 | if (hw < GPMC_NR_NAND_IRQS) { |
1256 | irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN); | |
1257 | irq_set_chip_and_handler(virq, &gpmc->irq_chip, | |
1258 | handle_simple_irq); | |
1259 | } else { | |
1260 | irq_set_chip_and_handler(virq, &gpmc->irq_chip, | |
1261 | handle_edge_irq); | |
1262 | } | |
384258f2 RQ |
1263 | |
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | static const struct irq_domain_ops gpmc_irq_domain_ops = { | |
1268 | .map = gpmc_irq_map, | |
1269 | .xlate = irq_domain_xlate_twocell, | |
1270 | }; | |
1271 | ||
1272 | static irqreturn_t gpmc_handle_irq(int irq, void *data) | |
1273 | { | |
1274 | int hwirq, virq; | |
b2bac25a | 1275 | u32 regval, regvalx; |
384258f2 | 1276 | struct gpmc_device *gpmc = data; |
6b6c32fc | 1277 | |
384258f2 | 1278 | regval = gpmc_read_reg(GPMC_IRQSTATUS); |
b2bac25a | 1279 | regvalx = regval; |
6b6c32fc | 1280 | |
384258f2 RQ |
1281 | if (!regval) |
1282 | return IRQ_NONE; | |
6b6c32fc | 1283 | |
b2bac25a RQ |
1284 | for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) { |
1285 | /* skip reserved status bits */ | |
1286 | if (hwirq == GPMC_NR_NAND_IRQS) | |
1287 | regvalx >>= 8 - GPMC_NR_NAND_IRQS; | |
1288 | ||
1289 | if (regvalx & BIT(hwirq)) { | |
384258f2 RQ |
1290 | virq = irq_find_mapping(gpmc_irq_domain, hwirq); |
1291 | if (!virq) { | |
1292 | dev_warn(gpmc->dev, | |
1293 | "spurious irq detected hwirq %d, virq %d\n", | |
1294 | hwirq, virq); | |
1295 | } | |
1296 | ||
1297 | generic_handle_irq(virq); | |
1298 | } | |
6b6c32fc AM |
1299 | } |
1300 | ||
384258f2 RQ |
1301 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
1302 | ||
1303 | return IRQ_HANDLED; | |
1304 | } | |
1305 | ||
1306 | static int gpmc_setup_irq(struct gpmc_device *gpmc) | |
1307 | { | |
1308 | u32 regval; | |
1309 | int rc; | |
1310 | ||
6b6c32fc AM |
1311 | /* Disable interrupts */ |
1312 | gpmc_write_reg(GPMC_IRQENABLE, 0); | |
1313 | ||
1314 | /* clear interrupts */ | |
1315 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
1316 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | |
1317 | ||
384258f2 | 1318 | gpmc->irq_chip.name = "gpmc"; |
384258f2 RQ |
1319 | gpmc->irq_chip.irq_enable = gpmc_irq_enable; |
1320 | gpmc->irq_chip.irq_disable = gpmc_irq_disable; | |
b2bac25a RQ |
1321 | gpmc->irq_chip.irq_ack = gpmc_irq_ack; |
1322 | gpmc->irq_chip.irq_mask = gpmc_irq_mask; | |
1323 | gpmc->irq_chip.irq_unmask = gpmc_irq_unmask; | |
1324 | gpmc->irq_chip.irq_set_type = gpmc_irq_set_type; | |
384258f2 RQ |
1325 | |
1326 | gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node, | |
b2bac25a | 1327 | gpmc->nirqs, |
384258f2 RQ |
1328 | &gpmc_irq_domain_ops, |
1329 | gpmc); | |
1330 | if (!gpmc_irq_domain) { | |
1331 | dev_err(gpmc->dev, "IRQ domain add failed\n"); | |
1332 | return -ENODEV; | |
1333 | } | |
1334 | ||
1335 | rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc); | |
1336 | if (rc) { | |
1337 | dev_err(gpmc->dev, "failed to request irq %d: %d\n", | |
1338 | gpmc->irq, rc); | |
1339 | irq_domain_remove(gpmc_irq_domain); | |
1340 | gpmc_irq_domain = NULL; | |
1341 | } | |
1342 | ||
1343 | return rc; | |
6b6c32fc AM |
1344 | } |
1345 | ||
384258f2 | 1346 | static int gpmc_free_irq(struct gpmc_device *gpmc) |
da496873 | 1347 | { |
384258f2 | 1348 | int hwirq; |
da496873 | 1349 | |
384258f2 | 1350 | free_irq(gpmc->irq, gpmc); |
da496873 | 1351 | |
b2bac25a | 1352 | for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) |
384258f2 | 1353 | irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq)); |
da496873 | 1354 | |
384258f2 RQ |
1355 | irq_domain_remove(gpmc_irq_domain); |
1356 | gpmc_irq_domain = NULL; | |
da496873 AM |
1357 | |
1358 | return 0; | |
1359 | } | |
1360 | ||
351a102d | 1361 | static void gpmc_mem_exit(void) |
da496873 AM |
1362 | { |
1363 | int cs; | |
1364 | ||
f34f3716 | 1365 | for (cs = 0; cs < gpmc_cs_num; cs++) { |
da496873 AM |
1366 | if (!gpmc_cs_mem_enabled(cs)) |
1367 | continue; | |
1368 | gpmc_cs_delete_mem(cs); | |
1369 | } | |
1370 | ||
1371 | } | |
1372 | ||
84b00f0e | 1373 | static void gpmc_mem_init(void) |
f37e4580 | 1374 | { |
84b00f0e | 1375 | int cs; |
f37e4580 | 1376 | |
bdd7e033 | 1377 | gpmc_mem_root.start = GPMC_MEM_START; |
f37e4580 ID |
1378 | gpmc_mem_root.end = GPMC_MEM_END; |
1379 | ||
1380 | /* Reserve all regions that has been set up by bootloader */ | |
f34f3716 | 1381 | for (cs = 0; cs < gpmc_cs_num; cs++) { |
f37e4580 ID |
1382 | u32 base, size; |
1383 | ||
1384 | if (!gpmc_cs_mem_enabled(cs)) | |
1385 | continue; | |
1386 | gpmc_cs_get_memconf(cs, &base, &size); | |
84b00f0e JH |
1387 | if (gpmc_cs_insert_mem(cs, base, size)) { |
1388 | pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", | |
1389 | __func__, cs, base, base + size); | |
1390 | gpmc_cs_disable_mem(cs); | |
8119024e | 1391 | } |
f37e4580 | 1392 | } |
4bbbc1ad JY |
1393 | } |
1394 | ||
246da26d AM |
1395 | static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) |
1396 | { | |
1397 | u32 temp; | |
1398 | int div; | |
1399 | ||
1400 | div = gpmc_calc_divider(sync_clk); | |
1401 | temp = gpmc_ps_to_ticks(time_ps); | |
1402 | temp = (temp + div - 1) / div; | |
1403 | return gpmc_ticks_to_ps(temp * div); | |
1404 | } | |
1405 | ||
1406 | /* XXX: can the cycles be avoided ? */ | |
1407 | static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1408 | struct gpmc_device_timings *dev_t, |
1409 | bool mux) | |
246da26d | 1410 | { |
246da26d AM |
1411 | u32 temp; |
1412 | ||
1413 | /* adv_rd_off */ | |
1414 | temp = dev_t->t_avdp_r; | |
1415 | /* XXX: mux check required ? */ | |
1416 | if (mux) { | |
1417 | /* XXX: t_avdp not to be required for sync, only added for tusb | |
1418 | * this indirectly necessitates requirement of t_avdp_r and | |
1419 | * t_avdp_w instead of having a single t_avdp | |
1420 | */ | |
1421 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); | |
1422 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1423 | } | |
1424 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
1425 | ||
1426 | /* oe_on */ | |
1427 | temp = dev_t->t_oeasu; /* XXX: remove this ? */ | |
1428 | if (mux) { | |
1429 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); | |
1430 | temp = max_t(u32, temp, gpmc_t->adv_rd_off + | |
1431 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); | |
1432 | } | |
1433 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
1434 | ||
1435 | /* access */ | |
1436 | /* XXX: any scope for improvement ?, by combining oe_on | |
1437 | * and clk_activation, need to check whether | |
1438 | * access = clk_activation + round to sync clk ? | |
1439 | */ | |
1440 | temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); | |
1441 | temp += gpmc_t->clk_activation; | |
1442 | if (dev_t->cyc_oe) | |
1443 | temp = max_t(u32, temp, gpmc_t->oe_on + | |
1444 | gpmc_ticks_to_ps(dev_t->cyc_oe)); | |
1445 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
1446 | ||
1447 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
1448 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
1449 | ||
1450 | /* rd_cycle */ | |
1451 | temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); | |
1452 | temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + | |
1453 | gpmc_t->access; | |
1454 | /* XXX: barter t_ce_rdyz with t_cez_r ? */ | |
1455 | if (dev_t->t_ce_rdyz) | |
1456 | temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); | |
1457 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
1458 | ||
1459 | return 0; | |
1460 | } | |
1461 | ||
1462 | static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1463 | struct gpmc_device_timings *dev_t, |
1464 | bool mux) | |
246da26d | 1465 | { |
246da26d AM |
1466 | u32 temp; |
1467 | ||
1468 | /* adv_wr_off */ | |
1469 | temp = dev_t->t_avdp_w; | |
1470 | if (mux) { | |
1471 | temp = max_t(u32, temp, | |
1472 | gpmc_t->clk_activation + dev_t->t_avdh); | |
1473 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1474 | } | |
1475 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
1476 | ||
1477 | /* wr_data_mux_bus */ | |
1478 | temp = max_t(u32, dev_t->t_weasu, | |
1479 | gpmc_t->clk_activation + dev_t->t_rdyo); | |
1480 | /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, | |
1481 | * and in that case remember to handle we_on properly | |
1482 | */ | |
1483 | if (mux) { | |
1484 | temp = max_t(u32, temp, | |
1485 | gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1486 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1487 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1488 | } | |
1489 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1490 | ||
1491 | /* we_on */ | |
1492 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1493 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1494 | else | |
1495 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1496 | ||
1497 | /* wr_access */ | |
1498 | /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ | |
1499 | gpmc_t->wr_access = gpmc_t->access; | |
1500 | ||
1501 | /* we_off */ | |
1502 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1503 | temp = max_t(u32, temp, | |
1504 | gpmc_t->wr_access + gpmc_ticks_to_ps(1)); | |
1505 | temp = max_t(u32, temp, | |
1506 | gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); | |
1507 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1508 | ||
1509 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1510 | dev_t->t_wph); | |
1511 | ||
1512 | /* wr_cycle */ | |
1513 | temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); | |
1514 | temp += gpmc_t->wr_access; | |
1515 | /* XXX: barter t_ce_rdyz with t_cez_w ? */ | |
1516 | if (dev_t->t_ce_rdyz) | |
1517 | temp = max_t(u32, temp, | |
1518 | gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); | |
1519 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1520 | ||
1521 | return 0; | |
1522 | } | |
1523 | ||
1524 | static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1525 | struct gpmc_device_timings *dev_t, |
1526 | bool mux) | |
246da26d | 1527 | { |
246da26d AM |
1528 | u32 temp; |
1529 | ||
1530 | /* adv_rd_off */ | |
1531 | temp = dev_t->t_avdp_r; | |
1532 | if (mux) | |
1533 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1534 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
1535 | ||
1536 | /* oe_on */ | |
1537 | temp = dev_t->t_oeasu; | |
1538 | if (mux) | |
1539 | temp = max_t(u32, temp, | |
1540 | gpmc_t->adv_rd_off + dev_t->t_aavdh); | |
1541 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
1542 | ||
1543 | /* access */ | |
1544 | temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ | |
1545 | gpmc_t->oe_on + dev_t->t_oe); | |
1546 | temp = max_t(u32, temp, | |
1547 | gpmc_t->cs_on + dev_t->t_ce); | |
1548 | temp = max_t(u32, temp, | |
1549 | gpmc_t->adv_on + dev_t->t_aa); | |
1550 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
1551 | ||
1552 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
1553 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
1554 | ||
1555 | /* rd_cycle */ | |
1556 | temp = max_t(u32, dev_t->t_rd_cycle, | |
1557 | gpmc_t->cs_rd_off + dev_t->t_cez_r); | |
1558 | temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); | |
1559 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
1560 | ||
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1565 | struct gpmc_device_timings *dev_t, |
1566 | bool mux) | |
246da26d | 1567 | { |
246da26d AM |
1568 | u32 temp; |
1569 | ||
1570 | /* adv_wr_off */ | |
1571 | temp = dev_t->t_avdp_w; | |
1572 | if (mux) | |
1573 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1574 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
1575 | ||
1576 | /* wr_data_mux_bus */ | |
1577 | temp = dev_t->t_weasu; | |
1578 | if (mux) { | |
1579 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1580 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1581 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1582 | } | |
1583 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1584 | ||
1585 | /* we_on */ | |
1586 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1587 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1588 | else | |
1589 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1590 | ||
1591 | /* we_off */ | |
1592 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1593 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1594 | ||
1595 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1596 | dev_t->t_wph); | |
1597 | ||
1598 | /* wr_cycle */ | |
1599 | temp = max_t(u32, dev_t->t_wr_cycle, | |
1600 | gpmc_t->cs_wr_off + dev_t->t_cez_w); | |
1601 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1602 | ||
1603 | return 0; | |
1604 | } | |
1605 | ||
1606 | static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, | |
1607 | struct gpmc_device_timings *dev_t) | |
1608 | { | |
1609 | u32 temp; | |
1610 | ||
1611 | gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * | |
1612 | gpmc_get_fclk_period(); | |
1613 | ||
1614 | gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( | |
1615 | dev_t->t_bacc, | |
1616 | gpmc_t->sync_clk); | |
1617 | ||
1618 | temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); | |
1619 | gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); | |
1620 | ||
1621 | if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) | |
1622 | return 0; | |
1623 | ||
1624 | if (dev_t->ce_xdelay) | |
1625 | gpmc_t->bool_timings.cs_extra_delay = true; | |
1626 | if (dev_t->avd_xdelay) | |
1627 | gpmc_t->bool_timings.adv_extra_delay = true; | |
1628 | if (dev_t->oe_xdelay) | |
1629 | gpmc_t->bool_timings.oe_extra_delay = true; | |
1630 | if (dev_t->we_xdelay) | |
1631 | gpmc_t->bool_timings.we_extra_delay = true; | |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1637 | struct gpmc_device_timings *dev_t, |
1638 | bool sync) | |
246da26d AM |
1639 | { |
1640 | u32 temp; | |
1641 | ||
1642 | /* cs_on */ | |
1643 | gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); | |
1644 | ||
1645 | /* adv_on */ | |
1646 | temp = dev_t->t_avdasu; | |
1647 | if (dev_t->t_ce_avd) | |
1648 | temp = max_t(u32, temp, | |
1649 | gpmc_t->cs_on + dev_t->t_ce_avd); | |
1650 | gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); | |
1651 | ||
c3be5b45 | 1652 | if (sync) |
246da26d AM |
1653 | gpmc_calc_sync_common_timings(gpmc_t, dev_t); |
1654 | ||
1655 | return 0; | |
1656 | } | |
1657 | ||
1658 | /* TODO: remove this function once all peripherals are confirmed to | |
1659 | * work with generic timing. Simultaneously gpmc_cs_set_timings() | |
1660 | * has to be modified to handle timings in ps instead of ns | |
1661 | */ | |
1662 | static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) | |
1663 | { | |
1664 | t->cs_on /= 1000; | |
1665 | t->cs_rd_off /= 1000; | |
1666 | t->cs_wr_off /= 1000; | |
1667 | t->adv_on /= 1000; | |
1668 | t->adv_rd_off /= 1000; | |
1669 | t->adv_wr_off /= 1000; | |
1670 | t->we_on /= 1000; | |
1671 | t->we_off /= 1000; | |
1672 | t->oe_on /= 1000; | |
1673 | t->oe_off /= 1000; | |
1674 | t->page_burst_access /= 1000; | |
1675 | t->access /= 1000; | |
1676 | t->rd_cycle /= 1000; | |
1677 | t->wr_cycle /= 1000; | |
1678 | t->bus_turnaround /= 1000; | |
1679 | t->cycle2cycle_delay /= 1000; | |
1680 | t->wait_monitoring /= 1000; | |
1681 | t->clk_activation /= 1000; | |
1682 | t->wr_access /= 1000; | |
1683 | t->wr_data_mux_bus /= 1000; | |
1684 | } | |
1685 | ||
1686 | int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1687 | struct gpmc_settings *gpmc_s, |
1688 | struct gpmc_device_timings *dev_t) | |
246da26d | 1689 | { |
c3be5b45 JH |
1690 | bool mux = false, sync = false; |
1691 | ||
1692 | if (gpmc_s) { | |
1693 | mux = gpmc_s->mux_add_data ? true : false; | |
1694 | sync = (gpmc_s->sync_read || gpmc_s->sync_write); | |
1695 | } | |
1696 | ||
246da26d AM |
1697 | memset(gpmc_t, 0, sizeof(*gpmc_t)); |
1698 | ||
c3be5b45 | 1699 | gpmc_calc_common_timings(gpmc_t, dev_t, sync); |
246da26d | 1700 | |
c3be5b45 JH |
1701 | if (gpmc_s && gpmc_s->sync_read) |
1702 | gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); | |
246da26d | 1703 | else |
c3be5b45 | 1704 | gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); |
246da26d | 1705 | |
c3be5b45 JH |
1706 | if (gpmc_s && gpmc_s->sync_write) |
1707 | gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); | |
246da26d | 1708 | else |
c3be5b45 | 1709 | gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); |
246da26d AM |
1710 | |
1711 | /* TODO: remove, see function definition */ | |
1712 | gpmc_convert_ps_to_ns(gpmc_t); | |
1713 | ||
1714 | return 0; | |
1715 | } | |
1716 | ||
aa8d4767 JH |
1717 | /** |
1718 | * gpmc_cs_program_settings - programs non-timing related settings | |
1719 | * @cs: GPMC chip-select to program | |
1720 | * @p: pointer to GPMC settings structure | |
1721 | * | |
1722 | * Programs non-timing related settings for a GPMC chip-select, such as | |
1723 | * bus-width, burst configuration, etc. Function should be called once | |
1724 | * for each chip-select that is being used and must be called before | |
1725 | * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 | |
1726 | * register will be initialised to zero by this function. Returns 0 on | |
1727 | * success and appropriate negative error code on failure. | |
1728 | */ | |
1729 | int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) | |
1730 | { | |
1731 | u32 config1; | |
1732 | ||
1733 | if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { | |
1734 | pr_err("%s: invalid width %d!", __func__, p->device_width); | |
1735 | return -EINVAL; | |
1736 | } | |
1737 | ||
1738 | /* Address-data multiplexing not supported for NAND devices */ | |
1739 | if (p->device_nand && p->mux_add_data) { | |
1740 | pr_err("%s: invalid configuration!\n", __func__); | |
1741 | return -EINVAL; | |
1742 | } | |
1743 | ||
1744 | if ((p->mux_add_data > GPMC_MUX_AD) || | |
1745 | ((p->mux_add_data == GPMC_MUX_AAD) && | |
1746 | !(gpmc_capability & GPMC_HAS_MUX_AAD))) { | |
1747 | pr_err("%s: invalid multiplex configuration!\n", __func__); | |
1748 | return -EINVAL; | |
1749 | } | |
1750 | ||
1751 | /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ | |
1752 | if (p->burst_read || p->burst_write) { | |
1753 | switch (p->burst_len) { | |
1754 | case GPMC_BURST_4: | |
1755 | case GPMC_BURST_8: | |
1756 | case GPMC_BURST_16: | |
1757 | break; | |
1758 | default: | |
1759 | pr_err("%s: invalid page/burst-length (%d)\n", | |
1760 | __func__, p->burst_len); | |
1761 | return -EINVAL; | |
1762 | } | |
1763 | } | |
1764 | ||
2b54057c | 1765 | if (p->wait_pin > gpmc_nr_waitpins) { |
aa8d4767 JH |
1766 | pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); |
1767 | return -EINVAL; | |
1768 | } | |
1769 | ||
1770 | config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); | |
1771 | ||
1772 | if (p->sync_read) | |
1773 | config1 |= GPMC_CONFIG1_READTYPE_SYNC; | |
1774 | if (p->sync_write) | |
1775 | config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; | |
1776 | if (p->wait_on_read) | |
1777 | config1 |= GPMC_CONFIG1_WAIT_READ_MON; | |
1778 | if (p->wait_on_write) | |
1779 | config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; | |
1780 | if (p->wait_on_read || p->wait_on_write) | |
1781 | config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); | |
1782 | if (p->device_nand) | |
1783 | config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); | |
1784 | if (p->mux_add_data) | |
1785 | config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); | |
1786 | if (p->burst_read) | |
1787 | config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; | |
1788 | if (p->burst_write) | |
1789 | config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; | |
1790 | if (p->burst_read || p->burst_write) { | |
1791 | config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); | |
1792 | config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; | |
1793 | } | |
1794 | ||
1795 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); | |
1796 | ||
1797 | return 0; | |
1798 | } | |
1799 | ||
bc6b1e7b | 1800 | #ifdef CONFIG_OF |
31957609 | 1801 | static const struct of_device_id gpmc_dt_ids[] = { |
bc6b1e7b DM |
1802 | { .compatible = "ti,omap2420-gpmc" }, |
1803 | { .compatible = "ti,omap2430-gpmc" }, | |
1804 | { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ | |
1805 | { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ | |
1806 | { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ | |
1807 | { } | |
1808 | }; | |
bc6b1e7b | 1809 | |
8c8a7771 JH |
1810 | /** |
1811 | * gpmc_read_settings_dt - read gpmc settings from device-tree | |
1812 | * @np: pointer to device-tree node for a gpmc child device | |
1813 | * @p: pointer to gpmc settings structure | |
1814 | * | |
1815 | * Reads the GPMC settings for a GPMC child device from device-tree and | |
1816 | * stores them in the GPMC settings structure passed. The GPMC settings | |
1817 | * structure is initialised to zero by this function and so any | |
1818 | * previously stored settings will be cleared. | |
1819 | */ | |
1820 | void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) | |
1821 | { | |
1822 | memset(p, 0, sizeof(struct gpmc_settings)); | |
1823 | ||
1824 | p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); | |
1825 | p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); | |
8c8a7771 JH |
1826 | of_property_read_u32(np, "gpmc,device-width", &p->device_width); |
1827 | of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); | |
1828 | ||
1829 | if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { | |
1830 | p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); | |
1831 | p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); | |
1832 | p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); | |
1833 | if (!p->burst_read && !p->burst_write) | |
1834 | pr_warn("%s: page/burst-length set but not used!\n", | |
1835 | __func__); | |
1836 | } | |
1837 | ||
1838 | if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { | |
1839 | p->wait_on_read = of_property_read_bool(np, | |
1840 | "gpmc,wait-on-read"); | |
1841 | p->wait_on_write = of_property_read_bool(np, | |
1842 | "gpmc,wait-on-write"); | |
1843 | if (!p->wait_on_read && !p->wait_on_write) | |
2b54057c RQ |
1844 | pr_debug("%s: rd/wr wait monitoring not enabled!\n", |
1845 | __func__); | |
8c8a7771 JH |
1846 | } |
1847 | } | |
1848 | ||
bc6b1e7b DM |
1849 | static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, |
1850 | struct gpmc_timings *gpmc_t) | |
1851 | { | |
d36b4cd4 JH |
1852 | struct gpmc_bool_timings *p; |
1853 | ||
1854 | if (!np || !gpmc_t) | |
1855 | return; | |
bc6b1e7b DM |
1856 | |
1857 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | |
1858 | ||
1859 | /* minimum clock period for syncronous mode */ | |
d36b4cd4 | 1860 | of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); |
bc6b1e7b DM |
1861 | |
1862 | /* chip select timtings */ | |
d36b4cd4 JH |
1863 | of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); |
1864 | of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); | |
1865 | of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); | |
bc6b1e7b DM |
1866 | |
1867 | /* ADV signal timings */ | |
d36b4cd4 JH |
1868 | of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); |
1869 | of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); | |
1870 | of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); | |
2c92c04b NA |
1871 | of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns", |
1872 | &gpmc_t->adv_aad_mux_on); | |
1873 | of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns", | |
1874 | &gpmc_t->adv_aad_mux_rd_off); | |
1875 | of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns", | |
1876 | &gpmc_t->adv_aad_mux_wr_off); | |
bc6b1e7b DM |
1877 | |
1878 | /* WE signal timings */ | |
d36b4cd4 JH |
1879 | of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); |
1880 | of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); | |
bc6b1e7b DM |
1881 | |
1882 | /* OE signal timings */ | |
d36b4cd4 JH |
1883 | of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); |
1884 | of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); | |
2c92c04b NA |
1885 | of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns", |
1886 | &gpmc_t->oe_aad_mux_on); | |
1887 | of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns", | |
1888 | &gpmc_t->oe_aad_mux_off); | |
bc6b1e7b DM |
1889 | |
1890 | /* access and cycle timings */ | |
d36b4cd4 JH |
1891 | of_property_read_u32(np, "gpmc,page-burst-access-ns", |
1892 | &gpmc_t->page_burst_access); | |
1893 | of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); | |
1894 | of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); | |
1895 | of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); | |
1896 | of_property_read_u32(np, "gpmc,bus-turnaround-ns", | |
1897 | &gpmc_t->bus_turnaround); | |
1898 | of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", | |
1899 | &gpmc_t->cycle2cycle_delay); | |
1900 | of_property_read_u32(np, "gpmc,wait-monitoring-ns", | |
1901 | &gpmc_t->wait_monitoring); | |
1902 | of_property_read_u32(np, "gpmc,clk-activation-ns", | |
1903 | &gpmc_t->clk_activation); | |
1904 | ||
1905 | /* only applicable to OMAP3+ */ | |
1906 | of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); | |
1907 | of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", | |
1908 | &gpmc_t->wr_data_mux_bus); | |
1909 | ||
1910 | /* bool timing parameters */ | |
1911 | p = &gpmc_t->bool_timings; | |
1912 | ||
1913 | p->cycle2cyclediffcsen = | |
1914 | of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); | |
1915 | p->cycle2cyclesamecsen = | |
1916 | of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); | |
1917 | p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); | |
1918 | p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); | |
1919 | p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); | |
1920 | p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); | |
1921 | p->time_para_granularity = | |
1922 | of_property_read_bool(np, "gpmc,time-para-granularity"); | |
bc6b1e7b DM |
1923 | } |
1924 | ||
980386d2 | 1925 | #if IS_ENABLED(CONFIG_MTD_ONENAND) |
75d3625e EG |
1926 | static int gpmc_probe_onenand_child(struct platform_device *pdev, |
1927 | struct device_node *child) | |
1928 | { | |
1929 | u32 val; | |
1930 | struct omap_onenand_platform_data *gpmc_onenand_data; | |
1931 | ||
1932 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1933 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1934 | child->full_name); | |
1935 | return -ENODEV; | |
1936 | } | |
1937 | ||
1938 | gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data), | |
1939 | GFP_KERNEL); | |
1940 | if (!gpmc_onenand_data) | |
1941 | return -ENOMEM; | |
1942 | ||
1943 | gpmc_onenand_data->cs = val; | |
1944 | gpmc_onenand_data->of_node = child; | |
1945 | gpmc_onenand_data->dma_channel = -1; | |
1946 | ||
1947 | if (!of_property_read_u32(child, "dma-channel", &val)) | |
1948 | gpmc_onenand_data->dma_channel = val; | |
1949 | ||
7807e086 | 1950 | return gpmc_onenand_init(gpmc_onenand_data); |
75d3625e EG |
1951 | } |
1952 | #else | |
1953 | static int gpmc_probe_onenand_child(struct platform_device *pdev, | |
1954 | struct device_node *child) | |
1955 | { | |
1956 | return 0; | |
1957 | } | |
1958 | #endif | |
1959 | ||
cdd6928c | 1960 | /** |
3af91cf7 | 1961 | * gpmc_probe_generic_child - configures the gpmc for a child device |
cdd6928c | 1962 | * @pdev: pointer to gpmc platform device |
3af91cf7 | 1963 | * @child: pointer to device-tree node for child device |
cdd6928c | 1964 | * |
3af91cf7 | 1965 | * Allocates and configures a GPMC chip-select for a child device. |
cdd6928c JH |
1966 | * Returns 0 on success and appropriate negative error code on failure. |
1967 | */ | |
3af91cf7 | 1968 | static int gpmc_probe_generic_child(struct platform_device *pdev, |
cdd6928c JH |
1969 | struct device_node *child) |
1970 | { | |
1971 | struct gpmc_settings gpmc_s; | |
1972 | struct gpmc_timings gpmc_t; | |
1973 | struct resource res; | |
1974 | unsigned long base; | |
9ed7a776 | 1975 | const char *name; |
cdd6928c | 1976 | int ret, cs; |
e378d22b | 1977 | u32 val; |
210325f0 RQ |
1978 | struct gpio_desc *waitpin_desc = NULL; |
1979 | struct gpmc_device *gpmc = platform_get_drvdata(pdev); | |
cdd6928c JH |
1980 | |
1981 | if (of_property_read_u32(child, "reg", &cs) < 0) { | |
1982 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1983 | child->full_name); | |
1984 | return -ENODEV; | |
1985 | } | |
1986 | ||
1987 | if (of_address_to_resource(child, 0, &res) < 0) { | |
1988 | dev_err(&pdev->dev, "%s has malformed 'reg' property\n", | |
1989 | child->full_name); | |
1990 | return -ENODEV; | |
1991 | } | |
1992 | ||
9ed7a776 TL |
1993 | /* |
1994 | * Check if we have multiple instances of the same device | |
1995 | * on a single chip select. If so, use the already initialized | |
1996 | * timings. | |
1997 | */ | |
1998 | name = gpmc_cs_get_name(cs); | |
1999 | if (name && child->name && of_node_cmp(child->name, name) == 0) | |
2000 | goto no_timings; | |
2001 | ||
cdd6928c JH |
2002 | ret = gpmc_cs_request(cs, resource_size(&res), &base); |
2003 | if (ret < 0) { | |
2004 | dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); | |
2005 | return ret; | |
2006 | } | |
9ed7a776 | 2007 | gpmc_cs_set_name(cs, child->name); |
cdd6928c | 2008 | |
35ac051e TL |
2009 | gpmc_read_settings_dt(child, &gpmc_s); |
2010 | gpmc_read_timings_dt(child, &gpmc_t); | |
cdd6928c | 2011 | |
fd4446f2 TL |
2012 | /* |
2013 | * For some GPMC devices we still need to rely on the bootloader | |
35ac051e TL |
2014 | * timings because the devices can be connected via FPGA. |
2015 | * REVISIT: Add timing support from slls644g.pdf. | |
fd4446f2 | 2016 | */ |
35ac051e TL |
2017 | if (!gpmc_t.cs_rd_off) { |
2018 | WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", | |
2019 | cs); | |
2020 | gpmc_cs_show_timings(cs, | |
2021 | "please add GPMC bootloader timings to .dts"); | |
fd4446f2 TL |
2022 | goto no_timings; |
2023 | } | |
2024 | ||
4cf27d2e RQ |
2025 | /* CS must be disabled while making changes to gpmc configuration */ |
2026 | gpmc_cs_disable_mem(cs); | |
2027 | ||
cdd6928c JH |
2028 | /* |
2029 | * FIXME: gpmc_cs_request() will map the CS to an arbitary | |
2030 | * location in the gpmc address space. When booting with | |
2031 | * device-tree we want the NOR flash to be mapped to the | |
2032 | * location specified in the device-tree blob. So remap the | |
2033 | * CS to this location. Once DT migration is complete should | |
2034 | * just make gpmc_cs_request() map a specific address. | |
2035 | */ | |
2036 | ret = gpmc_cs_remap(cs, res.start); | |
2037 | if (ret < 0) { | |
f70bf2a3 FE |
2038 | dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", |
2039 | cs, &res.start); | |
bdd7e033 RQ |
2040 | if (res.start < GPMC_MEM_START) { |
2041 | dev_info(&pdev->dev, | |
2042 | "GPMC CS %d start cannot be lesser than 0x%x\n", | |
2043 | cs, GPMC_MEM_START); | |
2044 | } else if (res.end > GPMC_MEM_END) { | |
2045 | dev_info(&pdev->dev, | |
2046 | "GPMC CS %d end cannot be greater than 0x%x\n", | |
2047 | cs, GPMC_MEM_END); | |
2048 | } | |
cdd6928c JH |
2049 | goto err; |
2050 | } | |
2051 | ||
c9711ec5 RQ |
2052 | if (of_node_cmp(child->name, "nand") == 0) { |
2053 | /* Warn about older DT blobs with no compatible property */ | |
2054 | if (!of_property_read_bool(child, "compatible")) { | |
2055 | dev_warn(&pdev->dev, | |
2056 | "Incompatible NAND node: missing compatible"); | |
2057 | ret = -EINVAL; | |
2058 | goto err; | |
2059 | } | |
2060 | } | |
2061 | ||
2062 | if (of_device_is_compatible(child, "ti,omap2-nand")) { | |
2063 | /* NAND specific setup */ | |
f679888f BB |
2064 | val = 8; |
2065 | of_property_read_u32(child, "nand-bus-width", &val); | |
c9711ec5 RQ |
2066 | switch (val) { |
2067 | case 8: | |
2068 | gpmc_s.device_width = GPMC_DEVWIDTH_8BIT; | |
2069 | break; | |
2070 | case 16: | |
2071 | gpmc_s.device_width = GPMC_DEVWIDTH_16BIT; | |
2072 | break; | |
2073 | default: | |
2074 | dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n", | |
2075 | child->name); | |
2076 | ret = -EINVAL; | |
2077 | goto err; | |
2078 | } | |
2079 | ||
2080 | /* disable write protect */ | |
2081 | gpmc_configure(GPMC_CONFIG_WP, 0); | |
2082 | gpmc_s.device_nand = true; | |
2083 | } else { | |
2084 | ret = of_property_read_u32(child, "bank-width", | |
2085 | &gpmc_s.device_width); | |
2086 | if (ret < 0) | |
2087 | goto err; | |
2088 | } | |
cdd6928c | 2089 | |
210325f0 RQ |
2090 | /* Reserve wait pin if it is required and valid */ |
2091 | if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) { | |
2092 | unsigned int wait_pin = gpmc_s.wait_pin; | |
2093 | ||
2094 | waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, | |
2095 | wait_pin, "WAITPIN"); | |
2096 | if (IS_ERR(waitpin_desc)) { | |
2097 | dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin); | |
2098 | ret = PTR_ERR(waitpin_desc); | |
2099 | goto err; | |
2100 | } | |
2101 | } | |
2102 | ||
fd820a1e | 2103 | gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); |
210325f0 | 2104 | |
cdd6928c JH |
2105 | ret = gpmc_cs_program_settings(cs, &gpmc_s); |
2106 | if (ret < 0) | |
210325f0 | 2107 | goto err_cs; |
cdd6928c | 2108 | |
2e676901 | 2109 | ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); |
7604baf3 RQ |
2110 | if (ret) { |
2111 | dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n", | |
2112 | child->name); | |
210325f0 | 2113 | goto err_cs; |
7604baf3 | 2114 | } |
cdd6928c | 2115 | |
e378d22b RQ |
2116 | /* Clear limited address i.e. enable A26-A11 */ |
2117 | val = gpmc_read_reg(GPMC_CONFIG); | |
2118 | val &= ~GPMC_CONFIG_LIMITEDADDRESS; | |
2119 | gpmc_write_reg(GPMC_CONFIG, val); | |
2120 | ||
4cf27d2e RQ |
2121 | /* Enable CS region */ |
2122 | gpmc_cs_enable_mem(cs); | |
cdd6928c | 2123 | |
fd4446f2 | 2124 | no_timings: |
b1dc1ca9 RA |
2125 | |
2126 | /* create platform device, NULL on error or when disabled */ | |
2127 | if (!of_platform_device_create(child, NULL, &pdev->dev)) | |
2128 | goto err_child_fail; | |
2129 | ||
2130 | /* is child a common bus? */ | |
2131 | if (of_match_node(of_default_bus_match_table, child)) | |
2132 | /* create children and other common bus children */ | |
9f2c519c | 2133 | if (of_platform_default_populate(child, NULL, &pdev->dev)) |
b1dc1ca9 RA |
2134 | goto err_child_fail; |
2135 | ||
2136 | return 0; | |
2137 | ||
2138 | err_child_fail: | |
cdd6928c JH |
2139 | |
2140 | dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); | |
e8ffd6fd | 2141 | ret = -ENODEV; |
cdd6928c | 2142 | |
210325f0 | 2143 | err_cs: |
3f41a3c4 | 2144 | gpiochip_free_own_desc(waitpin_desc); |
cdd6928c JH |
2145 | err: |
2146 | gpmc_cs_free(cs); | |
2147 | ||
2148 | return ret; | |
2149 | } | |
2150 | ||
bc6b1e7b DM |
2151 | static int gpmc_probe_dt(struct platform_device *pdev) |
2152 | { | |
2153 | int ret; | |
bc6b1e7b DM |
2154 | const struct of_device_id *of_id = |
2155 | of_match_device(gpmc_dt_ids, &pdev->dev); | |
2156 | ||
2157 | if (!of_id) | |
2158 | return 0; | |
2159 | ||
f34f3716 GP |
2160 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", |
2161 | &gpmc_cs_num); | |
2162 | if (ret < 0) { | |
2163 | pr_err("%s: number of chip-selects not defined\n", __func__); | |
2164 | return ret; | |
2165 | } else if (gpmc_cs_num < 1) { | |
2166 | pr_err("%s: all chip-selects are disabled\n", __func__); | |
2167 | return -EINVAL; | |
2168 | } else if (gpmc_cs_num > GPMC_CS_NUM) { | |
2169 | pr_err("%s: number of supported chip-selects cannot be > %d\n", | |
2170 | __func__, GPMC_CS_NUM); | |
2171 | return -EINVAL; | |
2172 | } | |
2173 | ||
9f833156 JH |
2174 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", |
2175 | &gpmc_nr_waitpins); | |
2176 | if (ret < 0) { | |
2177 | pr_err("%s: number of wait pins not found!\n", __func__); | |
2178 | return ret; | |
2179 | } | |
2180 | ||
d2d00862 RQ |
2181 | return 0; |
2182 | } | |
2183 | ||
23540d6e | 2184 | static void gpmc_probe_dt_children(struct platform_device *pdev) |
d2d00862 RQ |
2185 | { |
2186 | int ret; | |
2187 | struct device_node *child; | |
2188 | ||
68e2eb53 | 2189 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
bc6b1e7b | 2190 | |
f2b09f67 JMC |
2191 | if (!child->name) |
2192 | continue; | |
cdd6928c | 2193 | |
c9711ec5 | 2194 | if (of_node_cmp(child->name, "onenand") == 0) |
f2b09f67 | 2195 | ret = gpmc_probe_onenand_child(pdev, child); |
28a7eedd | 2196 | else |
f2b09f67 | 2197 | ret = gpmc_probe_generic_child(pdev, child); |
d2d00862 | 2198 | |
23540d6e JH |
2199 | if (ret) { |
2200 | dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n", | |
2201 | child->name, ret); | |
2202 | } | |
5330dc16 | 2203 | } |
bc6b1e7b DM |
2204 | } |
2205 | #else | |
2206 | static int gpmc_probe_dt(struct platform_device *pdev) | |
2207 | { | |
2208 | return 0; | |
2209 | } | |
d2d00862 | 2210 | |
23540d6e | 2211 | static void gpmc_probe_dt_children(struct platform_device *pdev) |
d2d00862 | 2212 | { |
d2d00862 | 2213 | } |
32dd625a RQ |
2214 | #endif /* CONFIG_OF */ |
2215 | ||
2216 | static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) | |
2217 | { | |
2218 | return 1; /* we're input only */ | |
2219 | } | |
2220 | ||
2221 | static int gpmc_gpio_direction_input(struct gpio_chip *chip, | |
2222 | unsigned int offset) | |
2223 | { | |
2224 | return 0; /* we're input only */ | |
2225 | } | |
2226 | ||
2227 | static int gpmc_gpio_direction_output(struct gpio_chip *chip, | |
2228 | unsigned int offset, int value) | |
2229 | { | |
2230 | return -EINVAL; /* we're input only */ | |
2231 | } | |
2232 | ||
2233 | static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
2234 | int value) | |
2235 | { | |
2236 | } | |
2237 | ||
2238 | static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
2239 | { | |
2240 | u32 reg; | |
2241 | ||
2242 | offset += 8; | |
2243 | ||
2244 | reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset); | |
2245 | ||
2246 | return !!reg; | |
2247 | } | |
2248 | ||
2249 | static int gpmc_gpio_init(struct gpmc_device *gpmc) | |
2250 | { | |
2251 | int ret; | |
2252 | ||
2253 | gpmc->gpio_chip.parent = gpmc->dev; | |
2254 | gpmc->gpio_chip.owner = THIS_MODULE; | |
2255 | gpmc->gpio_chip.label = DEVICE_NAME; | |
2256 | gpmc->gpio_chip.ngpio = gpmc_nr_waitpins; | |
2257 | gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction; | |
2258 | gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input; | |
2259 | gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output; | |
2260 | gpmc->gpio_chip.set = gpmc_gpio_set; | |
2261 | gpmc->gpio_chip.get = gpmc_gpio_get; | |
2262 | gpmc->gpio_chip.base = -1; | |
2263 | ||
525fe43f | 2264 | ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL); |
32dd625a RQ |
2265 | if (ret < 0) { |
2266 | dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret); | |
2267 | return ret; | |
2268 | } | |
2269 | ||
2270 | return 0; | |
2271 | } | |
2272 | ||
351a102d | 2273 | static int gpmc_probe(struct platform_device *pdev) |
4bbbc1ad | 2274 | { |
8119024e | 2275 | int rc; |
6b6c32fc | 2276 | u32 l; |
da496873 | 2277 | struct resource *res; |
384258f2 RQ |
2278 | struct gpmc_device *gpmc; |
2279 | ||
2280 | gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL); | |
2281 | if (!gpmc) | |
2282 | return -ENOMEM; | |
2283 | ||
2284 | gpmc->dev = &pdev->dev; | |
2285 | platform_set_drvdata(pdev, gpmc); | |
4bbbc1ad | 2286 | |
da496873 AM |
2287 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2288 | if (res == NULL) | |
2289 | return -ENOENT; | |
8d08436d | 2290 | |
da496873 AM |
2291 | phys_base = res->start; |
2292 | mem_size = resource_size(res); | |
fd1dc87d | 2293 | |
5857bd98 TR |
2294 | gpmc_base = devm_ioremap_resource(&pdev->dev, res); |
2295 | if (IS_ERR(gpmc_base)) | |
2296 | return PTR_ERR(gpmc_base); | |
da496873 AM |
2297 | |
2298 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
384258f2 RQ |
2299 | if (!res) { |
2300 | dev_err(&pdev->dev, "Failed to get resource: irq\n"); | |
2301 | return -ENOENT; | |
2302 | } | |
2303 | ||
2304 | gpmc->irq = res->start; | |
da496873 | 2305 | |
8bf9be56 | 2306 | gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); |
da496873 | 2307 | if (IS_ERR(gpmc_l3_clk)) { |
8bf9be56 | 2308 | dev_err(&pdev->dev, "Failed to get GPMC fck\n"); |
da496873 | 2309 | return PTR_ERR(gpmc_l3_clk); |
fd1dc87d PW |
2310 | } |
2311 | ||
8bf9be56 RQ |
2312 | if (!clk_get_rate(gpmc_l3_clk)) { |
2313 | dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); | |
2314 | return -EINVAL; | |
2315 | } | |
2316 | ||
d2d00862 RQ |
2317 | if (pdev->dev.of_node) { |
2318 | rc = gpmc_probe_dt(pdev); | |
2319 | if (rc) | |
2320 | return rc; | |
2321 | } else { | |
2322 | gpmc_cs_num = GPMC_CS_NUM; | |
2323 | gpmc_nr_waitpins = GPMC_NR_WAITPINS; | |
2324 | } | |
2325 | ||
b3f5525c | 2326 | pm_runtime_enable(&pdev->dev); |
2327 | pm_runtime_get_sync(&pdev->dev); | |
1daa8c1d | 2328 | |
4bbbc1ad | 2329 | l = gpmc_read_reg(GPMC_REVISION); |
aa8d4767 JH |
2330 | |
2331 | /* | |
2332 | * FIXME: Once device-tree migration is complete the below flags | |
2333 | * should be populated based upon the device-tree compatible | |
2334 | * string. For now just use the IP revision. OMAP3+ devices have | |
2335 | * the wr_access and wr_data_mux_bus register fields. OMAP4+ | |
2336 | * devices support the addr-addr-data multiplex protocol. | |
2337 | * | |
2338 | * GPMC IP revisions: | |
2339 | * - OMAP24xx = 2.0 | |
2340 | * - OMAP3xxx = 5.0 | |
2341 | * - OMAP44xx/54xx/AM335x = 6.0 | |
2342 | */ | |
da496873 AM |
2343 | if (GPMC_REVISION_MAJOR(l) > 0x4) |
2344 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; | |
aa8d4767 JH |
2345 | if (GPMC_REVISION_MAJOR(l) > 0x5) |
2346 | gpmc_capability |= GPMC_HAS_MUX_AAD; | |
384258f2 | 2347 | dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), |
da496873 AM |
2348 | GPMC_REVISION_MINOR(l)); |
2349 | ||
84b00f0e | 2350 | gpmc_mem_init(); |
d2d00862 RQ |
2351 | rc = gpmc_gpio_init(gpmc); |
2352 | if (rc) | |
2353 | goto gpio_init_failed; | |
db97eb7d | 2354 | |
b2bac25a | 2355 | gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins; |
384258f2 RQ |
2356 | rc = gpmc_setup_irq(gpmc); |
2357 | if (rc) { | |
2358 | dev_err(gpmc->dev, "gpmc_setup_irq failed\n"); | |
525fe43f | 2359 | goto gpio_init_failed; |
384258f2 | 2360 | } |
da496873 | 2361 | |
23540d6e | 2362 | gpmc_probe_dt_children(pdev); |
bc6b1e7b | 2363 | |
da496873 | 2364 | return 0; |
384258f2 | 2365 | |
d2d00862 RQ |
2366 | gpio_init_failed: |
2367 | gpmc_mem_exit(); | |
384258f2 | 2368 | pm_runtime_put_sync(&pdev->dev); |
d2d00862 RQ |
2369 | pm_runtime_disable(&pdev->dev); |
2370 | ||
384258f2 | 2371 | return rc; |
da496873 AM |
2372 | } |
2373 | ||
351a102d | 2374 | static int gpmc_remove(struct platform_device *pdev) |
da496873 | 2375 | { |
384258f2 RQ |
2376 | struct gpmc_device *gpmc = platform_get_drvdata(pdev); |
2377 | ||
2378 | gpmc_free_irq(gpmc); | |
da496873 | 2379 | gpmc_mem_exit(); |
b3f5525c | 2380 | pm_runtime_put_sync(&pdev->dev); |
2381 | pm_runtime_disable(&pdev->dev); | |
384258f2 | 2382 | |
da496873 AM |
2383 | return 0; |
2384 | } | |
2385 | ||
b536dd41 | 2386 | #ifdef CONFIG_PM_SLEEP |
2387 | static int gpmc_suspend(struct device *dev) | |
2388 | { | |
2389 | omap3_gpmc_save_context(); | |
2390 | pm_runtime_put_sync(dev); | |
2391 | return 0; | |
2392 | } | |
2393 | ||
2394 | static int gpmc_resume(struct device *dev) | |
2395 | { | |
2396 | pm_runtime_get_sync(dev); | |
2397 | omap3_gpmc_restore_context(); | |
2398 | return 0; | |
2399 | } | |
2400 | #endif | |
2401 | ||
2402 | static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); | |
2403 | ||
da496873 AM |
2404 | static struct platform_driver gpmc_driver = { |
2405 | .probe = gpmc_probe, | |
351a102d | 2406 | .remove = gpmc_remove, |
da496873 AM |
2407 | .driver = { |
2408 | .name = DEVICE_NAME, | |
bc6b1e7b | 2409 | .of_match_table = of_match_ptr(gpmc_dt_ids), |
b536dd41 | 2410 | .pm = &gpmc_pm_ops, |
da496873 AM |
2411 | }, |
2412 | }; | |
2413 | ||
2414 | static __init int gpmc_init(void) | |
2415 | { | |
2416 | return platform_driver_register(&gpmc_driver); | |
2417 | } | |
a8612809 | 2418 | postcore_initcall(gpmc_init); |
db97eb7d | 2419 | |
a2d3e7ba RN |
2420 | static struct omap3_gpmc_regs gpmc_context; |
2421 | ||
b2fa3b7c | 2422 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
2423 | { |
2424 | int i; | |
b2fa3b7c | 2425 | |
e984a179 TV |
2426 | if (!gpmc_base) |
2427 | return; | |
2428 | ||
a2d3e7ba RN |
2429 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
2430 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
2431 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
2432 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
2433 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
2434 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
2435 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
f34f3716 | 2436 | for (i = 0; i < gpmc_cs_num; i++) { |
a2d3e7ba RN |
2437 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); |
2438 | if (gpmc_context.cs_context[i].is_valid) { | |
2439 | gpmc_context.cs_context[i].config1 = | |
2440 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
2441 | gpmc_context.cs_context[i].config2 = | |
2442 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
2443 | gpmc_context.cs_context[i].config3 = | |
2444 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
2445 | gpmc_context.cs_context[i].config4 = | |
2446 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
2447 | gpmc_context.cs_context[i].config5 = | |
2448 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
2449 | gpmc_context.cs_context[i].config6 = | |
2450 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
2451 | gpmc_context.cs_context[i].config7 = | |
2452 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
2453 | } | |
2454 | } | |
2455 | } | |
2456 | ||
b2fa3b7c | 2457 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
2458 | { |
2459 | int i; | |
b2fa3b7c | 2460 | |
e984a179 TV |
2461 | if (!gpmc_base) |
2462 | return; | |
2463 | ||
a2d3e7ba RN |
2464 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
2465 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
2466 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
2467 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
2468 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
2469 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
2470 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
f34f3716 | 2471 | for (i = 0; i < gpmc_cs_num; i++) { |
a2d3e7ba RN |
2472 | if (gpmc_context.cs_context[i].is_valid) { |
2473 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
2474 | gpmc_context.cs_context[i].config1); | |
2475 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
2476 | gpmc_context.cs_context[i].config2); | |
2477 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
2478 | gpmc_context.cs_context[i].config3); | |
2479 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
2480 | gpmc_context.cs_context[i].config4); | |
2481 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
2482 | gpmc_context.cs_context[i].config5); | |
2483 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
2484 | gpmc_context.cs_context[i].config6); | |
2485 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
2486 | gpmc_context.cs_context[i].config7); | |
2487 | } | |
2488 | } | |
2489 | } |