Commit | Line | Data |
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4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
db97eb7d | 15 | #include <linux/irq.h> |
4bbbc1ad JY |
16 | #include <linux/kernel.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
f37e4580 ID |
20 | #include <linux/ioport.h> |
21 | #include <linux/spinlock.h> | |
fced80c7 | 22 | #include <linux/io.h> |
fd1dc87d | 23 | #include <linux/module.h> |
d2d00862 | 24 | #include <linux/gpio/driver.h> |
db97eb7d | 25 | #include <linux/interrupt.h> |
384258f2 | 26 | #include <linux/irqdomain.h> |
da496873 | 27 | #include <linux/platform_device.h> |
bc6b1e7b | 28 | #include <linux/of.h> |
cdd6928c | 29 | #include <linux/of_address.h> |
bc6b1e7b DM |
30 | #include <linux/of_mtd.h> |
31 | #include <linux/of_device.h> | |
b1dc1ca9 | 32 | #include <linux/of_platform.h> |
e639cd5b | 33 | #include <linux/omap-gpmc.h> |
b3f5525c | 34 | #include <linux/pm_runtime.h> |
4bbbc1ad | 35 | |
bc3668ea | 36 | #include <linux/platform_data/mtd-nand-omap2.h> |
e639cd5b | 37 | #include <linux/platform_data/mtd-onenand-omap2.h> |
4bbbc1ad | 38 | |
7f245162 | 39 | #include <asm/mach-types.h> |
72d0f1c3 | 40 | |
4be48fd5 AM |
41 | #define DEVICE_NAME "omap-gpmc" |
42 | ||
fd1dc87d | 43 | /* GPMC register offsets */ |
4bbbc1ad JY |
44 | #define GPMC_REVISION 0x00 |
45 | #define GPMC_SYSCONFIG 0x10 | |
46 | #define GPMC_SYSSTATUS 0x14 | |
47 | #define GPMC_IRQSTATUS 0x18 | |
48 | #define GPMC_IRQENABLE 0x1c | |
49 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
50 | #define GPMC_ERR_ADDRESS 0x44 | |
51 | #define GPMC_ERR_TYPE 0x48 | |
52 | #define GPMC_CONFIG 0x50 | |
53 | #define GPMC_STATUS 0x54 | |
54 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
55 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 56 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
57 | #define GPMC_PREFETCH_STATUS 0x1f0 |
58 | #define GPMC_ECC_CONFIG 0x1f4 | |
59 | #define GPMC_ECC_CONTROL 0x1f8 | |
60 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 61 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 62 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
2fdf0c98 AM |
63 | #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ |
64 | #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ | |
65 | #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ | |
27c9fd60 | 66 | #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ |
67 | #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ | |
68 | #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ | |
4bbbc1ad | 69 | |
2c65e744 YY |
70 | /* GPMC ECC control settings */ |
71 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
72 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
73 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
74 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
75 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
76 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
77 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
78 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
79 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
80 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
81 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
82 | ||
e378d22b RQ |
83 | #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) |
84 | ||
512d73d1 RQ |
85 | #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0) |
86 | ||
559d94b0 AM |
87 | #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) |
88 | #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) | |
89 | #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) | |
90 | #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) | |
91 | #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) | |
92 | #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) | |
93 | ||
948d38e7 | 94 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad | 95 | #define GPMC_CS_SIZE 0x30 |
2fdf0c98 | 96 | #define GPMC_BCH_SIZE 0x10 |
4bbbc1ad | 97 | |
bdd7e033 RQ |
98 | /* |
99 | * The first 1MB of GPMC address space is typically mapped to | |
100 | * the internal ROM. Never allocate the first page, to | |
101 | * facilitate bug detection; even if we didn't boot from ROM. | |
102 | * As GPMC minimum partition size is 16MB we can only start from | |
103 | * there. | |
104 | */ | |
105 | #define GPMC_MEM_START 0x1000000 | |
f37e4580 | 106 | #define GPMC_MEM_END 0x3FFFFFFF |
f37e4580 ID |
107 | |
108 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
109 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
110 | ||
59e9c5ae | 111 | #define CS_NUM_SHIFT 24 |
112 | #define ENABLE_PREFETCH (0x1 << 7) | |
113 | #define DMA_MPU_MODE 2 | |
114 | ||
da496873 AM |
115 | #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) |
116 | #define GPMC_REVISION_MINOR(l) (l & 0xf) | |
117 | ||
118 | #define GPMC_HAS_WR_ACCESS 0x1 | |
119 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | |
aa8d4767 | 120 | #define GPMC_HAS_MUX_AAD 0x4 |
da496873 | 121 | |
9f833156 JH |
122 | #define GPMC_NR_WAITPINS 4 |
123 | ||
e639cd5b TL |
124 | #define GPMC_CS_CONFIG1 0x00 |
125 | #define GPMC_CS_CONFIG2 0x04 | |
126 | #define GPMC_CS_CONFIG3 0x08 | |
127 | #define GPMC_CS_CONFIG4 0x0c | |
128 | #define GPMC_CS_CONFIG5 0x10 | |
129 | #define GPMC_CS_CONFIG6 0x14 | |
130 | #define GPMC_CS_CONFIG7 0x18 | |
131 | #define GPMC_CS_NAND_COMMAND 0x1c | |
132 | #define GPMC_CS_NAND_ADDRESS 0x20 | |
133 | #define GPMC_CS_NAND_DATA 0x24 | |
134 | ||
135 | /* Control Commands */ | |
136 | #define GPMC_CONFIG_RDY_BSY 0x00000001 | |
137 | #define GPMC_CONFIG_DEV_SIZE 0x00000002 | |
138 | #define GPMC_CONFIG_DEV_TYPE 0x00000003 | |
e639cd5b TL |
139 | |
140 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | |
141 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) | |
142 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) | |
143 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | |
144 | #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) | |
145 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) | |
146 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | |
147 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | |
4b613e9b RA |
148 | /** CLKACTIVATIONTIME Max Ticks */ |
149 | #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2 | |
e639cd5b | 150 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) |
4b613e9b RA |
151 | /** ATTACHEDDEVICEPAGELENGTH Max Value */ |
152 | #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2 | |
e639cd5b TL |
153 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) |
154 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | |
2e676901 RA |
155 | #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18) |
156 | /** WAITMONITORINGTIME Max Ticks */ | |
157 | #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2 | |
e639cd5b TL |
158 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) |
159 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | |
160 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | |
4b613e9b RA |
161 | /** DEVICESIZE Max Value */ |
162 | #define GPMC_CONFIG1_DEVICESIZE_MAX 1 | |
e639cd5b TL |
163 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) |
164 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | |
165 | #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) | |
166 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | |
167 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | |
168 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | |
169 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | |
170 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | |
171 | #define GPMC_CONFIG7_CSVALID (1 << 6) | |
172 | ||
9c4f757e SP |
173 | #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f |
174 | #define GPMC_CONFIG7_CSVALID_MASK BIT(6) | |
175 | #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8 | |
176 | #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET) | |
177 | /* All CONFIG7 bits except reserved bits */ | |
178 | #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \ | |
179 | GPMC_CONFIG7_CSVALID_MASK | \ | |
180 | GPMC_CONFIG7_MASKADDRESS_MASK) | |
181 | ||
e639cd5b TL |
182 | #define GPMC_DEVICETYPE_NOR 0 |
183 | #define GPMC_DEVICETYPE_NAND 2 | |
184 | #define GPMC_CONFIG_WRITEPROTECT 0x00000010 | |
185 | #define WR_RD_PIN_MONITORING 0x00600000 | |
186 | ||
e639cd5b TL |
187 | /* ECC commands */ |
188 | #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ | |
189 | #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ | |
190 | #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ | |
191 | ||
6b6c32fc AM |
192 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
193 | */ | |
194 | #define GPMC_NR_IRQ 2 | |
195 | ||
7f2e8c58 RA |
196 | enum gpmc_clk_domain { |
197 | GPMC_CD_FCLK, | |
198 | GPMC_CD_CLK | |
199 | }; | |
200 | ||
9ed7a776 TL |
201 | struct gpmc_cs_data { |
202 | const char *name; | |
203 | ||
204 | #define GPMC_CS_RESERVED (1 << 0) | |
205 | u32 flags; | |
206 | ||
207 | struct resource mem; | |
208 | }; | |
209 | ||
a2d3e7ba RN |
210 | /* Structure to save gpmc cs context */ |
211 | struct gpmc_cs_config { | |
212 | u32 config1; | |
213 | u32 config2; | |
214 | u32 config3; | |
215 | u32 config4; | |
216 | u32 config5; | |
217 | u32 config6; | |
218 | u32 config7; | |
219 | int is_valid; | |
220 | }; | |
221 | ||
222 | /* | |
223 | * Structure to save/restore gpmc context | |
224 | * to support core off on OMAP3 | |
225 | */ | |
226 | struct omap3_gpmc_regs { | |
227 | u32 sysconfig; | |
228 | u32 irqenable; | |
229 | u32 timeout_ctrl; | |
230 | u32 config; | |
231 | u32 prefetch_config1; | |
232 | u32 prefetch_config2; | |
233 | u32 prefetch_control; | |
234 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
235 | }; | |
236 | ||
384258f2 RQ |
237 | struct gpmc_device { |
238 | struct device *dev; | |
239 | int irq; | |
240 | struct irq_chip irq_chip; | |
d2d00862 | 241 | struct gpio_chip gpio_chip; |
384258f2 RQ |
242 | }; |
243 | ||
244 | static struct irq_domain *gpmc_irq_domain; | |
6b6c32fc | 245 | |
f37e4580 | 246 | static struct resource gpmc_mem_root; |
9ed7a776 | 247 | static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM]; |
87b247c4 | 248 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
6797b4fe | 249 | /* Define chip-selects as reserved by default until probe completes */ |
f34f3716 | 250 | static unsigned int gpmc_cs_num = GPMC_CS_NUM; |
9f833156 | 251 | static unsigned int gpmc_nr_waitpins; |
da496873 AM |
252 | static resource_size_t phys_base, mem_size; |
253 | static unsigned gpmc_capability; | |
fd1dc87d | 254 | static void __iomem *gpmc_base; |
4bbbc1ad | 255 | |
fd1dc87d | 256 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 257 | |
db97eb7d SG |
258 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
259 | ||
4bbbc1ad JY |
260 | static void gpmc_write_reg(int idx, u32 val) |
261 | { | |
edfaf05c | 262 | writel_relaxed(val, gpmc_base + idx); |
4bbbc1ad JY |
263 | } |
264 | ||
265 | static u32 gpmc_read_reg(int idx) | |
266 | { | |
edfaf05c | 267 | return readl_relaxed(gpmc_base + idx); |
4bbbc1ad JY |
268 | } |
269 | ||
270 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
271 | { | |
272 | void __iomem *reg_addr; | |
273 | ||
948d38e7 | 274 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
edfaf05c | 275 | writel_relaxed(val, reg_addr); |
4bbbc1ad JY |
276 | } |
277 | ||
3fc089e7 | 278 | static u32 gpmc_cs_read_reg(int cs, int idx) |
4bbbc1ad | 279 | { |
fd1dc87d PW |
280 | void __iomem *reg_addr; |
281 | ||
948d38e7 | 282 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
edfaf05c | 283 | return readl_relaxed(reg_addr); |
4bbbc1ad JY |
284 | } |
285 | ||
fd1dc87d | 286 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
3fc089e7 | 287 | static unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 288 | { |
fd1dc87d PW |
289 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
290 | ||
fd1dc87d PW |
291 | rate /= 1000; |
292 | rate = 1000000000 / rate; /* In picoseconds */ | |
293 | ||
294 | return rate; | |
4bbbc1ad JY |
295 | } |
296 | ||
7f2e8c58 RA |
297 | /** |
298 | * gpmc_get_clk_period - get period of selected clock domain in ps | |
299 | * @cs Chip Select Region. | |
300 | * @cd Clock Domain. | |
301 | * | |
302 | * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup | |
303 | * prior to calling this function with GPMC_CD_CLK. | |
304 | */ | |
305 | static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) | |
306 | { | |
307 | ||
308 | unsigned long tick_ps = gpmc_get_fclk_period(); | |
309 | u32 l; | |
310 | int div; | |
311 | ||
312 | switch (cd) { | |
313 | case GPMC_CD_CLK: | |
314 | /* get current clk divider */ | |
315 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
316 | div = (l & 0x03) + 1; | |
317 | /* get GPMC_CLK period */ | |
318 | tick_ps *= div; | |
319 | break; | |
320 | case GPMC_CD_FCLK: | |
321 | /* FALL-THROUGH */ | |
322 | default: | |
323 | break; | |
324 | } | |
325 | ||
326 | return tick_ps; | |
327 | ||
328 | } | |
329 | ||
330 | static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, | |
331 | enum gpmc_clk_domain cd) | |
4bbbc1ad JY |
332 | { |
333 | unsigned long tick_ps; | |
334 | ||
335 | /* Calculate in picosecs to yield more exact results */ | |
7f2e8c58 | 336 | tick_ps = gpmc_get_clk_period(cs, cd); |
4bbbc1ad JY |
337 | |
338 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
339 | } | |
340 | ||
7f2e8c58 RA |
341 | static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) |
342 | { | |
343 | return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); | |
344 | } | |
345 | ||
3fc089e7 | 346 | static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
a3551f5b AH |
347 | { |
348 | unsigned long tick_ps; | |
349 | ||
350 | /* Calculate in picosecs to yield more exact results */ | |
351 | tick_ps = gpmc_get_fclk_period(); | |
352 | ||
353 | return (time_ps + tick_ps - 1) / tick_ps; | |
354 | } | |
355 | ||
7f2e8c58 RA |
356 | unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs, |
357 | enum gpmc_clk_domain cd) | |
358 | { | |
359 | return ticks * gpmc_get_clk_period(cs, cd) / 1000; | |
360 | } | |
361 | ||
fd1dc87d PW |
362 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
363 | { | |
7f2e8c58 | 364 | return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK); |
fd1dc87d PW |
365 | } |
366 | ||
246da26d AM |
367 | static unsigned int gpmc_ticks_to_ps(unsigned int ticks) |
368 | { | |
369 | return ticks * gpmc_get_fclk_period(); | |
370 | } | |
371 | ||
372 | static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) | |
373 | { | |
374 | unsigned long ticks = gpmc_ps_to_ticks(time_ps); | |
375 | ||
376 | return ticks * gpmc_get_fclk_period(); | |
377 | } | |
378 | ||
559d94b0 AM |
379 | static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) |
380 | { | |
381 | u32 l; | |
382 | ||
383 | l = gpmc_cs_read_reg(cs, reg); | |
384 | if (value) | |
385 | l |= mask; | |
386 | else | |
387 | l &= ~mask; | |
388 | gpmc_cs_write_reg(cs, reg, l); | |
389 | } | |
390 | ||
391 | static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) | |
392 | { | |
393 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, | |
394 | GPMC_CONFIG1_TIME_PARA_GRAN, | |
395 | p->time_para_granularity); | |
396 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, | |
397 | GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); | |
398 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, | |
399 | GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); | |
400 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
401 | GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); | |
402 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
403 | GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay); | |
404 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
405 | GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, | |
406 | p->cycle2cyclesamecsen); | |
407 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
408 | GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, | |
409 | p->cycle2cyclediffcsen); | |
410 | } | |
411 | ||
63aa945b | 412 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
563dbb26 RA |
413 | /** |
414 | * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it. | |
415 | * @cs: Chip Select Region | |
416 | * @reg: GPMC_CS_CONFIGn register offset. | |
417 | * @st_bit: Start Bit | |
418 | * @end_bit: End Bit. Must be >= @st_bit. | |
4b613e9b RA |
419 | * @ma:x Maximum parameter value (before optional @shift). |
420 | * If 0, maximum is as high as @st_bit and @end_bit allow. | |
563dbb26 | 421 | * @name: DTS node name, w/o "gpmc," |
7f2e8c58 RA |
422 | * @cd: Clock Domain of timing parameter. |
423 | * @shift: Parameter value left shifts @shift, which is then printed instead of value. | |
563dbb26 RA |
424 | * @raw: Raw Format Option. |
425 | * raw format: gpmc,name = <value> | |
426 | * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/ | |
427 | * Where x ns -- y ns result in the same tick value. | |
4b613e9b | 428 | * When @max is exceeded, "invalid" is printed inside comment. |
563dbb26 | 429 | * @noval: Parameter values equal to 0 are not printed. |
563dbb26 RA |
430 | * @return: Specified timing parameter (after optional @shift). |
431 | * | |
432 | */ | |
7f2e8c58 RA |
433 | static int get_gpmc_timing_reg( |
434 | /* timing specifiers */ | |
4b613e9b | 435 | int cs, int reg, int st_bit, int end_bit, int max, |
7f2e8c58 RA |
436 | const char *name, const enum gpmc_clk_domain cd, |
437 | /* value transform */ | |
438 | int shift, | |
439 | /* format specifiers */ | |
440 | bool raw, bool noval) | |
35ac051e TL |
441 | { |
442 | u32 l; | |
563dbb26 RA |
443 | int nr_bits; |
444 | int mask; | |
4b613e9b | 445 | bool invalid; |
35ac051e TL |
446 | |
447 | l = gpmc_cs_read_reg(cs, reg); | |
448 | nr_bits = end_bit - st_bit + 1; | |
563dbb26 RA |
449 | mask = (1 << nr_bits) - 1; |
450 | l = (l >> st_bit) & mask; | |
4b613e9b RA |
451 | if (!max) |
452 | max = mask; | |
453 | invalid = l > max; | |
35ac051e TL |
454 | if (shift) |
455 | l = (shift << l); | |
456 | if (noval && (l == 0)) | |
457 | return 0; | |
458 | if (!raw) { | |
563dbb26 RA |
459 | /* DTS tick format for timings in ns */ |
460 | unsigned int time_ns; | |
461 | unsigned int time_ns_min = 0; | |
35ac051e | 462 | |
563dbb26 | 463 | if (l) |
7f2e8c58 RA |
464 | time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; |
465 | time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); | |
4b613e9b RA |
466 | pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n", |
467 | name, time_ns, time_ns_min, time_ns, l, | |
468 | invalid ? "; invalid " : " "); | |
35ac051e | 469 | } else { |
563dbb26 | 470 | /* raw format */ |
4b613e9b RA |
471 | pr_info("gpmc,%s = <%u>%s\n", name, l, |
472 | invalid ? " /* invalid */" : ""); | |
35ac051e TL |
473 | } |
474 | ||
475 | return l; | |
476 | } | |
477 | ||
478 | #define GPMC_PRINT_CONFIG(cs, config) \ | |
479 | pr_info("cs%i %s: 0x%08x\n", cs, #config, \ | |
480 | gpmc_cs_read_reg(cs, config)) | |
481 | #define GPMC_GET_RAW(reg, st, end, field) \ | |
4b613e9b RA |
482 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) |
483 | #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \ | |
484 | get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0) | |
35ac051e | 485 | #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ |
4b613e9b RA |
486 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1) |
487 | #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \ | |
488 | get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1) | |
35ac051e | 489 | #define GPMC_GET_TICKS(reg, st, end, field) \ |
4b613e9b | 490 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0) |
7f2e8c58 | 491 | #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \ |
4b613e9b RA |
492 | get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0) |
493 | #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \ | |
494 | get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0) | |
35ac051e TL |
495 | |
496 | static void gpmc_show_regs(int cs, const char *desc) | |
497 | { | |
498 | pr_info("gpmc cs%i %s:\n", cs, desc); | |
499 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); | |
500 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); | |
501 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); | |
502 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); | |
503 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); | |
504 | GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); | |
505 | } | |
506 | ||
507 | /* | |
508 | * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available, | |
509 | * see commit c9fb809. | |
510 | */ | |
511 | static void gpmc_cs_show_timings(int cs, const char *desc) | |
512 | { | |
513 | gpmc_show_regs(cs, desc); | |
514 | ||
515 | pr_info("gpmc cs%i access configuration:\n", cs); | |
516 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); | |
517 | GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); | |
4b613e9b RA |
518 | GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13, |
519 | GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); | |
35ac051e TL |
520 | GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); |
521 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); | |
522 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); | |
4b613e9b RA |
523 | GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4, |
524 | GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX, | |
525 | "burst-length"); | |
35ac051e TL |
526 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); |
527 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); | |
528 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); | |
529 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); | |
530 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); | |
531 | ||
532 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); | |
533 | ||
534 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); | |
535 | ||
536 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); | |
537 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); | |
538 | ||
539 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); | |
540 | GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); | |
541 | ||
542 | pr_info("gpmc cs%i timings configuration:\n", cs); | |
543 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); | |
544 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); | |
545 | GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); | |
546 | ||
547 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); | |
548 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); | |
549 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); | |
2c92c04b NA |
550 | if (gpmc_capability & GPMC_HAS_MUX_AAD) { |
551 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns"); | |
552 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26, | |
553 | "adv-aad-mux-rd-off-ns"); | |
554 | GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30, | |
555 | "adv-aad-mux-wr-off-ns"); | |
556 | } | |
35ac051e TL |
557 | |
558 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); | |
559 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); | |
2c92c04b NA |
560 | if (gpmc_capability & GPMC_HAS_MUX_AAD) { |
561 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns"); | |
562 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns"); | |
563 | } | |
35ac051e TL |
564 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); |
565 | GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); | |
566 | ||
567 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); | |
568 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); | |
569 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); | |
570 | ||
571 | GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); | |
572 | ||
573 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); | |
574 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); | |
575 | ||
4b613e9b RA |
576 | GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19, |
577 | GPMC_CONFIG1_WAITMONITORINGTIME_MAX, | |
578 | "wait-monitoring-ns", GPMC_CD_CLK); | |
579 | GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26, | |
580 | GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, | |
581 | "clk-activation-ns", GPMC_CD_FCLK); | |
35ac051e TL |
582 | |
583 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); | |
584 | GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); | |
585 | } | |
4bbbc1ad | 586 | #else |
35ac051e TL |
587 | static inline void gpmc_cs_show_timings(int cs, const char *desc) |
588 | { | |
589 | } | |
4bbbc1ad | 590 | #endif |
35ac051e | 591 | |
7f2e8c58 RA |
592 | /** |
593 | * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region. | |
594 | * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER | |
595 | * prior to calling this function with @cd equal to GPMC_CD_CLK. | |
596 | * | |
597 | * @cs: Chip Select Region. | |
598 | * @reg: GPMC_CS_CONFIGn register offset. | |
599 | * @st_bit: Start Bit | |
600 | * @end_bit: End Bit. Must be >= @st_bit. | |
4b613e9b RA |
601 | * @max: Maximum parameter value. |
602 | * If 0, maximum is as high as @st_bit and @end_bit allow. | |
7f2e8c58 RA |
603 | * @time: Timing parameter in ns. |
604 | * @cd: Timing parameter clock domain. | |
605 | * @name: Timing parameter name. | |
606 | * @return: 0 on success, -1 on error. | |
607 | */ | |
4b613e9b | 608 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, |
7f2e8c58 | 609 | int time, enum gpmc_clk_domain cd, const char *name) |
4bbbc1ad JY |
610 | { |
611 | u32 l; | |
612 | int ticks, mask, nr_bits; | |
613 | ||
614 | if (time == 0) | |
615 | ticks = 0; | |
616 | else | |
7f2e8c58 | 617 | ticks = gpmc_ns_to_clk_ticks(time, cs, cd); |
4bbbc1ad | 618 | nr_bits = end_bit - st_bit + 1; |
80323742 RQ |
619 | mask = (1 << nr_bits) - 1; |
620 | ||
4b613e9b RA |
621 | if (!max) |
622 | max = mask; | |
623 | ||
624 | if (ticks > max) { | |
7f2e8c58 | 625 | pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", |
4b613e9b | 626 | __func__, cs, name, time, ticks, max); |
80323742 | 627 | |
4bbbc1ad | 628 | return -1; |
1c22cc13 | 629 | } |
4bbbc1ad | 630 | |
4bbbc1ad | 631 | l = gpmc_cs_read_reg(cs, reg); |
63aa945b | 632 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
f585070b | 633 | pr_info( |
2affc816 | 634 | "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", |
7f2e8c58 | 635 | cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, |
1c22cc13 | 636 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
637 | #endif |
638 | l &= ~(mask << st_bit); | |
639 | l |= ticks << st_bit; | |
640 | gpmc_cs_write_reg(cs, reg, l); | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
4b613e9b RA |
645 | #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \ |
646 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \ | |
647 | t->field, (cd), #field) < 0) \ | |
4bbbc1ad | 648 | return -1 |
4bbbc1ad | 649 | |
7f2e8c58 | 650 | #define GPMC_SET_ONE(reg, st, end, field) \ |
4b613e9b | 651 | GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK) |
7f2e8c58 | 652 | |
2e676901 RA |
653 | /** |
654 | * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME | |
655 | * WAITMONITORINGTIME will be _at least_ as long as desired, i.e. | |
656 | * read --> don't sample bus too early | |
657 | * write --> data is longer on bus | |
658 | * | |
659 | * Formula: | |
660 | * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns) | |
661 | * / waitmonitoring_ticks) | |
662 | * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by | |
663 | * div <= 0 check. | |
664 | * | |
665 | * @wait_monitoring: WAITMONITORINGTIME in ns. | |
666 | * @return: -1 on failure to scale, else proper divider > 0. | |
667 | */ | |
668 | static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) | |
669 | { | |
670 | ||
671 | int div = gpmc_ns_to_ticks(wait_monitoring); | |
672 | ||
673 | div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; | |
674 | div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX; | |
675 | ||
676 | if (div > 4) | |
677 | return -1; | |
678 | if (div <= 0) | |
679 | div = 1; | |
680 | ||
681 | return div; | |
682 | ||
683 | } | |
684 | ||
685 | /** | |
686 | * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period. | |
687 | * @sync_clk: GPMC_CLK period in ps. | |
688 | * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK. | |
689 | * Else, returns -1. | |
690 | */ | |
1b47ca1a | 691 | int gpmc_calc_divider(unsigned int sync_clk) |
4bbbc1ad | 692 | { |
2e676901 | 693 | int div = gpmc_ps_to_ticks(sync_clk); |
4bbbc1ad | 694 | |
4bbbc1ad JY |
695 | if (div > 4) |
696 | return -1; | |
1c22cc13 | 697 | if (div <= 0) |
4bbbc1ad JY |
698 | div = 1; |
699 | ||
700 | return div; | |
701 | } | |
702 | ||
2e676901 RA |
703 | /** |
704 | * gpmc_cs_set_timings - program timing parameters for Chip Select Region. | |
705 | * @cs: Chip Select Region. | |
706 | * @t: GPMC timing parameters. | |
707 | * @s: GPMC timing settings. | |
708 | * @return: 0 on success, -1 on error. | |
709 | */ | |
710 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, | |
711 | const struct gpmc_settings *s) | |
4bbbc1ad JY |
712 | { |
713 | int div; | |
714 | u32 l; | |
715 | ||
1b47ca1a | 716 | div = gpmc_calc_divider(t->sync_clk); |
4bbbc1ad | 717 | if (div < 0) |
a032d33b | 718 | return div; |
4bbbc1ad | 719 | |
2e676901 RA |
720 | /* |
721 | * See if we need to change the divider for waitmonitoringtime. | |
722 | * | |
723 | * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for | |
724 | * pure asynchronous accesses, i.e. both read and write asynchronous. | |
725 | * However, only do so if WAITMONITORINGTIME is actually used, i.e. | |
726 | * either WAITREADMONITORING or WAITWRITEMONITORING is set. | |
727 | * | |
728 | * This statement must not change div to scale async WAITMONITORINGTIME | |
729 | * to protect mixed synchronous and asynchronous accesses. | |
730 | * | |
731 | * We raise an error later if WAITMONITORINGTIME does not fit. | |
732 | */ | |
733 | if (!s->sync_read && !s->sync_write && | |
734 | (s->wait_on_read || s->wait_on_write) | |
735 | ) { | |
736 | ||
737 | div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); | |
738 | if (div < 0) { | |
739 | pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n", | |
740 | __func__, | |
741 | t->wait_monitoring | |
742 | ); | |
743 | return -1; | |
744 | } | |
745 | } | |
746 | ||
4bbbc1ad JY |
747 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); |
748 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
749 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
750 | ||
751 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
752 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
753 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
2c92c04b NA |
754 | if (gpmc_capability & GPMC_HAS_MUX_AAD) { |
755 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on); | |
756 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off); | |
757 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off); | |
758 | } | |
4bbbc1ad JY |
759 | |
760 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
761 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
2c92c04b NA |
762 | if (gpmc_capability & GPMC_HAS_MUX_AAD) { |
763 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on); | |
764 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off); | |
765 | } | |
4bbbc1ad JY |
766 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); |
767 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
768 | ||
769 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
770 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
771 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
772 | ||
773 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
774 | ||
559d94b0 AM |
775 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); |
776 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); | |
777 | ||
da496873 | 778 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) |
cc26b3b0 | 779 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); |
da496873 | 780 | if (gpmc_capability & GPMC_HAS_WR_ACCESS) |
cc26b3b0 | 781 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); |
cc26b3b0 | 782 | |
1c22cc13 | 783 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); |
7f2e8c58 RA |
784 | l &= ~0x03; |
785 | l |= (div - 1); | |
786 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
787 | ||
4b613e9b RA |
788 | GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19, |
789 | GPMC_CONFIG1_WAITMONITORINGTIME_MAX, | |
790 | wait_monitoring, GPMC_CD_CLK); | |
791 | GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26, | |
792 | GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, | |
793 | clk_activation, GPMC_CD_FCLK); | |
7f2e8c58 | 794 | |
63aa945b | 795 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
f585070b RA |
796 | pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", |
797 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 798 | #endif |
4bbbc1ad | 799 | |
559d94b0 | 800 | gpmc_cs_bool_timings(cs, &t->bool_timings); |
35ac051e | 801 | gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); |
559d94b0 | 802 | |
4bbbc1ad JY |
803 | return 0; |
804 | } | |
805 | ||
4cf27d2e | 806 | static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) |
f37e4580 ID |
807 | { |
808 | u32 l; | |
809 | u32 mask; | |
810 | ||
c71f8e9b JH |
811 | /* |
812 | * Ensure that base address is aligned on a | |
813 | * boundary equal to or greater than size. | |
814 | */ | |
815 | if (base & (size - 1)) | |
816 | return -EINVAL; | |
817 | ||
9c4f757e | 818 | base >>= GPMC_CHUNK_SHIFT; |
f37e4580 | 819 | mask = (1 << GPMC_SECTION_SHIFT) - size; |
9c4f757e SP |
820 | mask >>= GPMC_CHUNK_SHIFT; |
821 | mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET; | |
822 | ||
f37e4580 | 823 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); |
9c4f757e SP |
824 | l &= ~GPMC_CONFIG7_MASK; |
825 | l |= base & GPMC_CONFIG7_BASEADDRESS_MASK; | |
826 | l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK; | |
a2d3e7ba | 827 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 | 828 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
c71f8e9b JH |
829 | |
830 | return 0; | |
f37e4580 ID |
831 | } |
832 | ||
4cf27d2e RQ |
833 | static void gpmc_cs_enable_mem(int cs) |
834 | { | |
835 | u32 l; | |
836 | ||
837 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
838 | l |= GPMC_CONFIG7_CSVALID; | |
839 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); | |
840 | } | |
841 | ||
f37e4580 ID |
842 | static void gpmc_cs_disable_mem(int cs) |
843 | { | |
844 | u32 l; | |
845 | ||
846 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 847 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
848 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
849 | } | |
850 | ||
851 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
852 | { | |
853 | u32 l; | |
854 | u32 mask; | |
855 | ||
856 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
857 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
858 | mask = (l >> 8) & 0x0f; | |
859 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
860 | } | |
861 | ||
862 | static int gpmc_cs_mem_enabled(int cs) | |
863 | { | |
864 | u32 l; | |
865 | ||
866 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 867 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
868 | } |
869 | ||
f5d8edaf | 870 | static void gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 871 | { |
9ed7a776 TL |
872 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
873 | ||
874 | gpmc->flags |= GPMC_CS_RESERVED; | |
f37e4580 ID |
875 | } |
876 | ||
ae9d908a | 877 | static bool gpmc_cs_reserved(int cs) |
f37e4580 | 878 | { |
9ed7a776 TL |
879 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
880 | ||
881 | return gpmc->flags & GPMC_CS_RESERVED; | |
882 | } | |
883 | ||
884 | static void gpmc_cs_set_name(int cs, const char *name) | |
885 | { | |
886 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; | |
887 | ||
888 | gpmc->name = name; | |
889 | } | |
890 | ||
2e25b0ec | 891 | static const char *gpmc_cs_get_name(int cs) |
9ed7a776 TL |
892 | { |
893 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; | |
894 | ||
895 | return gpmc->name; | |
f37e4580 ID |
896 | } |
897 | ||
898 | static unsigned long gpmc_mem_align(unsigned long size) | |
899 | { | |
900 | int order; | |
901 | ||
902 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
903 | order = GPMC_CHUNK_SHIFT - 1; | |
904 | do { | |
905 | size >>= 1; | |
906 | order++; | |
907 | } while (size); | |
908 | size = 1 << order; | |
909 | return size; | |
910 | } | |
911 | ||
912 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
913 | { | |
9ed7a776 TL |
914 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
915 | struct resource *res = &gpmc->mem; | |
f37e4580 ID |
916 | int r; |
917 | ||
918 | size = gpmc_mem_align(size); | |
919 | spin_lock(&gpmc_mem_lock); | |
920 | res->start = base; | |
921 | res->end = base + size - 1; | |
922 | r = request_resource(&gpmc_mem_root, res); | |
923 | spin_unlock(&gpmc_mem_lock); | |
924 | ||
925 | return r; | |
926 | } | |
927 | ||
da496873 AM |
928 | static int gpmc_cs_delete_mem(int cs) |
929 | { | |
9ed7a776 TL |
930 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
931 | struct resource *res = &gpmc->mem; | |
da496873 AM |
932 | int r; |
933 | ||
934 | spin_lock(&gpmc_mem_lock); | |
efe80723 | 935 | r = release_resource(res); |
da496873 AM |
936 | res->start = 0; |
937 | res->end = 0; | |
938 | spin_unlock(&gpmc_mem_lock); | |
939 | ||
940 | return r; | |
941 | } | |
942 | ||
cdd6928c JH |
943 | /** |
944 | * gpmc_cs_remap - remaps a chip-select physical base address | |
945 | * @cs: chip-select to remap | |
946 | * @base: physical base address to re-map chip-select to | |
947 | * | |
948 | * Re-maps a chip-select to a new physical base address specified by | |
949 | * "base". Returns 0 on success and appropriate negative error code | |
950 | * on failure. | |
951 | */ | |
952 | static int gpmc_cs_remap(int cs, u32 base) | |
953 | { | |
954 | int ret; | |
955 | u32 old_base, size; | |
956 | ||
f34f3716 GP |
957 | if (cs > gpmc_cs_num) { |
958 | pr_err("%s: requested chip-select is disabled\n", __func__); | |
cdd6928c | 959 | return -ENODEV; |
f34f3716 | 960 | } |
fb677ef7 TL |
961 | |
962 | /* | |
963 | * Make sure we ignore any device offsets from the GPMC partition | |
964 | * allocated for the chip select and that the new base confirms | |
965 | * to the GPMC 16MB minimum granularity. | |
966 | */ | |
967 | base &= ~(SZ_16M - 1); | |
968 | ||
cdd6928c JH |
969 | gpmc_cs_get_memconf(cs, &old_base, &size); |
970 | if (base == old_base) | |
971 | return 0; | |
4cf27d2e | 972 | |
cdd6928c JH |
973 | ret = gpmc_cs_delete_mem(cs); |
974 | if (ret < 0) | |
975 | return ret; | |
4cf27d2e | 976 | |
cdd6928c | 977 | ret = gpmc_cs_insert_mem(cs, base, size); |
c71f8e9b JH |
978 | if (ret < 0) |
979 | return ret; | |
cdd6928c | 980 | |
4cf27d2e RQ |
981 | ret = gpmc_cs_set_memconf(cs, base, size); |
982 | ||
983 | return ret; | |
cdd6928c JH |
984 | } |
985 | ||
f37e4580 ID |
986 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) |
987 | { | |
9ed7a776 TL |
988 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
989 | struct resource *res = &gpmc->mem; | |
f37e4580 ID |
990 | int r = -1; |
991 | ||
f34f3716 GP |
992 | if (cs > gpmc_cs_num) { |
993 | pr_err("%s: requested chip-select is disabled\n", __func__); | |
f37e4580 | 994 | return -ENODEV; |
f34f3716 | 995 | } |
f37e4580 ID |
996 | size = gpmc_mem_align(size); |
997 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
998 | return -ENOMEM; | |
999 | ||
1000 | spin_lock(&gpmc_mem_lock); | |
1001 | if (gpmc_cs_reserved(cs)) { | |
1002 | r = -EBUSY; | |
1003 | goto out; | |
1004 | } | |
1005 | if (gpmc_cs_mem_enabled(cs)) | |
1006 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
1007 | if (r < 0) | |
1008 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
1009 | size, NULL, NULL); | |
1010 | if (r < 0) | |
1011 | goto out; | |
1012 | ||
4cf27d2e RQ |
1013 | /* Disable CS while changing base address and size mask */ |
1014 | gpmc_cs_disable_mem(cs); | |
1015 | ||
1016 | r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); | |
c71f8e9b JH |
1017 | if (r < 0) { |
1018 | release_resource(res); | |
1019 | goto out; | |
1020 | } | |
1021 | ||
4cf27d2e RQ |
1022 | /* Enable CS */ |
1023 | gpmc_cs_enable_mem(cs); | |
f37e4580 ID |
1024 | *base = res->start; |
1025 | gpmc_cs_set_reserved(cs, 1); | |
1026 | out: | |
1027 | spin_unlock(&gpmc_mem_lock); | |
1028 | return r; | |
1029 | } | |
fd1dc87d | 1030 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
1031 | |
1032 | void gpmc_cs_free(int cs) | |
1033 | { | |
9ed7a776 TL |
1034 | struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; |
1035 | struct resource *res = &gpmc->mem; | |
efe80723 | 1036 | |
f37e4580 | 1037 | spin_lock(&gpmc_mem_lock); |
f34f3716 | 1038 | if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
1039 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
1040 | BUG(); | |
1041 | spin_unlock(&gpmc_mem_lock); | |
1042 | return; | |
1043 | } | |
1044 | gpmc_cs_disable_mem(cs); | |
efe80723 TL |
1045 | if (res->flags) |
1046 | release_resource(res); | |
f37e4580 ID |
1047 | gpmc_cs_set_reserved(cs, 0); |
1048 | spin_unlock(&gpmc_mem_lock); | |
1049 | } | |
fd1dc87d | 1050 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 1051 | |
948d38e7 | 1052 | /** |
3a544354 | 1053 | * gpmc_configure - write request to configure gpmc |
948d38e7 SG |
1054 | * @cmd: command type |
1055 | * @wval: value to write | |
1056 | * @return status of the operation | |
1057 | */ | |
3a544354 | 1058 | int gpmc_configure(int cmd, int wval) |
948d38e7 | 1059 | { |
3a544354 | 1060 | u32 regval; |
948d38e7 SG |
1061 | |
1062 | switch (cmd) { | |
948d38e7 SG |
1063 | case GPMC_CONFIG_WP: |
1064 | regval = gpmc_read_reg(GPMC_CONFIG); | |
1065 | if (wval) | |
1066 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
1067 | else | |
1068 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
1069 | gpmc_write_reg(GPMC_CONFIG, regval); | |
1070 | break; | |
1071 | ||
948d38e7 | 1072 | default: |
3a544354 JH |
1073 | pr_err("%s: command not supported\n", __func__); |
1074 | return -EINVAL; | |
948d38e7 SG |
1075 | } |
1076 | ||
3a544354 | 1077 | return 0; |
948d38e7 | 1078 | } |
3a544354 | 1079 | EXPORT_SYMBOL(gpmc_configure); |
948d38e7 | 1080 | |
52bd138d AM |
1081 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
1082 | { | |
2fdf0c98 AM |
1083 | int i; |
1084 | ||
52bd138d AM |
1085 | reg->gpmc_status = gpmc_base + GPMC_STATUS; |
1086 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + | |
1087 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | |
1088 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | |
1089 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | |
1090 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | |
1091 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | |
1092 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | |
1093 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | |
1094 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | |
1095 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | |
1096 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | |
1097 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | |
1098 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | |
1099 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | |
2fdf0c98 AM |
1100 | |
1101 | for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { | |
1102 | reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + | |
1103 | GPMC_BCH_SIZE * i; | |
1104 | reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + | |
1105 | GPMC_BCH_SIZE * i; | |
1106 | reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + | |
1107 | GPMC_BCH_SIZE * i; | |
1108 | reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + | |
1109 | GPMC_BCH_SIZE * i; | |
27c9fd60 | 1110 | reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + |
1111 | i * GPMC_BCH_SIZE; | |
1112 | reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + | |
1113 | i * GPMC_BCH_SIZE; | |
1114 | reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + | |
1115 | i * GPMC_BCH_SIZE; | |
2fdf0c98 | 1116 | } |
52bd138d AM |
1117 | } |
1118 | ||
512d73d1 RQ |
1119 | static bool gpmc_nand_writebuffer_empty(void) |
1120 | { | |
1121 | if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS) | |
1122 | return true; | |
1123 | ||
1124 | return false; | |
1125 | } | |
1126 | ||
1127 | static struct gpmc_nand_ops nand_ops = { | |
1128 | .nand_writebuffer_empty = gpmc_nand_writebuffer_empty, | |
1129 | }; | |
f47fcad6 RQ |
1130 | |
1131 | /** | |
1132 | * gpmc_omap_get_nand_ops - Get the GPMC NAND interface | |
1133 | * @regs: the GPMC NAND register map exclusive for NAND use. | |
1134 | * @cs: GPMC chip select number on which the NAND sits. The | |
1135 | * register map returned will be specific to this chip select. | |
1136 | * | |
1137 | * Returns NULL on error e.g. invalid cs. | |
1138 | */ | |
1139 | struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs) | |
1140 | { | |
1141 | if (cs >= gpmc_cs_num) | |
1142 | return NULL; | |
1143 | ||
1144 | gpmc_update_nand_reg(reg, cs); | |
1145 | ||
1146 | return &nand_ops; | |
1147 | } | |
1148 | EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops); | |
1149 | ||
6b6c32fc AM |
1150 | int gpmc_get_client_irq(unsigned irq_config) |
1151 | { | |
384258f2 RQ |
1152 | if (!gpmc_irq_domain) { |
1153 | pr_warn("%s called before GPMC IRQ domain available\n", | |
1154 | __func__); | |
6b6c32fc | 1155 | return 0; |
384258f2 | 1156 | } |
6b6c32fc | 1157 | |
384258f2 RQ |
1158 | if (irq_config >= GPMC_NR_IRQ) |
1159 | return 0; | |
6b6c32fc | 1160 | |
384258f2 | 1161 | return irq_create_mapping(gpmc_irq_domain, irq_config); |
6b6c32fc AM |
1162 | } |
1163 | ||
384258f2 | 1164 | static int gpmc_irq_endis(unsigned long hwirq, bool endis) |
6b6c32fc | 1165 | { |
6b6c32fc AM |
1166 | u32 regval; |
1167 | ||
384258f2 RQ |
1168 | regval = gpmc_read_reg(GPMC_IRQENABLE); |
1169 | if (endis) | |
1170 | regval |= BIT(hwirq); | |
1171 | else | |
1172 | regval &= ~BIT(hwirq); | |
1173 | gpmc_write_reg(GPMC_IRQENABLE, regval); | |
6b6c32fc AM |
1174 | |
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | static void gpmc_irq_disable(struct irq_data *p) | |
1179 | { | |
384258f2 | 1180 | gpmc_irq_endis(p->hwirq, false); |
6b6c32fc AM |
1181 | } |
1182 | ||
1183 | static void gpmc_irq_enable(struct irq_data *p) | |
1184 | { | |
384258f2 | 1185 | gpmc_irq_endis(p->hwirq, true); |
6b6c32fc AM |
1186 | } |
1187 | ||
1188 | static void gpmc_irq_noop(struct irq_data *data) { } | |
1189 | ||
1190 | static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } | |
1191 | ||
384258f2 RQ |
1192 | static int gpmc_irq_map(struct irq_domain *d, unsigned int virq, |
1193 | irq_hw_number_t hw) | |
6b6c32fc | 1194 | { |
384258f2 RQ |
1195 | struct gpmc_device *gpmc = d->host_data; |
1196 | ||
1197 | irq_set_chip_data(virq, gpmc); | |
1198 | irq_set_chip_and_handler(virq, &gpmc->irq_chip, handle_simple_irq); | |
1199 | irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN); | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static const struct irq_domain_ops gpmc_irq_domain_ops = { | |
1205 | .map = gpmc_irq_map, | |
1206 | .xlate = irq_domain_xlate_twocell, | |
1207 | }; | |
1208 | ||
1209 | static irqreturn_t gpmc_handle_irq(int irq, void *data) | |
1210 | { | |
1211 | int hwirq, virq; | |
6b6c32fc | 1212 | u32 regval; |
384258f2 | 1213 | struct gpmc_device *gpmc = data; |
6b6c32fc | 1214 | |
384258f2 | 1215 | regval = gpmc_read_reg(GPMC_IRQSTATUS); |
6b6c32fc | 1216 | |
384258f2 RQ |
1217 | if (!regval) |
1218 | return IRQ_NONE; | |
6b6c32fc | 1219 | |
384258f2 RQ |
1220 | for (hwirq = 0; hwirq < GPMC_NR_IRQ; hwirq++) { |
1221 | if (regval & BIT(hwirq)) { | |
1222 | virq = irq_find_mapping(gpmc_irq_domain, hwirq); | |
1223 | if (!virq) { | |
1224 | dev_warn(gpmc->dev, | |
1225 | "spurious irq detected hwirq %d, virq %d\n", | |
1226 | hwirq, virq); | |
1227 | } | |
1228 | ||
1229 | generic_handle_irq(virq); | |
1230 | } | |
6b6c32fc AM |
1231 | } |
1232 | ||
384258f2 RQ |
1233 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
1234 | ||
1235 | return IRQ_HANDLED; | |
1236 | } | |
1237 | ||
1238 | static int gpmc_setup_irq(struct gpmc_device *gpmc) | |
1239 | { | |
1240 | u32 regval; | |
1241 | int rc; | |
1242 | ||
6b6c32fc AM |
1243 | /* Disable interrupts */ |
1244 | gpmc_write_reg(GPMC_IRQENABLE, 0); | |
1245 | ||
1246 | /* clear interrupts */ | |
1247 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
1248 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | |
1249 | ||
384258f2 RQ |
1250 | gpmc->irq_chip.name = "gpmc"; |
1251 | gpmc->irq_chip.irq_startup = gpmc_irq_noop_ret; | |
1252 | gpmc->irq_chip.irq_enable = gpmc_irq_enable; | |
1253 | gpmc->irq_chip.irq_disable = gpmc_irq_disable; | |
1254 | gpmc->irq_chip.irq_shutdown = gpmc_irq_noop; | |
1255 | gpmc->irq_chip.irq_ack = gpmc_irq_noop; | |
1256 | gpmc->irq_chip.irq_mask = gpmc_irq_noop; | |
1257 | gpmc->irq_chip.irq_unmask = gpmc_irq_noop; | |
1258 | ||
1259 | gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node, | |
1260 | GPMC_NR_IRQ, | |
1261 | &gpmc_irq_domain_ops, | |
1262 | gpmc); | |
1263 | if (!gpmc_irq_domain) { | |
1264 | dev_err(gpmc->dev, "IRQ domain add failed\n"); | |
1265 | return -ENODEV; | |
1266 | } | |
1267 | ||
1268 | rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc); | |
1269 | if (rc) { | |
1270 | dev_err(gpmc->dev, "failed to request irq %d: %d\n", | |
1271 | gpmc->irq, rc); | |
1272 | irq_domain_remove(gpmc_irq_domain); | |
1273 | gpmc_irq_domain = NULL; | |
1274 | } | |
1275 | ||
1276 | return rc; | |
6b6c32fc AM |
1277 | } |
1278 | ||
384258f2 | 1279 | static int gpmc_free_irq(struct gpmc_device *gpmc) |
da496873 | 1280 | { |
384258f2 | 1281 | int hwirq; |
da496873 | 1282 | |
384258f2 | 1283 | free_irq(gpmc->irq, gpmc); |
da496873 | 1284 | |
384258f2 RQ |
1285 | for (hwirq = 0; hwirq < GPMC_NR_IRQ; hwirq++) |
1286 | irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq)); | |
da496873 | 1287 | |
384258f2 RQ |
1288 | irq_domain_remove(gpmc_irq_domain); |
1289 | gpmc_irq_domain = NULL; | |
da496873 AM |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
351a102d | 1294 | static void gpmc_mem_exit(void) |
da496873 AM |
1295 | { |
1296 | int cs; | |
1297 | ||
f34f3716 | 1298 | for (cs = 0; cs < gpmc_cs_num; cs++) { |
da496873 AM |
1299 | if (!gpmc_cs_mem_enabled(cs)) |
1300 | continue; | |
1301 | gpmc_cs_delete_mem(cs); | |
1302 | } | |
1303 | ||
1304 | } | |
1305 | ||
84b00f0e | 1306 | static void gpmc_mem_init(void) |
f37e4580 | 1307 | { |
84b00f0e | 1308 | int cs; |
f37e4580 | 1309 | |
bdd7e033 | 1310 | gpmc_mem_root.start = GPMC_MEM_START; |
f37e4580 ID |
1311 | gpmc_mem_root.end = GPMC_MEM_END; |
1312 | ||
1313 | /* Reserve all regions that has been set up by bootloader */ | |
f34f3716 | 1314 | for (cs = 0; cs < gpmc_cs_num; cs++) { |
f37e4580 ID |
1315 | u32 base, size; |
1316 | ||
1317 | if (!gpmc_cs_mem_enabled(cs)) | |
1318 | continue; | |
1319 | gpmc_cs_get_memconf(cs, &base, &size); | |
84b00f0e JH |
1320 | if (gpmc_cs_insert_mem(cs, base, size)) { |
1321 | pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", | |
1322 | __func__, cs, base, base + size); | |
1323 | gpmc_cs_disable_mem(cs); | |
8119024e | 1324 | } |
f37e4580 | 1325 | } |
4bbbc1ad JY |
1326 | } |
1327 | ||
246da26d AM |
1328 | static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) |
1329 | { | |
1330 | u32 temp; | |
1331 | int div; | |
1332 | ||
1333 | div = gpmc_calc_divider(sync_clk); | |
1334 | temp = gpmc_ps_to_ticks(time_ps); | |
1335 | temp = (temp + div - 1) / div; | |
1336 | return gpmc_ticks_to_ps(temp * div); | |
1337 | } | |
1338 | ||
1339 | /* XXX: can the cycles be avoided ? */ | |
1340 | static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1341 | struct gpmc_device_timings *dev_t, |
1342 | bool mux) | |
246da26d | 1343 | { |
246da26d AM |
1344 | u32 temp; |
1345 | ||
1346 | /* adv_rd_off */ | |
1347 | temp = dev_t->t_avdp_r; | |
1348 | /* XXX: mux check required ? */ | |
1349 | if (mux) { | |
1350 | /* XXX: t_avdp not to be required for sync, only added for tusb | |
1351 | * this indirectly necessitates requirement of t_avdp_r and | |
1352 | * t_avdp_w instead of having a single t_avdp | |
1353 | */ | |
1354 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); | |
1355 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1356 | } | |
1357 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
1358 | ||
1359 | /* oe_on */ | |
1360 | temp = dev_t->t_oeasu; /* XXX: remove this ? */ | |
1361 | if (mux) { | |
1362 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); | |
1363 | temp = max_t(u32, temp, gpmc_t->adv_rd_off + | |
1364 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); | |
1365 | } | |
1366 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
1367 | ||
1368 | /* access */ | |
1369 | /* XXX: any scope for improvement ?, by combining oe_on | |
1370 | * and clk_activation, need to check whether | |
1371 | * access = clk_activation + round to sync clk ? | |
1372 | */ | |
1373 | temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); | |
1374 | temp += gpmc_t->clk_activation; | |
1375 | if (dev_t->cyc_oe) | |
1376 | temp = max_t(u32, temp, gpmc_t->oe_on + | |
1377 | gpmc_ticks_to_ps(dev_t->cyc_oe)); | |
1378 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
1379 | ||
1380 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
1381 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
1382 | ||
1383 | /* rd_cycle */ | |
1384 | temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); | |
1385 | temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + | |
1386 | gpmc_t->access; | |
1387 | /* XXX: barter t_ce_rdyz with t_cez_r ? */ | |
1388 | if (dev_t->t_ce_rdyz) | |
1389 | temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); | |
1390 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1396 | struct gpmc_device_timings *dev_t, |
1397 | bool mux) | |
246da26d | 1398 | { |
246da26d AM |
1399 | u32 temp; |
1400 | ||
1401 | /* adv_wr_off */ | |
1402 | temp = dev_t->t_avdp_w; | |
1403 | if (mux) { | |
1404 | temp = max_t(u32, temp, | |
1405 | gpmc_t->clk_activation + dev_t->t_avdh); | |
1406 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1407 | } | |
1408 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
1409 | ||
1410 | /* wr_data_mux_bus */ | |
1411 | temp = max_t(u32, dev_t->t_weasu, | |
1412 | gpmc_t->clk_activation + dev_t->t_rdyo); | |
1413 | /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, | |
1414 | * and in that case remember to handle we_on properly | |
1415 | */ | |
1416 | if (mux) { | |
1417 | temp = max_t(u32, temp, | |
1418 | gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1419 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1420 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1421 | } | |
1422 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1423 | ||
1424 | /* we_on */ | |
1425 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1426 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1427 | else | |
1428 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1429 | ||
1430 | /* wr_access */ | |
1431 | /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ | |
1432 | gpmc_t->wr_access = gpmc_t->access; | |
1433 | ||
1434 | /* we_off */ | |
1435 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1436 | temp = max_t(u32, temp, | |
1437 | gpmc_t->wr_access + gpmc_ticks_to_ps(1)); | |
1438 | temp = max_t(u32, temp, | |
1439 | gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); | |
1440 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1441 | ||
1442 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1443 | dev_t->t_wph); | |
1444 | ||
1445 | /* wr_cycle */ | |
1446 | temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); | |
1447 | temp += gpmc_t->wr_access; | |
1448 | /* XXX: barter t_ce_rdyz with t_cez_w ? */ | |
1449 | if (dev_t->t_ce_rdyz) | |
1450 | temp = max_t(u32, temp, | |
1451 | gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); | |
1452 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1453 | ||
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1458 | struct gpmc_device_timings *dev_t, |
1459 | bool mux) | |
246da26d | 1460 | { |
246da26d AM |
1461 | u32 temp; |
1462 | ||
1463 | /* adv_rd_off */ | |
1464 | temp = dev_t->t_avdp_r; | |
1465 | if (mux) | |
1466 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1467 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
1468 | ||
1469 | /* oe_on */ | |
1470 | temp = dev_t->t_oeasu; | |
1471 | if (mux) | |
1472 | temp = max_t(u32, temp, | |
1473 | gpmc_t->adv_rd_off + dev_t->t_aavdh); | |
1474 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
1475 | ||
1476 | /* access */ | |
1477 | temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ | |
1478 | gpmc_t->oe_on + dev_t->t_oe); | |
1479 | temp = max_t(u32, temp, | |
1480 | gpmc_t->cs_on + dev_t->t_ce); | |
1481 | temp = max_t(u32, temp, | |
1482 | gpmc_t->adv_on + dev_t->t_aa); | |
1483 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
1484 | ||
1485 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
1486 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
1487 | ||
1488 | /* rd_cycle */ | |
1489 | temp = max_t(u32, dev_t->t_rd_cycle, | |
1490 | gpmc_t->cs_rd_off + dev_t->t_cez_r); | |
1491 | temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); | |
1492 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
1493 | ||
1494 | return 0; | |
1495 | } | |
1496 | ||
1497 | static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1498 | struct gpmc_device_timings *dev_t, |
1499 | bool mux) | |
246da26d | 1500 | { |
246da26d AM |
1501 | u32 temp; |
1502 | ||
1503 | /* adv_wr_off */ | |
1504 | temp = dev_t->t_avdp_w; | |
1505 | if (mux) | |
1506 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
1507 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
1508 | ||
1509 | /* wr_data_mux_bus */ | |
1510 | temp = dev_t->t_weasu; | |
1511 | if (mux) { | |
1512 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1513 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1514 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1515 | } | |
1516 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1517 | ||
1518 | /* we_on */ | |
1519 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1520 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1521 | else | |
1522 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1523 | ||
1524 | /* we_off */ | |
1525 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1526 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1527 | ||
1528 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1529 | dev_t->t_wph); | |
1530 | ||
1531 | /* wr_cycle */ | |
1532 | temp = max_t(u32, dev_t->t_wr_cycle, | |
1533 | gpmc_t->cs_wr_off + dev_t->t_cez_w); | |
1534 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1535 | ||
1536 | return 0; | |
1537 | } | |
1538 | ||
1539 | static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, | |
1540 | struct gpmc_device_timings *dev_t) | |
1541 | { | |
1542 | u32 temp; | |
1543 | ||
1544 | gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * | |
1545 | gpmc_get_fclk_period(); | |
1546 | ||
1547 | gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( | |
1548 | dev_t->t_bacc, | |
1549 | gpmc_t->sync_clk); | |
1550 | ||
1551 | temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); | |
1552 | gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); | |
1553 | ||
1554 | if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) | |
1555 | return 0; | |
1556 | ||
1557 | if (dev_t->ce_xdelay) | |
1558 | gpmc_t->bool_timings.cs_extra_delay = true; | |
1559 | if (dev_t->avd_xdelay) | |
1560 | gpmc_t->bool_timings.adv_extra_delay = true; | |
1561 | if (dev_t->oe_xdelay) | |
1562 | gpmc_t->bool_timings.oe_extra_delay = true; | |
1563 | if (dev_t->we_xdelay) | |
1564 | gpmc_t->bool_timings.we_extra_delay = true; | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1570 | struct gpmc_device_timings *dev_t, |
1571 | bool sync) | |
246da26d AM |
1572 | { |
1573 | u32 temp; | |
1574 | ||
1575 | /* cs_on */ | |
1576 | gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); | |
1577 | ||
1578 | /* adv_on */ | |
1579 | temp = dev_t->t_avdasu; | |
1580 | if (dev_t->t_ce_avd) | |
1581 | temp = max_t(u32, temp, | |
1582 | gpmc_t->cs_on + dev_t->t_ce_avd); | |
1583 | gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); | |
1584 | ||
c3be5b45 | 1585 | if (sync) |
246da26d AM |
1586 | gpmc_calc_sync_common_timings(gpmc_t, dev_t); |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
1591 | /* TODO: remove this function once all peripherals are confirmed to | |
1592 | * work with generic timing. Simultaneously gpmc_cs_set_timings() | |
1593 | * has to be modified to handle timings in ps instead of ns | |
1594 | */ | |
1595 | static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) | |
1596 | { | |
1597 | t->cs_on /= 1000; | |
1598 | t->cs_rd_off /= 1000; | |
1599 | t->cs_wr_off /= 1000; | |
1600 | t->adv_on /= 1000; | |
1601 | t->adv_rd_off /= 1000; | |
1602 | t->adv_wr_off /= 1000; | |
1603 | t->we_on /= 1000; | |
1604 | t->we_off /= 1000; | |
1605 | t->oe_on /= 1000; | |
1606 | t->oe_off /= 1000; | |
1607 | t->page_burst_access /= 1000; | |
1608 | t->access /= 1000; | |
1609 | t->rd_cycle /= 1000; | |
1610 | t->wr_cycle /= 1000; | |
1611 | t->bus_turnaround /= 1000; | |
1612 | t->cycle2cycle_delay /= 1000; | |
1613 | t->wait_monitoring /= 1000; | |
1614 | t->clk_activation /= 1000; | |
1615 | t->wr_access /= 1000; | |
1616 | t->wr_data_mux_bus /= 1000; | |
1617 | } | |
1618 | ||
1619 | int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | |
c3be5b45 JH |
1620 | struct gpmc_settings *gpmc_s, |
1621 | struct gpmc_device_timings *dev_t) | |
246da26d | 1622 | { |
c3be5b45 JH |
1623 | bool mux = false, sync = false; |
1624 | ||
1625 | if (gpmc_s) { | |
1626 | mux = gpmc_s->mux_add_data ? true : false; | |
1627 | sync = (gpmc_s->sync_read || gpmc_s->sync_write); | |
1628 | } | |
1629 | ||
246da26d AM |
1630 | memset(gpmc_t, 0, sizeof(*gpmc_t)); |
1631 | ||
c3be5b45 | 1632 | gpmc_calc_common_timings(gpmc_t, dev_t, sync); |
246da26d | 1633 | |
c3be5b45 JH |
1634 | if (gpmc_s && gpmc_s->sync_read) |
1635 | gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); | |
246da26d | 1636 | else |
c3be5b45 | 1637 | gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); |
246da26d | 1638 | |
c3be5b45 JH |
1639 | if (gpmc_s && gpmc_s->sync_write) |
1640 | gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); | |
246da26d | 1641 | else |
c3be5b45 | 1642 | gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); |
246da26d AM |
1643 | |
1644 | /* TODO: remove, see function definition */ | |
1645 | gpmc_convert_ps_to_ns(gpmc_t); | |
1646 | ||
1647 | return 0; | |
1648 | } | |
1649 | ||
aa8d4767 JH |
1650 | /** |
1651 | * gpmc_cs_program_settings - programs non-timing related settings | |
1652 | * @cs: GPMC chip-select to program | |
1653 | * @p: pointer to GPMC settings structure | |
1654 | * | |
1655 | * Programs non-timing related settings for a GPMC chip-select, such as | |
1656 | * bus-width, burst configuration, etc. Function should be called once | |
1657 | * for each chip-select that is being used and must be called before | |
1658 | * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 | |
1659 | * register will be initialised to zero by this function. Returns 0 on | |
1660 | * success and appropriate negative error code on failure. | |
1661 | */ | |
1662 | int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) | |
1663 | { | |
1664 | u32 config1; | |
1665 | ||
1666 | if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { | |
1667 | pr_err("%s: invalid width %d!", __func__, p->device_width); | |
1668 | return -EINVAL; | |
1669 | } | |
1670 | ||
1671 | /* Address-data multiplexing not supported for NAND devices */ | |
1672 | if (p->device_nand && p->mux_add_data) { | |
1673 | pr_err("%s: invalid configuration!\n", __func__); | |
1674 | return -EINVAL; | |
1675 | } | |
1676 | ||
1677 | if ((p->mux_add_data > GPMC_MUX_AD) || | |
1678 | ((p->mux_add_data == GPMC_MUX_AAD) && | |
1679 | !(gpmc_capability & GPMC_HAS_MUX_AAD))) { | |
1680 | pr_err("%s: invalid multiplex configuration!\n", __func__); | |
1681 | return -EINVAL; | |
1682 | } | |
1683 | ||
1684 | /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ | |
1685 | if (p->burst_read || p->burst_write) { | |
1686 | switch (p->burst_len) { | |
1687 | case GPMC_BURST_4: | |
1688 | case GPMC_BURST_8: | |
1689 | case GPMC_BURST_16: | |
1690 | break; | |
1691 | default: | |
1692 | pr_err("%s: invalid page/burst-length (%d)\n", | |
1693 | __func__, p->burst_len); | |
1694 | return -EINVAL; | |
1695 | } | |
1696 | } | |
1697 | ||
2b54057c | 1698 | if (p->wait_pin > gpmc_nr_waitpins) { |
aa8d4767 JH |
1699 | pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); |
1700 | return -EINVAL; | |
1701 | } | |
1702 | ||
1703 | config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); | |
1704 | ||
1705 | if (p->sync_read) | |
1706 | config1 |= GPMC_CONFIG1_READTYPE_SYNC; | |
1707 | if (p->sync_write) | |
1708 | config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; | |
1709 | if (p->wait_on_read) | |
1710 | config1 |= GPMC_CONFIG1_WAIT_READ_MON; | |
1711 | if (p->wait_on_write) | |
1712 | config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; | |
1713 | if (p->wait_on_read || p->wait_on_write) | |
1714 | config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); | |
1715 | if (p->device_nand) | |
1716 | config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); | |
1717 | if (p->mux_add_data) | |
1718 | config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); | |
1719 | if (p->burst_read) | |
1720 | config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; | |
1721 | if (p->burst_write) | |
1722 | config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; | |
1723 | if (p->burst_read || p->burst_write) { | |
1724 | config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); | |
1725 | config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; | |
1726 | } | |
1727 | ||
1728 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); | |
1729 | ||
1730 | return 0; | |
1731 | } | |
1732 | ||
bc6b1e7b | 1733 | #ifdef CONFIG_OF |
31957609 | 1734 | static const struct of_device_id gpmc_dt_ids[] = { |
bc6b1e7b DM |
1735 | { .compatible = "ti,omap2420-gpmc" }, |
1736 | { .compatible = "ti,omap2430-gpmc" }, | |
1737 | { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ | |
1738 | { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ | |
1739 | { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ | |
1740 | { } | |
1741 | }; | |
1742 | MODULE_DEVICE_TABLE(of, gpmc_dt_ids); | |
1743 | ||
8c8a7771 JH |
1744 | /** |
1745 | * gpmc_read_settings_dt - read gpmc settings from device-tree | |
1746 | * @np: pointer to device-tree node for a gpmc child device | |
1747 | * @p: pointer to gpmc settings structure | |
1748 | * | |
1749 | * Reads the GPMC settings for a GPMC child device from device-tree and | |
1750 | * stores them in the GPMC settings structure passed. The GPMC settings | |
1751 | * structure is initialised to zero by this function and so any | |
1752 | * previously stored settings will be cleared. | |
1753 | */ | |
1754 | void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) | |
1755 | { | |
1756 | memset(p, 0, sizeof(struct gpmc_settings)); | |
1757 | ||
1758 | p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); | |
1759 | p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); | |
8c8a7771 JH |
1760 | of_property_read_u32(np, "gpmc,device-width", &p->device_width); |
1761 | of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); | |
1762 | ||
1763 | if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { | |
1764 | p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); | |
1765 | p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); | |
1766 | p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); | |
1767 | if (!p->burst_read && !p->burst_write) | |
1768 | pr_warn("%s: page/burst-length set but not used!\n", | |
1769 | __func__); | |
1770 | } | |
1771 | ||
1772 | if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { | |
1773 | p->wait_on_read = of_property_read_bool(np, | |
1774 | "gpmc,wait-on-read"); | |
1775 | p->wait_on_write = of_property_read_bool(np, | |
1776 | "gpmc,wait-on-write"); | |
1777 | if (!p->wait_on_read && !p->wait_on_write) | |
2b54057c RQ |
1778 | pr_debug("%s: rd/wr wait monitoring not enabled!\n", |
1779 | __func__); | |
8c8a7771 JH |
1780 | } |
1781 | } | |
1782 | ||
bc6b1e7b DM |
1783 | static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, |
1784 | struct gpmc_timings *gpmc_t) | |
1785 | { | |
d36b4cd4 JH |
1786 | struct gpmc_bool_timings *p; |
1787 | ||
1788 | if (!np || !gpmc_t) | |
1789 | return; | |
bc6b1e7b DM |
1790 | |
1791 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | |
1792 | ||
1793 | /* minimum clock period for syncronous mode */ | |
d36b4cd4 | 1794 | of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); |
bc6b1e7b DM |
1795 | |
1796 | /* chip select timtings */ | |
d36b4cd4 JH |
1797 | of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); |
1798 | of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); | |
1799 | of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); | |
bc6b1e7b DM |
1800 | |
1801 | /* ADV signal timings */ | |
d36b4cd4 JH |
1802 | of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); |
1803 | of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); | |
1804 | of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); | |
2c92c04b NA |
1805 | of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns", |
1806 | &gpmc_t->adv_aad_mux_on); | |
1807 | of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns", | |
1808 | &gpmc_t->adv_aad_mux_rd_off); | |
1809 | of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns", | |
1810 | &gpmc_t->adv_aad_mux_wr_off); | |
bc6b1e7b DM |
1811 | |
1812 | /* WE signal timings */ | |
d36b4cd4 JH |
1813 | of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); |
1814 | of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); | |
bc6b1e7b DM |
1815 | |
1816 | /* OE signal timings */ | |
d36b4cd4 JH |
1817 | of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); |
1818 | of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); | |
2c92c04b NA |
1819 | of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns", |
1820 | &gpmc_t->oe_aad_mux_on); | |
1821 | of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns", | |
1822 | &gpmc_t->oe_aad_mux_off); | |
bc6b1e7b DM |
1823 | |
1824 | /* access and cycle timings */ | |
d36b4cd4 JH |
1825 | of_property_read_u32(np, "gpmc,page-burst-access-ns", |
1826 | &gpmc_t->page_burst_access); | |
1827 | of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); | |
1828 | of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); | |
1829 | of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); | |
1830 | of_property_read_u32(np, "gpmc,bus-turnaround-ns", | |
1831 | &gpmc_t->bus_turnaround); | |
1832 | of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", | |
1833 | &gpmc_t->cycle2cycle_delay); | |
1834 | of_property_read_u32(np, "gpmc,wait-monitoring-ns", | |
1835 | &gpmc_t->wait_monitoring); | |
1836 | of_property_read_u32(np, "gpmc,clk-activation-ns", | |
1837 | &gpmc_t->clk_activation); | |
1838 | ||
1839 | /* only applicable to OMAP3+ */ | |
1840 | of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); | |
1841 | of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", | |
1842 | &gpmc_t->wr_data_mux_bus); | |
1843 | ||
1844 | /* bool timing parameters */ | |
1845 | p = &gpmc_t->bool_timings; | |
1846 | ||
1847 | p->cycle2cyclediffcsen = | |
1848 | of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); | |
1849 | p->cycle2cyclesamecsen = | |
1850 | of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); | |
1851 | p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); | |
1852 | p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); | |
1853 | p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); | |
1854 | p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); | |
1855 | p->time_para_granularity = | |
1856 | of_property_read_bool(np, "gpmc,time-para-granularity"); | |
bc6b1e7b DM |
1857 | } |
1858 | ||
980386d2 | 1859 | #if IS_ENABLED(CONFIG_MTD_ONENAND) |
75d3625e EG |
1860 | static int gpmc_probe_onenand_child(struct platform_device *pdev, |
1861 | struct device_node *child) | |
1862 | { | |
1863 | u32 val; | |
1864 | struct omap_onenand_platform_data *gpmc_onenand_data; | |
1865 | ||
1866 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1867 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1868 | child->full_name); | |
1869 | return -ENODEV; | |
1870 | } | |
1871 | ||
1872 | gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data), | |
1873 | GFP_KERNEL); | |
1874 | if (!gpmc_onenand_data) | |
1875 | return -ENOMEM; | |
1876 | ||
1877 | gpmc_onenand_data->cs = val; | |
1878 | gpmc_onenand_data->of_node = child; | |
1879 | gpmc_onenand_data->dma_channel = -1; | |
1880 | ||
1881 | if (!of_property_read_u32(child, "dma-channel", &val)) | |
1882 | gpmc_onenand_data->dma_channel = val; | |
1883 | ||
1884 | gpmc_onenand_init(gpmc_onenand_data); | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | #else | |
1889 | static int gpmc_probe_onenand_child(struct platform_device *pdev, | |
1890 | struct device_node *child) | |
1891 | { | |
1892 | return 0; | |
1893 | } | |
1894 | #endif | |
1895 | ||
cdd6928c | 1896 | /** |
3af91cf7 | 1897 | * gpmc_probe_generic_child - configures the gpmc for a child device |
cdd6928c | 1898 | * @pdev: pointer to gpmc platform device |
3af91cf7 | 1899 | * @child: pointer to device-tree node for child device |
cdd6928c | 1900 | * |
3af91cf7 | 1901 | * Allocates and configures a GPMC chip-select for a child device. |
cdd6928c JH |
1902 | * Returns 0 on success and appropriate negative error code on failure. |
1903 | */ | |
3af91cf7 | 1904 | static int gpmc_probe_generic_child(struct platform_device *pdev, |
cdd6928c JH |
1905 | struct device_node *child) |
1906 | { | |
1907 | struct gpmc_settings gpmc_s; | |
1908 | struct gpmc_timings gpmc_t; | |
1909 | struct resource res; | |
1910 | unsigned long base; | |
9ed7a776 | 1911 | const char *name; |
cdd6928c | 1912 | int ret, cs; |
e378d22b | 1913 | u32 val; |
210325f0 RQ |
1914 | struct gpio_desc *waitpin_desc = NULL; |
1915 | struct gpmc_device *gpmc = platform_get_drvdata(pdev); | |
cdd6928c JH |
1916 | |
1917 | if (of_property_read_u32(child, "reg", &cs) < 0) { | |
1918 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1919 | child->full_name); | |
1920 | return -ENODEV; | |
1921 | } | |
1922 | ||
1923 | if (of_address_to_resource(child, 0, &res) < 0) { | |
1924 | dev_err(&pdev->dev, "%s has malformed 'reg' property\n", | |
1925 | child->full_name); | |
1926 | return -ENODEV; | |
1927 | } | |
1928 | ||
9ed7a776 TL |
1929 | /* |
1930 | * Check if we have multiple instances of the same device | |
1931 | * on a single chip select. If so, use the already initialized | |
1932 | * timings. | |
1933 | */ | |
1934 | name = gpmc_cs_get_name(cs); | |
1935 | if (name && child->name && of_node_cmp(child->name, name) == 0) | |
1936 | goto no_timings; | |
1937 | ||
cdd6928c JH |
1938 | ret = gpmc_cs_request(cs, resource_size(&res), &base); |
1939 | if (ret < 0) { | |
1940 | dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); | |
1941 | return ret; | |
1942 | } | |
9ed7a776 | 1943 | gpmc_cs_set_name(cs, child->name); |
cdd6928c | 1944 | |
35ac051e TL |
1945 | gpmc_read_settings_dt(child, &gpmc_s); |
1946 | gpmc_read_timings_dt(child, &gpmc_t); | |
cdd6928c | 1947 | |
fd4446f2 TL |
1948 | /* |
1949 | * For some GPMC devices we still need to rely on the bootloader | |
35ac051e TL |
1950 | * timings because the devices can be connected via FPGA. |
1951 | * REVISIT: Add timing support from slls644g.pdf. | |
fd4446f2 | 1952 | */ |
35ac051e TL |
1953 | if (!gpmc_t.cs_rd_off) { |
1954 | WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", | |
1955 | cs); | |
1956 | gpmc_cs_show_timings(cs, | |
1957 | "please add GPMC bootloader timings to .dts"); | |
fd4446f2 TL |
1958 | goto no_timings; |
1959 | } | |
1960 | ||
4cf27d2e RQ |
1961 | /* CS must be disabled while making changes to gpmc configuration */ |
1962 | gpmc_cs_disable_mem(cs); | |
1963 | ||
cdd6928c JH |
1964 | /* |
1965 | * FIXME: gpmc_cs_request() will map the CS to an arbitary | |
1966 | * location in the gpmc address space. When booting with | |
1967 | * device-tree we want the NOR flash to be mapped to the | |
1968 | * location specified in the device-tree blob. So remap the | |
1969 | * CS to this location. Once DT migration is complete should | |
1970 | * just make gpmc_cs_request() map a specific address. | |
1971 | */ | |
1972 | ret = gpmc_cs_remap(cs, res.start); | |
1973 | if (ret < 0) { | |
f70bf2a3 FE |
1974 | dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", |
1975 | cs, &res.start); | |
bdd7e033 RQ |
1976 | if (res.start < GPMC_MEM_START) { |
1977 | dev_info(&pdev->dev, | |
1978 | "GPMC CS %d start cannot be lesser than 0x%x\n", | |
1979 | cs, GPMC_MEM_START); | |
1980 | } else if (res.end > GPMC_MEM_END) { | |
1981 | dev_info(&pdev->dev, | |
1982 | "GPMC CS %d end cannot be greater than 0x%x\n", | |
1983 | cs, GPMC_MEM_END); | |
1984 | } | |
cdd6928c JH |
1985 | goto err; |
1986 | } | |
1987 | ||
c9711ec5 RQ |
1988 | if (of_node_cmp(child->name, "nand") == 0) { |
1989 | /* Warn about older DT blobs with no compatible property */ | |
1990 | if (!of_property_read_bool(child, "compatible")) { | |
1991 | dev_warn(&pdev->dev, | |
1992 | "Incompatible NAND node: missing compatible"); | |
1993 | ret = -EINVAL; | |
1994 | goto err; | |
1995 | } | |
1996 | } | |
1997 | ||
1998 | if (of_device_is_compatible(child, "ti,omap2-nand")) { | |
1999 | /* NAND specific setup */ | |
2000 | val = of_get_nand_bus_width(child); | |
2001 | switch (val) { | |
2002 | case 8: | |
2003 | gpmc_s.device_width = GPMC_DEVWIDTH_8BIT; | |
2004 | break; | |
2005 | case 16: | |
2006 | gpmc_s.device_width = GPMC_DEVWIDTH_16BIT; | |
2007 | break; | |
2008 | default: | |
2009 | dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n", | |
2010 | child->name); | |
2011 | ret = -EINVAL; | |
2012 | goto err; | |
2013 | } | |
2014 | ||
2015 | /* disable write protect */ | |
2016 | gpmc_configure(GPMC_CONFIG_WP, 0); | |
2017 | gpmc_s.device_nand = true; | |
2018 | } else { | |
2019 | ret = of_property_read_u32(child, "bank-width", | |
2020 | &gpmc_s.device_width); | |
2021 | if (ret < 0) | |
2022 | goto err; | |
2023 | } | |
cdd6928c | 2024 | |
210325f0 RQ |
2025 | /* Reserve wait pin if it is required and valid */ |
2026 | if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) { | |
2027 | unsigned int wait_pin = gpmc_s.wait_pin; | |
2028 | ||
2029 | waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, | |
2030 | wait_pin, "WAITPIN"); | |
2031 | if (IS_ERR(waitpin_desc)) { | |
2032 | dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin); | |
2033 | ret = PTR_ERR(waitpin_desc); | |
2034 | goto err; | |
2035 | } | |
2036 | } | |
2037 | ||
fd820a1e | 2038 | gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); |
210325f0 | 2039 | |
cdd6928c JH |
2040 | ret = gpmc_cs_program_settings(cs, &gpmc_s); |
2041 | if (ret < 0) | |
210325f0 | 2042 | goto err_cs; |
cdd6928c | 2043 | |
2e676901 | 2044 | ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); |
7604baf3 RQ |
2045 | if (ret) { |
2046 | dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n", | |
2047 | child->name); | |
210325f0 | 2048 | goto err_cs; |
7604baf3 | 2049 | } |
cdd6928c | 2050 | |
e378d22b RQ |
2051 | /* Clear limited address i.e. enable A26-A11 */ |
2052 | val = gpmc_read_reg(GPMC_CONFIG); | |
2053 | val &= ~GPMC_CONFIG_LIMITEDADDRESS; | |
2054 | gpmc_write_reg(GPMC_CONFIG, val); | |
2055 | ||
4cf27d2e RQ |
2056 | /* Enable CS region */ |
2057 | gpmc_cs_enable_mem(cs); | |
cdd6928c | 2058 | |
fd4446f2 | 2059 | no_timings: |
b1dc1ca9 RA |
2060 | |
2061 | /* create platform device, NULL on error or when disabled */ | |
2062 | if (!of_platform_device_create(child, NULL, &pdev->dev)) | |
2063 | goto err_child_fail; | |
2064 | ||
2065 | /* is child a common bus? */ | |
2066 | if (of_match_node(of_default_bus_match_table, child)) | |
2067 | /* create children and other common bus children */ | |
2068 | if (of_platform_populate(child, of_default_bus_match_table, | |
2069 | NULL, &pdev->dev)) | |
2070 | goto err_child_fail; | |
2071 | ||
2072 | return 0; | |
2073 | ||
2074 | err_child_fail: | |
cdd6928c JH |
2075 | |
2076 | dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); | |
e8ffd6fd | 2077 | ret = -ENODEV; |
cdd6928c | 2078 | |
210325f0 RQ |
2079 | err_cs: |
2080 | if (waitpin_desc) | |
2081 | gpiochip_free_own_desc(waitpin_desc); | |
2082 | ||
cdd6928c JH |
2083 | err: |
2084 | gpmc_cs_free(cs); | |
2085 | ||
2086 | return ret; | |
2087 | } | |
2088 | ||
d2d00862 RQ |
2089 | static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
2090 | { | |
2091 | return 1; /* we're input only */ | |
2092 | } | |
2093 | ||
2094 | static int gpmc_gpio_direction_input(struct gpio_chip *chip, | |
2095 | unsigned int offset) | |
2096 | { | |
2097 | return 0; /* we're input only */ | |
2098 | } | |
2099 | ||
2100 | static int gpmc_gpio_direction_output(struct gpio_chip *chip, | |
2101 | unsigned int offset, int value) | |
2102 | { | |
2103 | return -EINVAL; /* we're input only */ | |
2104 | } | |
2105 | ||
2106 | static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
2107 | int value) | |
2108 | { | |
2109 | } | |
2110 | ||
2111 | static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
2112 | { | |
2113 | u32 reg; | |
2114 | ||
2115 | offset += 8; | |
2116 | ||
2117 | reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset); | |
2118 | ||
2119 | return !!reg; | |
2120 | } | |
2121 | ||
2122 | static int gpmc_gpio_init(struct gpmc_device *gpmc) | |
2123 | { | |
2124 | int ret; | |
2125 | ||
2126 | gpmc->gpio_chip.parent = gpmc->dev; | |
2127 | gpmc->gpio_chip.owner = THIS_MODULE; | |
2128 | gpmc->gpio_chip.label = DEVICE_NAME; | |
2129 | gpmc->gpio_chip.ngpio = gpmc_nr_waitpins; | |
2130 | gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction; | |
2131 | gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input; | |
2132 | gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output; | |
2133 | gpmc->gpio_chip.set = gpmc_gpio_set; | |
2134 | gpmc->gpio_chip.get = gpmc_gpio_get; | |
2135 | gpmc->gpio_chip.base = -1; | |
2136 | ||
2137 | ret = gpiochip_add(&gpmc->gpio_chip); | |
2138 | if (ret < 0) { | |
2139 | dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret); | |
2140 | return ret; | |
2141 | } | |
2142 | ||
2143 | return 0; | |
2144 | } | |
2145 | ||
2146 | static void gpmc_gpio_exit(struct gpmc_device *gpmc) | |
2147 | { | |
2148 | gpiochip_remove(&gpmc->gpio_chip); | |
2149 | } | |
2150 | ||
bc6b1e7b DM |
2151 | static int gpmc_probe_dt(struct platform_device *pdev) |
2152 | { | |
2153 | int ret; | |
bc6b1e7b DM |
2154 | const struct of_device_id *of_id = |
2155 | of_match_device(gpmc_dt_ids, &pdev->dev); | |
2156 | ||
2157 | if (!of_id) | |
2158 | return 0; | |
2159 | ||
f34f3716 GP |
2160 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", |
2161 | &gpmc_cs_num); | |
2162 | if (ret < 0) { | |
2163 | pr_err("%s: number of chip-selects not defined\n", __func__); | |
2164 | return ret; | |
2165 | } else if (gpmc_cs_num < 1) { | |
2166 | pr_err("%s: all chip-selects are disabled\n", __func__); | |
2167 | return -EINVAL; | |
2168 | } else if (gpmc_cs_num > GPMC_CS_NUM) { | |
2169 | pr_err("%s: number of supported chip-selects cannot be > %d\n", | |
2170 | __func__, GPMC_CS_NUM); | |
2171 | return -EINVAL; | |
2172 | } | |
2173 | ||
9f833156 JH |
2174 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", |
2175 | &gpmc_nr_waitpins); | |
2176 | if (ret < 0) { | |
2177 | pr_err("%s: number of wait pins not found!\n", __func__); | |
2178 | return ret; | |
2179 | } | |
2180 | ||
d2d00862 RQ |
2181 | return 0; |
2182 | } | |
2183 | ||
2184 | static int gpmc_probe_dt_children(struct platform_device *pdev) | |
2185 | { | |
2186 | int ret; | |
2187 | struct device_node *child; | |
2188 | ||
68e2eb53 | 2189 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
bc6b1e7b | 2190 | |
f2b09f67 JMC |
2191 | if (!child->name) |
2192 | continue; | |
cdd6928c | 2193 | |
c9711ec5 | 2194 | if (of_node_cmp(child->name, "onenand") == 0) |
f2b09f67 | 2195 | ret = gpmc_probe_onenand_child(pdev, child); |
28a7eedd | 2196 | else |
f2b09f67 | 2197 | ret = gpmc_probe_generic_child(pdev, child); |
d2d00862 RQ |
2198 | |
2199 | if (ret) | |
2200 | return ret; | |
5330dc16 JMC |
2201 | } |
2202 | ||
bc6b1e7b DM |
2203 | return 0; |
2204 | } | |
2205 | #else | |
2206 | static int gpmc_probe_dt(struct platform_device *pdev) | |
2207 | { | |
2208 | return 0; | |
2209 | } | |
d2d00862 RQ |
2210 | |
2211 | static int gpmc_probe_dt_children(struct platform_device *pdev) | |
2212 | { | |
2213 | return 0; | |
2214 | } | |
bc6b1e7b DM |
2215 | #endif |
2216 | ||
351a102d | 2217 | static int gpmc_probe(struct platform_device *pdev) |
4bbbc1ad | 2218 | { |
8119024e | 2219 | int rc; |
6b6c32fc | 2220 | u32 l; |
da496873 | 2221 | struct resource *res; |
384258f2 RQ |
2222 | struct gpmc_device *gpmc; |
2223 | ||
2224 | gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL); | |
2225 | if (!gpmc) | |
2226 | return -ENOMEM; | |
2227 | ||
2228 | gpmc->dev = &pdev->dev; | |
2229 | platform_set_drvdata(pdev, gpmc); | |
4bbbc1ad | 2230 | |
da496873 AM |
2231 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2232 | if (res == NULL) | |
2233 | return -ENOENT; | |
8d08436d | 2234 | |
da496873 AM |
2235 | phys_base = res->start; |
2236 | mem_size = resource_size(res); | |
fd1dc87d | 2237 | |
5857bd98 TR |
2238 | gpmc_base = devm_ioremap_resource(&pdev->dev, res); |
2239 | if (IS_ERR(gpmc_base)) | |
2240 | return PTR_ERR(gpmc_base); | |
da496873 AM |
2241 | |
2242 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
384258f2 RQ |
2243 | if (!res) { |
2244 | dev_err(&pdev->dev, "Failed to get resource: irq\n"); | |
2245 | return -ENOENT; | |
2246 | } | |
2247 | ||
2248 | gpmc->irq = res->start; | |
da496873 | 2249 | |
8bf9be56 | 2250 | gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); |
da496873 | 2251 | if (IS_ERR(gpmc_l3_clk)) { |
8bf9be56 | 2252 | dev_err(&pdev->dev, "Failed to get GPMC fck\n"); |
da496873 | 2253 | return PTR_ERR(gpmc_l3_clk); |
fd1dc87d PW |
2254 | } |
2255 | ||
8bf9be56 RQ |
2256 | if (!clk_get_rate(gpmc_l3_clk)) { |
2257 | dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); | |
2258 | return -EINVAL; | |
2259 | } | |
2260 | ||
d2d00862 RQ |
2261 | if (pdev->dev.of_node) { |
2262 | rc = gpmc_probe_dt(pdev); | |
2263 | if (rc) | |
2264 | return rc; | |
2265 | } else { | |
2266 | gpmc_cs_num = GPMC_CS_NUM; | |
2267 | gpmc_nr_waitpins = GPMC_NR_WAITPINS; | |
2268 | } | |
2269 | ||
b3f5525c | 2270 | pm_runtime_enable(&pdev->dev); |
2271 | pm_runtime_get_sync(&pdev->dev); | |
1daa8c1d | 2272 | |
4bbbc1ad | 2273 | l = gpmc_read_reg(GPMC_REVISION); |
aa8d4767 JH |
2274 | |
2275 | /* | |
2276 | * FIXME: Once device-tree migration is complete the below flags | |
2277 | * should be populated based upon the device-tree compatible | |
2278 | * string. For now just use the IP revision. OMAP3+ devices have | |
2279 | * the wr_access and wr_data_mux_bus register fields. OMAP4+ | |
2280 | * devices support the addr-addr-data multiplex protocol. | |
2281 | * | |
2282 | * GPMC IP revisions: | |
2283 | * - OMAP24xx = 2.0 | |
2284 | * - OMAP3xxx = 5.0 | |
2285 | * - OMAP44xx/54xx/AM335x = 6.0 | |
2286 | */ | |
da496873 AM |
2287 | if (GPMC_REVISION_MAJOR(l) > 0x4) |
2288 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; | |
aa8d4767 JH |
2289 | if (GPMC_REVISION_MAJOR(l) > 0x5) |
2290 | gpmc_capability |= GPMC_HAS_MUX_AAD; | |
384258f2 | 2291 | dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), |
da496873 AM |
2292 | GPMC_REVISION_MINOR(l)); |
2293 | ||
84b00f0e | 2294 | gpmc_mem_init(); |
d2d00862 RQ |
2295 | rc = gpmc_gpio_init(gpmc); |
2296 | if (rc) | |
2297 | goto gpio_init_failed; | |
db97eb7d | 2298 | |
384258f2 RQ |
2299 | rc = gpmc_setup_irq(gpmc); |
2300 | if (rc) { | |
2301 | dev_err(gpmc->dev, "gpmc_setup_irq failed\n"); | |
d2d00862 | 2302 | goto setup_irq_failed; |
384258f2 | 2303 | } |
da496873 | 2304 | |
d2d00862 | 2305 | rc = gpmc_probe_dt_children(pdev); |
bc6b1e7b | 2306 | if (rc < 0) { |
d2d00862 RQ |
2307 | dev_err(gpmc->dev, "failed to probe DT children\n"); |
2308 | goto dt_children_failed; | |
bc6b1e7b DM |
2309 | } |
2310 | ||
da496873 | 2311 | return 0; |
384258f2 | 2312 | |
d2d00862 RQ |
2313 | dt_children_failed: |
2314 | gpmc_free_irq(gpmc); | |
2315 | setup_irq_failed: | |
2316 | gpmc_gpio_exit(gpmc); | |
2317 | gpio_init_failed: | |
2318 | gpmc_mem_exit(); | |
384258f2 | 2319 | pm_runtime_put_sync(&pdev->dev); |
d2d00862 RQ |
2320 | pm_runtime_disable(&pdev->dev); |
2321 | ||
384258f2 | 2322 | return rc; |
da496873 AM |
2323 | } |
2324 | ||
351a102d | 2325 | static int gpmc_remove(struct platform_device *pdev) |
da496873 | 2326 | { |
384258f2 RQ |
2327 | struct gpmc_device *gpmc = platform_get_drvdata(pdev); |
2328 | ||
2329 | gpmc_free_irq(gpmc); | |
d2d00862 | 2330 | gpmc_gpio_exit(gpmc); |
da496873 | 2331 | gpmc_mem_exit(); |
b3f5525c | 2332 | pm_runtime_put_sync(&pdev->dev); |
2333 | pm_runtime_disable(&pdev->dev); | |
384258f2 | 2334 | |
da496873 AM |
2335 | return 0; |
2336 | } | |
2337 | ||
b536dd41 | 2338 | #ifdef CONFIG_PM_SLEEP |
2339 | static int gpmc_suspend(struct device *dev) | |
2340 | { | |
2341 | omap3_gpmc_save_context(); | |
2342 | pm_runtime_put_sync(dev); | |
2343 | return 0; | |
2344 | } | |
2345 | ||
2346 | static int gpmc_resume(struct device *dev) | |
2347 | { | |
2348 | pm_runtime_get_sync(dev); | |
2349 | omap3_gpmc_restore_context(); | |
2350 | return 0; | |
2351 | } | |
2352 | #endif | |
2353 | ||
2354 | static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); | |
2355 | ||
da496873 AM |
2356 | static struct platform_driver gpmc_driver = { |
2357 | .probe = gpmc_probe, | |
351a102d | 2358 | .remove = gpmc_remove, |
da496873 AM |
2359 | .driver = { |
2360 | .name = DEVICE_NAME, | |
bc6b1e7b | 2361 | .of_match_table = of_match_ptr(gpmc_dt_ids), |
b536dd41 | 2362 | .pm = &gpmc_pm_ops, |
da496873 AM |
2363 | }, |
2364 | }; | |
2365 | ||
2366 | static __init int gpmc_init(void) | |
2367 | { | |
2368 | return platform_driver_register(&gpmc_driver); | |
2369 | } | |
2370 | ||
2371 | static __exit void gpmc_exit(void) | |
2372 | { | |
2373 | platform_driver_unregister(&gpmc_driver); | |
2374 | ||
db97eb7d | 2375 | } |
da496873 | 2376 | |
a8612809 | 2377 | postcore_initcall(gpmc_init); |
da496873 | 2378 | module_exit(gpmc_exit); |
db97eb7d | 2379 | |
a2d3e7ba RN |
2380 | static struct omap3_gpmc_regs gpmc_context; |
2381 | ||
b2fa3b7c | 2382 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
2383 | { |
2384 | int i; | |
b2fa3b7c | 2385 | |
e984a179 TV |
2386 | if (!gpmc_base) |
2387 | return; | |
2388 | ||
a2d3e7ba RN |
2389 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
2390 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
2391 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
2392 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
2393 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
2394 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
2395 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
f34f3716 | 2396 | for (i = 0; i < gpmc_cs_num; i++) { |
a2d3e7ba RN |
2397 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); |
2398 | if (gpmc_context.cs_context[i].is_valid) { | |
2399 | gpmc_context.cs_context[i].config1 = | |
2400 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
2401 | gpmc_context.cs_context[i].config2 = | |
2402 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
2403 | gpmc_context.cs_context[i].config3 = | |
2404 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
2405 | gpmc_context.cs_context[i].config4 = | |
2406 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
2407 | gpmc_context.cs_context[i].config5 = | |
2408 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
2409 | gpmc_context.cs_context[i].config6 = | |
2410 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
2411 | gpmc_context.cs_context[i].config7 = | |
2412 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
2413 | } | |
2414 | } | |
2415 | } | |
2416 | ||
b2fa3b7c | 2417 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
2418 | { |
2419 | int i; | |
b2fa3b7c | 2420 | |
e984a179 TV |
2421 | if (!gpmc_base) |
2422 | return; | |
2423 | ||
a2d3e7ba RN |
2424 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
2425 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
2426 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
2427 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
2428 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
2429 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
2430 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
f34f3716 | 2431 | for (i = 0; i < gpmc_cs_num; i++) { |
a2d3e7ba RN |
2432 | if (gpmc_context.cs_context[i].is_valid) { |
2433 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
2434 | gpmc_context.cs_context[i].config1); | |
2435 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
2436 | gpmc_context.cs_context[i].config2); | |
2437 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
2438 | gpmc_context.cs_context[i].config3); | |
2439 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
2440 | gpmc_context.cs_context[i].config4); | |
2441 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
2442 | gpmc_context.cs_context[i].config5); | |
2443 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
2444 | gpmc_context.cs_context[i].config6); | |
2445 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
2446 | gpmc_context.cs_context[i].config7); | |
2447 | } | |
2448 | } | |
2449 | } |