[linux-2.6-block.git] / drivers / memory / mtk-smi.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015-2016 MediaTek Inc.
 * Author: Yong Wu <yong.wu@mediatek.com>
 */
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <soc/mediatek/smi.h>
#include <dt-bindings/memory/mt2701-larb-port.h>

/* mt8173 */
#define SMI_LARB_MMU_EN		0xf00

/* mt2701 */
#define REG_SMI_SECUR_CON_BASE		0x5c0

/* every register control 8 port, register offset 0x4 */
#define REG_SMI_SECUR_CON_OFFSET(id)	(((id) >> 3) << 2)
#define REG_SMI_SECUR_CON_ADDR(id)	\
	(REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))

/*
 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
 * or non-security.
 */
#define SMI_SECUR_CON_VAL_MSK(id)	(~(0xf << (((id) & 0x7) << 2)))
#define SMI_SECUR_CON_VAL_VIRT(id)	BIT((((id) & 0x7) << 2) + 3)
/* mt2701 domain should be set to 3 */
#define SMI_SECUR_CON_VAL_DOMAIN(id)	(0x3 << ((((id) & 0x7) << 2) + 1))

/* mt2712 */
#define SMI_LARB_NONSEC_CON(id)	(0x380 + ((id) * 4))
#define F_MMU_EN		BIT(0)

/* SMI COMMON */
#define SMI_BUS_SEL			0x220
#define SMI_BUS_LARB_SHIFT(larbid)	((larbid) << 1)
/* All are MMU0 defaultly. Only specialize mmu1 here. */
#define F_MMU1_LARB(larbid)		(0x1 << SMI_BUS_LARB_SHIFT(larbid))

enum mtk_smi_gen {
	MTK_SMI_GEN1,
	MTK_SMI_GEN2
};

struct mtk_smi_common_plat {
	enum mtk_smi_gen gen;
	bool             has_gals;
	u32              bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
};

struct mtk_smi_larb_gen {
	int port_in_larb[MTK_LARB_NR_MAX + 1];
	void (*config_port)(struct device *);
	unsigned int			larb_direct_to_common_mask;
	bool				has_gals;
};

struct mtk_smi {
	struct device			*dev;
	struct clk			*clk_apb, *clk_smi;
	struct clk			*clk_gals0, *clk_gals1;
	struct clk			*clk_async; /*only needed by mt2701*/
	union {
		void __iomem		*smi_ao_base; /* only for gen1 */
		void __iomem		*base;	      /* only for gen2 */
	};
	const struct mtk_smi_common_plat *plat;
};

struct mtk_smi_larb { /* larb: local arbiter */
	struct mtk_smi			smi;
	void __iomem			*base;
	struct device			*smi_common_dev;
	const struct mtk_smi_larb_gen	*larb_gen;
	int				larbid;
	u32				*mmu;
};

static int mtk_smi_clk_enable(const struct mtk_smi *smi)
{
	int ret;

	ret = clk_prepare_enable(smi->clk_apb);
	if (ret)
		return ret;

	ret = clk_prepare_enable(smi->clk_smi);
	if (ret)
		goto err_disable_apb;

	ret = clk_prepare_enable(smi->clk_gals0);
	if (ret)
		goto err_disable_smi;

	ret = clk_prepare_enable(smi->clk_gals1);
	if (ret)
		goto err_disable_gals0;

	return 0;

err_disable_gals0:
	clk_disable_unprepare(smi->clk_gals0);
err_disable_smi:
	clk_disable_unprepare(smi->clk_smi);
err_disable_apb:
	clk_disable_unprepare(smi->clk_apb);
	return ret;
}

static void mtk_smi_clk_disable(const struct mtk_smi *smi)
{
	clk_disable_unprepare(smi->clk_gals1);
	clk_disable_unprepare(smi->clk_gals0);
	clk_disable_unprepare(smi->clk_smi);
	clk_disable_unprepare(smi->clk_apb);
}

int mtk_smi_larb_get(struct device *larbdev)
{
	int ret = pm_runtime_get_sync(larbdev);

	return (ret < 0) ? ret : 0;
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_get);

void mtk_smi_larb_put(struct device *larbdev)
{
	pm_runtime_put_sync(larbdev);
}
EXPORT_SYMBOL_GPL(mtk_smi_larb_put);

static int
mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	struct mtk_smi_larb_iommu *larb_mmu = data;
	unsigned int         i;

	for (i = 0; i < MTK_LARB_NR_MAX; i++) {
		if (dev == larb_mmu[i].dev) {
			larb->larbid = i;
			larb->mmu = &larb_mmu[i].mmu;
			return 0;
		}
	}
	return -ENODEV;
}

static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	u32 reg;
	int i;

	if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
		return;

	for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
		reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
		reg |= F_MMU_EN;
		writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
	}
}

static void mtk_smi_larb_config_port_mt8173(struct device *dev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);

	writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
}

static void mtk_smi_larb_config_port_gen1(struct device *dev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
	struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
	int i, m4u_port_id, larb_port_num;
	u32 sec_con_val, reg_val;

	m4u_port_id = larb_gen->port_in_larb[larb->larbid];
	larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
			- larb_gen->port_in_larb[larb->larbid];

	for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
		if (*larb->mmu & BIT(i)) {
			/* bit[port + 3] controls the virtual or physical */
			sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
		} else {
			/* do not need to enable m4u for this port */
			continue;
		}
		reg_val = readl(common->smi_ao_base
			+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
		reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
		reg_val |= sec_con_val;
		reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
		writel(reg_val,
			common->smi_ao_base
			+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
	}
}

static void
mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
{
	/* Do nothing as the iommu is always enabled. */
}

static const struct component_ops mtk_smi_larb_component_ops = {
	.bind = mtk_smi_larb_bind,
	.unbind = mtk_smi_larb_unbind,
};

static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
	/* mt8173 do not need the port in larb */
	.config_port = mtk_smi_larb_config_port_mt8173,
};

static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
	.port_in_larb = {
		LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
		LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
	},
	.config_port = mtk_smi_larb_config_port_gen1,
};

static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
	.config_port                = mtk_smi_larb_config_port_gen2_general,
	.larb_direct_to_common_mask = BIT(8) | BIT(9),      /* bdpsys */
};

static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
	.has_gals                   = true,
	.config_port                = mtk_smi_larb_config_port_gen2_general,
	.larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
				      /* IPU0 | IPU1 | CCU */
};

static const struct of_device_id mtk_smi_larb_of_ids[] = {
	{
		.compatible = "mediatek,mt8173-smi-larb",
		.data = &mtk_smi_larb_mt8173
	},
	{
		.compatible = "mediatek,mt2701-smi-larb",
		.data = &mtk_smi_larb_mt2701
	},
	{
		.compatible = "mediatek,mt2712-smi-larb",
		.data = &mtk_smi_larb_mt2712
	},
	{
		.compatible = "mediatek,mt8183-smi-larb",
		.data = &mtk_smi_larb_mt8183
	},
	{}
};

static int mtk_smi_larb_probe(struct platform_device *pdev)
{
	struct mtk_smi_larb *larb;
	struct resource *res;
	struct device *dev = &pdev->dev;
	struct device_node *smi_node;
	struct platform_device *smi_pdev;

	larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
	if (!larb)
		return -ENOMEM;

	larb->larb_gen = of_device_get_match_data(dev);
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	larb->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(larb->base))
		return PTR_ERR(larb->base);

	larb->smi.clk_apb = devm_clk_get(dev, "apb");
	if (IS_ERR(larb->smi.clk_apb))
		return PTR_ERR(larb->smi.clk_apb);

	larb->smi.clk_smi = devm_clk_get(dev, "smi");
	if (IS_ERR(larb->smi.clk_smi))
		return PTR_ERR(larb->smi.clk_smi);

	if (larb->larb_gen->has_gals) {
		/* The larbs may still haven't gals even if the SoC support.*/
		larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
		if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
			larb->smi.clk_gals0 = NULL;
		else if (IS_ERR(larb->smi.clk_gals0))
			return PTR_ERR(larb->smi.clk_gals0);
	}
	larb->smi.dev = dev;

	smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
	if (!smi_node)
		return -EINVAL;

	smi_pdev = of_find_device_by_node(smi_node);
	of_node_put(smi_node);
	if (smi_pdev) {
		if (!platform_get_drvdata(smi_pdev))
			return -EPROBE_DEFER;
		larb->smi_common_dev = &smi_pdev->dev;
	} else {
		dev_err(dev, "Failed to get the smi_common device\n");
		return -EINVAL;
	}

	pm_runtime_enable(dev);
	platform_set_drvdata(pdev, larb);
	return component_add(dev, &mtk_smi_larb_component_ops);
}

static int mtk_smi_larb_remove(struct platform_device *pdev)
{
	pm_runtime_disable(&pdev->dev);
	component_del(&pdev->dev, &mtk_smi_larb_component_ops);
	return 0;
}

static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
	int ret;

	/* Power on smi-common. */
	ret = pm_runtime_get_sync(larb->smi_common_dev);
	if (ret < 0) {
		dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
		return ret;
	}

	ret = mtk_smi_clk_enable(&larb->smi);
	if (ret < 0) {
		dev_err(dev, "Failed to enable clock(%d).\n", ret);
		pm_runtime_put_sync(larb->smi_common_dev);
		return ret;
	}

	/* Configure the basic setting for this larb */
	larb_gen->config_port(dev);

	return 0;
}

static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
{
	struct mtk_smi_larb *larb = dev_get_drvdata(dev);

	mtk_smi_clk_disable(&larb->smi);
	pm_runtime_put_sync(larb->smi_common_dev);
	return 0;
}

static const struct dev_pm_ops smi_larb_pm_ops = {
	SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				     pm_runtime_force_resume)
};

static struct platform_driver mtk_smi_larb_driver = {
	.probe	= mtk_smi_larb_probe,
	.remove	= mtk_smi_larb_remove,
	.driver	= {
		.name = "mtk-smi-larb",
		.of_match_table = mtk_smi_larb_of_ids,
		.pm             = &smi_larb_pm_ops,
	}
};

static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
	.gen = MTK_SMI_GEN1,
};

static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
	.gen = MTK_SMI_GEN2,
};

static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
	.gen      = MTK_SMI_GEN2,
	.has_gals = true,
	.bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
		    F_MMU1_LARB(7),
};

static const struct of_device_id mtk_smi_common_of_ids[] = {
	{
		.compatible = "mediatek,mt8173-smi-common",
		.data = &mtk_smi_common_gen2,
	},
	{
		.compatible = "mediatek,mt2701-smi-common",
		.data = &mtk_smi_common_gen1,
	},
	{
		.compatible = "mediatek,mt2712-smi-common",
		.data = &mtk_smi_common_gen2,
	},
	{
		.compatible = "mediatek,mt8183-smi-common",
		.data = &mtk_smi_common_mt8183,
	},
	{}
};

static int mtk_smi_common_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct mtk_smi *common;
	struct resource *res;
	int ret;

	common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
	if (!common)
		return -ENOMEM;
	common->dev = dev;
	common->plat = of_device_get_match_data(dev);

	common->clk_apb = devm_clk_get(dev, "apb");
	if (IS_ERR(common->clk_apb))
		return PTR_ERR(common->clk_apb);

	common->clk_smi = devm_clk_get(dev, "smi");
	if (IS_ERR(common->clk_smi))
		return PTR_ERR(common->clk_smi);

	if (common->plat->has_gals) {
		common->clk_gals0 = devm_clk_get(dev, "gals0");
		if (IS_ERR(common->clk_gals0))
			return PTR_ERR(common->clk_gals0);

		common->clk_gals1 = devm_clk_get(dev, "gals1");
		if (IS_ERR(common->clk_gals1))
			return PTR_ERR(common->clk_gals1);
	}

	/*
	 * for mtk smi gen 1, we need to get the ao(always on) base to config
	 * m4u port, and we need to enable the aync clock for transform the smi
	 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
	 * base.
	 */
	if (common->plat->gen == MTK_SMI_GEN1) {
		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		common->smi_ao_base = devm_ioremap_resource(dev, res);
		if (IS_ERR(common->smi_ao_base))
			return PTR_ERR(common->smi_ao_base);

		common->clk_async = devm_clk_get(dev, "async");
		if (IS_ERR(common->clk_async))
			return PTR_ERR(common->clk_async);

		ret = clk_prepare_enable(common->clk_async);
		if (ret)
			return ret;
	} else {
		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		common->base = devm_ioremap_resource(dev, res);
		if (IS_ERR(common->base))
			return PTR_ERR(common->base);
	}
	pm_runtime_enable(dev);
	platform_set_drvdata(pdev, common);
	return 0;
}

static int mtk_smi_common_remove(struct platform_device *pdev)
{
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static int __maybe_unused mtk_smi_common_resume(struct device *dev)
{
	struct mtk_smi *common = dev_get_drvdata(dev);
	u32 bus_sel = common->plat->bus_sel;
	int ret;

	ret = mtk_smi_clk_enable(common);
	if (ret) {
		dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
		return ret;
	}

	if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
		writel(bus_sel, common->base + SMI_BUS_SEL);
	return 0;
}

static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
{
	struct mtk_smi *common = dev_get_drvdata(dev);

	mtk_smi_clk_disable(common);
	return 0;
}

static const struct dev_pm_ops smi_common_pm_ops = {
	SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				     pm_runtime_force_resume)
};

static struct platform_driver mtk_smi_common_driver = {
	.probe	= mtk_smi_common_probe,
	.remove = mtk_smi_common_remove,
	.driver	= {
		.name = "mtk-smi-common",
		.of_match_table = mtk_smi_common_of_ids,
		.pm             = &smi_common_pm_ops,
	}
};

static int __init mtk_smi_init(void)
{
	int ret;

	ret = platform_driver_register(&mtk_smi_common_driver);
	if (ret != 0) {
		pr_err("Failed to register SMI driver\n");
		return ret;
	}

	ret = platform_driver_register(&mtk_smi_larb_driver);
	if (ret != 0) {
		pr_err("Failed to register SMI-LARB driver\n");
		goto err_unreg_smi;
	}
	return ret;

err_unreg_smi:
	platform_driver_unregister(&mtk_smi_common_driver);
	return ret;
}

module_init(mtk_smi_init);
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
cc8bbe1a YW	2	/*
	3	* Copyright (c) 2015-2016 MediaTek Inc.
	4	* Author: Yong Wu <yong.wu@mediatek.com>
cc8bbe1a YW	5	*/
	6	#include <linux/clk.h>
	7	#include <linux/component.h>
	8	#include <linux/device.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
4f608d38	11	#include <linux/module.h>
cc8bbe1a YW	12	#include <linux/of.h>
	13	#include <linux/of_platform.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pm_runtime.h>
	16	#include <soc/mediatek/smi.h>
3c8f4ad8	17	#include <dt-bindings/memory/mt2701-larb-port.h>
cc8bbe1a	18
e6dec923	19	/* mt8173 */
cc8bbe1a	20	#define SMI_LARB_MMU_EN 0xf00
e6dec923 YW	21
e6dec923 YW	22	/* mt2701 */
3c8f4ad8 HZ	23	#define REG_SMI_SECUR_CON_BASE 0x5c0
	24
	25	/* every register control 8 port, register offset 0x4 */
	26	#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
	27	#define REG_SMI_SECUR_CON_ADDR(id) \
	28	(REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
	29
	30	/*
	31	* every port have 4 bit to control, bit[port + 3] control virtual or physical,
	32	* bit[port + 2 : port + 1] control the domain, bit[port] control the security
	33	* or non-security.
	34	*/
	35	#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
	36	#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
	37	/* mt2701 domain should be set to 3 */
	38	#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
	39
e6dec923 YW	40	/* mt2712 */
	41	#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
	42	#define F_MMU_EN BIT(0)
	43
567e58cf YW	44	/* SMI COMMON */
	45	#define SMI_BUS_SEL 0x220
	46	#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
	47	/* All are MMU0 defaultly. Only specialize mmu1 here. */
	48	#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
	49
42d42c76 YW	50	enum mtk_smi_gen {
	51	MTK_SMI_GEN1,
	52	MTK_SMI_GEN2
	53	};
	54
	55	struct mtk_smi_common_plat {
	56	enum mtk_smi_gen gen;
64fea74a	57	bool has_gals;
567e58cf	58	u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
42d42c76 YW	59	};
42d42c76 YW	60
3c8f4ad8 HZ	61	struct mtk_smi_larb_gen {
	62	int port_in_larb[MTK_LARB_NR_MAX + 1];
	63	void (config_port)(struct device );
2e9b0908	64	unsigned int larb_direct_to_common_mask;
64fea74a	65	bool has_gals;
3c8f4ad8	66	};
cc8bbe1a YW	67
cc8bbe1a YW	68	struct mtk_smi {
3c8f4ad8 HZ	69	struct device *dev;
3c8f4ad8 HZ	70	struct clk clk_apb, clk_smi;
64fea74a	71	struct clk clk_gals0, clk_gals1;
3c8f4ad8	72	struct clk clk_async; /only needed by mt2701*/
567e58cf YW	73	union {
	74	void __iomem smi_ao_base; / only for gen1 */
	75	void __iomem base; / only for gen2 */
	76	};
42d42c76	77	const struct mtk_smi_common_plat *plat;
cc8bbe1a YW	78	};
	79
	80	struct mtk_smi_larb { /* larb: local arbiter */
3c8f4ad8 HZ	81	struct mtk_smi smi;
	82	void __iomem *base;
	83	struct device *smi_common_dev;
	84	const struct mtk_smi_larb_gen *larb_gen;
	85	int larbid;
	86	u32 *mmu;
	87	};
	88
4f0a1a1a	89	static int mtk_smi_clk_enable(const struct mtk_smi *smi)
cc8bbe1a YW	90	{
	91	int ret;
	92
cc8bbe1a YW	93	ret = clk_prepare_enable(smi->clk_apb);
cc8bbe1a YW	94	if (ret)
4f0a1a1a	95	return ret;
cc8bbe1a YW	96
	97	ret = clk_prepare_enable(smi->clk_smi);
	98	if (ret)
	99	goto err_disable_apb;
	100
64fea74a YW	101	ret = clk_prepare_enable(smi->clk_gals0);
	102	if (ret)
	103	goto err_disable_smi;
	104
	105	ret = clk_prepare_enable(smi->clk_gals1);
	106	if (ret)
	107	goto err_disable_gals0;
	108
cc8bbe1a YW	109	return 0;
cc8bbe1a YW	110
64fea74a YW	111	err_disable_gals0:
	112	clk_disable_unprepare(smi->clk_gals0);
	113	err_disable_smi:
	114	clk_disable_unprepare(smi->clk_smi);
cc8bbe1a YW	115	err_disable_apb:
cc8bbe1a YW	116	clk_disable_unprepare(smi->clk_apb);
cc8bbe1a YW	117	return ret;
	118	}
	119
4f0a1a1a	120	static void mtk_smi_clk_disable(const struct mtk_smi *smi)
cc8bbe1a	121	{
64fea74a YW	122	clk_disable_unprepare(smi->clk_gals1);
64fea74a YW	123	clk_disable_unprepare(smi->clk_gals0);
cc8bbe1a YW	124	clk_disable_unprepare(smi->clk_smi);
cc8bbe1a YW	125	clk_disable_unprepare(smi->clk_apb);
cc8bbe1a YW	126	}
	127
	128	int mtk_smi_larb_get(struct device *larbdev)
	129	{
4f0a1a1a	130	int ret = pm_runtime_get_sync(larbdev);
cc8bbe1a	131
4f0a1a1a	132	return (ret < 0) ? ret : 0;
cc8bbe1a	133	}
cb1b5dff	134	EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
cc8bbe1a YW	135
	136	void mtk_smi_larb_put(struct device *larbdev)
	137	{
4f0a1a1a	138	pm_runtime_put_sync(larbdev);
cc8bbe1a	139	}
cb1b5dff	140	EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
cc8bbe1a YW	141
	142	static int
	143	mtk_smi_larb_bind(struct device dev, struct device master, void *data)
	144	{
	145	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
1ee9feb2	146	struct mtk_smi_larb_iommu *larb_mmu = data;
cc8bbe1a YW	147	unsigned int i;
cc8bbe1a YW	148
ec2da07c	149	for (i = 0; i < MTK_LARB_NR_MAX; i++) {
1ee9feb2	150	if (dev == larb_mmu[i].dev) {
ec2da07c	151	larb->larbid = i;
1ee9feb2	152	larb->mmu = &larb_mmu[i].mmu;
cc8bbe1a YW	153	return 0;
	154	}
	155	}
	156	return -ENODEV;
	157	}
	158
2e9b0908	159	static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
3c8f4ad8 HZ	160	{
3c8f4ad8 HZ	161	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
e6dec923 YW	162	u32 reg;
e6dec923 YW	163	int i;
3c8f4ad8	164
2e9b0908	165	if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
e6dec923 YW	166	return;
	167
	168	for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
	169	reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
	170	reg \|= F_MMU_EN;
	171	writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
	172	}
3c8f4ad8 HZ	173	}
3c8f4ad8 HZ	174
e6dec923 YW	175	static void mtk_smi_larb_config_port_mt8173(struct device *dev)
	176	{
	177	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	178
	179	writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
	180	}
3c8f4ad8 HZ	181
	182	static void mtk_smi_larb_config_port_gen1(struct device *dev)
	183	{
	184	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	185	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
	186	struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
	187	int i, m4u_port_id, larb_port_num;
	188	u32 sec_con_val, reg_val;
	189
	190	m4u_port_id = larb_gen->port_in_larb[larb->larbid];
	191	larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
	192	- larb_gen->port_in_larb[larb->larbid];
	193
	194	for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
	195	if (*larb->mmu & BIT(i)) {
	196	/* bit[port + 3] controls the virtual or physical */
	197	sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
	198	} else {
	199	/* do not need to enable m4u for this port */
	200	continue;
	201	}
	202	reg_val = readl(common->smi_ao_base
	203	+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
	204	reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
	205	reg_val \|= sec_con_val;
	206	reg_val \|= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
	207	writel(reg_val,
	208	common->smi_ao_base
	209	+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
	210	}
	211	}
	212
cc8bbe1a YW	213	static void
	214	mtk_smi_larb_unbind(struct device dev, struct device master, void *data)
	215	{
	216	/* Do nothing as the iommu is always enabled. */
	217	}
	218
	219	static const struct component_ops mtk_smi_larb_component_ops = {
	220	.bind = mtk_smi_larb_bind,
	221	.unbind = mtk_smi_larb_unbind,
	222	};
	223
3c8f4ad8 HZ	224	static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
3c8f4ad8 HZ	225	/* mt8173 do not need the port in larb */
e6dec923	226	.config_port = mtk_smi_larb_config_port_mt8173,
3c8f4ad8 HZ	227	};
	228
	229	static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
	230	.port_in_larb = {
	231	LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
	232	LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
	233	},
	234	.config_port = mtk_smi_larb_config_port_gen1,
	235	};
	236
e6dec923	237	static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
2e9b0908 YW	238	.config_port = mtk_smi_larb_config_port_gen2_general,
2e9b0908 YW	239	.larb_direct_to_common_mask = BIT(8) \| BIT(9), /* bdpsys */
e6dec923 YW	240	};
e6dec923 YW	241
907ba6a1 YW	242	static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
	243	.has_gals = true,
	244	.config_port = mtk_smi_larb_config_port_gen2_general,
	245	.larb_direct_to_common_mask = BIT(2) \| BIT(3) \| BIT(7),
	246	/* IPU0 \| IPU1 \| CCU */
	247	};
	248
3c8f4ad8 HZ	249	static const struct of_device_id mtk_smi_larb_of_ids[] = {
	250	{
	251	.compatible = "mediatek,mt8173-smi-larb",
	252	.data = &mtk_smi_larb_mt8173
	253	},
	254	{
	255	.compatible = "mediatek,mt2701-smi-larb",
	256	.data = &mtk_smi_larb_mt2701
	257	},
e6dec923 YW	258	{
	259	.compatible = "mediatek,mt2712-smi-larb",
	260	.data = &mtk_smi_larb_mt2712
	261	},
907ba6a1 YW	262	{
	263	.compatible = "mediatek,mt8183-smi-larb",
	264	.data = &mtk_smi_larb_mt8183
	265	},
3c8f4ad8 HZ	266	{}
	267	};
	268
cc8bbe1a YW	269	static int mtk_smi_larb_probe(struct platform_device *pdev)
	270	{
	271	struct mtk_smi_larb *larb;
	272	struct resource *res;
	273	struct device *dev = &pdev->dev;
	274	struct device_node *smi_node;
	275	struct platform_device *smi_pdev;
	276
cc8bbe1a YW	277	larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
	278	if (!larb)
	279	return -ENOMEM;
	280
75487860	281	larb->larb_gen = of_device_get_match_data(dev);
cc8bbe1a YW	282	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	283	larb->base = devm_ioremap_resource(dev, res);
	284	if (IS_ERR(larb->base))
	285	return PTR_ERR(larb->base);
	286
	287	larb->smi.clk_apb = devm_clk_get(dev, "apb");
	288	if (IS_ERR(larb->smi.clk_apb))
	289	return PTR_ERR(larb->smi.clk_apb);
	290
	291	larb->smi.clk_smi = devm_clk_get(dev, "smi");
	292	if (IS_ERR(larb->smi.clk_smi))
	293	return PTR_ERR(larb->smi.clk_smi);
64fea74a YW	294
	295	if (larb->larb_gen->has_gals) {
	296	/* The larbs may still haven't gals even if the SoC support.*/
	297	larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
	298	if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
	299	larb->smi.clk_gals0 = NULL;
	300	else if (IS_ERR(larb->smi.clk_gals0))
	301	return PTR_ERR(larb->smi.clk_gals0);
	302	}
cc8bbe1a YW	303	larb->smi.dev = dev;
	304
	305	smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
	306	if (!smi_node)
	307	return -EINVAL;
	308
	309	smi_pdev = of_find_device_by_node(smi_node);
	310	of_node_put(smi_node);
	311	if (smi_pdev) {
4f608d38 YW	312	if (!platform_get_drvdata(smi_pdev))
4f608d38 YW	313	return -EPROBE_DEFER;
cc8bbe1a YW	314	larb->smi_common_dev = &smi_pdev->dev;
	315	} else {
	316	dev_err(dev, "Failed to get the smi_common device\n");
	317	return -EINVAL;
	318	}
	319
	320	pm_runtime_enable(dev);
	321	platform_set_drvdata(pdev, larb);
	322	return component_add(dev, &mtk_smi_larb_component_ops);
	323	}
	324
	325	static int mtk_smi_larb_remove(struct platform_device *pdev)
	326	{
	327	pm_runtime_disable(&pdev->dev);
	328	component_del(&pdev->dev, &mtk_smi_larb_component_ops);
	329	return 0;
	330	}
	331
4f0a1a1a YW	332	static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
	333	{
	334	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	335	const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
	336	int ret;
	337
	338	/* Power on smi-common. */
	339	ret = pm_runtime_get_sync(larb->smi_common_dev);
	340	if (ret < 0) {
	341	dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
	342	return ret;
	343	}
	344
	345	ret = mtk_smi_clk_enable(&larb->smi);
	346	if (ret < 0) {
	347	dev_err(dev, "Failed to enable clock(%d).\n", ret);
	348	pm_runtime_put_sync(larb->smi_common_dev);
	349	return ret;
	350	}
	351
	352	/* Configure the basic setting for this larb */
	353	larb_gen->config_port(dev);
	354
	355	return 0;
	356	}
	357
	358	static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
	359	{
	360	struct mtk_smi_larb *larb = dev_get_drvdata(dev);
	361
	362	mtk_smi_clk_disable(&larb->smi);
	363	pm_runtime_put_sync(larb->smi_common_dev);
	364	return 0;
	365	}
	366
	367	static const struct dev_pm_ops smi_larb_pm_ops = {
	368	SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
fb03082a YW	369	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
fb03082a YW	370	pm_runtime_force_resume)
4f0a1a1a YW	371	};
4f0a1a1a YW	372
cc8bbe1a YW	373	static struct platform_driver mtk_smi_larb_driver = {
cc8bbe1a YW	374	.probe = mtk_smi_larb_probe,
3c8f4ad8	375	.remove = mtk_smi_larb_remove,
cc8bbe1a YW	376	.driver = {
	377	.name = "mtk-smi-larb",
	378	.of_match_table = mtk_smi_larb_of_ids,
4f0a1a1a	379	.pm = &smi_larb_pm_ops,
cc8bbe1a YW	380	}
	381	};
	382
42d42c76 YW	383	static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
	384	.gen = MTK_SMI_GEN1,
	385	};
	386
	387	static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
	388	.gen = MTK_SMI_GEN2,
	389	};
	390
907ba6a1 YW	391	static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
	392	.gen = MTK_SMI_GEN2,
	393	.has_gals = true,
567e58cf YW	394	.bus_sel = F_MMU1_LARB(1) \| F_MMU1_LARB(2) \| F_MMU1_LARB(5) \|
567e58cf YW	395	F_MMU1_LARB(7),
907ba6a1 YW	396	};
907ba6a1 YW	397
3c8f4ad8 HZ	398	static const struct of_device_id mtk_smi_common_of_ids[] = {
	399	{
	400	.compatible = "mediatek,mt8173-smi-common",
42d42c76	401	.data = &mtk_smi_common_gen2,
3c8f4ad8 HZ	402	},
	403	{
	404	.compatible = "mediatek,mt2701-smi-common",
42d42c76	405	.data = &mtk_smi_common_gen1,
3c8f4ad8	406	},
e6dec923 YW	407	{
e6dec923 YW	408	.compatible = "mediatek,mt2712-smi-common",
42d42c76	409	.data = &mtk_smi_common_gen2,
e6dec923	410	},
907ba6a1 YW	411	{
	412	.compatible = "mediatek,mt8183-smi-common",
	413	.data = &mtk_smi_common_mt8183,
	414	},
3c8f4ad8 HZ	415	{}
	416	};
	417
cc8bbe1a YW	418	static int mtk_smi_common_probe(struct platform_device *pdev)
	419	{
	420	struct device *dev = &pdev->dev;
	421	struct mtk_smi *common;
3c8f4ad8	422	struct resource *res;
46cc815d	423	int ret;
cc8bbe1a	424
cc8bbe1a YW	425	common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
	426	if (!common)
	427	return -ENOMEM;
	428	common->dev = dev;
42d42c76	429	common->plat = of_device_get_match_data(dev);
cc8bbe1a YW	430
	431	common->clk_apb = devm_clk_get(dev, "apb");
	432	if (IS_ERR(common->clk_apb))
	433	return PTR_ERR(common->clk_apb);
	434
	435	common->clk_smi = devm_clk_get(dev, "smi");
	436	if (IS_ERR(common->clk_smi))
	437	return PTR_ERR(common->clk_smi);
	438
64fea74a YW	439	if (common->plat->has_gals) {
	440	common->clk_gals0 = devm_clk_get(dev, "gals0");
	441	if (IS_ERR(common->clk_gals0))
	442	return PTR_ERR(common->clk_gals0);
	443
	444	common->clk_gals1 = devm_clk_get(dev, "gals1");
	445	if (IS_ERR(common->clk_gals1))
	446	return PTR_ERR(common->clk_gals1);
	447	}
	448
3c8f4ad8 HZ	449	/*
	450	* for mtk smi gen 1, we need to get the ao(always on) base to config
	451	* m4u port, and we need to enable the aync clock for transform the smi
	452	* clock into emi clock domain, but for mtk smi gen2, there's no smi ao
	453	* base.
	454	*/
42d42c76	455	if (common->plat->gen == MTK_SMI_GEN1) {
3c8f4ad8 HZ	456	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	457	common->smi_ao_base = devm_ioremap_resource(dev, res);
	458	if (IS_ERR(common->smi_ao_base))
	459	return PTR_ERR(common->smi_ao_base);
	460
	461	common->clk_async = devm_clk_get(dev, "async");
	462	if (IS_ERR(common->clk_async))
	463	return PTR_ERR(common->clk_async);
	464
46cc815d AY	465	ret = clk_prepare_enable(common->clk_async);
	466	if (ret)
	467	return ret;
567e58cf YW	468	} else {
	469	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	470	common->base = devm_ioremap_resource(dev, res);
	471	if (IS_ERR(common->base))
	472	return PTR_ERR(common->base);
3c8f4ad8	473	}
cc8bbe1a YW	474	pm_runtime_enable(dev);
	475	platform_set_drvdata(pdev, common);
	476	return 0;
	477	}
	478
	479	static int mtk_smi_common_remove(struct platform_device *pdev)
	480	{
	481	pm_runtime_disable(&pdev->dev);
	482	return 0;
	483	}
	484
4f0a1a1a YW	485	static int __maybe_unused mtk_smi_common_resume(struct device *dev)
	486	{
	487	struct mtk_smi *common = dev_get_drvdata(dev);
567e58cf	488	u32 bus_sel = common->plat->bus_sel;
4f0a1a1a YW	489	int ret;
	490
	491	ret = mtk_smi_clk_enable(common);
	492	if (ret) {
	493	dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
	494	return ret;
	495	}
567e58cf YW	496
	497	if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
	498	writel(bus_sel, common->base + SMI_BUS_SEL);
4f0a1a1a YW	499	return 0;
	500	}
	501
	502	static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
	503	{
	504	struct mtk_smi *common = dev_get_drvdata(dev);
	505
	506	mtk_smi_clk_disable(common);
	507	return 0;
	508	}
	509
	510	static const struct dev_pm_ops smi_common_pm_ops = {
	511	SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
fb03082a YW	512	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
fb03082a YW	513	pm_runtime_force_resume)
4f0a1a1a YW	514	};
4f0a1a1a YW	515
cc8bbe1a YW	516	static struct platform_driver mtk_smi_common_driver = {
	517	.probe = mtk_smi_common_probe,
	518	.remove = mtk_smi_common_remove,
	519	.driver = {
	520	.name = "mtk-smi-common",
	521	.of_match_table = mtk_smi_common_of_ids,
4f0a1a1a	522	.pm = &smi_common_pm_ops,
cc8bbe1a YW	523	}
	524	};
	525
	526	static int __init mtk_smi_init(void)
	527	{
	528	int ret;
	529
	530	ret = platform_driver_register(&mtk_smi_common_driver);
	531	if (ret != 0) {
	532	pr_err("Failed to register SMI driver\n");
	533	return ret;
	534	}
	535
	536	ret = platform_driver_register(&mtk_smi_larb_driver);
	537	if (ret != 0) {
	538	pr_err("Failed to register SMI-LARB driver\n");
	539	goto err_unreg_smi;
	540	}
	541	return ret;
	542
	543	err_unreg_smi:
	544	platform_driver_unregister(&mtk_smi_common_driver);
	545	return ret;
	546	}
3c8f4ad8	547
4f608d38	548	module_init(mtk_smi_init);