[linux-2.6-block.git] / drivers / memory / jz4780-nemc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * JZ4780 NAND/external memory controller (NEMC)
 *
 * Copyright (c) 2015 Imagination Technologies
 * Author: Alex Smith <alex@alex-smith.me.uk>
 */

#include <linux/clk.h>
#include <linux/init.h>
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <linux/jz4780-nemc.h>

#define NEMC_SMCRn(n)		(0x14 + (((n) - 1) * 4))
#define NEMC_NFCSR		0x50

#define NEMC_SMCR_SMT		BIT(0)
#define NEMC_SMCR_BW_SHIFT	6
#define NEMC_SMCR_BW_MASK	(0x3 << NEMC_SMCR_BW_SHIFT)
#define NEMC_SMCR_BW_8		(0 << 6)
#define NEMC_SMCR_TAS_SHIFT	8
#define NEMC_SMCR_TAS_MASK	(0xf << NEMC_SMCR_TAS_SHIFT)
#define NEMC_SMCR_TAH_SHIFT	12
#define NEMC_SMCR_TAH_MASK	(0xf << NEMC_SMCR_TAH_SHIFT)
#define NEMC_SMCR_TBP_SHIFT	16
#define NEMC_SMCR_TBP_MASK	(0xf << NEMC_SMCR_TBP_SHIFT)
#define NEMC_SMCR_TAW_SHIFT	20
#define NEMC_SMCR_TAW_MASK	(0xf << NEMC_SMCR_TAW_SHIFT)
#define NEMC_SMCR_TSTRV_SHIFT	24
#define NEMC_SMCR_TSTRV_MASK	(0x3f << NEMC_SMCR_TSTRV_SHIFT)

#define NEMC_NFCSR_NFEn(n)	BIT(((n) - 1) << 1)
#define NEMC_NFCSR_NFCEn(n)	BIT((((n) - 1) << 1) + 1)
#define NEMC_NFCSR_TNFEn(n)	BIT(16 + (n) - 1)

struct jz_soc_info {
	u8 tas_tah_cycles_max;
};

struct jz4780_nemc {
	spinlock_t lock;
	struct device *dev;
	const struct jz_soc_info *soc_info;
	void __iomem *base;
	struct clk *clk;
	uint32_t clk_period;
	unsigned long banks_present;
};

/**
 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
 * @dev: device to count banks for, must be a child of the NEMC.
 *
 * Return: The number of unique NEMC banks referred to by the specified NEMC
 * child device. Unique here means that a device that references the same bank
 * multiple times in its "reg" property will only count once.
 */
unsigned int jz4780_nemc_num_banks(struct device *dev)
{
	const __be32 *prop;
	unsigned int bank, count = 0;
	unsigned long referenced = 0;
	int i = 0;

	while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {
		bank = of_read_number(prop, 1);
		if (!(referenced & BIT(bank))) {
			referenced |= BIT(bank);
			count++;
		}
	}

	return count;
}
EXPORT_SYMBOL(jz4780_nemc_num_banks);

/**
 * jz4780_nemc_set_type() - set the type of device connected to a bank
 * @dev: child device of the NEMC.
 * @bank: bank number to configure.
 * @type: type of device connected to the bank.
 */
void jz4780_nemc_set_type(struct device *dev, unsigned int bank,
			  enum jz4780_nemc_bank_type type)
{
	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
	uint32_t nfcsr;

	nfcsr = readl(nemc->base + NEMC_NFCSR);

	/* TODO: Support toggle NAND devices. */
	switch (type) {
	case JZ4780_NEMC_BANK_SRAM:
		nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank));
		break;
	case JZ4780_NEMC_BANK_NAND:
		nfcsr &= ~NEMC_NFCSR_TNFEn(bank);
		nfcsr |= NEMC_NFCSR_NFEn(bank);
		break;
	}

	writel(nfcsr, nemc->base + NEMC_NFCSR);
}
EXPORT_SYMBOL(jz4780_nemc_set_type);

/**
 * jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
 * @dev: child device of the NEMC.
 * @bank: bank number of device.
 * @assert: whether the chip enable pin should be asserted.
 *
 * (De-)asserts the chip enable pin for the NAND device connected to the
 * specified bank.
 */
void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)
{
	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
	uint32_t nfcsr;

	nfcsr = readl(nemc->base + NEMC_NFCSR);

	if (assert)
		nfcsr |= NEMC_NFCSR_NFCEn(bank);
	else
		nfcsr &= ~NEMC_NFCSR_NFCEn(bank);

	writel(nfcsr, nemc->base + NEMC_NFCSR);
}
EXPORT_SYMBOL(jz4780_nemc_assert);

static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc)
{
	unsigned long rate;

	rate = clk_get_rate(nemc->clk);
	if (!rate)
		return 0;

	/* Return in picoseconds. */
	return div64_ul(1000000000000ull, rate);
}

static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns)
{
	return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;
}

static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc,
				       unsigned int bank,
				       struct device_node *node)
{
	uint32_t smcr, val, cycles;

	/*
	 * Conversion of tBP and tAW cycle counts to values supported by the
	 * hardware (round up to the next supported value).
	 */
	static const u8 convert_tBP_tAW[] = {
		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,

		/* 11 - 12 -> 12 cycles */
		11, 11,

		/* 13 - 15 -> 15 cycles */
		12, 12, 12,

		/* 16 - 20 -> 20 cycles */
		13, 13, 13, 13, 13,

		/* 21 - 25 -> 25 cycles */
		14, 14, 14, 14, 14,

		/* 26 - 31 -> 31 cycles */
		15, 15, 15, 15, 15, 15
	};

	smcr = readl(nemc->base + NEMC_SMCRn(bank));
	smcr &= ~NEMC_SMCR_SMT;

	if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {
		smcr &= ~NEMC_SMCR_BW_MASK;
		switch (val) {
		case 8:
			smcr |= NEMC_SMCR_BW_8;
			break;
		default:
			/*
			 * Earlier SoCs support a 16 bit bus width (the 4780
			 * does not), until those are properly supported, error.
			 */
			dev_err(nemc->dev, "unsupported bus width: %u\n", val);
			return false;
		}
	}

	if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
		smcr &= ~NEMC_SMCR_TAS_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > nemc->soc_info->tas_tah_cycles_max) {
			dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= cycles << NEMC_SMCR_TAS_SHIFT;
	}

	if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
		smcr &= ~NEMC_SMCR_TAH_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > nemc->soc_info->tas_tah_cycles_max) {
			dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= cycles << NEMC_SMCR_TAH_SHIFT;
	}

	if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {
		smcr &= ~NEMC_SMCR_TBP_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > 31) {
			dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT;
	}

	if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {
		smcr &= ~NEMC_SMCR_TAW_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > 31) {
			dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT;
	}

	if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {
		smcr &= ~NEMC_SMCR_TSTRV_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > 63) {
			dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT;
	}

	writel(smcr, nemc->base + NEMC_SMCRn(bank));
	return true;
}

static int jz4780_nemc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct jz4780_nemc *nemc;
	struct resource *res;
	struct device_node *child;
	const __be32 *prop;
	unsigned int bank;
	unsigned long referenced;
	int i, ret;

	nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL);
	if (!nemc)
		return -ENOMEM;

	nemc->soc_info = device_get_match_data(dev);
	if (!nemc->soc_info)
		return -EINVAL;

	spin_lock_init(&nemc->lock);
	nemc->dev = dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	nemc->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(nemc->base)) {
		dev_err(dev, "failed to get I/O memory\n");
		return PTR_ERR(nemc->base);
	}

	writel(0, nemc->base + NEMC_NFCSR);

	nemc->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(nemc->clk)) {
		dev_err(dev, "failed to get clock\n");
		return PTR_ERR(nemc->clk);
	}

	ret = clk_prepare_enable(nemc->clk);
	if (ret) {
		dev_err(dev, "failed to enable clock: %d\n", ret);
		return ret;
	}

	nemc->clk_period = jz4780_nemc_clk_period(nemc);
	if (!nemc->clk_period) {
		dev_err(dev, "failed to calculate clock period\n");
		clk_disable_unprepare(nemc->clk);
		return -EINVAL;
	}

	/*
	 * Iterate over child devices, check that they do not conflict with
	 * each other, and register child devices for them. If a child device
	 * has invalid properties, it is ignored and no platform device is
	 * registered for it.
	 */
	for_each_child_of_node(nemc->dev->of_node, child) {
		referenced = 0;
		i = 0;
		while ((prop = of_get_address(child, i++, NULL, NULL))) {
			bank = of_read_number(prop, 1);
			if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) {
				dev_err(nemc->dev,
					"%pOF requests invalid bank %u\n",
					child, bank);

				/* Will continue the outer loop below. */
				referenced = 0;
				break;
			}

			referenced |= BIT(bank);
		}

		if (!referenced) {
			dev_err(nemc->dev, "%pOF has no addresses\n",
				child);
			continue;
		} else if (nemc->banks_present & referenced) {
			dev_err(nemc->dev, "%pOF conflicts with another node\n",
				child);
			continue;
		}

		/* Configure bank parameters. */
		for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {
			if (!jz4780_nemc_configure_bank(nemc, bank, child)) {
				referenced = 0;
				break;
			}
		}

		if (referenced) {
			if (of_platform_device_create(child, NULL, nemc->dev))
				nemc->banks_present |= referenced;
		}
	}

	platform_set_drvdata(pdev, nemc);
	dev_info(dev, "JZ4780 NEMC initialised\n");
	return 0;
}

static int jz4780_nemc_remove(struct platform_device *pdev)
{
	struct jz4780_nemc *nemc = platform_get_drvdata(pdev);

	clk_disable_unprepare(nemc->clk);
	return 0;
}

static const struct jz_soc_info jz4740_soc_info = {
	.tas_tah_cycles_max = 7,
};

static const struct jz_soc_info jz4780_soc_info = {
	.tas_tah_cycles_max = 15,
};

static const struct of_device_id jz4780_nemc_dt_match[] = {
	{ .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
	{ .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
	{},
};

static struct platform_driver jz4780_nemc_driver = {
	.probe		= jz4780_nemc_probe,
	.remove		= jz4780_nemc_remove,
	.driver	= {
		.name	= "jz4780-nemc",
		.of_match_table = of_match_ptr(jz4780_nemc_dt_match),
	},
};

static int __init jz4780_nemc_init(void)
{
	return platform_driver_register(&jz4780_nemc_driver);
}
subsys_initcall(jz4780_nemc_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
911a8882 AS	2	/*
	3	* JZ4780 NAND/external memory controller (NEMC)
	4	*
	5	* Copyright (c) 2015 Imagination Technologies
	6	* Author: Alex Smith <alex@alex-smith.me.uk>
911a8882 AS	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/init.h>
	11	#include <linux/math64.h>
	12	#include <linux/of.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_device.h>
	15	#include <linux/of_platform.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/slab.h>
	18	#include <linux/spinlock.h>
	19
	20	#include <linux/jz4780-nemc.h>
	21
	22	#define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
	23	#define NEMC_NFCSR 0x50
	24
	25	#define NEMC_SMCR_SMT BIT(0)
	26	#define NEMC_SMCR_BW_SHIFT 6
	27	#define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT)
	28	#define NEMC_SMCR_BW_8 (0 << 6)
	29	#define NEMC_SMCR_TAS_SHIFT 8
	30	#define NEMC_SMCR_TAS_MASK (0xf << NEMC_SMCR_TAS_SHIFT)
	31	#define NEMC_SMCR_TAH_SHIFT 12
	32	#define NEMC_SMCR_TAH_MASK (0xf << NEMC_SMCR_TAH_SHIFT)
	33	#define NEMC_SMCR_TBP_SHIFT 16
	34	#define NEMC_SMCR_TBP_MASK (0xf << NEMC_SMCR_TBP_SHIFT)
	35	#define NEMC_SMCR_TAW_SHIFT 20
	36	#define NEMC_SMCR_TAW_MASK (0xf << NEMC_SMCR_TAW_SHIFT)
	37	#define NEMC_SMCR_TSTRV_SHIFT 24
	38	#define NEMC_SMCR_TSTRV_MASK (0x3f << NEMC_SMCR_TSTRV_SHIFT)
	39
	40	#define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
	41	#define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
	42	#define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
	43
a00b0042 PC	44	struct jz_soc_info {
	45	u8 tas_tah_cycles_max;
	46	};
	47
911a8882 AS	48	struct jz4780_nemc {
	49	spinlock_t lock;
	50	struct device *dev;
a00b0042	51	const struct jz_soc_info *soc_info;
911a8882 AS	52	void __iomem *base;
	53	struct clk *clk;
	54	uint32_t clk_period;
	55	unsigned long banks_present;
	56	};
	57
	58	/**
	59	* jz4780_nemc_num_banks() - count the number of banks referenced by a device
	60	* @dev: device to count banks for, must be a child of the NEMC.
	61	*
	62	* Return: The number of unique NEMC banks referred to by the specified NEMC
	63	* child device. Unique here means that a device that references the same bank
d171df6b	64	* multiple times in its "reg" property will only count once.
911a8882 AS	65	*/
	66	unsigned int jz4780_nemc_num_banks(struct device *dev)
	67	{
	68	const __be32 *prop;
	69	unsigned int bank, count = 0;
	70	unsigned long referenced = 0;
	71	int i = 0;
	72
	73	while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {
	74	bank = of_read_number(prop, 1);
	75	if (!(referenced & BIT(bank))) {
	76	referenced \|= BIT(bank);
	77	count++;
	78	}
	79	}
	80
	81	return count;
	82	}
	83	EXPORT_SYMBOL(jz4780_nemc_num_banks);
	84
	85	/**
	86	* jz4780_nemc_set_type() - set the type of device connected to a bank
	87	* @dev: child device of the NEMC.
	88	* @bank: bank number to configure.
	89	* @type: type of device connected to the bank.
	90	*/
	91	void jz4780_nemc_set_type(struct device *dev, unsigned int bank,
	92	enum jz4780_nemc_bank_type type)
	93	{
	94	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
	95	uint32_t nfcsr;
	96
	97	nfcsr = readl(nemc->base + NEMC_NFCSR);
	98
	99	/* TODO: Support toggle NAND devices. */
	100	switch (type) {
	101	case JZ4780_NEMC_BANK_SRAM:
	102	nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) \| NEMC_NFCSR_NFEn(bank));
	103	break;
	104	case JZ4780_NEMC_BANK_NAND:
	105	nfcsr &= ~NEMC_NFCSR_TNFEn(bank);
	106	nfcsr \|= NEMC_NFCSR_NFEn(bank);
	107	break;
	108	}
	109
	110	writel(nfcsr, nemc->base + NEMC_NFCSR);
	111	}
	112	EXPORT_SYMBOL(jz4780_nemc_set_type);
	113
	114	/**
	115	* jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
	116	* @dev: child device of the NEMC.
	117	* @bank: bank number of device.
	118	* @assert: whether the chip enable pin should be asserted.
	119	*
	120	* (De-)asserts the chip enable pin for the NAND device connected to the
	121	* specified bank.
	122	*/
	123	void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)
	124	{
	125	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
	126	uint32_t nfcsr;
	127
	128	nfcsr = readl(nemc->base + NEMC_NFCSR);
129
130	if (assert)
131	nfcsr \|= NEMC_NFCSR_NFCEn(bank);
132	else
133	nfcsr &= ~NEMC_NFCSR_NFCEn(bank);
134
135	writel(nfcsr, nemc->base + NEMC_NFCSR);
136	}
137	EXPORT_SYMBOL(jz4780_nemc_assert);
138
139	static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc)
140	{
141	unsigned long rate;
142
143	rate = clk_get_rate(nemc->clk);
144	if (!rate)
145	return 0;
146
147	/* Return in picoseconds. */
148	return div64_ul(1000000000000ull, rate);
149	}
150
151	static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns)
152	{
153	return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;
154	}
155
156	static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc,
157	unsigned int bank,
158	struct device_node *node)
159	{
160	uint32_t smcr, val, cycles;
161
162	/*
163	* Conversion of tBP and tAW cycle counts to values supported by the
164	* hardware (round up to the next supported value).
165	*/
1a927ad6	166	static const u8 convert_tBP_tAW[] = {
911a8882 AS	167	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
	168
	169	/* 11 - 12 -> 12 cycles */
	170	11, 11,
	171
	172	/* 13 - 15 -> 15 cycles */
	173	12, 12, 12,
	174
	175	/* 16 - 20 -> 20 cycles */
	176	13, 13, 13, 13, 13,
	177
	178	/* 21 - 25 -> 25 cycles */
	179	14, 14, 14, 14, 14,
	180
	181	/* 26 - 31 -> 31 cycles */
	182	15, 15, 15, 15, 15, 15
	183	};
	184
	185	smcr = readl(nemc->base + NEMC_SMCRn(bank));
	186	smcr &= ~NEMC_SMCR_SMT;
	187
	188	if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {
	189	smcr &= ~NEMC_SMCR_BW_MASK;
	190	switch (val) {
	191	case 8:
	192	smcr \|= NEMC_SMCR_BW_8;
	193	break;
	194	default:
	195	/*
	196	* Earlier SoCs support a 16 bit bus width (the 4780
	197	* does not), until those are properly supported, error.
	198	*/
	199	dev_err(nemc->dev, "unsupported bus width: %u\n", val);
	200	return false;
	201	}
	202	}
	203
	204	if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
	205	smcr &= ~NEMC_SMCR_TAS_MASK;
	206	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
a00b0042	207	if (cycles > nemc->soc_info->tas_tah_cycles_max) {
911a8882 AS	208	dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
	209	val, cycles);
	210	return false;
	211	}
	212
	213	smcr \|= cycles << NEMC_SMCR_TAS_SHIFT;
	214	}
	215
	216	if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
	217	smcr &= ~NEMC_SMCR_TAH_MASK;
	218	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
a00b0042	219	if (cycles > nemc->soc_info->tas_tah_cycles_max) {
911a8882 AS	220	dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
	221	val, cycles);
	222	return false;
	223	}
	224
	225	smcr \|= cycles << NEMC_SMCR_TAH_SHIFT;
	226	}
	227
	228	if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {
	229	smcr &= ~NEMC_SMCR_TBP_MASK;
	230	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
	231	if (cycles > 31) {
	232	dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",
	233	val, cycles);
	234	return false;
	235	}
	236
	237	smcr \|= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT;
	238	}
	239
	240	if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {
	241	smcr &= ~NEMC_SMCR_TAW_MASK;
	242	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
	243	if (cycles > 31) {
	244	dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",
	245	val, cycles);
	246	return false;
	247	}
	248
	249	smcr \|= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT;
	250	}
	251
	252	if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {
	253	smcr &= ~NEMC_SMCR_TSTRV_MASK;
	254	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
	255	if (cycles > 63) {
	256	dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",
	257	val, cycles);
	258	return false;
	259	}
	260
	261	smcr \|= cycles << NEMC_SMCR_TSTRV_SHIFT;
	262	}
	263
	264	writel(smcr, nemc->base + NEMC_SMCRn(bank));
	265	return true;
	266	}
	267
	268	static int jz4780_nemc_probe(struct platform_device *pdev)
	269	{
	270	struct device *dev = &pdev->dev;
	271	struct jz4780_nemc *nemc;
	272	struct resource *res;
	273	struct device_node *child;
	274	const __be32 *prop;
	275	unsigned int bank;
	276	unsigned long referenced;
	277	int i, ret;
	278
	279	nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL);
	280	if (!nemc)
	281	return -ENOMEM;
	282
a00b0042 PC	283	nemc->soc_info = device_get_match_data(dev);
	284	if (!nemc->soc_info)
	285	return -EINVAL;
	286
911a8882 AS	287	spin_lock_init(&nemc->lock);
	288	nemc->dev = dev;
	289
	290	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	291	nemc->base = devm_ioremap_resource(dev, res);
	292	if (IS_ERR(nemc->base)) {
	293	dev_err(dev, "failed to get I/O memory\n");
	294	return PTR_ERR(nemc->base);
	295	}
	296
	297	writel(0, nemc->base + NEMC_NFCSR);
	298
	299	nemc->clk = devm_clk_get(dev, NULL);
	300	if (IS_ERR(nemc->clk)) {
	301	dev_err(dev, "failed to get clock\n");
	302	return PTR_ERR(nemc->clk);
	303	}
	304
	305	ret = clk_prepare_enable(nemc->clk);
	306	if (ret) {
	307	dev_err(dev, "failed to enable clock: %d\n", ret);
	308	return ret;
	309	}
	310
	311	nemc->clk_period = jz4780_nemc_clk_period(nemc);
	312	if (!nemc->clk_period) {
	313	dev_err(dev, "failed to calculate clock period\n");
	314	clk_disable_unprepare(nemc->clk);
	315	return -EINVAL;
	316	}
	317
	318	/*
	319	* Iterate over child devices, check that they do not conflict with
	320	* each other, and register child devices for them. If a child device
	321	* has invalid properties, it is ignored and no platform device is
	322	* registered for it.
	323	*/
	324	for_each_child_of_node(nemc->dev->of_node, child) {
	325	referenced = 0;
	326	i = 0;
	327	while ((prop = of_get_address(child, i++, NULL, NULL))) {
	328	bank = of_read_number(prop, 1);
	329	if (bank < 1 \|\| bank >= JZ4780_NEMC_NUM_BANKS) {
	330	dev_err(nemc->dev,
db749d17 RH	331	"%pOF requests invalid bank %u\n",
db749d17 RH	332	child, bank);
911a8882 AS	333
	334	/* Will continue the outer loop below. */
	335	referenced = 0;
	336	break;
	337	}
	338
	339	referenced \|= BIT(bank);
	340	}
	341
	342	if (!referenced) {
db749d17 RH	343	dev_err(nemc->dev, "%pOF has no addresses\n",
db749d17 RH	344	child);
911a8882 AS	345	continue;
911a8882 AS	346	} else if (nemc->banks_present & referenced) {
db749d17 RH	347	dev_err(nemc->dev, "%pOF conflicts with another node\n",
db749d17 RH	348	child);
911a8882 AS	349	continue;
	350	}
	351
	352	/* Configure bank parameters. */
	353	for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {
	354	if (!jz4780_nemc_configure_bank(nemc, bank, child)) {
	355	referenced = 0;
	356	break;
	357	}
	358	}
	359
	360	if (referenced) {
	361	if (of_platform_device_create(child, NULL, nemc->dev))
	362	nemc->banks_present \|= referenced;
	363	}
	364	}
	365
	366	platform_set_drvdata(pdev, nemc);
	367	dev_info(dev, "JZ4780 NEMC initialised\n");
	368	return 0;
	369	}
	370
	371	static int jz4780_nemc_remove(struct platform_device *pdev)
	372	{
	373	struct jz4780_nemc *nemc = platform_get_drvdata(pdev);
	374
	375	clk_disable_unprepare(nemc->clk);
	376	return 0;
	377	}
	378
a00b0042 PC	379	static const struct jz_soc_info jz4740_soc_info = {
	380	.tas_tah_cycles_max = 7,
	381	};
	382
	383	static const struct jz_soc_info jz4780_soc_info = {
	384	.tas_tah_cycles_max = 15,
	385	};
	386
911a8882	387	static const struct of_device_id jz4780_nemc_dt_match[] = {
a00b0042 PC	388	{ .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
a00b0042 PC	389	{ .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
911a8882 AS	390	{},
	391	};
	392
	393	static struct platform_driver jz4780_nemc_driver = {
	394	.probe = jz4780_nemc_probe,
	395	.remove = jz4780_nemc_remove,
	396	.driver = {
	397	.name = "jz4780-nemc",
	398	.of_match_table = of_match_ptr(jz4780_nemc_dt_match),
	399	},
	400	};
	401
	402	static int __init jz4780_nemc_init(void)
	403	{
	404	return platform_driver_register(&jz4780_nemc_driver);
	405	}
	406	subsys_initcall(jz4780_nemc_init);