[linux-block.git] / drivers / memory / jz4780-nemc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * JZ4780 NAND/external memory controller (NEMC)
 *
 * Copyright (c) 2015 Imagination Technologies
 * Author: Alex Smith <alex@alex-smith.me.uk>
 */

#include <linux/clk.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <linux/jz4780-nemc.h>

#define NEMC_SMCRn(n)		(0x14 + (((n) - 1) * 4))
#define NEMC_NFCSR		0x50

#define NEMC_REG_LEN		0x54

#define NEMC_SMCR_SMT		BIT(0)
#define NEMC_SMCR_BW_SHIFT	6
#define NEMC_SMCR_BW_MASK	(0x3 << NEMC_SMCR_BW_SHIFT)
#define NEMC_SMCR_BW_8		(0 << 6)
#define NEMC_SMCR_TAS_SHIFT	8
#define NEMC_SMCR_TAS_MASK	(0xf << NEMC_SMCR_TAS_SHIFT)
#define NEMC_SMCR_TAH_SHIFT	12
#define NEMC_SMCR_TAH_MASK	(0xf << NEMC_SMCR_TAH_SHIFT)
#define NEMC_SMCR_TBP_SHIFT	16
#define NEMC_SMCR_TBP_MASK	(0xf << NEMC_SMCR_TBP_SHIFT)
#define NEMC_SMCR_TAW_SHIFT	20
#define NEMC_SMCR_TAW_MASK	(0xf << NEMC_SMCR_TAW_SHIFT)
#define NEMC_SMCR_TSTRV_SHIFT	24
#define NEMC_SMCR_TSTRV_MASK	(0x3f << NEMC_SMCR_TSTRV_SHIFT)

#define NEMC_NFCSR_NFEn(n)	BIT(((n) - 1) << 1)
#define NEMC_NFCSR_NFCEn(n)	BIT((((n) - 1) << 1) + 1)
#define NEMC_NFCSR_TNFEn(n)	BIT(16 + (n) - 1)

struct jz_soc_info {
	u8 tas_tah_cycles_max;
};

struct jz4780_nemc {
	spinlock_t lock;
	struct device *dev;
	const struct jz_soc_info *soc_info;
	void __iomem *base;
	struct clk *clk;
	uint32_t clk_period;
	unsigned long banks_present;
};

/**
 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
 * @dev: device to count banks for, must be a child of the NEMC.
 *
 * Return: The number of unique NEMC banks referred to by the specified NEMC
 * child device. Unique here means that a device that references the same bank
 * multiple times in its "reg" property will only count once.
 */
unsigned int jz4780_nemc_num_banks(struct device *dev)
{
	const __be32 *prop;
	unsigned int bank, count = 0;
	unsigned long referenced = 0;
	int i = 0;

	while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {
		bank = of_read_number(prop, 1);
		if (!(referenced & BIT(bank))) {
			referenced |= BIT(bank);
			count++;
		}
	}

	return count;
}
EXPORT_SYMBOL(jz4780_nemc_num_banks);

/**
 * jz4780_nemc_set_type() - set the type of device connected to a bank
 * @dev: child device of the NEMC.
 * @bank: bank number to configure.
 * @type: type of device connected to the bank.
 */
void jz4780_nemc_set_type(struct device *dev, unsigned int bank,
			  enum jz4780_nemc_bank_type type)
{
	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
	uint32_t nfcsr;

	nfcsr = readl(nemc->base + NEMC_NFCSR);

	/* TODO: Support toggle NAND devices. */
	switch (type) {
	case JZ4780_NEMC_BANK_SRAM:
		nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank));
		break;
	case JZ4780_NEMC_BANK_NAND:
		nfcsr &= ~NEMC_NFCSR_TNFEn(bank);
		nfcsr |= NEMC_NFCSR_NFEn(bank);
		break;
	}

	writel(nfcsr, nemc->base + NEMC_NFCSR);
}
EXPORT_SYMBOL(jz4780_nemc_set_type);

/**
 * jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
 * @dev: child device of the NEMC.
 * @bank: bank number of device.
 * @assert: whether the chip enable pin should be asserted.
 *
 * (De-)asserts the chip enable pin for the NAND device connected to the
 * specified bank.
 */
void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)
{
	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
	uint32_t nfcsr;

	nfcsr = readl(nemc->base + NEMC_NFCSR);

	if (assert)
		nfcsr |= NEMC_NFCSR_NFCEn(bank);
	else
		nfcsr &= ~NEMC_NFCSR_NFCEn(bank);

	writel(nfcsr, nemc->base + NEMC_NFCSR);
}
EXPORT_SYMBOL(jz4780_nemc_assert);

static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc)
{
	unsigned long rate;

	rate = clk_get_rate(nemc->clk);
	if (!rate)
		return 0;

	/* Return in picoseconds. */
	return div64_ul(1000000000000ull, rate);
}

static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns)
{
	return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;
}

static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc,
				       unsigned int bank,
				       struct device_node *node)
{
	uint32_t smcr, val, cycles;

	/*
	 * Conversion of tBP and tAW cycle counts to values supported by the
	 * hardware (round up to the next supported value).
	 */
	static const u8 convert_tBP_tAW[] = {
		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,

		/* 11 - 12 -> 12 cycles */
		11, 11,

		/* 13 - 15 -> 15 cycles */
		12, 12, 12,

		/* 16 - 20 -> 20 cycles */
		13, 13, 13, 13, 13,

		/* 21 - 25 -> 25 cycles */
		14, 14, 14, 14, 14,

		/* 26 - 31 -> 31 cycles */
		15, 15, 15, 15, 15, 15
	};

	smcr = readl(nemc->base + NEMC_SMCRn(bank));
	smcr &= ~NEMC_SMCR_SMT;

	if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {
		smcr &= ~NEMC_SMCR_BW_MASK;
		switch (val) {
		case 8:
			smcr |= NEMC_SMCR_BW_8;
			break;
		default:
			/*
			 * Earlier SoCs support a 16 bit bus width (the 4780
			 * does not), until those are properly supported, error.
			 */
			dev_err(nemc->dev, "unsupported bus width: %u\n", val);
			return false;
		}
	}

	if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
		smcr &= ~NEMC_SMCR_TAS_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > nemc->soc_info->tas_tah_cycles_max) {
			dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= cycles << NEMC_SMCR_TAS_SHIFT;
	}

	if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
		smcr &= ~NEMC_SMCR_TAH_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > nemc->soc_info->tas_tah_cycles_max) {
			dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= cycles << NEMC_SMCR_TAH_SHIFT;
	}

	if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {
		smcr &= ~NEMC_SMCR_TBP_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > 31) {
			dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT;
	}

	if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {
		smcr &= ~NEMC_SMCR_TAW_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > 31) {
			dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT;
	}

	if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {
		smcr &= ~NEMC_SMCR_TSTRV_MASK;
		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
		if (cycles > 63) {
			dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",
				val, cycles);
			return false;
		}

		smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT;
	}

	writel(smcr, nemc->base + NEMC_SMCRn(bank));
	return true;
}

static int jz4780_nemc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct jz4780_nemc *nemc;
	struct resource *res;
	struct device_node *child;
	const __be32 *prop;
	unsigned int bank;
	unsigned long referenced;
	int i, ret;

	nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL);
	if (!nemc)
		return -ENOMEM;

	nemc->soc_info = device_get_match_data(dev);
	if (!nemc->soc_info)
		return -EINVAL;

	spin_lock_init(&nemc->lock);
	nemc->dev = dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EINVAL;

	/*
	 * The driver currently only uses the registers up to offset
	 * NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
	 * NEMC registers, we only request the registers we will use for now;
	 * that way the EFUSE driver can probe too.
	 */
	if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
		dev_err(dev, "unable to request I/O memory region\n");
		return -EBUSY;
	}

	nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
	if (!nemc->base) {
		dev_err(dev, "failed to get I/O memory\n");
		return -ENOMEM;
	}

	writel(0, nemc->base + NEMC_NFCSR);

	nemc->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(nemc->clk)) {
		dev_err(dev, "failed to get clock\n");
		return PTR_ERR(nemc->clk);
	}

	ret = clk_prepare_enable(nemc->clk);
	if (ret) {
		dev_err(dev, "failed to enable clock: %d\n", ret);
		return ret;
	}

	nemc->clk_period = jz4780_nemc_clk_period(nemc);
	if (!nemc->clk_period) {
		dev_err(dev, "failed to calculate clock period\n");
		clk_disable_unprepare(nemc->clk);
		return -EINVAL;
	}

	/*
	 * Iterate over child devices, check that they do not conflict with
	 * each other, and register child devices for them. If a child device
	 * has invalid properties, it is ignored and no platform device is
	 * registered for it.
	 */
	for_each_child_of_node(nemc->dev->of_node, child) {
		referenced = 0;
		i = 0;
		while ((prop = of_get_address(child, i++, NULL, NULL))) {
			bank = of_read_number(prop, 1);
			if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) {
				dev_err(nemc->dev,
					"%pOF requests invalid bank %u\n",
					child, bank);

				/* Will continue the outer loop below. */
				referenced = 0;
				break;
			}

			referenced |= BIT(bank);
		}

		if (!referenced) {
			dev_err(nemc->dev, "%pOF has no addresses\n",
				child);
			continue;
		} else if (nemc->banks_present & referenced) {
			dev_err(nemc->dev, "%pOF conflicts with another node\n",
				child);
			continue;
		}

		/* Configure bank parameters. */
		for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {
			if (!jz4780_nemc_configure_bank(nemc, bank, child)) {
				referenced = 0;
				break;
			}
		}

		if (referenced) {
			if (of_platform_device_create(child, NULL, nemc->dev))
				nemc->banks_present |= referenced;
		}
	}

	platform_set_drvdata(pdev, nemc);
	dev_info(dev, "JZ4780 NEMC initialised\n");
	return 0;
}

static int jz4780_nemc_remove(struct platform_device *pdev)
{
	struct jz4780_nemc *nemc = platform_get_drvdata(pdev);

	clk_disable_unprepare(nemc->clk);
	return 0;
}

static const struct jz_soc_info jz4740_soc_info = {
	.tas_tah_cycles_max = 7,
};

static const struct jz_soc_info jz4780_soc_info = {
	.tas_tah_cycles_max = 15,
};

static const struct of_device_id jz4780_nemc_dt_match[] = {
	{ .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
	{ .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
	{},
};

static struct platform_driver jz4780_nemc_driver = {
	.probe		= jz4780_nemc_probe,
	.remove		= jz4780_nemc_remove,
	.driver	= {
		.name	= "jz4780-nemc",
		.of_match_table = of_match_ptr(jz4780_nemc_dt_match),
	},
};

static int __init jz4780_nemc_init(void)
{
	return platform_driver_register(&jz4780_nemc_driver);
}
subsys_initcall(jz4780_nemc_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
911a8882 AS	2	/*
	3	* JZ4780 NAND/external memory controller (NEMC)
	4	*
	5	* Copyright (c) 2015 Imagination Technologies
	6	* Author: Alex Smith <alex@alex-smith.me.uk>
911a8882 AS	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/init.h>
f046e4a3	11	#include <linux/io.h>
911a8882 AS	12	#include <linux/math64.h>
	13	#include <linux/of.h>
	14	#include <linux/of_address.h>
	15	#include <linux/of_device.h>
	16	#include <linux/of_platform.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/slab.h>
	19	#include <linux/spinlock.h>
	20
	21	#include <linux/jz4780-nemc.h>
	22
	23	#define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
	24	#define NEMC_NFCSR 0x50
	25
f046e4a3 PC	26	#define NEMC_REG_LEN 0x54
f046e4a3 PC	27
911a8882 AS	28	#define NEMC_SMCR_SMT BIT(0)
	29	#define NEMC_SMCR_BW_SHIFT 6
	30	#define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT)
	31	#define NEMC_SMCR_BW_8 (0 << 6)
	32	#define NEMC_SMCR_TAS_SHIFT 8
	33	#define NEMC_SMCR_TAS_MASK (0xf << NEMC_SMCR_TAS_SHIFT)
	34	#define NEMC_SMCR_TAH_SHIFT 12
	35	#define NEMC_SMCR_TAH_MASK (0xf << NEMC_SMCR_TAH_SHIFT)
	36	#define NEMC_SMCR_TBP_SHIFT 16
	37	#define NEMC_SMCR_TBP_MASK (0xf << NEMC_SMCR_TBP_SHIFT)
	38	#define NEMC_SMCR_TAW_SHIFT 20
	39	#define NEMC_SMCR_TAW_MASK (0xf << NEMC_SMCR_TAW_SHIFT)
	40	#define NEMC_SMCR_TSTRV_SHIFT 24
	41	#define NEMC_SMCR_TSTRV_MASK (0x3f << NEMC_SMCR_TSTRV_SHIFT)
	42
	43	#define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
	44	#define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
	45	#define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
	46
a00b0042 PC	47	struct jz_soc_info {
	48	u8 tas_tah_cycles_max;
	49	};
	50
911a8882 AS	51	struct jz4780_nemc {
	52	spinlock_t lock;
	53	struct device *dev;
a00b0042	54	const struct jz_soc_info *soc_info;
911a8882 AS	55	void __iomem *base;
	56	struct clk *clk;
	57	uint32_t clk_period;
	58	unsigned long banks_present;
	59	};
	60
	61	/**
	62	* jz4780_nemc_num_banks() - count the number of banks referenced by a device
	63	* @dev: device to count banks for, must be a child of the NEMC.
	64	*
	65	* Return: The number of unique NEMC banks referred to by the specified NEMC
	66	* child device. Unique here means that a device that references the same bank
d171df6b	67	* multiple times in its "reg" property will only count once.
911a8882 AS	68	*/
	69	unsigned int jz4780_nemc_num_banks(struct device *dev)
	70	{
	71	const __be32 *prop;
	72	unsigned int bank, count = 0;
	73	unsigned long referenced = 0;
	74	int i = 0;
	75
	76	while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {
	77	bank = of_read_number(prop, 1);
	78	if (!(referenced & BIT(bank))) {
	79	referenced \|= BIT(bank);
	80	count++;
	81	}
	82	}
	83
	84	return count;
	85	}
	86	EXPORT_SYMBOL(jz4780_nemc_num_banks);
	87
	88	/**
	89	* jz4780_nemc_set_type() - set the type of device connected to a bank
	90	* @dev: child device of the NEMC.
	91	* @bank: bank number to configure.
	92	* @type: type of device connected to the bank.
	93	*/
	94	void jz4780_nemc_set_type(struct device *dev, unsigned int bank,
	95	enum jz4780_nemc_bank_type type)
	96	{
	97	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
	98	uint32_t nfcsr;
	99
	100	nfcsr = readl(nemc->base + NEMC_NFCSR);
	101
	102	/* TODO: Support toggle NAND devices. */
	103	switch (type) {
	104	case JZ4780_NEMC_BANK_SRAM:
	105	nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) \| NEMC_NFCSR_NFEn(bank));
	106	break;
	107	case JZ4780_NEMC_BANK_NAND:
	108	nfcsr &= ~NEMC_NFCSR_TNFEn(bank);
	109	nfcsr \|= NEMC_NFCSR_NFEn(bank);
	110	break;
	111	}
	112
	113	writel(nfcsr, nemc->base + NEMC_NFCSR);
	114	}
	115	EXPORT_SYMBOL(jz4780_nemc_set_type);
	116
	117	/**
	118	* jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
	119	* @dev: child device of the NEMC.
	120	* @bank: bank number of device.
	121	* @assert: whether the chip enable pin should be asserted.
	122	*
	123	* (De-)asserts the chip enable pin for the NAND device connected to the
	124	* specified bank.
	125	*/
	126	void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)
	127	{
	128	struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
	129	uint32_t nfcsr;
	130
	131	nfcsr = readl(nemc->base + NEMC_NFCSR);
132
133	if (assert)
134	nfcsr \|= NEMC_NFCSR_NFCEn(bank);
135	else
136	nfcsr &= ~NEMC_NFCSR_NFCEn(bank);
137
138	writel(nfcsr, nemc->base + NEMC_NFCSR);
139	}
140	EXPORT_SYMBOL(jz4780_nemc_assert);
141
142	static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc)
143	{
144	unsigned long rate;
145
146	rate = clk_get_rate(nemc->clk);
147	if (!rate)
148	return 0;
149
150	/* Return in picoseconds. */
151	return div64_ul(1000000000000ull, rate);
152	}
153
154	static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns)
155	{
156	return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;
157	}
158
159	static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc,
160	unsigned int bank,
161	struct device_node *node)
162	{
163	uint32_t smcr, val, cycles;
164
165	/*
166	* Conversion of tBP and tAW cycle counts to values supported by the
167	* hardware (round up to the next supported value).
168	*/
1a927ad6	169	static const u8 convert_tBP_tAW[] = {
911a8882 AS	170	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
	171
	172	/* 11 - 12 -> 12 cycles */
	173	11, 11,
	174
	175	/* 13 - 15 -> 15 cycles */
	176	12, 12, 12,
	177
	178	/* 16 - 20 -> 20 cycles */
	179	13, 13, 13, 13, 13,
	180
	181	/* 21 - 25 -> 25 cycles */
	182	14, 14, 14, 14, 14,
	183
	184	/* 26 - 31 -> 31 cycles */
	185	15, 15, 15, 15, 15, 15
	186	};
	187
	188	smcr = readl(nemc->base + NEMC_SMCRn(bank));
	189	smcr &= ~NEMC_SMCR_SMT;
	190
	191	if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {
	192	smcr &= ~NEMC_SMCR_BW_MASK;
	193	switch (val) {
	194	case 8:
	195	smcr \|= NEMC_SMCR_BW_8;
	196	break;
	197	default:
	198	/*
	199	* Earlier SoCs support a 16 bit bus width (the 4780
	200	* does not), until those are properly supported, error.
	201	*/
	202	dev_err(nemc->dev, "unsupported bus width: %u\n", val);
	203	return false;
	204	}
	205	}
	206
	207	if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
	208	smcr &= ~NEMC_SMCR_TAS_MASK;
	209	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
a00b0042	210	if (cycles > nemc->soc_info->tas_tah_cycles_max) {
911a8882 AS	211	dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
	212	val, cycles);
	213	return false;
	214	}
	215
	216	smcr \|= cycles << NEMC_SMCR_TAS_SHIFT;
	217	}
	218
	219	if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
	220	smcr &= ~NEMC_SMCR_TAH_MASK;
	221	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
a00b0042	222	if (cycles > nemc->soc_info->tas_tah_cycles_max) {
911a8882 AS	223	dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
	224	val, cycles);
	225	return false;
	226	}
	227
	228	smcr \|= cycles << NEMC_SMCR_TAH_SHIFT;
	229	}
	230
	231	if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {
	232	smcr &= ~NEMC_SMCR_TBP_MASK;
	233	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
	234	if (cycles > 31) {
	235	dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",
	236	val, cycles);
	237	return false;
	238	}
	239
	240	smcr \|= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT;
	241	}
	242
	243	if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {
	244	smcr &= ~NEMC_SMCR_TAW_MASK;
	245	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
	246	if (cycles > 31) {
	247	dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",
	248	val, cycles);
	249	return false;
	250	}
	251
	252	smcr \|= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT;
	253	}
	254
	255	if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {
	256	smcr &= ~NEMC_SMCR_TSTRV_MASK;
	257	cycles = jz4780_nemc_ns_to_cycles(nemc, val);
	258	if (cycles > 63) {
	259	dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",
	260	val, cycles);
	261	return false;
	262	}
	263
	264	smcr \|= cycles << NEMC_SMCR_TSTRV_SHIFT;
	265	}
	266
	267	writel(smcr, nemc->base + NEMC_SMCRn(bank));
	268	return true;
	269	}
	270
	271	static int jz4780_nemc_probe(struct platform_device *pdev)
	272	{
	273	struct device *dev = &pdev->dev;
	274	struct jz4780_nemc *nemc;
	275	struct resource *res;
	276	struct device_node *child;
	277	const __be32 *prop;
	278	unsigned int bank;
	279	unsigned long referenced;
	280	int i, ret;
	281
	282	nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL);
	283	if (!nemc)
	284	return -ENOMEM;
	285
a00b0042 PC	286	nemc->soc_info = device_get_match_data(dev);
	287	if (!nemc->soc_info)
	288	return -EINVAL;
	289
911a8882 AS	290	spin_lock_init(&nemc->lock);
	291	nemc->dev = dev;
	292
	293	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4bfa0730 ZC	294	if (!res)
4bfa0730 ZC	295	return -EINVAL;
f046e4a3 PC	296
	297	/*
	298	* The driver currently only uses the registers up to offset
	299	* NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
	300	* NEMC registers, we only request the registers we will use for now;
	301	* that way the EFUSE driver can probe too.
	302	*/
	303	if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
	304	dev_err(dev, "unable to request I/O memory region\n");
	305	return -EBUSY;
	306	}
	307
	308	nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
96999c79	309	if (!nemc->base) {
911a8882	310	dev_err(dev, "failed to get I/O memory\n");
96999c79	311	return -ENOMEM;
911a8882 AS	312	}
	313
	314	writel(0, nemc->base + NEMC_NFCSR);
	315
	316	nemc->clk = devm_clk_get(dev, NULL);
	317	if (IS_ERR(nemc->clk)) {
	318	dev_err(dev, "failed to get clock\n");
	319	return PTR_ERR(nemc->clk);
	320	}
	321
	322	ret = clk_prepare_enable(nemc->clk);
	323	if (ret) {
	324	dev_err(dev, "failed to enable clock: %d\n", ret);
	325	return ret;
	326	}
	327
	328	nemc->clk_period = jz4780_nemc_clk_period(nemc);
	329	if (!nemc->clk_period) {
	330	dev_err(dev, "failed to calculate clock period\n");
	331	clk_disable_unprepare(nemc->clk);
	332	return -EINVAL;
	333	}
	334
	335	/*
	336	* Iterate over child devices, check that they do not conflict with
	337	* each other, and register child devices for them. If a child device
	338	* has invalid properties, it is ignored and no platform device is
	339	* registered for it.
	340	*/
	341	for_each_child_of_node(nemc->dev->of_node, child) {
	342	referenced = 0;
	343	i = 0;
	344	while ((prop = of_get_address(child, i++, NULL, NULL))) {
	345	bank = of_read_number(prop, 1);
	346	if (bank < 1 \|\| bank >= JZ4780_NEMC_NUM_BANKS) {
	347	dev_err(nemc->dev,
db749d17 RH	348	"%pOF requests invalid bank %u\n",
db749d17 RH	349	child, bank);
911a8882 AS	350
	351	/* Will continue the outer loop below. */
	352	referenced = 0;
	353	break;
	354	}
	355
	356	referenced \|= BIT(bank);
	357	}
	358
	359	if (!referenced) {
db749d17 RH	360	dev_err(nemc->dev, "%pOF has no addresses\n",
db749d17 RH	361	child);
911a8882 AS	362	continue;
911a8882 AS	363	} else if (nemc->banks_present & referenced) {
db749d17 RH	364	dev_err(nemc->dev, "%pOF conflicts with another node\n",
db749d17 RH	365	child);
911a8882 AS	366	continue;
	367	}
	368
	369	/* Configure bank parameters. */
	370	for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {
	371	if (!jz4780_nemc_configure_bank(nemc, bank, child)) {
	372	referenced = 0;
	373	break;
	374	}
	375	}
	376
	377	if (referenced) {
	378	if (of_platform_device_create(child, NULL, nemc->dev))
	379	nemc->banks_present \|= referenced;
	380	}
	381	}
	382
	383	platform_set_drvdata(pdev, nemc);
	384	dev_info(dev, "JZ4780 NEMC initialised\n");
	385	return 0;
	386	}
	387
	388	static int jz4780_nemc_remove(struct platform_device *pdev)
	389	{
	390	struct jz4780_nemc *nemc = platform_get_drvdata(pdev);
	391
	392	clk_disable_unprepare(nemc->clk);
	393	return 0;
	394	}
	395
a00b0042 PC	396	static const struct jz_soc_info jz4740_soc_info = {
	397	.tas_tah_cycles_max = 7,
	398	};
	399
	400	static const struct jz_soc_info jz4780_soc_info = {
	401	.tas_tah_cycles_max = 15,
	402	};
	403
911a8882	404	static const struct of_device_id jz4780_nemc_dt_match[] = {
a00b0042 PC	405	{ .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
a00b0042 PC	406	{ .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
911a8882 AS	407	{},
	408	};
	409
	410	static struct platform_driver jz4780_nemc_driver = {
	411	.probe = jz4780_nemc_probe,
	412	.remove = jz4780_nemc_remove,
	413	.driver = {
	414	.name = "jz4780-nemc",
	415	.of_match_table = of_match_ptr(jz4780_nemc_dt_match),
	416	},
	417	};
	418
	419	static int __init jz4780_nemc_init(void)
	420	{
	421	return platform_driver_register(&jz4780_nemc_driver);
	422	}
	423	subsys_initcall(jz4780_nemc_init);