[linux-2.6-block.git] / drivers / memory / fsl_ifc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2011 Freescale Semiconductor, Inc
 *
 * Freescale Integrated Flash Controller
 *
 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/fsl_ifc.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
EXPORT_SYMBOL(fsl_ifc_ctrl_dev);

/*
 * convert_ifc_address - convert the base address
 * @addr_base:	base address of the memory bank
 */
unsigned int convert_ifc_address(phys_addr_t addr_base)
{
	return addr_base & CSPR_BA;
}
EXPORT_SYMBOL(convert_ifc_address);

/*
 * fsl_ifc_find - find IFC bank
 * @addr_base:	base address of the memory bank
 *
 * This function walks IFC banks comparing "Base address" field of the CSPR
 * registers with the supplied addr_base argument. When bases match this
 * function returns bank number (starting with 0), otherwise it returns
 * appropriate errno value.
 */
int fsl_ifc_find(phys_addr_t addr_base)
{
	int i = 0;

	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
		return -ENODEV;

	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
		u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
				convert_ifc_address(addr_base))
			return i;
	}

	return -ENOENT;
}
EXPORT_SYMBOL(fsl_ifc_find);

static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
{
	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;

	/*
	 * Clear all the common status and event registers
	 */
	if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);

	/* enable all error and events */
	ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);

	/* enable all error and event interrupts */
	ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
	ifc_out32(0x0, &ifc->cm_erattr0);
	ifc_out32(0x0, &ifc->cm_erattr1);

	return 0;
}

static int fsl_ifc_ctrl_remove(struct platform_device *dev)
{
	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);

	free_irq(ctrl->nand_irq, ctrl);
	free_irq(ctrl->irq, ctrl);

	irq_dispose_mapping(ctrl->nand_irq);
	irq_dispose_mapping(ctrl->irq);

	iounmap(ctrl->gregs);

	dev_set_drvdata(&dev->dev, NULL);
	kfree(ctrl);

	return 0;
}

/*
 * NAND events are split between an operational interrupt which only
 * receives OPC, and an error interrupt that receives everything else,
 * including non-NAND errors.  Whichever interrupt gets to it first
 * records the status and wakes the wait queue.
 */
static DEFINE_SPINLOCK(nand_irq_lock);

static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
{
	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
	unsigned long flags;
	u32 stat;

	spin_lock_irqsave(&nand_irq_lock, flags);

	stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
	if (stat) {
		ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
		ctrl->nand_stat = stat;
		wake_up(&ctrl->nand_wait);
	}

	spin_unlock_irqrestore(&nand_irq_lock, flags);

	return stat;
}

static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
{
	struct fsl_ifc_ctrl *ctrl = data;

	if (check_nand_stat(ctrl))
		return IRQ_HANDLED;

	return IRQ_NONE;
}

/*
 * NOTE: This interrupt is used to report ifc events of various kinds,
 * such as transaction errors on the chipselects.
 */
static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
{
	struct fsl_ifc_ctrl *ctrl = data;
	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
	u32 err_axiid, err_srcid, status, cs_err, err_addr;
	irqreturn_t ret = IRQ_NONE;

	/* read for chip select error */
	cs_err = ifc_in32(&ifc->cm_evter_stat);
	if (cs_err) {
		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
				"any memory bank 0x%08X\n", cs_err);
		/* clear the chip select error */
		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);

		/* read error attribute registers print the error information */
		status = ifc_in32(&ifc->cm_erattr0);
		err_addr = ifc_in32(&ifc->cm_erattr1);

		if (status & IFC_CM_ERATTR0_ERTYP_READ)
			dev_err(ctrl->dev, "Read transaction error"
				"CM_ERATTR0 0x%08X\n", status);
		else
			dev_err(ctrl->dev, "Write transaction error"
				"CM_ERATTR0 0x%08X\n", status);

		err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
					IFC_CM_ERATTR0_ERAID_SHIFT;
		dev_err(ctrl->dev, "AXI ID of the error"
					"transaction 0x%08X\n", err_axiid);

		err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
					IFC_CM_ERATTR0_ESRCID_SHIFT;
		dev_err(ctrl->dev, "SRC ID of the error"
					"transaction 0x%08X\n", err_srcid);

		dev_err(ctrl->dev, "Transaction Address corresponding to error"
					"ERADDR 0x%08X\n", err_addr);

		ret = IRQ_HANDLED;
	}

	if (check_nand_stat(ctrl))
		ret = IRQ_HANDLED;

	return ret;
}

/*
 * fsl_ifc_ctrl_probe
 *
 * called by device layer when it finds a device matching
 * one our driver can handled. This code allocates all of
 * the resources needed for the controller only.  The
 * resources for the NAND banks themselves are allocated
 * in the chip probe function.
*/
static int fsl_ifc_ctrl_probe(struct platform_device *dev)
{
	int ret = 0;
	int version, banks;
	void __iomem *addr;

	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");

	fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
	if (!fsl_ifc_ctrl_dev)
		return -ENOMEM;

	dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);

	/* IOMAP the entire IFC region */
	fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
	if (!fsl_ifc_ctrl_dev->gregs) {
		dev_err(&dev->dev, "failed to get memory region\n");
		ret = -ENODEV;
		goto err;
	}

	if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
		fsl_ifc_ctrl_dev->little_endian = true;
		dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
	} else {
		fsl_ifc_ctrl_dev->little_endian = false;
		dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
	}

	version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
			FSL_IFC_VERSION_MASK;

	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
		version >> 24, (version >> 16) & 0xf, banks);

	fsl_ifc_ctrl_dev->version = version;
	fsl_ifc_ctrl_dev->banks = banks;

	addr = fsl_ifc_ctrl_dev->gregs;
	if (version >= FSL_IFC_VERSION_2_0_0)
		addr += PGOFFSET_64K;
	else
		addr += PGOFFSET_4K;
	fsl_ifc_ctrl_dev->rregs = addr;

	/* get the Controller level irq */
	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
	if (fsl_ifc_ctrl_dev->irq == 0) {
		dev_err(&dev->dev, "failed to get irq resource "
							"for IFC\n");
		ret = -ENODEV;
		goto err;
	}

	/* get the nand machine irq */
	fsl_ifc_ctrl_dev->nand_irq =
			irq_of_parse_and_map(dev->dev.of_node, 1);

	fsl_ifc_ctrl_dev->dev = &dev->dev;

	ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
	if (ret < 0)
		goto err;

	init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);

	ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
			  "fsl-ifc", fsl_ifc_ctrl_dev);
	if (ret != 0) {
		dev_err(&dev->dev, "failed to install irq (%d)\n",
			fsl_ifc_ctrl_dev->irq);
		goto err_irq;
	}

	if (fsl_ifc_ctrl_dev->nand_irq) {
		ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
				0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
		if (ret != 0) {
			dev_err(&dev->dev, "failed to install irq (%d)\n",
				fsl_ifc_ctrl_dev->nand_irq);
			goto err_nandirq;
		}
	}

	return 0;

err_nandirq:
	free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
	irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
err_irq:
	free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
	irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
err:
	return ret;
}

static const struct of_device_id fsl_ifc_match[] = {
	{
		.compatible = "fsl,ifc",
	},
	{},
};

static struct platform_driver fsl_ifc_ctrl_driver = {
	.driver = {
		.name	= "fsl-ifc",
		.of_match_table = fsl_ifc_match,
	},
	.probe       = fsl_ifc_ctrl_probe,
	.remove      = fsl_ifc_ctrl_remove,
};

static int __init fsl_ifc_init(void)
{
	return platform_driver_register(&fsl_ifc_ctrl_driver);
}
subsys_initcall(fsl_ifc_init);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Freescale Semiconductor");
MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
Commit	Line	Data
74ba9207	1	// SPDX-License-Identifier: GPL-2.0-or-later
a20cbdef PK	2	/*
	3	* Copyright 2011 Freescale Semiconductor, Inc
	4	*
	5	* Freescale Integrated Flash Controller
	6	*
	7	* Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
a20cbdef	8	*/
a20cbdef PK	9	#include <linux/module.h>
	10	#include <linux/kernel.h>
	11	#include <linux/compiler.h>
c4aa1937	12	#include <linux/sched.h>
a20cbdef PK	13	#include <linux/spinlock.h>
	14	#include <linux/types.h>
	15	#include <linux/slab.h>
	16	#include <linux/io.h>
	17	#include <linux/of.h>
	18	#include <linux/of_device.h>
	19	#include <linux/platform_device.h>
d2ae2e20	20	#include <linux/fsl_ifc.h>
8ea126bc RD	21	#include <linux/irqdomain.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
a20cbdef PK	24
	25	struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
	26	EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
	27
	28	/*
	29	* convert_ifc_address - convert the base address
	30	* @addr_base: base address of the memory bank
	31	*/
	32	unsigned int convert_ifc_address(phys_addr_t addr_base)
	33	{
	34	return addr_base & CSPR_BA;
	35	}
	36	EXPORT_SYMBOL(convert_ifc_address);
	37
	38	/*
	39	* fsl_ifc_find - find IFC bank
	40	* @addr_base: base address of the memory bank
	41	*
	42	* This function walks IFC banks comparing "Base address" field of the CSPR
	43	* registers with the supplied addr_base argument. When bases match this
	44	* function returns bank number (starting with 0), otherwise it returns
	45	* appropriate errno value.
	46	*/
	47	int fsl_ifc_find(phys_addr_t addr_base)
	48	{
	49	int i = 0;
	50
7a654172	51	if (!fsl_ifc_ctrl_dev \|\| !fsl_ifc_ctrl_dev->gregs)
a20cbdef PK	52	return -ENODEV;
a20cbdef PK	53
09691661	54	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
7a654172	55	u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
a20cbdef PK	56	if (cspr & CSPR_V && (cspr & CSPR_BA) ==
	57	convert_ifc_address(addr_base))
	58	return i;
	59	}
	60
	61	return -ENOENT;
	62	}
	63	EXPORT_SYMBOL(fsl_ifc_find);
	64
cad5cef6	65	static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
a20cbdef	66	{
7a654172	67	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
a20cbdef PK	68
	69	/*
	70	* Clear all the common status and event registers
	71	*/
cf184dc2 JS	72	if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
cf184dc2 JS	73	ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
a20cbdef PK	74
a20cbdef PK	75	/* enable all error and events */
cf184dc2	76	ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
a20cbdef PK	77
a20cbdef PK	78	/* enable all error and event interrupts */
cf184dc2 JS	79	ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
	80	ifc_out32(0x0, &ifc->cm_erattr0);
	81	ifc_out32(0x0, &ifc->cm_erattr1);
a20cbdef PK	82
	83	return 0;
	84	}
	85
	86	static int fsl_ifc_ctrl_remove(struct platform_device *dev)
	87	{
	88	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
	89
	90	free_irq(ctrl->nand_irq, ctrl);
	91	free_irq(ctrl->irq, ctrl);
	92
	93	irq_dispose_mapping(ctrl->nand_irq);
	94	irq_dispose_mapping(ctrl->irq);
	95
7a654172	96	iounmap(ctrl->gregs);
a20cbdef PK	97
	98	dev_set_drvdata(&dev->dev, NULL);
	99	kfree(ctrl);
	100
	101	return 0;
	102	}
	103
	104	/*
	105	* NAND events are split between an operational interrupt which only
	106	* receives OPC, and an error interrupt that receives everything else,
	107	* including non-NAND errors. Whichever interrupt gets to it first
	108	* records the status and wakes the wait queue.
	109	*/
	110	static DEFINE_SPINLOCK(nand_irq_lock);
	111
	112	static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
	113	{
7a654172	114	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
a20cbdef PK	115	unsigned long flags;
	116	u32 stat;
	117
	118	spin_lock_irqsave(&nand_irq_lock, flags);
	119
cf184dc2	120	stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
a20cbdef	121	if (stat) {
cf184dc2	122	ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
a20cbdef PK	123	ctrl->nand_stat = stat;
	124	wake_up(&ctrl->nand_wait);
	125	}
	126
	127	spin_unlock_irqrestore(&nand_irq_lock, flags);
	128
	129	return stat;
	130	}
	131
	132	static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
	133	{
	134	struct fsl_ifc_ctrl *ctrl = data;
	135
	136	if (check_nand_stat(ctrl))
	137	return IRQ_HANDLED;
	138
	139	return IRQ_NONE;
	140	}
	141
	142	/*
	143	* NOTE: This interrupt is used to report ifc events of various kinds,
	144	* such as transaction errors on the chipselects.
	145	*/
	146	static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
	147	{
	148	struct fsl_ifc_ctrl *ctrl = data;
7a654172	149	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
a20cbdef PK	150	u32 err_axiid, err_srcid, status, cs_err, err_addr;
	151	irqreturn_t ret = IRQ_NONE;
	152
	153	/* read for chip select error */
cf184dc2	154	cs_err = ifc_in32(&ifc->cm_evter_stat);
a20cbdef PK	155	if (cs_err) {
	156	dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
	157	"any memory bank 0x%08X\n", cs_err);
	158	/* clear the chip select error */
cf184dc2	159	ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
a20cbdef PK	160
a20cbdef PK	161	/* read error attribute registers print the error information */
cf184dc2 JS	162	status = ifc_in32(&ifc->cm_erattr0);
cf184dc2 JS	163	err_addr = ifc_in32(&ifc->cm_erattr1);
a20cbdef PK	164
	165	if (status & IFC_CM_ERATTR0_ERTYP_READ)
	166	dev_err(ctrl->dev, "Read transaction error"
	167	"CM_ERATTR0 0x%08X\n", status);
	168	else
	169	dev_err(ctrl->dev, "Write transaction error"
	170	"CM_ERATTR0 0x%08X\n", status);
	171
	172	err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
	173	IFC_CM_ERATTR0_ERAID_SHIFT;
	174	dev_err(ctrl->dev, "AXI ID of the error"
	175	"transaction 0x%08X\n", err_axiid);
	176
	177	err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
	178	IFC_CM_ERATTR0_ESRCID_SHIFT;
	179	dev_err(ctrl->dev, "SRC ID of the error"
	180	"transaction 0x%08X\n", err_srcid);
	181
	182	dev_err(ctrl->dev, "Transaction Address corresponding to error"
	183	"ERADDR 0x%08X\n", err_addr);
	184
	185	ret = IRQ_HANDLED;
	186	}
	187
	188	if (check_nand_stat(ctrl))
	189	ret = IRQ_HANDLED;
	190
	191	return ret;
	192	}
	193
	194	/*
	195	* fsl_ifc_ctrl_probe
	196	*
	197	* called by device layer when it finds a device matching
	198	* one our driver can handled. This code allocates all of
	199	* the resources needed for the controller only. The
	200	* resources for the NAND banks themselves are allocated
	201	* in the chip probe function.
	202	*/
cad5cef6	203	static int fsl_ifc_ctrl_probe(struct platform_device *dev)
a20cbdef PK	204	{
a20cbdef PK	205	int ret = 0;
09691661	206	int version, banks;
7a654172	207	void __iomem *addr;
a20cbdef PK	208
	209	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
	210
	211	fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
	212	if (!fsl_ifc_ctrl_dev)
	213	return -ENOMEM;
	214
	215	dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
	216
	217	/* IOMAP the entire IFC region */
7a654172 RD	218	fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
7a654172 RD	219	if (!fsl_ifc_ctrl_dev->gregs) {
a20cbdef PK	220	dev_err(&dev->dev, "failed to get memory region\n");
	221	ret = -ENODEV;
	222	goto err;
	223	}
	224
cf184dc2 JS	225	if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
	226	fsl_ifc_ctrl_dev->little_endian = true;
	227	dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
	228	} else {
	229	fsl_ifc_ctrl_dev->little_endian = false;
	230	dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
	231	}
	232
7a654172	233	version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
09691661	234	FSL_IFC_VERSION_MASK;
7a654172	235
09691661 AS	236	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
	237	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
	238	version >> 24, (version >> 16) & 0xf, banks);
	239
	240	fsl_ifc_ctrl_dev->version = version;
	241	fsl_ifc_ctrl_dev->banks = banks;
	242
7a654172 RD	243	addr = fsl_ifc_ctrl_dev->gregs;
	244	if (version >= FSL_IFC_VERSION_2_0_0)
	245	addr += PGOFFSET_64K;
	246	else
	247	addr += PGOFFSET_4K;
	248	fsl_ifc_ctrl_dev->rregs = addr;
	249
a20cbdef PK	250	/* get the Controller level irq */
a20cbdef PK	251	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
ed4eeba7	252	if (fsl_ifc_ctrl_dev->irq == 0) {
a20cbdef PK	253	dev_err(&dev->dev, "failed to get irq resource "
	254	"for IFC\n");
	255	ret = -ENODEV;
	256	goto err;
	257	}
	258
	259	/* get the nand machine irq */
	260	fsl_ifc_ctrl_dev->nand_irq =
	261	irq_of_parse_and_map(dev->dev.of_node, 1);
a20cbdef PK	262
	263	fsl_ifc_ctrl_dev->dev = &dev->dev;
	264
	265	ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
	266	if (ret < 0)
	267	goto err;
	268
	269	init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
	270
	271	ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
	272	"fsl-ifc", fsl_ifc_ctrl_dev);
	273	if (ret != 0) {
	274	dev_err(&dev->dev, "failed to install irq (%d)\n",
	275	fsl_ifc_ctrl_dev->irq);
	276	goto err_irq;
	277	}
	278
721c0705 PK	279	if (fsl_ifc_ctrl_dev->nand_irq) {
	280	ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
	281	0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
	282	if (ret != 0) {
	283	dev_err(&dev->dev, "failed to install irq (%d)\n",
	284	fsl_ifc_ctrl_dev->nand_irq);
	285	goto err_nandirq;
	286	}
a20cbdef PK	287	}
	288
	289	return 0;
	290
	291	err_nandirq:
	292	free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
	293	irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
	294	err_irq:
	295	free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
	296	irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
	297	err:
	298	return ret;
	299	}
	300
	301	static const struct of_device_id fsl_ifc_match[] = {
	302	{
	303	.compatible = "fsl,ifc",
	304	},
	305	{},
	306	};
	307
	308	static struct platform_driver fsl_ifc_ctrl_driver = {
	309	.driver = {
	310	.name = "fsl-ifc",
	311	.of_match_table = fsl_ifc_match,
	312	},
	313	.probe = fsl_ifc_ctrl_probe,
	314	.remove = fsl_ifc_ctrl_remove,
	315	};
	316
d2ae2e20 PK	317	static int __init fsl_ifc_init(void)
	318	{
	319	return platform_driver_register(&fsl_ifc_ctrl_driver);
	320	}
	321	subsys_initcall(fsl_ifc_init);
a20cbdef PK	322
	323	MODULE_LICENSE("GPL");
	324	MODULE_AUTHOR("Freescale Semiconductor");
	325	MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");