projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 6c8b0906 A |
1 | /* |
| 2 | * Defines for the EMIF driver | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Texas Instruments, Inc. | |
| 5 | * | |
| 6 | * Benoit Cousson (b-cousson@ti.com) | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | #ifndef __EMIF_H | |
| 13 | #define __EMIF_H | |
| 14 | ||
| 15 | /* Registers offset */ | |
| 16 | #define EMIF_MODULE_ID_AND_REVISION 0x0000 | |
| 17 | #define EMIF_STATUS 0x0004 | |
| 18 | #define EMIF_SDRAM_CONFIG 0x0008 | |
| 19 | #define EMIF_SDRAM_CONFIG_2 0x000c | |
| 20 | #define EMIF_SDRAM_REFRESH_CONTROL 0x0010 | |
| 21 | #define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014 | |
| 22 | #define EMIF_SDRAM_TIMING_1 0x0018 | |
| 23 | #define EMIF_SDRAM_TIMING_1_SHDW 0x001c | |
| 24 | #define EMIF_SDRAM_TIMING_2 0x0020 | |
| 25 | #define EMIF_SDRAM_TIMING_2_SHDW 0x0024 | |
| 26 | #define EMIF_SDRAM_TIMING_3 0x0028 | |
| 27 | #define EMIF_SDRAM_TIMING_3_SHDW 0x002c | |
| 28 | #define EMIF_LPDDR2_NVM_TIMING 0x0030 | |
| 29 | #define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034 | |
| 30 | #define EMIF_POWER_MANAGEMENT_CONTROL 0x0038 | |
| 31 | #define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c | |
| 32 | #define EMIF_LPDDR2_MODE_REG_DATA 0x0040 | |
| 33 | #define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050 | |
| 34 | #define EMIF_OCP_CONFIG 0x0054 | |
| 35 | #define EMIF_OCP_CONFIG_VALUE_1 0x0058 | |
| 36 | #define EMIF_OCP_CONFIG_VALUE_2 0x005c | |
| 37 | #define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060 | |
| 38 | #define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064 | |
| 39 | #define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068 | |
| 40 | #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c | |
| 41 | #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070 | |
| 42 | #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074 | |
| 43 | #define EMIF_PERFORMANCE_COUNTER_1 0x0080 | |
| 44 | #define EMIF_PERFORMANCE_COUNTER_2 0x0084 | |
| 45 | #define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088 | |
| 46 | #define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c | |
| 47 | #define EMIF_PERFORMANCE_COUNTER_TIME 0x0090 | |
| 48 | #define EMIF_MISC_REG 0x0094 | |
| 49 | #define EMIF_DLL_CALIB_CTRL 0x0098 | |
| 50 | #define EMIF_DLL_CALIB_CTRL_SHDW 0x009c | |
| 51 | #define EMIF_END_OF_INTERRUPT 0x00a0 | |
| 52 | #define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4 | |
| 53 | #define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8 | |
| 54 | #define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac | |
| 55 | #define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0 | |
| 56 | #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4 | |
| 57 | #define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8 | |
| 58 | #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc | |
| 59 | #define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0 | |
| 60 | #define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8 | |
| 61 | #define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc | |
| 62 | #define EMIF_OCP_ERROR_LOG 0x00d0 | |
| 63 | #define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4 | |
| 64 | #define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8 | |
| 65 | #define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc | |
| 66 | #define EMIF_DDR_PHY_CTRL_1 0x00e4 | |
| 67 | #define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8 | |
| 68 | #define EMIF_DDR_PHY_CTRL_2 0x00ec | |
| 69 | #define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100 | |
| 70 | #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104 | |
| 71 | #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108 | |
| 72 | #define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120 | |
| 73 | #define EMIF_COS_CONFIG 0x0124 | |
| 74 | #define EMIF_PHY_STATUS_1 0x0140 | |
| 75 | #define EMIF_PHY_STATUS_2 0x0144 | |
| 76 | #define EMIF_PHY_STATUS_3 0x0148 | |
| 77 | #define EMIF_PHY_STATUS_4 0x014c | |
| 78 | #define EMIF_PHY_STATUS_5 0x0150 | |
| 79 | #define EMIF_PHY_STATUS_6 0x0154 | |
| 80 | #define EMIF_PHY_STATUS_7 0x0158 | |
| 81 | #define EMIF_PHY_STATUS_8 0x015c | |
| 82 | #define EMIF_PHY_STATUS_9 0x0160 | |
| 83 | #define EMIF_PHY_STATUS_10 0x0164 | |
| 84 | #define EMIF_PHY_STATUS_11 0x0168 | |
| 85 | #define EMIF_PHY_STATUS_12 0x016c | |
| 86 | #define EMIF_PHY_STATUS_13 0x0170 | |
| 87 | #define EMIF_PHY_STATUS_14 0x0174 | |
| 88 | #define EMIF_PHY_STATUS_15 0x0178 | |
| 89 | #define EMIF_PHY_STATUS_16 0x017c | |
| 90 | #define EMIF_PHY_STATUS_17 0x0180 | |
| 91 | #define EMIF_PHY_STATUS_18 0x0184 | |
| 92 | #define EMIF_PHY_STATUS_19 0x0188 | |
| 93 | #define EMIF_PHY_STATUS_20 0x018c | |
| 94 | #define EMIF_PHY_STATUS_21 0x0190 | |
| 95 | #define EMIF_EXT_PHY_CTRL_1 0x0200 | |
| 96 | #define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204 | |
| 97 | #define EMIF_EXT_PHY_CTRL_2 0x0208 | |
| 98 | #define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c | |
| 99 | #define EMIF_EXT_PHY_CTRL_3 0x0210 | |
| 100 | #define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214 | |
| 101 | #define EMIF_EXT_PHY_CTRL_4 0x0218 | |
| 102 | #define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c | |
| 103 | #define EMIF_EXT_PHY_CTRL_5 0x0220 | |
| 104 | #define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224 | |
| 105 | #define EMIF_EXT_PHY_CTRL_6 0x0228 | |
| 106 | #define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c | |
| 107 | #define EMIF_EXT_PHY_CTRL_7 0x0230 | |
| 108 | #define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234 | |
| 109 | #define EMIF_EXT_PHY_CTRL_8 0x0238 | |
| 110 | #define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c | |
| 111 | #define EMIF_EXT_PHY_CTRL_9 0x0240 | |
| 112 | #define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244 | |
| 113 | #define EMIF_EXT_PHY_CTRL_10 0x0248 | |
| 114 | #define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c | |
| 115 | #define EMIF_EXT_PHY_CTRL_11 0x0250 | |
| 116 | #define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254 | |
| 117 | #define EMIF_EXT_PHY_CTRL_12 0x0258 | |
| 118 | #define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c | |
| 119 | #define EMIF_EXT_PHY_CTRL_13 0x0260 | |
| 120 | #define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264 | |
| 121 | #define EMIF_EXT_PHY_CTRL_14 0x0268 | |
| 122 | #define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c | |
| 123 | #define EMIF_EXT_PHY_CTRL_15 0x0270 | |
| 124 | #define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274 | |
| 125 | #define EMIF_EXT_PHY_CTRL_16 0x0278 | |
| 126 | #define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c | |
| 127 | #define EMIF_EXT_PHY_CTRL_17 0x0280 | |
| 128 | #define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284 | |
| 129 | #define EMIF_EXT_PHY_CTRL_18 0x0288 | |
| 130 | #define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c | |
| 131 | #define EMIF_EXT_PHY_CTRL_19 0x0290 | |
| 132 | #define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294 | |
| 133 | #define EMIF_EXT_PHY_CTRL_20 0x0298 | |
| 134 | #define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c | |
| 135 | #define EMIF_EXT_PHY_CTRL_21 0x02a0 | |
| 136 | #define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4 | |
| 137 | #define EMIF_EXT_PHY_CTRL_22 0x02a8 | |
| 138 | #define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac | |
| 139 | #define EMIF_EXT_PHY_CTRL_23 0x02b0 | |
| 140 | #define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4 | |
| 141 | #define EMIF_EXT_PHY_CTRL_24 0x02b8 | |
| 142 | #define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc | |
| 143 | #define EMIF_EXT_PHY_CTRL_25 0x02c0 | |
| 144 | #define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4 | |
| 145 | #define EMIF_EXT_PHY_CTRL_26 0x02c8 | |
| 146 | #define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc | |
| 147 | #define EMIF_EXT_PHY_CTRL_27 0x02d0 | |
| 148 | #define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4 | |
| 149 | #define EMIF_EXT_PHY_CTRL_28 0x02d8 | |
| 150 | #define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc | |
| 151 | #define EMIF_EXT_PHY_CTRL_29 0x02e0 | |
| 152 | #define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4 | |
| 153 | #define EMIF_EXT_PHY_CTRL_30 0x02e8 | |
| 154 | #define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec | |
| 155 | ||
| 156 | /* Registers shifts and masks */ | |
| 157 | ||
| 158 | /* EMIF_MODULE_ID_AND_REVISION */ | |
| 159 | #define SCHEME_SHIFT 30 | |
| 160 | #define SCHEME_MASK (0x3 << 30) | |
| 161 | #define MODULE_ID_SHIFT 16 | |
| 162 | #define MODULE_ID_MASK (0xfff << 16) | |
| 163 | #define RTL_VERSION_SHIFT 11 | |
| 164 | #define RTL_VERSION_MASK (0x1f << 11) | |
| 165 | #define MAJOR_REVISION_SHIFT 8 | |
| 166 | #define MAJOR_REVISION_MASK (0x7 << 8) | |
| 167 | #define MINOR_REVISION_SHIFT 0 | |
| 168 | #define MINOR_REVISION_MASK (0x3f << 0) | |
| 169 | ||
| 170 | /* STATUS */ | |
| 171 | #define BE_SHIFT 31 | |
| 172 | #define BE_MASK (1 << 31) | |
| 173 | #define DUAL_CLK_MODE_SHIFT 30 | |
| 174 | #define DUAL_CLK_MODE_MASK (1 << 30) | |
| 175 | #define FAST_INIT_SHIFT 29 | |
| 176 | #define FAST_INIT_MASK (1 << 29) | |
| 177 | #define RDLVLGATETO_SHIFT 6 | |
| 178 | #define RDLVLGATETO_MASK (1 << 6) | |
| 179 | #define RDLVLTO_SHIFT 5 | |
| 180 | #define RDLVLTO_MASK (1 << 5) | |
| 181 | #define WRLVLTO_SHIFT 4 | |
| 182 | #define WRLVLTO_MASK (1 << 4) | |
| 183 | #define PHY_DLL_READY_SHIFT 2 | |
| 184 | #define PHY_DLL_READY_MASK (1 << 2) | |
| 185 | ||
| 186 | /* SDRAM_CONFIG */ | |
| 187 | #define SDRAM_TYPE_SHIFT 29 | |
| 188 | #define SDRAM_TYPE_MASK (0x7 << 29) | |
| 189 | #define IBANK_POS_SHIFT 27 | |
| 190 | #define IBANK_POS_MASK (0x3 << 27) | |
| 191 | #define DDR_TERM_SHIFT 24 | |
| 192 | #define DDR_TERM_MASK (0x7 << 24) | |
| 193 | #define DDR2_DDQS_SHIFT 23 | |
| 194 | #define DDR2_DDQS_MASK (1 << 23) | |
| 195 | #define DYN_ODT_SHIFT 21 | |
| 196 | #define DYN_ODT_MASK (0x3 << 21) | |
| 197 | #define DDR_DISABLE_DLL_SHIFT 20 | |
| 198 | #define DDR_DISABLE_DLL_MASK (1 << 20) | |
| 199 | #define SDRAM_DRIVE_SHIFT 18 | |
| 200 | #define SDRAM_DRIVE_MASK (0x3 << 18) | |
| 201 | #define CWL_SHIFT 16 | |
| 202 | #define CWL_MASK (0x3 << 16) | |
| 203 | #define NARROW_MODE_SHIFT 14 | |
| 204 | #define NARROW_MODE_MASK (0x3 << 14) | |
| 205 | #define CL_SHIFT 10 | |
| 206 | #define CL_MASK (0xf << 10) | |
| 207 | #define ROWSIZE_SHIFT 7 | |
| 208 | #define ROWSIZE_MASK (0x7 << 7) | |
| 209 | #define IBANK_SHIFT 4 | |
| 210 | #define IBANK_MASK (0x7 << 4) | |
| 211 | #define EBANK_SHIFT 3 | |
| 212 | #define EBANK_MASK (1 << 3) | |
| 213 | #define PAGESIZE_SHIFT 0 | |
| 214 | #define PAGESIZE_MASK (0x7 << 0) | |
| 215 | ||
| 216 | /* SDRAM_CONFIG_2 */ | |
| 217 | #define CS1NVMEN_SHIFT 30 | |
| 218 | #define CS1NVMEN_MASK (1 << 30) | |
| 219 | #define EBANK_POS_SHIFT 27 | |
| 220 | #define EBANK_POS_MASK (1 << 27) | |
| 221 | #define RDBNUM_SHIFT 4 | |
| 222 | #define RDBNUM_MASK (0x3 << 4) | |
| 223 | #define RDBSIZE_SHIFT 0 | |
| 224 | #define RDBSIZE_MASK (0x7 << 0) | |
| 225 | ||
| 226 | /* SDRAM_REFRESH_CONTROL */ | |
| 227 | #define INITREF_DIS_SHIFT 31 | |
| 228 | #define INITREF_DIS_MASK (1 << 31) | |
| 229 | #define SRT_SHIFT 29 | |
| 230 | #define SRT_MASK (1 << 29) | |
| 231 | #define ASR_SHIFT 28 | |
| 232 | #define ASR_MASK (1 << 28) | |
| 233 | #define PASR_SHIFT 24 | |
| 234 | #define PASR_MASK (0x7 << 24) | |
| 235 | #define REFRESH_RATE_SHIFT 0 | |
| 236 | #define REFRESH_RATE_MASK (0xffff << 0) | |
| 237 | ||
| 238 | /* SDRAM_TIMING_1 */ | |
| 239 | #define T_RTW_SHIFT 29 | |
| 240 | #define T_RTW_MASK (0x7 << 29) | |
| 241 | #define T_RP_SHIFT 25 | |
| 242 | #define T_RP_MASK (0xf << 25) | |
| 243 | #define T_RCD_SHIFT 21 | |
| 244 | #define T_RCD_MASK (0xf << 21) | |
| 245 | #define T_WR_SHIFT 17 | |
| 246 | #define T_WR_MASK (0xf << 17) | |
| 247 | #define T_RAS_SHIFT 12 | |
| 248 | #define T_RAS_MASK (0x1f << 12) | |
| 249 | #define T_RC_SHIFT 6 | |
| 250 | #define T_RC_MASK (0x3f << 6) | |
| 251 | #define T_RRD_SHIFT 3 | |
| 252 | #define T_RRD_MASK (0x7 << 3) | |
| 253 | #define T_WTR_SHIFT 0 | |
| 254 | #define T_WTR_MASK (0x7 << 0) | |
| 255 | ||
| 256 | /* SDRAM_TIMING_2 */ | |
| 257 | #define T_XP_SHIFT 28 | |
| 258 | #define T_XP_MASK (0x7 << 28) | |
| 259 | #define T_ODT_SHIFT 25 | |
| 260 | #define T_ODT_MASK (0x7 << 25) | |
| 261 | #define T_XSNR_SHIFT 16 | |
| 262 | #define T_XSNR_MASK (0x1ff << 16) | |
| 263 | #define T_XSRD_SHIFT 6 | |
| 264 | #define T_XSRD_MASK (0x3ff << 6) | |
| 265 | #define T_RTP_SHIFT 3 | |
| 266 | #define T_RTP_MASK (0x7 << 3) | |
| 267 | #define T_CKE_SHIFT 0 | |
| 268 | #define T_CKE_MASK (0x7 << 0) | |
| 269 | ||
| 270 | /* SDRAM_TIMING_3 */ | |
| 271 | #define T_PDLL_UL_SHIFT 28 | |
| 272 | #define T_PDLL_UL_MASK (0xf << 28) | |
| 273 | #define T_CSTA_SHIFT 24 | |
| 274 | #define T_CSTA_MASK (0xf << 24) | |
| 275 | #define T_CKESR_SHIFT 21 | |
| 276 | #define T_CKESR_MASK (0x7 << 21) | |
| 277 | #define ZQ_ZQCS_SHIFT 15 | |
| 278 | #define ZQ_ZQCS_MASK (0x3f << 15) | |
| 279 | #define T_TDQSCKMAX_SHIFT 13 | |
| 280 | #define T_TDQSCKMAX_MASK (0x3 << 13) | |
| 281 | #define T_RFC_SHIFT 4 | |
| 282 | #define T_RFC_MASK (0x1ff << 4) | |
| 283 | #define T_RAS_MAX_SHIFT 0 | |
| 284 | #define T_RAS_MAX_MASK (0xf << 0) | |
| 285 | ||
| 286 | /* POWER_MANAGEMENT_CONTROL */ | |
| 287 | #define PD_TIM_SHIFT 12 | |
| 288 | #define PD_TIM_MASK (0xf << 12) | |
| 289 | #define DPD_EN_SHIFT 11 | |
| 290 | #define DPD_EN_MASK (1 << 11) | |
| 291 | #define LP_MODE_SHIFT 8 | |
| 292 | #define LP_MODE_MASK (0x7 << 8) | |
| 293 | #define SR_TIM_SHIFT 4 | |
| 294 | #define SR_TIM_MASK (0xf << 4) | |
| 295 | #define CS_TIM_SHIFT 0 | |
| 296 | #define CS_TIM_MASK (0xf << 0) | |
| 297 | ||
| 298 | /* LPDDR2_MODE_REG_DATA */ | |
| 299 | #define VALUE_0_SHIFT 0 | |
| 300 | #define VALUE_0_MASK (0x7f << 0) | |
| 301 | ||
| 302 | /* LPDDR2_MODE_REG_CONFIG */ | |
| 303 | #define CS_SHIFT 31 | |
| 304 | #define CS_MASK (1 << 31) | |
| 305 | #define REFRESH_EN_SHIFT 30 | |
| 306 | #define REFRESH_EN_MASK (1 << 30) | |
| 307 | #define ADDRESS_SHIFT 0 | |
| 308 | #define ADDRESS_MASK (0xff << 0) | |
| 309 | ||
| 310 | /* OCP_CONFIG */ | |
| 311 | #define SYS_THRESH_MAX_SHIFT 24 | |
| 312 | #define SYS_THRESH_MAX_MASK (0xf << 24) | |
| 313 | #define MPU_THRESH_MAX_SHIFT 20 | |
| 314 | #define MPU_THRESH_MAX_MASK (0xf << 20) | |
| 315 | #define LL_THRESH_MAX_SHIFT 16 | |
| 316 | #define LL_THRESH_MAX_MASK (0xf << 16) | |
| 317 | ||
| 318 | /* PERFORMANCE_COUNTER_1 */ | |
| 319 | #define COUNTER1_SHIFT 0 | |
| 320 | #define COUNTER1_MASK (0xffffffff << 0) | |
| 321 | ||
| 322 | /* PERFORMANCE_COUNTER_2 */ | |
| 323 | #define COUNTER2_SHIFT 0 | |
| 324 | #define COUNTER2_MASK (0xffffffff << 0) | |
| 325 | ||
| 326 | /* PERFORMANCE_COUNTER_CONFIG */ | |
| 327 | #define CNTR2_MCONNID_EN_SHIFT 31 | |
| 328 | #define CNTR2_MCONNID_EN_MASK (1 << 31) | |
| 329 | #define CNTR2_REGION_EN_SHIFT 30 | |
| 330 | #define CNTR2_REGION_EN_MASK (1 << 30) | |
| 331 | #define CNTR2_CFG_SHIFT 16 | |
| 332 | #define CNTR2_CFG_MASK (0xf << 16) | |
| 333 | #define CNTR1_MCONNID_EN_SHIFT 15 | |
| 334 | #define CNTR1_MCONNID_EN_MASK (1 << 15) | |
| 335 | #define CNTR1_REGION_EN_SHIFT 14 | |
| 336 | #define CNTR1_REGION_EN_MASK (1 << 14) | |
| 337 | #define CNTR1_CFG_SHIFT 0 | |
| 338 | #define CNTR1_CFG_MASK (0xf << 0) | |
| 339 | ||
| 340 | /* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */ | |
| 341 | #define MCONNID2_SHIFT 24 | |
| 342 | #define MCONNID2_MASK (0xff << 24) | |
| 343 | #define REGION_SEL2_SHIFT 16 | |
| 344 | #define REGION_SEL2_MASK (0x3 << 16) | |
| 345 | #define MCONNID1_SHIFT 8 | |
| 346 | #define MCONNID1_MASK (0xff << 8) | |
| 347 | #define REGION_SEL1_SHIFT 0 | |
| 348 | #define REGION_SEL1_MASK (0x3 << 0) | |
| 349 | ||
| 350 | /* PERFORMANCE_COUNTER_TIME */ | |
| 351 | #define TOTAL_TIME_SHIFT 0 | |
| 352 | #define TOTAL_TIME_MASK (0xffffffff << 0) | |
| 353 | ||
| 354 | /* DLL_CALIB_CTRL */ | |
| 355 | #define ACK_WAIT_SHIFT 16 | |
| 356 | #define ACK_WAIT_MASK (0xf << 16) | |
| 357 | #define DLL_CALIB_INTERVAL_SHIFT 0 | |
| 358 | #define DLL_CALIB_INTERVAL_MASK (0x1ff << 0) | |
| 359 | ||
| 360 | /* END_OF_INTERRUPT */ | |
| 361 | #define EOI_SHIFT 0 | |
| 362 | #define EOI_MASK (1 << 0) | |
| 363 | ||
| 364 | /* SYSTEM_OCP_INTERRUPT_RAW_STATUS */ | |
| 365 | #define DNV_SYS_SHIFT 2 | |
| 366 | #define DNV_SYS_MASK (1 << 2) | |
| 367 | #define TA_SYS_SHIFT 1 | |
| 368 | #define TA_SYS_MASK (1 << 1) | |
| 369 | #define ERR_SYS_SHIFT 0 | |
| 370 | #define ERR_SYS_MASK (1 << 0) | |
| 371 | ||
| 372 | /* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */ | |
| 373 | #define DNV_LL_SHIFT 2 | |
| 374 | #define DNV_LL_MASK (1 << 2) | |
| 375 | #define TA_LL_SHIFT 1 | |
| 376 | #define TA_LL_MASK (1 << 1) | |
| 377 | #define ERR_LL_SHIFT 0 | |
| 378 | #define ERR_LL_MASK (1 << 0) | |
| 379 | ||
| 380 | /* SYSTEM_OCP_INTERRUPT_ENABLE_SET */ | |
| 381 | #define EN_DNV_SYS_SHIFT 2 | |
| 382 | #define EN_DNV_SYS_MASK (1 << 2) | |
| 383 | #define EN_TA_SYS_SHIFT 1 | |
| 384 | #define EN_TA_SYS_MASK (1 << 1) | |
| 385 | #define EN_ERR_SYS_SHIFT 0 | |
| 386 | #define EN_ERR_SYS_MASK (1 << 0) | |
| 387 | ||
| 388 | /* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */ | |
| 389 | #define EN_DNV_LL_SHIFT 2 | |
| 390 | #define EN_DNV_LL_MASK (1 << 2) | |
| 391 | #define EN_TA_LL_SHIFT 1 | |
| 392 | #define EN_TA_LL_MASK (1 << 1) | |
| 393 | #define EN_ERR_LL_SHIFT 0 | |
| 394 | #define EN_ERR_LL_MASK (1 << 0) | |
| 395 | ||
| 396 | /* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */ | |
| 397 | #define ZQ_CS1EN_SHIFT 31 | |
| 398 | #define ZQ_CS1EN_MASK (1 << 31) | |
| 399 | #define ZQ_CS0EN_SHIFT 30 | |
| 400 | #define ZQ_CS0EN_MASK (1 << 30) | |
| 401 | #define ZQ_DUALCALEN_SHIFT 29 | |
| 402 | #define ZQ_DUALCALEN_MASK (1 << 29) | |
| 403 | #define ZQ_SFEXITEN_SHIFT 28 | |
| 404 | #define ZQ_SFEXITEN_MASK (1 << 28) | |
| 405 | #define ZQ_ZQINIT_MULT_SHIFT 18 | |
| 406 | #define ZQ_ZQINIT_MULT_MASK (0x3 << 18) | |
| 407 | #define ZQ_ZQCL_MULT_SHIFT 16 | |
| 408 | #define ZQ_ZQCL_MULT_MASK (0x3 << 16) | |
| 409 | #define ZQ_REFINTERVAL_SHIFT 0 | |
| 410 | #define ZQ_REFINTERVAL_MASK (0xffff << 0) | |
| 411 | ||
| 412 | /* TEMPERATURE_ALERT_CONFIG */ | |
| 413 | #define TA_CS1EN_SHIFT 31 | |
| 414 | #define TA_CS1EN_MASK (1 << 31) | |
| 415 | #define TA_CS0EN_SHIFT 30 | |
| 416 | #define TA_CS0EN_MASK (1 << 30) | |
| 417 | #define TA_SFEXITEN_SHIFT 28 | |
| 418 | #define TA_SFEXITEN_MASK (1 << 28) | |
| 419 | #define TA_DEVWDT_SHIFT 26 | |
| 420 | #define TA_DEVWDT_MASK (0x3 << 26) | |
| 421 | #define TA_DEVCNT_SHIFT 24 | |
| 422 | #define TA_DEVCNT_MASK (0x3 << 24) | |
| 423 | #define TA_REFINTERVAL_SHIFT 0 | |
| 424 | #define TA_REFINTERVAL_MASK (0x3fffff << 0) | |
| 425 | ||
| 426 | /* OCP_ERROR_LOG */ | |
| 427 | #define MADDRSPACE_SHIFT 14 | |
| 428 | #define MADDRSPACE_MASK (0x3 << 14) | |
| 429 | #define MBURSTSEQ_SHIFT 11 | |
| 430 | #define MBURSTSEQ_MASK (0x7 << 11) | |
| 431 | #define MCMD_SHIFT 8 | |
| 432 | #define MCMD_MASK (0x7 << 8) | |
| 433 | #define MCONNID_SHIFT 0 | |
| 434 | #define MCONNID_MASK (0xff << 0) | |
| 435 | ||
| 436 | /* DDR_PHY_CTRL_1 - EMIF4D */ | |
| 437 | #define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4 | |
| 438 | #define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4) | |
| 439 | #define READ_LATENCY_SHIFT_4D 0 | |
| 440 | #define READ_LATENCY_MASK_4D (0xf << 0) | |
| 441 | ||
| 442 | /* DDR_PHY_CTRL_1 - EMIF4D5 */ | |
| 443 | #define DLL_HALF_DELAY_SHIFT_4D5 21 | |
| 444 | #define DLL_HALF_DELAY_MASK_4D5 (1 << 21) | |
| 445 | #define READ_LATENCY_SHIFT_4D5 0 | |
| 446 | #define READ_LATENCY_MASK_4D5 (0x1f << 0) | |
| 447 | ||
| 448 | /* DDR_PHY_CTRL_1_SHDW */ | |
| 449 | #define DDR_PHY_CTRL_1_SHDW_SHIFT 5 | |
| 450 | #define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5) | |
| 451 | #define READ_LATENCY_SHDW_SHIFT 0 | |
| 452 | #define READ_LATENCY_SHDW_MASK (0x1f << 0) | |
| 453 | ||
| 454 | #endif |