[linux-block.git] / drivers / memory / brcmstb_dpfe.c

/*
 * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
 *
 * Copyright (c) 2017 Broadcom
 *
 * Released under the GPLv2 only.
 * SPDX-License-Identifier: GPL-2.0
 */

/*
 * This driver provides access to the DPFE interface of Broadcom STB SoCs.
 * The firmware running on the DCPU inside the DDR PHY can provide current
 * information about the system's RAM, for instance the DRAM refresh rate.
 * This can be used as an indirect indicator for the DRAM's temperature.
 * Slower refresh rate means cooler RAM, higher refresh rate means hotter
 * RAM.
 *
 * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
 * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
 *
 * Note regarding the loading of the firmware image: we use be32_to_cpu()
 * and le_32_to_cpu(), so we can support the following four cases:
 *     - LE kernel + LE firmware image (the most common case)
 *     - LE kernel + BE firmware image
 *     - BE kernel + LE firmware image
 *     - BE kernel + BE firmware image
 *
 * The DPCU always runs in big endian mode. The firwmare image, however, can
 * be in either format. Also, communication between host CPU and DCPU is
 * always in little endian.
 */

#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>

#define DRVNAME			"brcmstb-dpfe"
#define FIRMWARE_NAME		"dpfe.bin"

/* DCPU register offsets */
#define REG_DCPU_RESET		0x0
#define REG_TO_DCPU_MBOX	0x10
#define REG_TO_HOST_MBOX	0x14

/* Message RAM */
#define DCPU_MSG_RAM(x)		(0x100 + (x) * sizeof(u32))

/* DRAM Info Offsets & Masks */
#define DRAM_INFO_INTERVAL	0x0
#define DRAM_INFO_MR4		0x4
#define DRAM_INFO_ERROR		0x8
#define DRAM_INFO_MR4_MASK	0xff

/* DRAM MR4 Offsets & Masks */
#define DRAM_MR4_REFRESH	0x0	/* Refresh rate */
#define DRAM_MR4_SR_ABORT	0x3	/* Self Refresh Abort */
#define DRAM_MR4_PPRE		0x4	/* Post-package repair entry/exit */
#define DRAM_MR4_TH_OFFS	0x5	/* Thermal Offset; vendor specific */
#define DRAM_MR4_TUF		0x7	/* Temperature Update Flag */

#define DRAM_MR4_REFRESH_MASK	0x7
#define DRAM_MR4_SR_ABORT_MASK	0x1
#define DRAM_MR4_PPRE_MASK	0x1
#define DRAM_MR4_TH_OFFS_MASK	0x3
#define DRAM_MR4_TUF_MASK	0x1

/* DRAM Vendor Offsets & Masks */
#define DRAM_VENDOR_MR5		0x0
#define DRAM_VENDOR_MR6		0x4
#define DRAM_VENDOR_MR7		0x8
#define DRAM_VENDOR_MR8		0xc
#define DRAM_VENDOR_ERROR	0x10
#define DRAM_VENDOR_MASK	0xff

/* Reset register bits & masks */
#define DCPU_RESET_SHIFT	0x0
#define DCPU_RESET_MASK		0x1
#define DCPU_CLK_DISABLE_SHIFT	0x2

/* DCPU return codes */
#define DCPU_RET_ERROR_BIT	BIT(31)
#define DCPU_RET_SUCCESS	0x1
#define DCPU_RET_ERR_HEADER	(DCPU_RET_ERROR_BIT | BIT(0))
#define DCPU_RET_ERR_INVAL	(DCPU_RET_ERROR_BIT | BIT(1))
#define DCPU_RET_ERR_CHKSUM	(DCPU_RET_ERROR_BIT | BIT(2))
#define DCPU_RET_ERR_COMMAND	(DCPU_RET_ERROR_BIT | BIT(3))
/* This error code is not firmware defined and only used in the driver. */
#define DCPU_RET_ERR_TIMEDOUT	(DCPU_RET_ERROR_BIT | BIT(4))

/* Firmware magic */
#define DPFE_BE_MAGIC		0xfe1010fe
#define DPFE_LE_MAGIC		0xfe0101fe

/* Error codes */
#define ERR_INVALID_MAGIC	-1
#define ERR_INVALID_SIZE	-2
#define ERR_INVALID_CHKSUM	-3

/* Message types */
#define DPFE_MSG_TYPE_COMMAND	1
#define DPFE_MSG_TYPE_RESPONSE	2

#define DELAY_LOOP_MAX		200000

enum dpfe_msg_fields {
	MSG_HEADER,
	MSG_COMMAND,
	MSG_ARG_COUNT,
	MSG_ARG0,
	MSG_CHKSUM,
	MSG_FIELD_MAX /* Last entry */
};

enum dpfe_commands {
	DPFE_CMD_GET_INFO,
	DPFE_CMD_GET_REFRESH,
	DPFE_CMD_GET_VENDOR,
	DPFE_CMD_MAX /* Last entry */
};

struct dpfe_msg {
	u32 header;
	u32 command;
	u32 arg_count;
	u32 arg0;
	u32 chksum; /* This is the sum of all other entries. */
};

/*
 * Format of the binary firmware file:
 *
 *   entry
 *      0    header
 *              value:  0xfe0101fe  <== little endian
 *                      0xfe1010fe  <== big endian
 *      1    sequence:
 *              [31:16] total segments on this build
 *              [15:0]  this segment sequence.
 *      2    FW version
 *      3    IMEM byte size
 *      4    DMEM byte size
 *           IMEM
 *           DMEM
 *      last checksum ==> sum of everything
 */
struct dpfe_firmware_header {
	u32 magic;
	u32 sequence;
	u32 version;
	u32 imem_size;
	u32 dmem_size;
};

/* Things we only need during initialization. */
struct init_data {
	unsigned int dmem_len;
	unsigned int imem_len;
	unsigned int chksum;
	bool is_big_endian;
};

/* Things we need for as long as we are active. */
struct private_data {
	void __iomem *regs;
	void __iomem *dmem;
	void __iomem *imem;
	struct device *dev;
	unsigned int index;
	struct mutex lock;
};

static const char *error_text[] = {
	"Success", "Header code incorrect", "Unknown command or argument",
	"Incorrect checksum", "Malformed command", "Timed out",
};

/* List of supported firmware commands */
static const u32 dpfe_commands[DPFE_CMD_MAX][MSG_FIELD_MAX] = {
	[DPFE_CMD_GET_INFO] = {
		[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
		[MSG_COMMAND] = 1,
		[MSG_ARG_COUNT] = 1,
		[MSG_ARG0] = 1,
		[MSG_CHKSUM] = 4,
	},
	[DPFE_CMD_GET_REFRESH] = {
		[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
		[MSG_COMMAND] = 2,
		[MSG_ARG_COUNT] = 1,
		[MSG_ARG0] = 1,
		[MSG_CHKSUM] = 5,
	},
	[DPFE_CMD_GET_VENDOR] = {
		[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
		[MSG_COMMAND] = 2,
		[MSG_ARG_COUNT] = 1,
		[MSG_ARG0] = 2,
		[MSG_CHKSUM] = 6,
	},
};

static bool is_dcpu_enabled(void __iomem *regs)
{
	u32 val;

	val = readl_relaxed(regs + REG_DCPU_RESET);

	return !(val & DCPU_RESET_MASK);
}

static void __disable_dcpu(void __iomem *regs)
{
	u32 val;

	if (!is_dcpu_enabled(regs))
		return;

	/* Put DCPU in reset if it's running. */
	val = readl_relaxed(regs + REG_DCPU_RESET);
	val |= (1 << DCPU_RESET_SHIFT);
	writel_relaxed(val, regs + REG_DCPU_RESET);
}

static void __enable_dcpu(void __iomem *regs)
{
	u32 val;

	/* Clear mailbox registers. */
	writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
	writel_relaxed(0, regs + REG_TO_HOST_MBOX);

	/* Disable DCPU clock gating */
	val = readl_relaxed(regs + REG_DCPU_RESET);
	val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
	writel_relaxed(val, regs + REG_DCPU_RESET);

	/* Take DCPU out of reset */
	val = readl_relaxed(regs + REG_DCPU_RESET);
	val &= ~(1 << DCPU_RESET_SHIFT);
	writel_relaxed(val, regs + REG_DCPU_RESET);
}

static unsigned int get_msg_chksum(const u32 msg[])
{
	unsigned int sum = 0;
	unsigned int i;

	/* Don't include the last field in the checksum. */
	for (i = 0; i < MSG_FIELD_MAX - 1; i++)
		sum += msg[i];

	return sum;
}

static int __send_command(struct private_data *priv, unsigned int cmd,
			  u32 result[])
{
	const u32 *msg = dpfe_commands[cmd];
	void __iomem *regs = priv->regs;
	unsigned int i, chksum;
	int ret = 0;
	u32 resp;

	if (cmd >= DPFE_CMD_MAX)
		return -1;

	mutex_lock(&priv->lock);

	/* Write command and arguments to message area */
	for (i = 0; i < MSG_FIELD_MAX; i++)
		writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));

	/* Tell DCPU there is a command waiting */
	writel_relaxed(1, regs + REG_TO_DCPU_MBOX);

	/* Wait for DCPU to process the command */
	for (i = 0; i < DELAY_LOOP_MAX; i++) {
		/* Read response code */
		resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
		if (resp > 0)
			break;
		udelay(5);
	}

	if (i == DELAY_LOOP_MAX) {
		resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
		ret = -ffs(resp);
	} else {
		/* Read response data */
		for (i = 0; i < MSG_FIELD_MAX; i++)
			result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
	}

	/* Tell DCPU we are done */
	writel_relaxed(0, regs + REG_TO_HOST_MBOX);

	mutex_unlock(&priv->lock);

	if (ret)
		return ret;

	/* Verify response */
	chksum = get_msg_chksum(result);
	if (chksum != result[MSG_CHKSUM])
		resp = DCPU_RET_ERR_CHKSUM;

	if (resp != DCPU_RET_SUCCESS) {
		resp &= ~DCPU_RET_ERROR_BIT;
		ret = -ffs(resp);
	}

	return ret;
}

/* Ensure that the firmware file loaded meets all the requirements. */
static int __verify_firmware(struct init_data *init,
			     const struct firmware *fw)
{
	const struct dpfe_firmware_header *header = (void *)fw->data;
	unsigned int dmem_size, imem_size, total_size;
	bool is_big_endian = false;
	const u32 *chksum_ptr;

	if (header->magic == DPFE_BE_MAGIC)
		is_big_endian = true;
	else if (header->magic != DPFE_LE_MAGIC)
		return ERR_INVALID_MAGIC;

	if (is_big_endian) {
		dmem_size = be32_to_cpu(header->dmem_size);
		imem_size = be32_to_cpu(header->imem_size);
	} else {
		dmem_size = le32_to_cpu(header->dmem_size);
		imem_size = le32_to_cpu(header->imem_size);
	}

	/* Data and instruction sections are 32 bit words. */
	if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
		return ERR_INVALID_SIZE;

	/*
	 * The header + the data section + the instruction section + the
	 * checksum must be equal to the total firmware size.
	 */
	total_size = dmem_size + imem_size + sizeof(*header) +
		sizeof(*chksum_ptr);
	if (total_size != fw->size)
		return ERR_INVALID_SIZE;

	/* The checksum comes at the very end. */
	chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;

	init->is_big_endian = is_big_endian;
	init->dmem_len = dmem_size;
	init->imem_len = imem_size;
	init->chksum = (is_big_endian)
		? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);

	return 0;
}

/* Verify checksum by reading back the firmware from co-processor RAM. */
static int __verify_fw_checksum(struct init_data *init,
				struct private_data *priv,
				const struct dpfe_firmware_header *header,
				u32 checksum)
{
	u32 magic, sequence, version, sum;
	u32 __iomem *dmem = priv->dmem;
	u32 __iomem *imem = priv->imem;
	unsigned int i;

	if (init->is_big_endian) {
		magic = be32_to_cpu(header->magic);
		sequence = be32_to_cpu(header->sequence);
		version = be32_to_cpu(header->version);
	} else {
		magic = le32_to_cpu(header->magic);
		sequence = le32_to_cpu(header->sequence);
		version = le32_to_cpu(header->version);
	}

	sum = magic + sequence + version + init->dmem_len + init->imem_len;

	for (i = 0; i < init->dmem_len / sizeof(u32); i++)
		sum += readl_relaxed(dmem + i);

	for (i = 0; i < init->imem_len / sizeof(u32); i++)
		sum += readl_relaxed(imem + i);

	return (sum == checksum) ? 0 : -1;
}

static int __write_firmware(u32 __iomem *mem, const u32 *fw,
			    unsigned int size, bool is_big_endian)
{
	unsigned int i;

	/* Convert size to 32-bit words. */
	size /= sizeof(u32);

	/* It is recommended to clear the firmware area first. */
	for (i = 0; i < size; i++)
		writel_relaxed(0, mem + i);

	/* Now copy it. */
	if (is_big_endian) {
		for (i = 0; i < size; i++)
			writel_relaxed(be32_to_cpu(fw[i]), mem + i);
	} else {
		for (i = 0; i < size; i++)
			writel_relaxed(le32_to_cpu(fw[i]), mem + i);
	}

	return 0;
}

static int brcmstb_dpfe_download_firmware(struct platform_device *pdev,
					  struct init_data *init)
{
	const struct dpfe_firmware_header *header;
	unsigned int dmem_size, imem_size;
	struct device *dev = &pdev->dev;
	bool is_big_endian = false;
	struct private_data *priv;
	const struct firmware *fw;
	const u32 *dmem, *imem;
	const void *fw_blob;
	int ret;

	priv = platform_get_drvdata(pdev);

	/*
	 * Skip downloading the firmware if the DCPU is already running and
	 * responding to commands.
	 */
	if (is_dcpu_enabled(priv->regs)) {
		u32 response[MSG_FIELD_MAX];

		ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
		if (!ret)
			return 0;
	}

	ret = request_firmware(&fw, FIRMWARE_NAME, dev);
	/* request_firmware() prints its own error messages. */
	if (ret)
		return ret;

	ret = __verify_firmware(init, fw);
	if (ret)
		return -EFAULT;

	__disable_dcpu(priv->regs);

	is_big_endian = init->is_big_endian;
	dmem_size = init->dmem_len;
	imem_size = init->imem_len;

	/* At the beginning of the firmware blob is a header. */
	header = (struct dpfe_firmware_header *)fw->data;
	/* Void pointer to the beginning of the actual firmware. */
	fw_blob = fw->data + sizeof(*header);
	/* IMEM comes right after the header. */
	imem = fw_blob;
	/* DMEM follows after IMEM. */
	dmem = fw_blob + imem_size;

	ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
	if (ret)
		return ret;
	ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
	if (ret)
		return ret;

	ret = __verify_fw_checksum(init, priv, header, init->chksum);
	if (ret)
		return ret;

	__enable_dcpu(priv->regs);

	return 0;
}

static ssize_t generic_show(unsigned int command, u32 response[],
			    struct device *dev, char *buf)
{
	struct private_data *priv;
	int ret;

	priv = dev_get_drvdata(dev);
	if (!priv)
		return sprintf(buf, "ERROR: driver private data not set\n");

	ret = __send_command(priv, command, response);
	if (ret < 0)
		return sprintf(buf, "ERROR: %s\n", error_text[-ret]);

	return 0;
}

static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
			 char *buf)
{
	u32 response[MSG_FIELD_MAX];
	unsigned int info;
	ssize_t ret;

	ret = generic_show(DPFE_CMD_GET_INFO, response, dev, buf);
	if (ret)
		return ret;

	info = response[MSG_ARG0];

	return sprintf(buf, "%u.%u.%u.%u\n",
		       (info >> 24) & 0xff,
		       (info >> 16) & 0xff,
		       (info >> 8) & 0xff,
		       info & 0xff);
}

static ssize_t show_refresh(struct device *dev,
			    struct device_attribute *devattr, char *buf)
{
	u32 response[MSG_FIELD_MAX];
	void __iomem *info;
	struct private_data *priv;
	unsigned int offset;
	u8 refresh, sr_abort, ppre, thermal_offs, tuf;
	u32 mr4;
	ssize_t ret;

	ret = generic_show(DPFE_CMD_GET_REFRESH, response, dev, buf);
	if (ret)
		return ret;

	priv = dev_get_drvdata(dev);
	offset = response[MSG_ARG0];
	info = priv->dmem + offset;

	mr4 = readl_relaxed(info + DRAM_INFO_MR4) & DRAM_INFO_MR4_MASK;

	refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
	sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
	ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
	thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
	tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;

	return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
		       readl_relaxed(info + DRAM_INFO_INTERVAL),
		       refresh, sr_abort, ppre, thermal_offs, tuf,
		       readl_relaxed(info + DRAM_INFO_ERROR));
}

static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
			  const char *buf, size_t count)
{
	u32 response[MSG_FIELD_MAX];
	struct private_data *priv;
	void __iomem *info;
	unsigned int offset;
	unsigned long val;
	int ret;

	if (kstrtoul(buf, 0, &val) < 0)
		return -EINVAL;

	priv = dev_get_drvdata(dev);

	ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
	if (ret)
		return ret;

	offset = response[MSG_ARG0];
	info = priv->dmem + offset;
	writel_relaxed(val, info + DRAM_INFO_INTERVAL);

	return count;
}

static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
			 char *buf)
{
	u32 response[MSG_FIELD_MAX];
	struct private_data *priv;
	void __iomem *info;
	unsigned int offset;
	ssize_t ret;

	ret = generic_show(DPFE_CMD_GET_VENDOR, response, dev, buf);
	if (ret)
		return ret;

	offset = response[MSG_ARG0];
	priv = dev_get_drvdata(dev);
	info = priv->dmem + offset;

	return sprintf(buf, "%#x %#x %#x %#x %#x\n",
		       readl_relaxed(info + DRAM_VENDOR_MR5) & DRAM_VENDOR_MASK,
		       readl_relaxed(info + DRAM_VENDOR_MR6) & DRAM_VENDOR_MASK,
		       readl_relaxed(info + DRAM_VENDOR_MR7) & DRAM_VENDOR_MASK,
		       readl_relaxed(info + DRAM_VENDOR_MR8) & DRAM_VENDOR_MASK,
		       readl_relaxed(info + DRAM_VENDOR_ERROR) &
				     DRAM_VENDOR_MASK);
}

static int brcmstb_dpfe_resume(struct platform_device *pdev)
{
	struct init_data init;

	return brcmstb_dpfe_download_firmware(pdev, &init);
}

static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
static struct attribute *dpfe_attrs[] = {
	&dev_attr_dpfe_info.attr,
	&dev_attr_dpfe_refresh.attr,
	&dev_attr_dpfe_vendor.attr,
	NULL
};
ATTRIBUTE_GROUPS(dpfe);

static int brcmstb_dpfe_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct private_data *priv;
	struct device *dpfe_dev;
	struct init_data init;
	struct resource *res;
	u32 index;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	mutex_init(&priv->lock);
	platform_set_drvdata(pdev, priv);

	/* Cell index is optional; default to 0 if not present. */
	ret = of_property_read_u32(dev->of_node, "cell-index", &index);
	if (ret)
		index = 0;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu");
	priv->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->regs)) {
		dev_err(dev, "couldn't map DCPU registers\n");
		return -ENODEV;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem");
	priv->dmem = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->dmem)) {
		dev_err(dev, "Couldn't map DCPU data memory\n");
		return -ENOENT;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem");
	priv->imem = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->imem)) {
		dev_err(dev, "Couldn't map DCPU instruction memory\n");
		return -ENOENT;
	}

	ret = brcmstb_dpfe_download_firmware(pdev, &init);
	if (ret)
		goto err;

	dpfe_dev = devm_kzalloc(dev, sizeof(*dpfe_dev), GFP_KERNEL);
	if (!dpfe_dev) {
		ret = -ENOMEM;
		goto err;
	}

	priv->dev = dpfe_dev;
	priv->index = index;

	dpfe_dev->parent = dev;
	dpfe_dev->groups = dpfe_groups;
	dpfe_dev->of_node = dev->of_node;
	dev_set_drvdata(dpfe_dev, priv);
	dev_set_name(dpfe_dev, "dpfe%u", index);

	ret = device_register(dpfe_dev);
	if (ret)
		goto err;

	dev_info(dev, "registered.\n");

	return 0;

err:
	dev_err(dev, "failed to initialize -- error %d\n", ret);

	return ret;
}

static const struct of_device_id brcmstb_dpfe_of_match[] = {
	{ .compatible = "brcm,dpfe-cpu", },
	{}
};
MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);

static struct platform_driver brcmstb_dpfe_driver = {
	.driver	= {
		.name = DRVNAME,
		.of_match_table = brcmstb_dpfe_of_match,
	},
	.probe = brcmstb_dpfe_probe,
	.resume = brcmstb_dpfe_resume,
};

module_platform_driver(brcmstb_dpfe_driver);

MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2f330caf MM	1	/*
	2	* DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
	3	*
	4	* Copyright (c) 2017 Broadcom
	5	*
	6	* Released under the GPLv2 only.
	7	* SPDX-License-Identifier: GPL-2.0
	8	*/
	9
	10	/*
	11	* This driver provides access to the DPFE interface of Broadcom STB SoCs.
	12	* The firmware running on the DCPU inside the DDR PHY can provide current
	13	* information about the system's RAM, for instance the DRAM refresh rate.
	14	* This can be used as an indirect indicator for the DRAM's temperature.
	15	* Slower refresh rate means cooler RAM, higher refresh rate means hotter
	16	* RAM.
	17	*
	18	* Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
	19	* already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
	20	*
	21	* Note regarding the loading of the firmware image: we use be32_to_cpu()
	22	* and le_32_to_cpu(), so we can support the following four cases:
	23	* - LE kernel + LE firmware image (the most common case)
	24	* - LE kernel + BE firmware image
	25	* - BE kernel + LE firmware image
	26	* - BE kernel + BE firmware image
	27	*
	28	* The DPCU always runs in big endian mode. The firwmare image, however, can
	29	* be in either format. Also, communication between host CPU and DCPU is
	30	* always in little endian.
	31	*/
	32
	33	#include <linux/delay.h>
	34	#include <linux/firmware.h>
	35	#include <linux/io.h>
	36	#include <linux/module.h>
	37	#include <linux/of_address.h>
	38	#include <linux/platform_device.h>
	39
	40	#define DRVNAME "brcmstb-dpfe"
	41	#define FIRMWARE_NAME "dpfe.bin"
	42
	43	/* DCPU register offsets */
	44	#define REG_DCPU_RESET 0x0
	45	#define REG_TO_DCPU_MBOX 0x10
	46	#define REG_TO_HOST_MBOX 0x14
	47
	48	/* Message RAM */
	49	#define DCPU_MSG_RAM(x) (0x100 + (x) * sizeof(u32))
	50
	51	/* DRAM Info Offsets & Masks */
	52	#define DRAM_INFO_INTERVAL 0x0
	53	#define DRAM_INFO_MR4 0x4
	54	#define DRAM_INFO_ERROR 0x8
	55	#define DRAM_INFO_MR4_MASK 0xff
	56
	57	/* DRAM MR4 Offsets & Masks */
	58	#define DRAM_MR4_REFRESH 0x0 /* Refresh rate */
	59	#define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */
	60	#define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */
	61	#define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */
	62	#define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */
	63
	64	#define DRAM_MR4_REFRESH_MASK 0x7
65	#define DRAM_MR4_SR_ABORT_MASK 0x1
66	#define DRAM_MR4_PPRE_MASK 0x1
67	#define DRAM_MR4_TH_OFFS_MASK 0x3
68	#define DRAM_MR4_TUF_MASK 0x1
69
70	/* DRAM Vendor Offsets & Masks */
71	#define DRAM_VENDOR_MR5 0x0
72	#define DRAM_VENDOR_MR6 0x4
73	#define DRAM_VENDOR_MR7 0x8
74	#define DRAM_VENDOR_MR8 0xc
75	#define DRAM_VENDOR_ERROR 0x10
76	#define DRAM_VENDOR_MASK 0xff
77
78	/* Reset register bits & masks */
79	#define DCPU_RESET_SHIFT 0x0
80	#define DCPU_RESET_MASK 0x1
81	#define DCPU_CLK_DISABLE_SHIFT 0x2
82
83	/* DCPU return codes */
84	#define DCPU_RET_ERROR_BIT BIT(31)
85	#define DCPU_RET_SUCCESS 0x1
86	#define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT \| BIT(0))
87	#define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT \| BIT(1))
88	#define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT \| BIT(2))
89	#define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT \| BIT(3))
90	/* This error code is not firmware defined and only used in the driver. */
91	#define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT \| BIT(4))
92
93	/* Firmware magic */
94	#define DPFE_BE_MAGIC 0xfe1010fe
95	#define DPFE_LE_MAGIC 0xfe0101fe
96
97	/* Error codes */
98	#define ERR_INVALID_MAGIC -1
99	#define ERR_INVALID_SIZE -2
100	#define ERR_INVALID_CHKSUM -3
101
102	/* Message types */
103	#define DPFE_MSG_TYPE_COMMAND 1
104	#define DPFE_MSG_TYPE_RESPONSE 2
105
106	#define DELAY_LOOP_MAX 200000
107
108	enum dpfe_msg_fields {
109	MSG_HEADER,
110	MSG_COMMAND,
111	MSG_ARG_COUNT,
112	MSG_ARG0,
113	MSG_CHKSUM,
114	MSG_FIELD_MAX /* Last entry */
115	};
116
117	enum dpfe_commands {
118	DPFE_CMD_GET_INFO,
119	DPFE_CMD_GET_REFRESH,
120	DPFE_CMD_GET_VENDOR,
121	DPFE_CMD_MAX /* Last entry */
122	};
123
124	struct dpfe_msg {
125	u32 header;
126	u32 command;
127	u32 arg_count;
128	u32 arg0;
129	u32 chksum; /* This is the sum of all other entries. */
130	};
131
132	/*
133	* Format of the binary firmware file:
134	*
135	* entry
136	* 0 header
137	* value: 0xfe0101fe <== little endian
138	* 0xfe1010fe <== big endian
139	* 1 sequence:
140	* [31:16] total segments on this build
141	* [15:0] this segment sequence.
142	* 2 FW version
143	* 3 IMEM byte size
144	* 4 DMEM byte size
145	* IMEM
146	* DMEM
147	* last checksum ==> sum of everything
148	*/
149	struct dpfe_firmware_header {
150	u32 magic;
151	u32 sequence;
152	u32 version;
153	u32 imem_size;
154	u32 dmem_size;
155	};
156
157	/* Things we only need during initialization. */
158	struct init_data {
159	unsigned int dmem_len;
160	unsigned int imem_len;
161	unsigned int chksum;
162	bool is_big_endian;
163	};
164
165	/* Things we need for as long as we are active. */
166	struct private_data {
167	void __iomem *regs;
168	void __iomem *dmem;
169	void __iomem *imem;
170	struct device *dev;
171	unsigned int index;
172	struct mutex lock;
173	};
174
175	static const char *error_text[] = {
176	"Success", "Header code incorrect", "Unknown command or argument",
177	"Incorrect checksum", "Malformed command", "Timed out",
178	};
179
180	/* List of supported firmware commands */
181	static const u32 dpfe_commands[DPFE_CMD_MAX][MSG_FIELD_MAX] = {
182	[DPFE_CMD_GET_INFO] = {
183	[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
184	[MSG_COMMAND] = 1,
185	[MSG_ARG_COUNT] = 1,
186	[MSG_ARG0] = 1,
187	[MSG_CHKSUM] = 4,
188	},
189	[DPFE_CMD_GET_REFRESH] = {
190	[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
191	[MSG_COMMAND] = 2,
192	[MSG_ARG_COUNT] = 1,
193	[MSG_ARG0] = 1,
194	[MSG_CHKSUM] = 5,
195	},
196	[DPFE_CMD_GET_VENDOR] = {
197	[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
198	[MSG_COMMAND] = 2,
199	[MSG_ARG_COUNT] = 1,
200	[MSG_ARG0] = 2,
201	[MSG_CHKSUM] = 6,
202	},
203	};
204
d56e746f MM	205	static bool is_dcpu_enabled(void __iomem *regs)
	206	{
	207	u32 val;
	208
	209	val = readl_relaxed(regs + REG_DCPU_RESET);
	210
	211	return !(val & DCPU_RESET_MASK);
	212	}
	213
2f330caf MM	214	static void __disable_dcpu(void __iomem *regs)
	215	{
	216	u32 val;
	217
d56e746f MM	218	if (!is_dcpu_enabled(regs))
	219	return;
	220
	221	/* Put DCPU in reset if it's running. */
2f330caf	222	val = readl_relaxed(regs + REG_DCPU_RESET);
d56e746f MM	223	val \|= (1 << DCPU_RESET_SHIFT);
d56e746f MM	224	writel_relaxed(val, regs + REG_DCPU_RESET);
2f330caf MM	225	}
	226
	227	static void __enable_dcpu(void __iomem *regs)
	228	{
	229	u32 val;
	230
	231	/* Clear mailbox registers. */
	232	writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
	233	writel_relaxed(0, regs + REG_TO_HOST_MBOX);
	234
	235	/* Disable DCPU clock gating */
	236	val = readl_relaxed(regs + REG_DCPU_RESET);
	237	val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
	238	writel_relaxed(val, regs + REG_DCPU_RESET);
	239
	240	/* Take DCPU out of reset */
	241	val = readl_relaxed(regs + REG_DCPU_RESET);
	242	val &= ~(1 << DCPU_RESET_SHIFT);
	243	writel_relaxed(val, regs + REG_DCPU_RESET);
	244	}
	245
	246	static unsigned int get_msg_chksum(const u32 msg[])
	247	{
	248	unsigned int sum = 0;
	249	unsigned int i;
	250
	251	/* Don't include the last field in the checksum. */
	252	for (i = 0; i < MSG_FIELD_MAX - 1; i++)
	253	sum += msg[i];
	254
	255	return sum;
	256	}
	257
	258	static int __send_command(struct private_data *priv, unsigned int cmd,
	259	u32 result[])
	260	{
	261	const u32 *msg = dpfe_commands[cmd];
	262	void __iomem *regs = priv->regs;
	263	unsigned int i, chksum;
	264	int ret = 0;
	265	u32 resp;
	266
	267	if (cmd >= DPFE_CMD_MAX)
	268	return -1;
	269
	270	mutex_lock(&priv->lock);
	271
	272	/* Write command and arguments to message area */
	273	for (i = 0; i < MSG_FIELD_MAX; i++)
	274	writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
	275
	276	/* Tell DCPU there is a command waiting */
	277	writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
	278
	279	/* Wait for DCPU to process the command */
	280	for (i = 0; i < DELAY_LOOP_MAX; i++) {
	281	/* Read response code */
	282	resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
	283	if (resp > 0)
	284	break;
	285	udelay(5);
	286	}
	287
	288	if (i == DELAY_LOOP_MAX) {
289	resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
290	ret = -ffs(resp);
291	} else {
292	/* Read response data */
293	for (i = 0; i < MSG_FIELD_MAX; i++)
294	result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
295	}
296
297	/* Tell DCPU we are done */
298	writel_relaxed(0, regs + REG_TO_HOST_MBOX);
299
300	mutex_unlock(&priv->lock);
301
302	if (ret)
303	return ret;
304
305	/* Verify response */
306	chksum = get_msg_chksum(result);
307	if (chksum != result[MSG_CHKSUM])
308	resp = DCPU_RET_ERR_CHKSUM;
309
310	if (resp != DCPU_RET_SUCCESS) {
311	resp &= ~DCPU_RET_ERROR_BIT;
312	ret = -ffs(resp);
313	}
314
315	return ret;
316	}
317
318	/* Ensure that the firmware file loaded meets all the requirements. */
319	static int __verify_firmware(struct init_data *init,
320	const struct firmware *fw)
321	{
322	const struct dpfe_firmware_header header = (void )fw->data;
323	unsigned int dmem_size, imem_size, total_size;
324	bool is_big_endian = false;
325	const u32 *chksum_ptr;
326
327	if (header->magic == DPFE_BE_MAGIC)
328	is_big_endian = true;
329	else if (header->magic != DPFE_LE_MAGIC)
330	return ERR_INVALID_MAGIC;
331
332	if (is_big_endian) {
333	dmem_size = be32_to_cpu(header->dmem_size);
334	imem_size = be32_to_cpu(header->imem_size);
335	} else {
336	dmem_size = le32_to_cpu(header->dmem_size);
337	imem_size = le32_to_cpu(header->imem_size);
338	}
339
340	/* Data and instruction sections are 32 bit words. */
341	if ((dmem_size % sizeof(u32)) != 0 \|\| (imem_size % sizeof(u32)) != 0)
342	return ERR_INVALID_SIZE;
343
344	/*
345	* The header + the data section + the instruction section + the
346	* checksum must be equal to the total firmware size.
347	*/
348	total_size = dmem_size + imem_size + sizeof(*header) +
349	sizeof(*chksum_ptr);
350	if (total_size != fw->size)
351	return ERR_INVALID_SIZE;
352
353	/* The checksum comes at the very end. */
354	chksum_ptr = (void )fw->data + sizeof(header) + dmem_size + imem_size;
355
356	init->is_big_endian = is_big_endian;
357	init->dmem_len = dmem_size;
358	init->imem_len = imem_size;
359	init->chksum = (is_big_endian)
360	? be32_to_cpu(chksum_ptr) : le32_to_cpu(chksum_ptr);
361
362	return 0;
363	}
364
365	/* Verify checksum by reading back the firmware from co-processor RAM. */
366	static int __verify_fw_checksum(struct init_data *init,
367	struct private_data *priv,
368	const struct dpfe_firmware_header *header,
369	u32 checksum)
370	{
371	u32 magic, sequence, version, sum;
372	u32 __iomem *dmem = priv->dmem;
373	u32 __iomem *imem = priv->imem;
374	unsigned int i;
375
376	if (init->is_big_endian) {
377	magic = be32_to_cpu(header->magic);
378	sequence = be32_to_cpu(header->sequence);
379	version = be32_to_cpu(header->version);
380	} else {
381	magic = le32_to_cpu(header->magic);
382	sequence = le32_to_cpu(header->sequence);
383	version = le32_to_cpu(header->version);
384	}
385
386	sum = magic + sequence + version + init->dmem_len + init->imem_len;
387
388	for (i = 0; i < init->dmem_len / sizeof(u32); i++)
389	sum += readl_relaxed(dmem + i);
390
391	for (i = 0; i < init->imem_len / sizeof(u32); i++)
392	sum += readl_relaxed(imem + i);
393
394	return (sum == checksum) ? 0 : -1;
395	}
396
397	static int __write_firmware(u32 __iomem mem, const u32 fw,
398	unsigned int size, bool is_big_endian)
399	{
400	unsigned int i;
401
402	/* Convert size to 32-bit words. */
403	size /= sizeof(u32);
404
405	/* It is recommended to clear the firmware area first. */
406	for (i = 0; i < size; i++)
407	writel_relaxed(0, mem + i);
408
409	/* Now copy it. */
410	if (is_big_endian) {
411	for (i = 0; i < size; i++)
412	writel_relaxed(be32_to_cpu(fw[i]), mem + i);
413	} else {
414	for (i = 0; i < size; i++)
415	writel_relaxed(le32_to_cpu(fw[i]), mem + i);
416	}
417
418	return 0;
419	}
420
421	static int brcmstb_dpfe_download_firmware(struct platform_device *pdev,
422	struct init_data *init)
423	{
424	const struct dpfe_firmware_header *header;
425	unsigned int dmem_size, imem_size;
426	struct device *dev = &pdev->dev;
427	bool is_big_endian = false;
428	struct private_data *priv;
429	const struct firmware *fw;
430	const u32 dmem, imem;
431	const void *fw_blob;
432	int ret;
433
a56d339e MM	434	priv = platform_get_drvdata(pdev);
	435
	436	/*
	437	* Skip downloading the firmware if the DCPU is already running and
	438	* responding to commands.
	439	*/
	440	if (is_dcpu_enabled(priv->regs)) {
	441	u32 response[MSG_FIELD_MAX];
	442
	443	ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
	444	if (!ret)
	445	return 0;
	446	}
	447
2f330caf MM	448	ret = request_firmware(&fw, FIRMWARE_NAME, dev);
	449	/* request_firmware() prints its own error messages. */
	450	if (ret)
	451	return ret;
	452
2f330caf MM	453	ret = __verify_firmware(init, fw);
	454	if (ret)
	455	return -EFAULT;
	456
	457	__disable_dcpu(priv->regs);
	458
	459	is_big_endian = init->is_big_endian;
	460	dmem_size = init->dmem_len;
	461	imem_size = init->imem_len;
	462
	463	/* At the beginning of the firmware blob is a header. */
	464	header = (struct dpfe_firmware_header *)fw->data;
	465	/* Void pointer to the beginning of the actual firmware. */
	466	fw_blob = fw->data + sizeof(*header);
	467	/* IMEM comes right after the header. */
	468	imem = fw_blob;
	469	/* DMEM follows after IMEM. */
	470	dmem = fw_blob + imem_size;
	471
	472	ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
	473	if (ret)
	474	return ret;
	475	ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
	476	if (ret)
	477	return ret;
	478
	479	ret = __verify_fw_checksum(init, priv, header, init->chksum);
	480	if (ret)
	481	return ret;
	482
	483	__enable_dcpu(priv->regs);
	484
	485	return 0;
	486	}
	487
	488	static ssize_t generic_show(unsigned int command, u32 response[],
	489	struct device dev, char buf)
	490	{
	491	struct private_data *priv;
	492	int ret;
	493
	494	priv = dev_get_drvdata(dev);
	495	if (!priv)
	496	return sprintf(buf, "ERROR: driver private data not set\n");
	497
	498	ret = __send_command(priv, command, response);
	499	if (ret < 0)
	500	return sprintf(buf, "ERROR: %s\n", error_text[-ret]);
	501
	502	return 0;
	503	}
	504
	505	static ssize_t show_info(struct device dev, struct device_attribute devattr,
	506	char *buf)
	507	{
	508	u32 response[MSG_FIELD_MAX];
	509	unsigned int info;
9f2c4d95	510	ssize_t ret;
2f330caf MM	511
	512	ret = generic_show(DPFE_CMD_GET_INFO, response, dev, buf);
	513	if (ret)
	514	return ret;
	515
	516	info = response[MSG_ARG0];
	517
	518	return sprintf(buf, "%u.%u.%u.%u\n",
	519	(info >> 24) & 0xff,
	520	(info >> 16) & 0xff,
	521	(info >> 8) & 0xff,
	522	info & 0xff);
	523	}
	524
	525	static ssize_t show_refresh(struct device *dev,
	526	struct device_attribute devattr, char buf)
	527	{
	528	u32 response[MSG_FIELD_MAX];
	529	void __iomem *info;
	530	struct private_data *priv;
	531	unsigned int offset;
	532	u8 refresh, sr_abort, ppre, thermal_offs, tuf;
	533	u32 mr4;
9f2c4d95	534	ssize_t ret;
2f330caf MM	535
	536	ret = generic_show(DPFE_CMD_GET_REFRESH, response, dev, buf);
	537	if (ret)
	538	return ret;
	539
	540	priv = dev_get_drvdata(dev);
	541	offset = response[MSG_ARG0];
	542	info = priv->dmem + offset;
	543
	544	mr4 = readl_relaxed(info + DRAM_INFO_MR4) & DRAM_INFO_MR4_MASK;
	545
	546	refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
	547	sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
	548	ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
	549	thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
	550	tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
	551
	552	return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
	553	readl_relaxed(info + DRAM_INFO_INTERVAL),
	554	refresh, sr_abort, ppre, thermal_offs, tuf,
	555	readl_relaxed(info + DRAM_INFO_ERROR));
	556	}
	557
	558	static ssize_t store_refresh(struct device dev, struct device_attribute attr,
	559	const char *buf, size_t count)
	560	{
	561	u32 response[MSG_FIELD_MAX];
	562	struct private_data *priv;
	563	void __iomem *info;
	564	unsigned int offset;
	565	unsigned long val;
	566	int ret;
	567
	568	if (kstrtoul(buf, 0, &val) < 0)
	569	return -EINVAL;
	570
	571	priv = dev_get_drvdata(dev);
	572
	573	ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
	574	if (ret)
	575	return ret;
	576
	577	offset = response[MSG_ARG0];
	578	info = priv->dmem + offset;
	579	writel_relaxed(val, info + DRAM_INFO_INTERVAL);
	580
	581	return count;
	582	}
	583
	584	static ssize_t show_vendor(struct device dev, struct device_attribute devattr,
	585	char *buf)
	586	{
	587	u32 response[MSG_FIELD_MAX];
	588	struct private_data *priv;
	589	void __iomem *info;
	590	unsigned int offset;
9f2c4d95	591	ssize_t ret;
2f330caf MM	592
	593	ret = generic_show(DPFE_CMD_GET_VENDOR, response, dev, buf);
	594	if (ret)
	595	return ret;
	596
	597	offset = response[MSG_ARG0];
	598	priv = dev_get_drvdata(dev);
	599	info = priv->dmem + offset;
	600
	601	return sprintf(buf, "%#x %#x %#x %#x %#x\n",
	602	readl_relaxed(info + DRAM_VENDOR_MR5) & DRAM_VENDOR_MASK,
	603	readl_relaxed(info + DRAM_VENDOR_MR6) & DRAM_VENDOR_MASK,
	604	readl_relaxed(info + DRAM_VENDOR_MR7) & DRAM_VENDOR_MASK,
	605	readl_relaxed(info + DRAM_VENDOR_MR8) & DRAM_VENDOR_MASK,
69d7d954 MM	606	readl_relaxed(info + DRAM_VENDOR_ERROR) &
69d7d954 MM	607	DRAM_VENDOR_MASK);
2f330caf MM	608	}
	609
	610	static int brcmstb_dpfe_resume(struct platform_device *pdev)
	611	{
	612	struct init_data init;
	613
	614	return brcmstb_dpfe_download_firmware(pdev, &init);
	615	}
	616
	617	static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
	618	static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
	619	static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
	620	static struct attribute *dpfe_attrs[] = {
	621	&dev_attr_dpfe_info.attr,
	622	&dev_attr_dpfe_refresh.attr,
	623	&dev_attr_dpfe_vendor.attr,
	624	NULL
	625	};
	626	ATTRIBUTE_GROUPS(dpfe);
	627
	628	static int brcmstb_dpfe_probe(struct platform_device *pdev)
	629	{
	630	struct device *dev = &pdev->dev;
	631	struct private_data *priv;
	632	struct device *dpfe_dev;
	633	struct init_data init;
	634	struct resource *res;
	635	u32 index;
	636	int ret;
	637
	638	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	639	if (!priv)
	640	return -ENOMEM;
	641
	642	mutex_init(&priv->lock);
	643	platform_set_drvdata(pdev, priv);
	644
	645	/* Cell index is optional; default to 0 if not present. */
	646	ret = of_property_read_u32(dev->of_node, "cell-index", &index);
	647	if (ret)
	648	index = 0;
	649
	650	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu");
	651	priv->regs = devm_ioremap_resource(dev, res);
	652	if (IS_ERR(priv->regs)) {
	653	dev_err(dev, "couldn't map DCPU registers\n");
	654	return -ENODEV;
	655	}
	656
	657	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem");
	658	priv->dmem = devm_ioremap_resource(dev, res);
	659	if (IS_ERR(priv->dmem)) {
	660	dev_err(dev, "Couldn't map DCPU data memory\n");
	661	return -ENOENT;
	662	}
	663
	664	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem");
	665	priv->imem = devm_ioremap_resource(dev, res);
	666	if (IS_ERR(priv->imem)) {
	667	dev_err(dev, "Couldn't map DCPU instruction memory\n");
	668	return -ENOENT;
	669	}
	670
	671	ret = brcmstb_dpfe_download_firmware(pdev, &init);
672	if (ret)
673	goto err;
674
675	dpfe_dev = devm_kzalloc(dev, sizeof(*dpfe_dev), GFP_KERNEL);
676	if (!dpfe_dev) {
677	ret = -ENOMEM;
678	goto err;
679	}
680
681	priv->dev = dpfe_dev;
682	priv->index = index;
683
684	dpfe_dev->parent = dev;
685	dpfe_dev->groups = dpfe_groups;
686	dpfe_dev->of_node = dev->of_node;
687	dev_set_drvdata(dpfe_dev, priv);
688	dev_set_name(dpfe_dev, "dpfe%u", index);
689
690	ret = device_register(dpfe_dev);
691	if (ret)
692	goto err;
693
694	dev_info(dev, "registered.\n");
695
696	return 0;
697
698	err:
699	dev_err(dev, "failed to initialize -- error %d\n", ret);
700
701	return ret;
702	}
703
704	static const struct of_device_id brcmstb_dpfe_of_match[] = {
705	{ .compatible = "brcm,dpfe-cpu", },
706	{}
707	};
708	MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
709
710	static struct platform_driver brcmstb_dpfe_driver = {
711	.driver = {
712	.name = DRVNAME,
713	.of_match_table = brcmstb_dpfe_of_match,
714	},
715	.probe = brcmstb_dpfe_probe,
716	.resume = brcmstb_dpfe_resume,
717	};
718
719	module_platform_driver(brcmstb_dpfe_driver);
720
721	MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
722	MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
723	MODULE_LICENSE("GPL");