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memory: brcmstb: dpfe: add locking around DCPU enable/disable
[linux-block.git] / drivers / memory / brcmstb_dpfe.c
CommitLineData
714c29cf 1// SPDX-License-Identifier: GPL-2.0-only
2f330caf
MM		 2/*
3 * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
4 *
5 * Copyright (c) 2017 Broadcom
2f330caf
MM		 6 */
7
8/*
9 * This driver provides access to the DPFE interface of Broadcom STB SoCs.
10 * The firmware running on the DCPU inside the DDR PHY can provide current
11 * information about the system's RAM, for instance the DRAM refresh rate.
12 * This can be used as an indirect indicator for the DRAM's temperature.
13 * Slower refresh rate means cooler RAM, higher refresh rate means hotter
14 * RAM.
15 *
16 * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
17 * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
18 *
19 * Note regarding the loading of the firmware image: we use be32_to_cpu()
20 * and le_32_to_cpu(), so we can support the following four cases:
21 * - LE kernel + LE firmware image (the most common case)
22 * - LE kernel + BE firmware image
23 * - BE kernel + LE firmware image
24 * - BE kernel + BE firmware image
25 *
26 * The DPCU always runs in big endian mode. The firwmare image, however, can
27 * be in either format. Also, communication between host CPU and DCPU is
28 * always in little endian.
29 */
30
31#include <linux/delay.h>
32#include <linux/firmware.h>
33#include <linux/io.h>
34#include <linux/module.h>
35#include <linux/of_address.h>
58a8499f 36#include <linux/of_device.h>
2f330caf
MM		 37#include <linux/platform_device.h>
38
39#define DRVNAME "brcmstb-dpfe"
2f330caf
MM		 40
41/* DCPU register offsets */
42#define REG_DCPU_RESET 0x0
43#define REG_TO_DCPU_MBOX 0x10
44#define REG_TO_HOST_MBOX 0x14
45
fee5f1ef
MM		 46/* Macros to process offsets returned by the DCPU */
47#define DRAM_MSG_ADDR_OFFSET 0x0
48#define DRAM_MSG_TYPE_OFFSET 0x1c
49#define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
50#define DRAM_MSG_TYPE_MASK ((1UL << \
51 (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
52
2f330caf 53/* Message RAM */
fee5f1ef
MM		 54#define DCPU_MSG_RAM_START 0x100
55#define DCPU_MSG_RAM(x) (DCPU_MSG_RAM_START + (x) * sizeof(u32))
2f330caf
MM		 56
57/* DRAM Info Offsets & Masks */
58#define DRAM_INFO_INTERVAL 0x0
59#define DRAM_INFO_MR4 0x4
60#define DRAM_INFO_ERROR 0x8
61#define DRAM_INFO_MR4_MASK 0xff
78a6f5be 62#define DRAM_INFO_MR4_SHIFT 24 /* We need to look at byte 3 */
2f330caf
MM		 63
64/* DRAM MR4 Offsets & Masks */
65#define DRAM_MR4_REFRESH 0x0 /* Refresh rate */
66#define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */
67#define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */
68#define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */
69#define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */
70
71#define DRAM_MR4_REFRESH_MASK 0x7
72#define DRAM_MR4_SR_ABORT_MASK 0x1
73#define DRAM_MR4_PPRE_MASK 0x1
74#define DRAM_MR4_TH_OFFS_MASK 0x3
75#define DRAM_MR4_TUF_MASK 0x1
76
e3b74723 77/* DRAM Vendor Offsets & Masks (API v2) */
2f330caf
MM		 78#define DRAM_VENDOR_MR5 0x0
79#define DRAM_VENDOR_MR6 0x4
80#define DRAM_VENDOR_MR7 0x8
81#define DRAM_VENDOR_MR8 0xc
82#define DRAM_VENDOR_ERROR 0x10
83#define DRAM_VENDOR_MASK 0xff
78a6f5be 84#define DRAM_VENDOR_SHIFT 24 /* We need to look at byte 3 */
2f330caf 85
e3b74723
MM		 86/* DRAM Information Offsets & Masks (API v3) */
87#define DRAM_DDR_INFO_MR4 0x0
88#define DRAM_DDR_INFO_MR5 0x4
89#define DRAM_DDR_INFO_MR6 0x8
90#define DRAM_DDR_INFO_MR7 0xc
91#define DRAM_DDR_INFO_MR8 0x10
92#define DRAM_DDR_INFO_ERROR 0x14
93#define DRAM_DDR_INFO_MASK 0xff
2f330caf
MM		 94
95/* Reset register bits & masks */
96#define DCPU_RESET_SHIFT 0x0
97#define DCPU_RESET_MASK 0x1
98#define DCPU_CLK_DISABLE_SHIFT 0x2
99
100/* DCPU return codes */
101#define DCPU_RET_ERROR_BIT BIT(31)
102#define DCPU_RET_SUCCESS 0x1
103#define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0))
104#define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1))
105#define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2))
106#define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3))
107/* This error code is not firmware defined and only used in the driver. */
108#define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4))
109
110/* Firmware magic */
111#define DPFE_BE_MAGIC 0xfe1010fe
112#define DPFE_LE_MAGIC 0xfe0101fe
113
114/* Error codes */
115#define ERR_INVALID_MAGIC -1
116#define ERR_INVALID_SIZE -2
117#define ERR_INVALID_CHKSUM -3
118
119/* Message types */
120#define DPFE_MSG_TYPE_COMMAND 1
121#define DPFE_MSG_TYPE_RESPONSE 2
122
7ccd2ffc 123#define DELAY_LOOP_MAX 1000
2f330caf
MM		 124
125enum dpfe_msg_fields {
126 MSG_HEADER,
127 MSG_COMMAND,
128 MSG_ARG_COUNT,
129 MSG_ARG0,
130 MSG_CHKSUM,
e3b74723 131 MSG_FIELD_MAX = 16 /* Max number of arguments */
2f330caf
MM		 132};
133
134enum dpfe_commands {
135 DPFE_CMD_GET_INFO,
136 DPFE_CMD_GET_REFRESH,
137 DPFE_CMD_GET_VENDOR,
138 DPFE_CMD_MAX /* Last entry */
139};
140
2f330caf
MM		 141/*
142 * Format of the binary firmware file:
143 *
144 * entry
145 * 0 header
146 * value: 0xfe0101fe <== little endian
147 * 0xfe1010fe <== big endian
148 * 1 sequence:
149 * [31:16] total segments on this build
150 * [15:0] this segment sequence.
151 * 2 FW version
152 * 3 IMEM byte size
153 * 4 DMEM byte size
154 * IMEM
155 * DMEM
156 * last checksum ==> sum of everything
157 */
158struct dpfe_firmware_header {
159 u32 magic;
160 u32 sequence;
161 u32 version;
162 u32 imem_size;
163 u32 dmem_size;
164};
165
166/* Things we only need during initialization. */
167struct init_data {
168 unsigned int dmem_len;
169 unsigned int imem_len;
170 unsigned int chksum;
171 bool is_big_endian;
172};
173
58a8499f
MM		 174/* API version and corresponding commands */
175struct dpfe_api {
176 int version;
177 const char *fw_name;
5ef108b4 178 const struct attribute_group **sysfs_attrs;
58a8499f
MM		 179 u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX];
180};
181
2f330caf 182/* Things we need for as long as we are active. */
abf94566 183struct brcmstb_dpfe_priv {
2f330caf
MM		 184 void __iomem *regs;
185 void __iomem *dmem;
186 void __iomem *imem;
187 struct device *dev;
58a8499f 188 const struct dpfe_api *dpfe_api;
2f330caf
MM		 189 struct mutex lock;
190};
191
192static const char *error_text[] = {
193 "Success", "Header code incorrect", "Unknown command or argument",
194 "Incorrect checksum", "Malformed command", "Timed out",
195};
196
5ef108b4
MM		 197/*
198 * Forward declaration of our sysfs attribute functions, so we can declare the
199 * attribute data structures early.
200 */
201static ssize_t show_info(struct device *, struct device_attribute *, char *);
202static ssize_t show_refresh(struct device *, struct device_attribute *, char *);
203static ssize_t store_refresh(struct device *, struct device_attribute *,
204 const char *, size_t);
205static ssize_t show_vendor(struct device *, struct device_attribute *, char *);
e3b74723 206static ssize_t show_dram(struct device *, struct device_attribute *, char *);
5ef108b4
MM		 207
208/*
209 * Declare our attributes early, so they can be referenced in the API data
210 * structure. We need to do this, because the attributes depend on the API
211 * version.
212 */
213static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
214static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
215static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
e3b74723 216static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL);
5ef108b4
MM		 217
218/* API v2 sysfs attributes */
219static struct attribute *dpfe_v2_attrs[] = {
220 &dev_attr_dpfe_info.attr,
221 &dev_attr_dpfe_refresh.attr,
222 &dev_attr_dpfe_vendor.attr,
223 NULL
224};
225ATTRIBUTE_GROUPS(dpfe_v2);
226
e3b74723
MM		 227/* API v3 sysfs attributes */
228static struct attribute *dpfe_v3_attrs[] = {
229 &dev_attr_dpfe_info.attr,
230 &dev_attr_dpfe_dram.attr,
231 NULL
232};
233ATTRIBUTE_GROUPS(dpfe_v3);
234
58a8499f
MM		 235/* API v2 firmware commands */
236static const struct dpfe_api dpfe_api_v2 = {
237 .version = 2,
238 .fw_name = "dpfe.bin",
5ef108b4 239 .sysfs_attrs = dpfe_v2_groups,
58a8499f
MM		 240 .command = {
241 [DPFE_CMD_GET_INFO] = {
242 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
243 [MSG_COMMAND] = 1,
244 [MSG_ARG_COUNT] = 1,
245 [MSG_ARG0] = 1,
246 [MSG_CHKSUM] = 4,
247 },
248 [DPFE_CMD_GET_REFRESH] = {
249 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
250 [MSG_COMMAND] = 2,
251 [MSG_ARG_COUNT] = 1,
252 [MSG_ARG0] = 1,
253 [MSG_CHKSUM] = 5,
254 },
255 [DPFE_CMD_GET_VENDOR] = {
256 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
257 [MSG_COMMAND] = 2,
258 [MSG_ARG_COUNT] = 1,
259 [MSG_ARG0] = 2,
260 [MSG_CHKSUM] = 6,
261 },
262 }
2f330caf
MM		 263};
264
e3b74723
MM		 265/* API v3 firmware commands */
266static const struct dpfe_api dpfe_api_v3 = {
267 .version = 3,
268 .fw_name = NULL, /* We expect the firmware to have been downloaded! */
269 .sysfs_attrs = dpfe_v3_groups,
270 .command = {
271 [DPFE_CMD_GET_INFO] = {
272 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
273 [MSG_COMMAND] = 0x0101,
274 [MSG_ARG_COUNT] = 1,
275 [MSG_ARG0] = 1,
276 [MSG_CHKSUM] = 0x104,
277 },
278 [DPFE_CMD_GET_REFRESH] = {
279 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
280 [MSG_COMMAND] = 0x0202,
281 [MSG_ARG_COUNT] = 0,
282 /*
283 * This is a bit ugly. Without arguments, the checksum
284 * follows right after the argument count and not at
285 * offset MSG_CHKSUM.
286 */
287 [MSG_ARG0] = 0x203,
288 },
289 /* There's no GET_VENDOR command in API v3. */
2f330caf
MM		 290 },
291};
292
75d316e7 293static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv)
d56e746f
MM		 294{
295 u32 val;
296
75d316e7
MM		 297 mutex_lock(&priv->lock);
298 val = readl_relaxed(priv->regs + REG_DCPU_RESET);
299 mutex_unlock(&priv->lock);
d56e746f
MM		 300
301 return !(val & DCPU_RESET_MASK);
302}
303
75d316e7 304static void __disable_dcpu(struct brcmstb_dpfe_priv *priv)
2f330caf
MM		 305{
306 u32 val;
307
75d316e7 308 if (!is_dcpu_enabled(priv))
d56e746f
MM		 309 return;
310
75d316e7
MM		 311 mutex_lock(&priv->lock);
312
d56e746f 313 /* Put DCPU in reset if it's running. */
75d316e7 314 val = readl_relaxed(priv->regs + REG_DCPU_RESET);
d56e746f 315 val |= (1 << DCPU_RESET_SHIFT);
75d316e7
MM		 316 writel_relaxed(val, priv->regs + REG_DCPU_RESET);
317
318 mutex_unlock(&priv->lock);
2f330caf
MM		 319}
320
75d316e7 321static void __enable_dcpu(struct brcmstb_dpfe_priv *priv)
2f330caf 322{
75d316e7 323 void __iomem *regs = priv->regs;
2f330caf
MM		 324 u32 val;
325
75d316e7
MM		 326 mutex_lock(&priv->lock);
327
2f330caf
MM		 328 /* Clear mailbox registers. */
329 writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
330 writel_relaxed(0, regs + REG_TO_HOST_MBOX);
331
332 /* Disable DCPU clock gating */
333 val = readl_relaxed(regs + REG_DCPU_RESET);
334 val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
335 writel_relaxed(val, regs + REG_DCPU_RESET);
336
337 /* Take DCPU out of reset */
338 val = readl_relaxed(regs + REG_DCPU_RESET);
339 val &= ~(1 << DCPU_RESET_SHIFT);
340 writel_relaxed(val, regs + REG_DCPU_RESET);
75d316e7
MM		 341
342 mutex_unlock(&priv->lock);
2f330caf
MM		 343}
344
e3b74723 345static unsigned int get_msg_chksum(const u32 msg[], unsigned int max)
2f330caf
MM		 346{
347 unsigned int sum = 0;
348 unsigned int i;
349
350 /* Don't include the last field in the checksum. */
e3b74723 351 for (i = 0; i < max; i++)
2f330caf
MM		 352 sum += msg[i];
353
354 return sum;
355}
356
abf94566 357static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response,
fee5f1ef
MM		 358 char *buf, ssize_t *size)
359{
360 unsigned int msg_type;
361 unsigned int offset;
362 void __iomem *ptr = NULL;
363
e3b74723
MM		 364 /* There is no need to use this function for API v3 or later. */
365 if (unlikely(priv->dpfe_api->version >= 3)) {
366 return NULL;
367 }
368
fee5f1ef
MM		 369 msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
370 offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
371
372 /*
373 * msg_type == 1: the offset is relative to the message RAM
374 * msg_type == 0: the offset is relative to the data RAM (this is the
375 * previous way of passing data)
376 * msg_type is anything else: there's critical hardware problem
377 */
378 switch (msg_type) {
379 case 1:
380 ptr = priv->regs + DCPU_MSG_RAM_START + offset;
381 break;
382 case 0:
383 ptr = priv->dmem + offset;
384 break;
385 default:
386 dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
387 response);
388 if (buf && size)
389 *size = sprintf(buf,
390 "FATAL: communication error with DCPU\n");
391 }
392
393 return ptr;
394}
395
abf94566 396static void __finalize_command(struct brcmstb_dpfe_priv *priv)
e3b74723
MM		 397{
398 unsigned int release_mbox;
399
400 /*
401 * It depends on the API version which MBOX register we have to write to
402 * to signal we are done.
403 */
404 release_mbox = (priv->dpfe_api->version < 3)
405 ? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;
406 writel_relaxed(0, priv->regs + release_mbox);
407}
408
abf94566 409static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd,
2f330caf
MM		 410 u32 result[])
411{
58a8499f 412 const u32 *msg = priv->dpfe_api->command[cmd];
2f330caf 413 void __iomem *regs = priv->regs;
e3b74723 414 unsigned int i, chksum, chksum_idx;
2f330caf
MM		 415 int ret = 0;
416 u32 resp;
417
418 if (cmd >= DPFE_CMD_MAX)
419 return -1;
420
421 mutex_lock(&priv->lock);
422
a7c25759
MM		 423 /* Wait for DCPU to become ready */
424 for (i = 0; i < DELAY_LOOP_MAX; i++) {
425 resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
426 if (resp == 0)
427 break;
428 msleep(1);
429 }
430 if (resp != 0) {
431 mutex_unlock(&priv->lock);
432 return -ETIMEDOUT;
433 }
434
2f330caf
MM		 435 /* Write command and arguments to message area */
436 for (i = 0; i < MSG_FIELD_MAX; i++)
437 writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
438
439 /* Tell DCPU there is a command waiting */
440 writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
441
442 /* Wait for DCPU to process the command */
443 for (i = 0; i < DELAY_LOOP_MAX; i++) {
444 /* Read response code */
445 resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
446 if (resp > 0)
447 break;
7ccd2ffc 448 msleep(1);
2f330caf
MM		 449 }
450
451 if (i == DELAY_LOOP_MAX) {
452 resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
453 ret = -ffs(resp);
454 } else {
455 /* Read response data */
456 for (i = 0; i < MSG_FIELD_MAX; i++)
457 result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
e3b74723 458 chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
2f330caf
MM		 459 }
460
461 /* Tell DCPU we are done */
e3b74723 462 __finalize_command(priv);
2f330caf
MM		 463
464 mutex_unlock(&priv->lock);
465
466 if (ret)
467 return ret;
468
469 /* Verify response */
e3b74723
MM		 470 chksum = get_msg_chksum(result, chksum_idx);
471 if (chksum != result[chksum_idx])
2f330caf
MM		 472 resp = DCPU_RET_ERR_CHKSUM;
473
474 if (resp != DCPU_RET_SUCCESS) {
475 resp &= ~DCPU_RET_ERROR_BIT;
476 ret = -ffs(resp);
477 }
478
479 return ret;
480}
481
482/* Ensure that the firmware file loaded meets all the requirements. */
483static int __verify_firmware(struct init_data *init,
484 const struct firmware *fw)
485{
486 const struct dpfe_firmware_header *header = (void *)fw->data;
487 unsigned int dmem_size, imem_size, total_size;
488 bool is_big_endian = false;
489 const u32 *chksum_ptr;
490
491 if (header->magic == DPFE_BE_MAGIC)
492 is_big_endian = true;
493 else if (header->magic != DPFE_LE_MAGIC)
494 return ERR_INVALID_MAGIC;
495
496 if (is_big_endian) {
497 dmem_size = be32_to_cpu(header->dmem_size);
498 imem_size = be32_to_cpu(header->imem_size);
499 } else {
500 dmem_size = le32_to_cpu(header->dmem_size);
501 imem_size = le32_to_cpu(header->imem_size);
502 }
503
504 /* Data and instruction sections are 32 bit words. */
505 if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
506 return ERR_INVALID_SIZE;
507
508 /*
509 * The header + the data section + the instruction section + the
510 * checksum must be equal to the total firmware size.
511 */
512 total_size = dmem_size + imem_size + sizeof(*header) +
513 sizeof(*chksum_ptr);
514 if (total_size != fw->size)
515 return ERR_INVALID_SIZE;
516
517 /* The checksum comes at the very end. */
518 chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
519
520 init->is_big_endian = is_big_endian;
521 init->dmem_len = dmem_size;
522 init->imem_len = imem_size;
523 init->chksum = (is_big_endian)
524 ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
525
526 return 0;
527}
528
529/* Verify checksum by reading back the firmware from co-processor RAM. */
530static int __verify_fw_checksum(struct init_data *init,
abf94566 531 struct brcmstb_dpfe_priv *priv,
2f330caf
MM		 532 const struct dpfe_firmware_header *header,
533 u32 checksum)
534{
535 u32 magic, sequence, version, sum;
536 u32 __iomem *dmem = priv->dmem;
537 u32 __iomem *imem = priv->imem;
538 unsigned int i;
539
540 if (init->is_big_endian) {
541 magic = be32_to_cpu(header->magic);
542 sequence = be32_to_cpu(header->sequence);
543 version = be32_to_cpu(header->version);
544 } else {
545 magic = le32_to_cpu(header->magic);
546 sequence = le32_to_cpu(header->sequence);
547 version = le32_to_cpu(header->version);
548 }
549
550 sum = magic + sequence + version + init->dmem_len + init->imem_len;
551
552 for (i = 0; i < init->dmem_len / sizeof(u32); i++)
553 sum += readl_relaxed(dmem + i);
554
555 for (i = 0; i < init->imem_len / sizeof(u32); i++)
556 sum += readl_relaxed(imem + i);
557
558 return (sum == checksum) ? 0 : -1;
559}
560
561static int __write_firmware(u32 __iomem *mem, const u32 *fw,
562 unsigned int size, bool is_big_endian)
563{
564 unsigned int i;
565
566 /* Convert size to 32-bit words. */
567 size /= sizeof(u32);
568
569 /* It is recommended to clear the firmware area first. */
570 for (i = 0; i < size; i++)
571 writel_relaxed(0, mem + i);
572
573 /* Now copy it. */
574 if (is_big_endian) {
575 for (i = 0; i < size; i++)
576 writel_relaxed(be32_to_cpu(fw[i]), mem + i);
577 } else {
578 for (i = 0; i < size; i++)
579 writel_relaxed(le32_to_cpu(fw[i]), mem + i);
580 }
581
582 return 0;
583}
584
585static int brcmstb_dpfe_download_firmware(struct platform_device *pdev,
586 struct init_data *init)
587{
588 const struct dpfe_firmware_header *header;
589 unsigned int dmem_size, imem_size;
590 struct device *dev = &pdev->dev;
591 bool is_big_endian = false;
abf94566 592 struct brcmstb_dpfe_priv *priv;
2f330caf
MM		 593 const struct firmware *fw;
594 const u32 *dmem, *imem;
595 const void *fw_blob;
596 int ret;
597
a56d339e
MM		 598 priv = platform_get_drvdata(pdev);
599
600 /*
601 * Skip downloading the firmware if the DCPU is already running and
602 * responding to commands.
603 */
75d316e7 604 if (is_dcpu_enabled(priv)) {
a56d339e
MM		 605 u32 response[MSG_FIELD_MAX];
606
607 ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
608 if (!ret)
609 return 0;
610 }
611
58a8499f
MM		 612 /*
613 * If the firmware filename is NULL it means the boot firmware has to
614 * download the DCPU firmware for us. If that didn't work, we have to
615 * bail, since downloading it ourselves wouldn't work either.
616 */
617 if (!priv->dpfe_api->fw_name)
618 return -ENODEV;
619
620 ret = request_firmware(&fw, priv->dpfe_api->fw_name, dev);
2f330caf
MM		 621 /* request_firmware() prints its own error messages. */
622 if (ret)
623 return ret;
624
2f330caf
MM		 625 ret = __verify_firmware(init, fw);
626 if (ret)
627 return -EFAULT;
628
75d316e7 629 __disable_dcpu(priv);
2f330caf
MM		 630
631 is_big_endian = init->is_big_endian;
632 dmem_size = init->dmem_len;
633 imem_size = init->imem_len;
634
635 /* At the beginning of the firmware blob is a header. */
636 header = (struct dpfe_firmware_header *)fw->data;
637 /* Void pointer to the beginning of the actual firmware. */
638 fw_blob = fw->data + sizeof(*header);
639 /* IMEM comes right after the header. */
640 imem = fw_blob;
641 /* DMEM follows after IMEM. */
642 dmem = fw_blob + imem_size;
643
644 ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
645 if (ret)
646 return ret;
647 ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
648 if (ret)
649 return ret;
650
651 ret = __verify_fw_checksum(init, priv, header, init->chksum);
652 if (ret)
653 return ret;
654
75d316e7 655 __enable_dcpu(priv);
2f330caf
MM		 656
657 return 0;
658}
659
660static ssize_t generic_show(unsigned int command, u32 response[],
abf94566 661 struct brcmstb_dpfe_priv *priv, char *buf)
2f330caf 662{
2f330caf
MM		 663 int ret;
664
2f330caf
MM		 665 if (!priv)
666 return sprintf(buf, "ERROR: driver private data not set\n");
667
668 ret = __send_command(priv, command, response);
669 if (ret < 0)
670 return sprintf(buf, "ERROR: %s\n", error_text[-ret]);
671
672 return 0;
673}
674
675static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
676 char *buf)
677{
678 u32 response[MSG_FIELD_MAX];
abf94566 679 struct brcmstb_dpfe_priv *priv;
2f330caf 680 unsigned int info;
9f2c4d95 681 ssize_t ret;
2f330caf 682
900c8f57
MM		 683 priv = dev_get_drvdata(dev);
684 ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf);
2f330caf
MM		 685 if (ret)
686 return ret;
687
688 info = response[MSG_ARG0];
689
690 return sprintf(buf, "%u.%u.%u.%u\n",
691 (info >> 24) & 0xff,
692 (info >> 16) & 0xff,
693 (info >> 8) & 0xff,
694 info & 0xff);
695}
696
697static ssize_t show_refresh(struct device *dev,
698 struct device_attribute *devattr, char *buf)
699{
700 u32 response[MSG_FIELD_MAX];
701 void __iomem *info;
abf94566 702 struct brcmstb_dpfe_priv *priv;
2f330caf
MM		 703 u8 refresh, sr_abort, ppre, thermal_offs, tuf;
704 u32 mr4;
9f2c4d95 705 ssize_t ret;
2f330caf 706
900c8f57
MM		 707 priv = dev_get_drvdata(dev);
708 ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
2f330caf
MM		 709 if (ret)
710 return ret;
711
fee5f1ef
MM		 712 info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
713 if (!info)
714 return ret;
2f330caf 715
78a6f5be 716 mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &
1ffc0b58 717 DRAM_INFO_MR4_MASK;
2f330caf
MM		 718
719 refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
720 sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
721 ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
722 thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
723 tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
724
725 return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
726 readl_relaxed(info + DRAM_INFO_INTERVAL),
727 refresh, sr_abort, ppre, thermal_offs, tuf,
728 readl_relaxed(info + DRAM_INFO_ERROR));
729}
730
731static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
732 const char *buf, size_t count)
733{
734 u32 response[MSG_FIELD_MAX];
abf94566 735 struct brcmstb_dpfe_priv *priv;
2f330caf 736 void __iomem *info;
2f330caf
MM		 737 unsigned long val;
738 int ret;
739
740 if (kstrtoul(buf, 0, &val) < 0)
741 return -EINVAL;
742
743 priv = dev_get_drvdata(dev);
2f330caf
MM		 744 ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
745 if (ret)
746 return ret;
747
fee5f1ef
MM		 748 info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
749 if (!info)
750 return -EIO;
751
2f330caf
MM		 752 writel_relaxed(val, info + DRAM_INFO_INTERVAL);
753
754 return count;
755}
756
757static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
1ffc0b58 758 char *buf)
2f330caf
MM		 759{
760 u32 response[MSG_FIELD_MAX];
abf94566 761 struct brcmstb_dpfe_priv *priv;
2f330caf 762 void __iomem *info;
9f2c4d95 763 ssize_t ret;
78a6f5be 764 u32 mr5, mr6, mr7, mr8, err;
2f330caf 765
900c8f57
MM		 766 priv = dev_get_drvdata(dev);
767 ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf);
2f330caf
MM		 768 if (ret)
769 return ret;
770
fee5f1ef
MM		 771 info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
772 if (!info)
773 return ret;
2f330caf 774
78a6f5be
MM		 775 mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) &
776 DRAM_VENDOR_MASK;
777 mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) &
778 DRAM_VENDOR_MASK;
779 mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) &
780 DRAM_VENDOR_MASK;
781 mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) &
782 DRAM_VENDOR_MASK;
783 err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK;
784
785 return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err);
2f330caf
MM		 786}
787
e3b74723
MM		 788static ssize_t show_dram(struct device *dev, struct device_attribute *devattr,
789 char *buf)
790{
791 u32 response[MSG_FIELD_MAX];
abf94566 792 struct brcmstb_dpfe_priv *priv;
e3b74723
MM		 793 ssize_t ret;
794 u32 mr4, mr5, mr6, mr7, mr8, err;
795
796 priv = dev_get_drvdata(dev);
797 ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
798 if (ret)
799 return ret;
800
801 mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;
802 mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK;
803 mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK;
804 mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK;
805 mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK;
806 err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK;
807
808 return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,
809 mr8, err);
2f330caf
MM		 810}
811
812static int brcmstb_dpfe_resume(struct platform_device *pdev)
813{
814 struct init_data init;
815
816 return brcmstb_dpfe_download_firmware(pdev, &init);
817}
818
2f330caf
MM		 819static int brcmstb_dpfe_probe(struct platform_device *pdev)
820{
821 struct device *dev = &pdev->dev;
abf94566 822 struct brcmstb_dpfe_priv *priv;
2f330caf
MM		 823 struct init_data init;
824 struct resource *res;
2f330caf
MM		 825 int ret;
826
827 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
828 if (!priv)
829 return -ENOMEM;
830
56ece3fa
MM		 831 priv->dev = dev;
832
2f330caf
MM		 833 mutex_init(&priv->lock);
834 platform_set_drvdata(pdev, priv);
835
2f330caf
MM		 836 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu");
837 priv->regs = devm_ioremap_resource(dev, res);
838 if (IS_ERR(priv->regs)) {
839 dev_err(dev, "couldn't map DCPU registers\n");
840 return -ENODEV;
841 }
842
843 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem");
844 priv->dmem = devm_ioremap_resource(dev, res);
845 if (IS_ERR(priv->dmem)) {
846 dev_err(dev, "Couldn't map DCPU data memory\n");
847 return -ENOENT;
848 }
849
850 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem");
851 priv->imem = devm_ioremap_resource(dev, res);
852 if (IS_ERR(priv->imem)) {
853 dev_err(dev, "Couldn't map DCPU instruction memory\n");
854 return -ENOENT;
855 }
856
58a8499f
MM		 857 priv->dpfe_api = of_device_get_match_data(dev);
858 if (unlikely(!priv->dpfe_api)) {
859 /*
860 * It should be impossible to end up here, but to be safe we
861 * check anyway.
862 */
863 dev_err(dev, "Couldn't determine API\n");
864 return -ENOENT;
865 }
866
2f330caf 867 ret = brcmstb_dpfe_download_firmware(pdev, &init);
6ca5d2ba
MM		 868 if (ret) {
869 dev_err(dev, "Couldn't download firmware -- %d\n", ret);
b1d0973e 870 return ret;
6ca5d2ba 871 }
2f330caf 872
5ef108b4 873 ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
b1d0973e 874 if (!ret)
58a8499f
MM		 875 dev_info(dev, "registered with API v%d.\n",
876 priv->dpfe_api->version);
2f330caf 877
b1d0973e
FF		 878 return ret;
879}
2f330caf 880
b1d0973e
FF		 881static int brcmstb_dpfe_remove(struct platform_device *pdev)
882{
abf94566 883 struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev);
5ef108b4
MM		 884
885 sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
2f330caf
MM		 886
887 return 0;
2f330caf
MM		 888}
889
890static const struct of_device_id brcmstb_dpfe_of_match[] = {
e3b74723
MM		 891 /* Use legacy API v2 for a select number of chips */
892 { .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_v2 },
893 { .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_v2 },
894 { .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_v2 },
895 { .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_v2 },
896 /* API v3 is the default going forward */
897 { .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 },
2f330caf
MM		 898 {}
899};
900MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
901
902static struct platform_driver brcmstb_dpfe_driver = {
903 .driver = {
904 .name = DRVNAME,
905 .of_match_table = brcmstb_dpfe_of_match,
906 },
907 .probe = brcmstb_dpfe_probe,
b1d0973e 908 .remove = brcmstb_dpfe_remove,
2f330caf
MM		 909 .resume = brcmstb_dpfe_resume,
910};
911
912module_platform_driver(brcmstb_dpfe_driver);
913
914MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
915MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
916MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)