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714c29cf | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2f330caf MM |
2 | /* |
3 | * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs | |
4 | * | |
5 | * Copyright (c) 2017 Broadcom | |
2f330caf MM |
6 | */ |
7 | ||
8 | /* | |
9 | * This driver provides access to the DPFE interface of Broadcom STB SoCs. | |
10 | * The firmware running on the DCPU inside the DDR PHY can provide current | |
11 | * information about the system's RAM, for instance the DRAM refresh rate. | |
12 | * This can be used as an indirect indicator for the DRAM's temperature. | |
13 | * Slower refresh rate means cooler RAM, higher refresh rate means hotter | |
14 | * RAM. | |
15 | * | |
16 | * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which | |
17 | * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls. | |
18 | * | |
19 | * Note regarding the loading of the firmware image: we use be32_to_cpu() | |
20 | * and le_32_to_cpu(), so we can support the following four cases: | |
21 | * - LE kernel + LE firmware image (the most common case) | |
22 | * - LE kernel + BE firmware image | |
23 | * - BE kernel + LE firmware image | |
24 | * - BE kernel + BE firmware image | |
25 | * | |
26 | * The DPCU always runs in big endian mode. The firwmare image, however, can | |
27 | * be in either format. Also, communication between host CPU and DCPU is | |
28 | * always in little endian. | |
29 | */ | |
30 | ||
31 | #include <linux/delay.h> | |
32 | #include <linux/firmware.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/of_address.h> | |
58a8499f | 36 | #include <linux/of_device.h> |
2f330caf MM |
37 | #include <linux/platform_device.h> |
38 | ||
39 | #define DRVNAME "brcmstb-dpfe" | |
2f330caf MM |
40 | |
41 | /* DCPU register offsets */ | |
42 | #define REG_DCPU_RESET 0x0 | |
43 | #define REG_TO_DCPU_MBOX 0x10 | |
44 | #define REG_TO_HOST_MBOX 0x14 | |
45 | ||
fee5f1ef MM |
46 | /* Macros to process offsets returned by the DCPU */ |
47 | #define DRAM_MSG_ADDR_OFFSET 0x0 | |
48 | #define DRAM_MSG_TYPE_OFFSET 0x1c | |
49 | #define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1) | |
50 | #define DRAM_MSG_TYPE_MASK ((1UL << \ | |
51 | (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1) | |
52 | ||
2f330caf | 53 | /* Message RAM */ |
fee5f1ef MM |
54 | #define DCPU_MSG_RAM_START 0x100 |
55 | #define DCPU_MSG_RAM(x) (DCPU_MSG_RAM_START + (x) * sizeof(u32)) | |
2f330caf MM |
56 | |
57 | /* DRAM Info Offsets & Masks */ | |
58 | #define DRAM_INFO_INTERVAL 0x0 | |
59 | #define DRAM_INFO_MR4 0x4 | |
60 | #define DRAM_INFO_ERROR 0x8 | |
61 | #define DRAM_INFO_MR4_MASK 0xff | |
78a6f5be | 62 | #define DRAM_INFO_MR4_SHIFT 24 /* We need to look at byte 3 */ |
2f330caf MM |
63 | |
64 | /* DRAM MR4 Offsets & Masks */ | |
65 | #define DRAM_MR4_REFRESH 0x0 /* Refresh rate */ | |
66 | #define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */ | |
67 | #define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */ | |
68 | #define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */ | |
69 | #define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */ | |
70 | ||
71 | #define DRAM_MR4_REFRESH_MASK 0x7 | |
72 | #define DRAM_MR4_SR_ABORT_MASK 0x1 | |
73 | #define DRAM_MR4_PPRE_MASK 0x1 | |
74 | #define DRAM_MR4_TH_OFFS_MASK 0x3 | |
75 | #define DRAM_MR4_TUF_MASK 0x1 | |
76 | ||
e3b74723 | 77 | /* DRAM Vendor Offsets & Masks (API v2) */ |
2f330caf MM |
78 | #define DRAM_VENDOR_MR5 0x0 |
79 | #define DRAM_VENDOR_MR6 0x4 | |
80 | #define DRAM_VENDOR_MR7 0x8 | |
81 | #define DRAM_VENDOR_MR8 0xc | |
82 | #define DRAM_VENDOR_ERROR 0x10 | |
83 | #define DRAM_VENDOR_MASK 0xff | |
78a6f5be | 84 | #define DRAM_VENDOR_SHIFT 24 /* We need to look at byte 3 */ |
2f330caf | 85 | |
e3b74723 MM |
86 | /* DRAM Information Offsets & Masks (API v3) */ |
87 | #define DRAM_DDR_INFO_MR4 0x0 | |
88 | #define DRAM_DDR_INFO_MR5 0x4 | |
89 | #define DRAM_DDR_INFO_MR6 0x8 | |
90 | #define DRAM_DDR_INFO_MR7 0xc | |
91 | #define DRAM_DDR_INFO_MR8 0x10 | |
92 | #define DRAM_DDR_INFO_ERROR 0x14 | |
93 | #define DRAM_DDR_INFO_MASK 0xff | |
2f330caf MM |
94 | |
95 | /* Reset register bits & masks */ | |
96 | #define DCPU_RESET_SHIFT 0x0 | |
97 | #define DCPU_RESET_MASK 0x1 | |
98 | #define DCPU_CLK_DISABLE_SHIFT 0x2 | |
99 | ||
100 | /* DCPU return codes */ | |
101 | #define DCPU_RET_ERROR_BIT BIT(31) | |
102 | #define DCPU_RET_SUCCESS 0x1 | |
103 | #define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0)) | |
104 | #define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1)) | |
105 | #define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2)) | |
106 | #define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3)) | |
107 | /* This error code is not firmware defined and only used in the driver. */ | |
108 | #define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4)) | |
109 | ||
110 | /* Firmware magic */ | |
111 | #define DPFE_BE_MAGIC 0xfe1010fe | |
112 | #define DPFE_LE_MAGIC 0xfe0101fe | |
113 | ||
114 | /* Error codes */ | |
115 | #define ERR_INVALID_MAGIC -1 | |
116 | #define ERR_INVALID_SIZE -2 | |
117 | #define ERR_INVALID_CHKSUM -3 | |
118 | ||
119 | /* Message types */ | |
120 | #define DPFE_MSG_TYPE_COMMAND 1 | |
121 | #define DPFE_MSG_TYPE_RESPONSE 2 | |
122 | ||
7ccd2ffc | 123 | #define DELAY_LOOP_MAX 1000 |
2f330caf MM |
124 | |
125 | enum dpfe_msg_fields { | |
126 | MSG_HEADER, | |
127 | MSG_COMMAND, | |
128 | MSG_ARG_COUNT, | |
129 | MSG_ARG0, | |
e3b74723 | 130 | MSG_FIELD_MAX = 16 /* Max number of arguments */ |
2f330caf MM |
131 | }; |
132 | ||
133 | enum dpfe_commands { | |
134 | DPFE_CMD_GET_INFO, | |
135 | DPFE_CMD_GET_REFRESH, | |
136 | DPFE_CMD_GET_VENDOR, | |
137 | DPFE_CMD_MAX /* Last entry */ | |
138 | }; | |
139 | ||
2f330caf MM |
140 | /* |
141 | * Format of the binary firmware file: | |
142 | * | |
143 | * entry | |
144 | * 0 header | |
145 | * value: 0xfe0101fe <== little endian | |
146 | * 0xfe1010fe <== big endian | |
147 | * 1 sequence: | |
148 | * [31:16] total segments on this build | |
149 | * [15:0] this segment sequence. | |
150 | * 2 FW version | |
151 | * 3 IMEM byte size | |
152 | * 4 DMEM byte size | |
153 | * IMEM | |
154 | * DMEM | |
155 | * last checksum ==> sum of everything | |
156 | */ | |
157 | struct dpfe_firmware_header { | |
158 | u32 magic; | |
159 | u32 sequence; | |
160 | u32 version; | |
161 | u32 imem_size; | |
162 | u32 dmem_size; | |
163 | }; | |
164 | ||
165 | /* Things we only need during initialization. */ | |
166 | struct init_data { | |
167 | unsigned int dmem_len; | |
168 | unsigned int imem_len; | |
169 | unsigned int chksum; | |
170 | bool is_big_endian; | |
171 | }; | |
172 | ||
58a8499f MM |
173 | /* API version and corresponding commands */ |
174 | struct dpfe_api { | |
175 | int version; | |
176 | const char *fw_name; | |
5ef108b4 | 177 | const struct attribute_group **sysfs_attrs; |
58a8499f MM |
178 | u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX]; |
179 | }; | |
180 | ||
2f330caf | 181 | /* Things we need for as long as we are active. */ |
abf94566 | 182 | struct brcmstb_dpfe_priv { |
2f330caf MM |
183 | void __iomem *regs; |
184 | void __iomem *dmem; | |
185 | void __iomem *imem; | |
186 | struct device *dev; | |
58a8499f | 187 | const struct dpfe_api *dpfe_api; |
2f330caf MM |
188 | struct mutex lock; |
189 | }; | |
190 | ||
191 | static const char *error_text[] = { | |
192 | "Success", "Header code incorrect", "Unknown command or argument", | |
193 | "Incorrect checksum", "Malformed command", "Timed out", | |
194 | }; | |
195 | ||
5ef108b4 MM |
196 | /* |
197 | * Forward declaration of our sysfs attribute functions, so we can declare the | |
198 | * attribute data structures early. | |
199 | */ | |
200 | static ssize_t show_info(struct device *, struct device_attribute *, char *); | |
201 | static ssize_t show_refresh(struct device *, struct device_attribute *, char *); | |
202 | static ssize_t store_refresh(struct device *, struct device_attribute *, | |
203 | const char *, size_t); | |
204 | static ssize_t show_vendor(struct device *, struct device_attribute *, char *); | |
e3b74723 | 205 | static ssize_t show_dram(struct device *, struct device_attribute *, char *); |
5ef108b4 MM |
206 | |
207 | /* | |
208 | * Declare our attributes early, so they can be referenced in the API data | |
209 | * structure. We need to do this, because the attributes depend on the API | |
210 | * version. | |
211 | */ | |
212 | static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL); | |
213 | static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh); | |
214 | static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL); | |
e3b74723 | 215 | static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL); |
5ef108b4 MM |
216 | |
217 | /* API v2 sysfs attributes */ | |
218 | static struct attribute *dpfe_v2_attrs[] = { | |
219 | &dev_attr_dpfe_info.attr, | |
220 | &dev_attr_dpfe_refresh.attr, | |
221 | &dev_attr_dpfe_vendor.attr, | |
222 | NULL | |
223 | }; | |
224 | ATTRIBUTE_GROUPS(dpfe_v2); | |
225 | ||
e3b74723 MM |
226 | /* API v3 sysfs attributes */ |
227 | static struct attribute *dpfe_v3_attrs[] = { | |
228 | &dev_attr_dpfe_info.attr, | |
229 | &dev_attr_dpfe_dram.attr, | |
230 | NULL | |
231 | }; | |
232 | ATTRIBUTE_GROUPS(dpfe_v3); | |
233 | ||
58a8499f MM |
234 | /* API v2 firmware commands */ |
235 | static const struct dpfe_api dpfe_api_v2 = { | |
236 | .version = 2, | |
237 | .fw_name = "dpfe.bin", | |
5ef108b4 | 238 | .sysfs_attrs = dpfe_v2_groups, |
58a8499f MM |
239 | .command = { |
240 | [DPFE_CMD_GET_INFO] = { | |
241 | [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, | |
242 | [MSG_COMMAND] = 1, | |
243 | [MSG_ARG_COUNT] = 1, | |
244 | [MSG_ARG0] = 1, | |
58a8499f MM |
245 | }, |
246 | [DPFE_CMD_GET_REFRESH] = { | |
247 | [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, | |
248 | [MSG_COMMAND] = 2, | |
249 | [MSG_ARG_COUNT] = 1, | |
250 | [MSG_ARG0] = 1, | |
58a8499f MM |
251 | }, |
252 | [DPFE_CMD_GET_VENDOR] = { | |
253 | [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, | |
254 | [MSG_COMMAND] = 2, | |
255 | [MSG_ARG_COUNT] = 1, | |
256 | [MSG_ARG0] = 2, | |
58a8499f MM |
257 | }, |
258 | } | |
2f330caf MM |
259 | }; |
260 | ||
e3b74723 MM |
261 | /* API v3 firmware commands */ |
262 | static const struct dpfe_api dpfe_api_v3 = { | |
263 | .version = 3, | |
264 | .fw_name = NULL, /* We expect the firmware to have been downloaded! */ | |
265 | .sysfs_attrs = dpfe_v3_groups, | |
266 | .command = { | |
267 | [DPFE_CMD_GET_INFO] = { | |
268 | [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, | |
269 | [MSG_COMMAND] = 0x0101, | |
270 | [MSG_ARG_COUNT] = 1, | |
271 | [MSG_ARG0] = 1, | |
e3b74723 MM |
272 | }, |
273 | [DPFE_CMD_GET_REFRESH] = { | |
274 | [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, | |
275 | [MSG_COMMAND] = 0x0202, | |
276 | [MSG_ARG_COUNT] = 0, | |
e3b74723 MM |
277 | }, |
278 | /* There's no GET_VENDOR command in API v3. */ | |
2f330caf MM |
279 | }, |
280 | }; | |
281 | ||
75d316e7 | 282 | static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv) |
d56e746f MM |
283 | { |
284 | u32 val; | |
285 | ||
75d316e7 MM |
286 | mutex_lock(&priv->lock); |
287 | val = readl_relaxed(priv->regs + REG_DCPU_RESET); | |
288 | mutex_unlock(&priv->lock); | |
d56e746f MM |
289 | |
290 | return !(val & DCPU_RESET_MASK); | |
291 | } | |
292 | ||
75d316e7 | 293 | static void __disable_dcpu(struct brcmstb_dpfe_priv *priv) |
2f330caf MM |
294 | { |
295 | u32 val; | |
296 | ||
75d316e7 | 297 | if (!is_dcpu_enabled(priv)) |
d56e746f MM |
298 | return; |
299 | ||
75d316e7 MM |
300 | mutex_lock(&priv->lock); |
301 | ||
d56e746f | 302 | /* Put DCPU in reset if it's running. */ |
75d316e7 | 303 | val = readl_relaxed(priv->regs + REG_DCPU_RESET); |
d56e746f | 304 | val |= (1 << DCPU_RESET_SHIFT); |
75d316e7 MM |
305 | writel_relaxed(val, priv->regs + REG_DCPU_RESET); |
306 | ||
307 | mutex_unlock(&priv->lock); | |
2f330caf MM |
308 | } |
309 | ||
75d316e7 | 310 | static void __enable_dcpu(struct brcmstb_dpfe_priv *priv) |
2f330caf | 311 | { |
75d316e7 | 312 | void __iomem *regs = priv->regs; |
2f330caf MM |
313 | u32 val; |
314 | ||
75d316e7 MM |
315 | mutex_lock(&priv->lock); |
316 | ||
2f330caf MM |
317 | /* Clear mailbox registers. */ |
318 | writel_relaxed(0, regs + REG_TO_DCPU_MBOX); | |
319 | writel_relaxed(0, regs + REG_TO_HOST_MBOX); | |
320 | ||
321 | /* Disable DCPU clock gating */ | |
322 | val = readl_relaxed(regs + REG_DCPU_RESET); | |
323 | val &= ~(1 << DCPU_CLK_DISABLE_SHIFT); | |
324 | writel_relaxed(val, regs + REG_DCPU_RESET); | |
325 | ||
326 | /* Take DCPU out of reset */ | |
327 | val = readl_relaxed(regs + REG_DCPU_RESET); | |
328 | val &= ~(1 << DCPU_RESET_SHIFT); | |
329 | writel_relaxed(val, regs + REG_DCPU_RESET); | |
75d316e7 MM |
330 | |
331 | mutex_unlock(&priv->lock); | |
2f330caf MM |
332 | } |
333 | ||
e3b74723 | 334 | static unsigned int get_msg_chksum(const u32 msg[], unsigned int max) |
2f330caf MM |
335 | { |
336 | unsigned int sum = 0; | |
337 | unsigned int i; | |
338 | ||
339 | /* Don't include the last field in the checksum. */ | |
e3b74723 | 340 | for (i = 0; i < max; i++) |
2f330caf MM |
341 | sum += msg[i]; |
342 | ||
343 | return sum; | |
344 | } | |
345 | ||
abf94566 | 346 | static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response, |
fee5f1ef MM |
347 | char *buf, ssize_t *size) |
348 | { | |
349 | unsigned int msg_type; | |
350 | unsigned int offset; | |
351 | void __iomem *ptr = NULL; | |
352 | ||
e3b74723 MM |
353 | /* There is no need to use this function for API v3 or later. */ |
354 | if (unlikely(priv->dpfe_api->version >= 3)) { | |
355 | return NULL; | |
356 | } | |
357 | ||
fee5f1ef MM |
358 | msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK; |
359 | offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK; | |
360 | ||
361 | /* | |
362 | * msg_type == 1: the offset is relative to the message RAM | |
363 | * msg_type == 0: the offset is relative to the data RAM (this is the | |
364 | * previous way of passing data) | |
365 | * msg_type is anything else: there's critical hardware problem | |
366 | */ | |
367 | switch (msg_type) { | |
368 | case 1: | |
369 | ptr = priv->regs + DCPU_MSG_RAM_START + offset; | |
370 | break; | |
371 | case 0: | |
372 | ptr = priv->dmem + offset; | |
373 | break; | |
374 | default: | |
375 | dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n", | |
376 | response); | |
377 | if (buf && size) | |
378 | *size = sprintf(buf, | |
379 | "FATAL: communication error with DCPU\n"); | |
380 | } | |
381 | ||
382 | return ptr; | |
383 | } | |
384 | ||
abf94566 | 385 | static void __finalize_command(struct brcmstb_dpfe_priv *priv) |
e3b74723 MM |
386 | { |
387 | unsigned int release_mbox; | |
388 | ||
389 | /* | |
390 | * It depends on the API version which MBOX register we have to write to | |
391 | * to signal we are done. | |
392 | */ | |
393 | release_mbox = (priv->dpfe_api->version < 3) | |
394 | ? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX; | |
395 | writel_relaxed(0, priv->regs + release_mbox); | |
396 | } | |
397 | ||
abf94566 | 398 | static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd, |
2f330caf MM |
399 | u32 result[]) |
400 | { | |
58a8499f | 401 | const u32 *msg = priv->dpfe_api->command[cmd]; |
2f330caf | 402 | void __iomem *regs = priv->regs; |
e3b74723 | 403 | unsigned int i, chksum, chksum_idx; |
2f330caf MM |
404 | int ret = 0; |
405 | u32 resp; | |
406 | ||
407 | if (cmd >= DPFE_CMD_MAX) | |
408 | return -1; | |
409 | ||
410 | mutex_lock(&priv->lock); | |
411 | ||
a7c25759 MM |
412 | /* Wait for DCPU to become ready */ |
413 | for (i = 0; i < DELAY_LOOP_MAX; i++) { | |
414 | resp = readl_relaxed(regs + REG_TO_HOST_MBOX); | |
415 | if (resp == 0) | |
416 | break; | |
417 | msleep(1); | |
418 | } | |
419 | if (resp != 0) { | |
420 | mutex_unlock(&priv->lock); | |
421 | return -ETIMEDOUT; | |
422 | } | |
423 | ||
5d06f53d FF |
424 | /* Compute checksum over the message */ |
425 | chksum_idx = msg[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1; | |
426 | chksum = get_msg_chksum(msg, chksum_idx); | |
427 | ||
2f330caf | 428 | /* Write command and arguments to message area */ |
5d06f53d FF |
429 | for (i = 0; i < MSG_FIELD_MAX; i++) { |
430 | if (i == chksum_idx) | |
431 | writel_relaxed(chksum, regs + DCPU_MSG_RAM(i)); | |
432 | else | |
433 | writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i)); | |
434 | } | |
2f330caf MM |
435 | |
436 | /* Tell DCPU there is a command waiting */ | |
437 | writel_relaxed(1, regs + REG_TO_DCPU_MBOX); | |
438 | ||
439 | /* Wait for DCPU to process the command */ | |
440 | for (i = 0; i < DELAY_LOOP_MAX; i++) { | |
441 | /* Read response code */ | |
442 | resp = readl_relaxed(regs + REG_TO_HOST_MBOX); | |
443 | if (resp > 0) | |
444 | break; | |
7ccd2ffc | 445 | msleep(1); |
2f330caf MM |
446 | } |
447 | ||
448 | if (i == DELAY_LOOP_MAX) { | |
449 | resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT); | |
450 | ret = -ffs(resp); | |
451 | } else { | |
452 | /* Read response data */ | |
453 | for (i = 0; i < MSG_FIELD_MAX; i++) | |
454 | result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i)); | |
e3b74723 | 455 | chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1; |
2f330caf MM |
456 | } |
457 | ||
458 | /* Tell DCPU we are done */ | |
e3b74723 | 459 | __finalize_command(priv); |
2f330caf MM |
460 | |
461 | mutex_unlock(&priv->lock); | |
462 | ||
463 | if (ret) | |
464 | return ret; | |
465 | ||
466 | /* Verify response */ | |
e3b74723 MM |
467 | chksum = get_msg_chksum(result, chksum_idx); |
468 | if (chksum != result[chksum_idx]) | |
2f330caf MM |
469 | resp = DCPU_RET_ERR_CHKSUM; |
470 | ||
471 | if (resp != DCPU_RET_SUCCESS) { | |
472 | resp &= ~DCPU_RET_ERROR_BIT; | |
473 | ret = -ffs(resp); | |
474 | } | |
475 | ||
476 | return ret; | |
477 | } | |
478 | ||
479 | /* Ensure that the firmware file loaded meets all the requirements. */ | |
480 | static int __verify_firmware(struct init_data *init, | |
481 | const struct firmware *fw) | |
482 | { | |
483 | const struct dpfe_firmware_header *header = (void *)fw->data; | |
484 | unsigned int dmem_size, imem_size, total_size; | |
485 | bool is_big_endian = false; | |
486 | const u32 *chksum_ptr; | |
487 | ||
488 | if (header->magic == DPFE_BE_MAGIC) | |
489 | is_big_endian = true; | |
490 | else if (header->magic != DPFE_LE_MAGIC) | |
491 | return ERR_INVALID_MAGIC; | |
492 | ||
493 | if (is_big_endian) { | |
494 | dmem_size = be32_to_cpu(header->dmem_size); | |
495 | imem_size = be32_to_cpu(header->imem_size); | |
496 | } else { | |
497 | dmem_size = le32_to_cpu(header->dmem_size); | |
498 | imem_size = le32_to_cpu(header->imem_size); | |
499 | } | |
500 | ||
501 | /* Data and instruction sections are 32 bit words. */ | |
502 | if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0) | |
503 | return ERR_INVALID_SIZE; | |
504 | ||
505 | /* | |
506 | * The header + the data section + the instruction section + the | |
507 | * checksum must be equal to the total firmware size. | |
508 | */ | |
509 | total_size = dmem_size + imem_size + sizeof(*header) + | |
510 | sizeof(*chksum_ptr); | |
511 | if (total_size != fw->size) | |
512 | return ERR_INVALID_SIZE; | |
513 | ||
514 | /* The checksum comes at the very end. */ | |
515 | chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size; | |
516 | ||
517 | init->is_big_endian = is_big_endian; | |
518 | init->dmem_len = dmem_size; | |
519 | init->imem_len = imem_size; | |
520 | init->chksum = (is_big_endian) | |
521 | ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr); | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | /* Verify checksum by reading back the firmware from co-processor RAM. */ | |
527 | static int __verify_fw_checksum(struct init_data *init, | |
abf94566 | 528 | struct brcmstb_dpfe_priv *priv, |
2f330caf MM |
529 | const struct dpfe_firmware_header *header, |
530 | u32 checksum) | |
531 | { | |
532 | u32 magic, sequence, version, sum; | |
533 | u32 __iomem *dmem = priv->dmem; | |
534 | u32 __iomem *imem = priv->imem; | |
535 | unsigned int i; | |
536 | ||
537 | if (init->is_big_endian) { | |
538 | magic = be32_to_cpu(header->magic); | |
539 | sequence = be32_to_cpu(header->sequence); | |
540 | version = be32_to_cpu(header->version); | |
541 | } else { | |
542 | magic = le32_to_cpu(header->magic); | |
543 | sequence = le32_to_cpu(header->sequence); | |
544 | version = le32_to_cpu(header->version); | |
545 | } | |
546 | ||
547 | sum = magic + sequence + version + init->dmem_len + init->imem_len; | |
548 | ||
549 | for (i = 0; i < init->dmem_len / sizeof(u32); i++) | |
550 | sum += readl_relaxed(dmem + i); | |
551 | ||
552 | for (i = 0; i < init->imem_len / sizeof(u32); i++) | |
553 | sum += readl_relaxed(imem + i); | |
554 | ||
555 | return (sum == checksum) ? 0 : -1; | |
556 | } | |
557 | ||
558 | static int __write_firmware(u32 __iomem *mem, const u32 *fw, | |
559 | unsigned int size, bool is_big_endian) | |
560 | { | |
561 | unsigned int i; | |
562 | ||
563 | /* Convert size to 32-bit words. */ | |
564 | size /= sizeof(u32); | |
565 | ||
566 | /* It is recommended to clear the firmware area first. */ | |
567 | for (i = 0; i < size; i++) | |
568 | writel_relaxed(0, mem + i); | |
569 | ||
570 | /* Now copy it. */ | |
571 | if (is_big_endian) { | |
572 | for (i = 0; i < size; i++) | |
573 | writel_relaxed(be32_to_cpu(fw[i]), mem + i); | |
574 | } else { | |
575 | for (i = 0; i < size; i++) | |
576 | writel_relaxed(le32_to_cpu(fw[i]), mem + i); | |
577 | } | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
ac2ea9cf | 582 | static int brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv *priv) |
2f330caf MM |
583 | { |
584 | const struct dpfe_firmware_header *header; | |
585 | unsigned int dmem_size, imem_size; | |
ac2ea9cf | 586 | struct device *dev = priv->dev; |
2f330caf | 587 | bool is_big_endian = false; |
2f330caf MM |
588 | const struct firmware *fw; |
589 | const u32 *dmem, *imem; | |
6ef972b1 | 590 | struct init_data init; |
2f330caf MM |
591 | const void *fw_blob; |
592 | int ret; | |
593 | ||
a56d339e MM |
594 | /* |
595 | * Skip downloading the firmware if the DCPU is already running and | |
596 | * responding to commands. | |
597 | */ | |
75d316e7 | 598 | if (is_dcpu_enabled(priv)) { |
a56d339e MM |
599 | u32 response[MSG_FIELD_MAX]; |
600 | ||
601 | ret = __send_command(priv, DPFE_CMD_GET_INFO, response); | |
602 | if (!ret) | |
603 | return 0; | |
604 | } | |
605 | ||
58a8499f MM |
606 | /* |
607 | * If the firmware filename is NULL it means the boot firmware has to | |
608 | * download the DCPU firmware for us. If that didn't work, we have to | |
609 | * bail, since downloading it ourselves wouldn't work either. | |
610 | */ | |
611 | if (!priv->dpfe_api->fw_name) | |
612 | return -ENODEV; | |
613 | ||
242fb2f1 MM |
614 | ret = firmware_request_nowarn(&fw, priv->dpfe_api->fw_name, dev); |
615 | /* | |
616 | * Defer the firmware download if the firmware file couldn't be found. | |
617 | * The root file system may not be available yet. | |
618 | */ | |
2f330caf | 619 | if (ret) |
242fb2f1 | 620 | return (ret == -ENOENT) ? -EPROBE_DEFER : ret; |
2f330caf | 621 | |
6ef972b1 | 622 | ret = __verify_firmware(&init, fw); |
2f330caf MM |
623 | if (ret) |
624 | return -EFAULT; | |
625 | ||
75d316e7 | 626 | __disable_dcpu(priv); |
2f330caf | 627 | |
6ef972b1 MM |
628 | is_big_endian = init.is_big_endian; |
629 | dmem_size = init.dmem_len; | |
630 | imem_size = init.imem_len; | |
2f330caf MM |
631 | |
632 | /* At the beginning of the firmware blob is a header. */ | |
633 | header = (struct dpfe_firmware_header *)fw->data; | |
634 | /* Void pointer to the beginning of the actual firmware. */ | |
635 | fw_blob = fw->data + sizeof(*header); | |
636 | /* IMEM comes right after the header. */ | |
637 | imem = fw_blob; | |
638 | /* DMEM follows after IMEM. */ | |
639 | dmem = fw_blob + imem_size; | |
640 | ||
641 | ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian); | |
642 | if (ret) | |
643 | return ret; | |
644 | ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian); | |
645 | if (ret) | |
646 | return ret; | |
647 | ||
6ef972b1 | 648 | ret = __verify_fw_checksum(&init, priv, header, init.chksum); |
2f330caf MM |
649 | if (ret) |
650 | return ret; | |
651 | ||
75d316e7 | 652 | __enable_dcpu(priv); |
2f330caf MM |
653 | |
654 | return 0; | |
655 | } | |
656 | ||
657 | static ssize_t generic_show(unsigned int command, u32 response[], | |
abf94566 | 658 | struct brcmstb_dpfe_priv *priv, char *buf) |
2f330caf | 659 | { |
2f330caf MM |
660 | int ret; |
661 | ||
2f330caf MM |
662 | if (!priv) |
663 | return sprintf(buf, "ERROR: driver private data not set\n"); | |
664 | ||
665 | ret = __send_command(priv, command, response); | |
666 | if (ret < 0) | |
667 | return sprintf(buf, "ERROR: %s\n", error_text[-ret]); | |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
672 | static ssize_t show_info(struct device *dev, struct device_attribute *devattr, | |
673 | char *buf) | |
674 | { | |
675 | u32 response[MSG_FIELD_MAX]; | |
abf94566 | 676 | struct brcmstb_dpfe_priv *priv; |
2f330caf | 677 | unsigned int info; |
9f2c4d95 | 678 | ssize_t ret; |
2f330caf | 679 | |
900c8f57 MM |
680 | priv = dev_get_drvdata(dev); |
681 | ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf); | |
2f330caf MM |
682 | if (ret) |
683 | return ret; | |
684 | ||
685 | info = response[MSG_ARG0]; | |
686 | ||
687 | return sprintf(buf, "%u.%u.%u.%u\n", | |
688 | (info >> 24) & 0xff, | |
689 | (info >> 16) & 0xff, | |
690 | (info >> 8) & 0xff, | |
691 | info & 0xff); | |
692 | } | |
693 | ||
694 | static ssize_t show_refresh(struct device *dev, | |
695 | struct device_attribute *devattr, char *buf) | |
696 | { | |
697 | u32 response[MSG_FIELD_MAX]; | |
698 | void __iomem *info; | |
abf94566 | 699 | struct brcmstb_dpfe_priv *priv; |
2f330caf MM |
700 | u8 refresh, sr_abort, ppre, thermal_offs, tuf; |
701 | u32 mr4; | |
9f2c4d95 | 702 | ssize_t ret; |
2f330caf | 703 | |
900c8f57 MM |
704 | priv = dev_get_drvdata(dev); |
705 | ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf); | |
2f330caf MM |
706 | if (ret) |
707 | return ret; | |
708 | ||
fee5f1ef MM |
709 | info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret); |
710 | if (!info) | |
711 | return ret; | |
2f330caf | 712 | |
78a6f5be | 713 | mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) & |
1ffc0b58 | 714 | DRAM_INFO_MR4_MASK; |
2f330caf MM |
715 | |
716 | refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK; | |
717 | sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK; | |
718 | ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK; | |
719 | thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK; | |
720 | tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK; | |
721 | ||
722 | return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n", | |
723 | readl_relaxed(info + DRAM_INFO_INTERVAL), | |
724 | refresh, sr_abort, ppre, thermal_offs, tuf, | |
725 | readl_relaxed(info + DRAM_INFO_ERROR)); | |
726 | } | |
727 | ||
728 | static ssize_t store_refresh(struct device *dev, struct device_attribute *attr, | |
729 | const char *buf, size_t count) | |
730 | { | |
731 | u32 response[MSG_FIELD_MAX]; | |
abf94566 | 732 | struct brcmstb_dpfe_priv *priv; |
2f330caf | 733 | void __iomem *info; |
2f330caf MM |
734 | unsigned long val; |
735 | int ret; | |
736 | ||
737 | if (kstrtoul(buf, 0, &val) < 0) | |
738 | return -EINVAL; | |
739 | ||
740 | priv = dev_get_drvdata(dev); | |
2f330caf MM |
741 | ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response); |
742 | if (ret) | |
743 | return ret; | |
744 | ||
fee5f1ef MM |
745 | info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL); |
746 | if (!info) | |
747 | return -EIO; | |
748 | ||
2f330caf MM |
749 | writel_relaxed(val, info + DRAM_INFO_INTERVAL); |
750 | ||
751 | return count; | |
752 | } | |
753 | ||
754 | static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr, | |
1ffc0b58 | 755 | char *buf) |
2f330caf MM |
756 | { |
757 | u32 response[MSG_FIELD_MAX]; | |
abf94566 | 758 | struct brcmstb_dpfe_priv *priv; |
2f330caf | 759 | void __iomem *info; |
9f2c4d95 | 760 | ssize_t ret; |
78a6f5be | 761 | u32 mr5, mr6, mr7, mr8, err; |
2f330caf | 762 | |
900c8f57 MM |
763 | priv = dev_get_drvdata(dev); |
764 | ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf); | |
2f330caf MM |
765 | if (ret) |
766 | return ret; | |
767 | ||
fee5f1ef MM |
768 | info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret); |
769 | if (!info) | |
770 | return ret; | |
2f330caf | 771 | |
78a6f5be MM |
772 | mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) & |
773 | DRAM_VENDOR_MASK; | |
774 | mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) & | |
775 | DRAM_VENDOR_MASK; | |
776 | mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) & | |
777 | DRAM_VENDOR_MASK; | |
778 | mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) & | |
779 | DRAM_VENDOR_MASK; | |
780 | err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK; | |
781 | ||
782 | return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err); | |
2f330caf MM |
783 | } |
784 | ||
e3b74723 MM |
785 | static ssize_t show_dram(struct device *dev, struct device_attribute *devattr, |
786 | char *buf) | |
787 | { | |
788 | u32 response[MSG_FIELD_MAX]; | |
abf94566 | 789 | struct brcmstb_dpfe_priv *priv; |
e3b74723 MM |
790 | ssize_t ret; |
791 | u32 mr4, mr5, mr6, mr7, mr8, err; | |
792 | ||
793 | priv = dev_get_drvdata(dev); | |
794 | ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf); | |
795 | if (ret) | |
796 | return ret; | |
797 | ||
798 | mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK; | |
799 | mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK; | |
800 | mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK; | |
801 | mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK; | |
802 | mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK; | |
803 | err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK; | |
804 | ||
805 | return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7, | |
806 | mr8, err); | |
2f330caf MM |
807 | } |
808 | ||
809 | static int brcmstb_dpfe_resume(struct platform_device *pdev) | |
810 | { | |
ac2ea9cf MM |
811 | struct brcmstb_dpfe_priv *priv = platform_get_drvdata(pdev); |
812 | ||
813 | return brcmstb_dpfe_download_firmware(priv); | |
2f330caf MM |
814 | } |
815 | ||
2f330caf MM |
816 | static int brcmstb_dpfe_probe(struct platform_device *pdev) |
817 | { | |
818 | struct device *dev = &pdev->dev; | |
abf94566 | 819 | struct brcmstb_dpfe_priv *priv; |
2f330caf | 820 | struct resource *res; |
2f330caf MM |
821 | int ret; |
822 | ||
823 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
824 | if (!priv) | |
825 | return -ENOMEM; | |
826 | ||
56ece3fa MM |
827 | priv->dev = dev; |
828 | ||
2f330caf MM |
829 | mutex_init(&priv->lock); |
830 | platform_set_drvdata(pdev, priv); | |
831 | ||
2f330caf MM |
832 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu"); |
833 | priv->regs = devm_ioremap_resource(dev, res); | |
834 | if (IS_ERR(priv->regs)) { | |
835 | dev_err(dev, "couldn't map DCPU registers\n"); | |
836 | return -ENODEV; | |
837 | } | |
838 | ||
839 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem"); | |
840 | priv->dmem = devm_ioremap_resource(dev, res); | |
841 | if (IS_ERR(priv->dmem)) { | |
842 | dev_err(dev, "Couldn't map DCPU data memory\n"); | |
843 | return -ENOENT; | |
844 | } | |
845 | ||
846 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem"); | |
847 | priv->imem = devm_ioremap_resource(dev, res); | |
848 | if (IS_ERR(priv->imem)) { | |
849 | dev_err(dev, "Couldn't map DCPU instruction memory\n"); | |
850 | return -ENOENT; | |
851 | } | |
852 | ||
58a8499f MM |
853 | priv->dpfe_api = of_device_get_match_data(dev); |
854 | if (unlikely(!priv->dpfe_api)) { | |
855 | /* | |
856 | * It should be impossible to end up here, but to be safe we | |
857 | * check anyway. | |
858 | */ | |
859 | dev_err(dev, "Couldn't determine API\n"); | |
860 | return -ENOENT; | |
861 | } | |
862 | ||
ac2ea9cf | 863 | ret = brcmstb_dpfe_download_firmware(priv); |
6ca5d2ba | 864 | if (ret) { |
242fb2f1 MM |
865 | if (ret != -EPROBE_DEFER) |
866 | dev_err(dev, "Couldn't download firmware -- %d\n", ret); | |
b1d0973e | 867 | return ret; |
6ca5d2ba | 868 | } |
2f330caf | 869 | |
5ef108b4 | 870 | ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs); |
b1d0973e | 871 | if (!ret) |
58a8499f MM |
872 | dev_info(dev, "registered with API v%d.\n", |
873 | priv->dpfe_api->version); | |
2f330caf | 874 | |
b1d0973e FF |
875 | return ret; |
876 | } | |
2f330caf | 877 | |
b1d0973e FF |
878 | static int brcmstb_dpfe_remove(struct platform_device *pdev) |
879 | { | |
abf94566 | 880 | struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev); |
5ef108b4 MM |
881 | |
882 | sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs); | |
2f330caf MM |
883 | |
884 | return 0; | |
2f330caf MM |
885 | } |
886 | ||
887 | static const struct of_device_id brcmstb_dpfe_of_match[] = { | |
e3b74723 MM |
888 | /* Use legacy API v2 for a select number of chips */ |
889 | { .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_v2 }, | |
890 | { .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_v2 }, | |
891 | { .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_v2 }, | |
892 | { .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_v2 }, | |
893 | /* API v3 is the default going forward */ | |
894 | { .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 }, | |
2f330caf MM |
895 | {} |
896 | }; | |
897 | MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match); | |
898 | ||
899 | static struct platform_driver brcmstb_dpfe_driver = { | |
900 | .driver = { | |
901 | .name = DRVNAME, | |
902 | .of_match_table = brcmstb_dpfe_of_match, | |
903 | }, | |
904 | .probe = brcmstb_dpfe_probe, | |
b1d0973e | 905 | .remove = brcmstb_dpfe_remove, |
2f330caf MM |
906 | .resume = brcmstb_dpfe_resume, |
907 | }; | |
908 | ||
909 | module_platform_driver(brcmstb_dpfe_driver); | |
910 | ||
911 | MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>"); | |
912 | MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver"); | |
913 | MODULE_LICENSE("GPL"); |