Merge tag 'x86_cpu_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[linux-block.git] / drivers / memory / Kconfig
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ec8f24b7 1# SPDX-License-Identifier: GPL-2.0-only
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2#
3# Memory devices
4#
5
6menuconfig MEMORY
7 bool "Memory Controller drivers"
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8 help
9 This option allows to enable specific memory controller drivers,
10 useful mostly on embedded systems. These could be controllers
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
12 vary from memory tuning and frequency scaling to enabling
13 access to attached peripherals through memory bus.
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14
15if MEMORY
16
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17config DDR
18 bool
19 help
20 Data from JEDEC specs for DDR SDRAM memories,
21 particularly the AC timing parameters and addressing
22 information. This data is useful for drivers handling
23 DDR SDRAM controllers.
24
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25config ARM_PL172_MPMC
26 tristate "ARM PL172 MPMC driver"
27 depends on ARM_AMBA && OF
28 help
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
30 If you have an embedded system with an AMBA bus and a PL172
31 controller, say Y or M here.
32
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33config ATMEL_SDRAMC
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
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35 default y if ARCH_AT91
36 depends on ARCH_AT91 || COMPILE_TEST
37 depends on OF
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38 help
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
41 Starting with the at91sam9g45, this controller supports SDR, DDR and
42 LP-DDR memories.
43
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44config ATMEL_EBI
45 bool "Atmel EBI driver"
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46 default y if ARCH_AT91
47 depends on ARCH_AT91 || COMPILE_TEST
48 depends on OF
6a4ec4cd 49 select MFD_SYSCON
8eb8c7d8 50 select MFD_ATMEL_SMC
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51 help
52 Driver for Atmel EBI controller.
53 Used to configure the EBI (external bus interface) when the device-
54 tree is used. This bus supports NANDs, external ethernet controller,
55 SRAMs, ATA devices, etc.
56
904ffa81 57config BRCMSTB_DPFE
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58 tristate "Broadcom STB DPFE driver"
59 default ARCH_BRCMSTB
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60 depends on ARCH_BRCMSTB || COMPILE_TEST
61 help
62 This driver provides access to the DPFE interface of Broadcom
63 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
64 provide current information about the system's RAM, for instance
65 the DRAM refresh rate. This can be used as an indirect indicator
66 for the DRAM's temperature. Slower refresh rate means cooler RAM,
67 higher refresh rate means hotter RAM.
68
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69config BRCMSTB_MEMC
70 tristate "Broadcom STB MEMC driver"
71 default ARCH_BRCMSTB
72 depends on ARCH_BRCMSTB || COMPILE_TEST
73 help
74 This driver provides a way to configure the Broadcom STB memory
75 controller and specifically control the Self Refresh Power Down
76 (SRPD) inactivity timeout.
77
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78config BT1_L2_CTL
79 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
80 depends on MIPS_BAIKAL_T1 || COMPILE_TEST
81 select MFD_SYSCON
82 help
83 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
84 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
85 possible to tune the L2 cache performance up by setting the data,
86 tags and way-select latencies of RAM access. This driver provides a
87 dt properties-based and sysfs interface for it.
88
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89config TI_AEMIF
90 tristate "Texas Instruments AEMIF driver"
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91 depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
92 depends on OF
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93 help
94 This driver is for the AEMIF module available in Texas Instruments
95 SoCs. AEMIF stands for Asynchronous External Memory Interface and
96 is intended to provide a glue-less interface to a variety of
97 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
98 of 256M bytes of any of these memories can be accessed at a given
99 time via four chip selects with 64M byte access per chip select.
100
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101config TI_EMIF
102 tristate "Texas Instruments EMIF driver"
ea0c0ad6 103 depends on ARCH_OMAP2PLUS || COMPILE_TEST
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104 select DDR
105 help
106 This driver is for the EMIF module available in Texas Instruments
107 SoCs. EMIF is an SDRAM controller that, based on its revision,
108 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
109 This driver takes care of only LPDDR2 memories presently. The
110 functions of the driver includes re-configuring AC timing
111 parameters and other settings during frequency, voltage and
112 temperature changes
113
18640193 114config OMAP_GPMC
854fd920 115 tristate "Texas Instruments OMAP SoC GPMC driver"
26cb1d2f 116 depends on OF_ADDRESS
67c7fc6c 117 depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
d2d00862 118 select GPIOLIB
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119 help
120 This driver is for the General Purpose Memory Controller (GPMC)
121 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
122 interfacing to a variety of asynchronous as well as synchronous
123 memory drives like NOR, NAND, OneNAND, SRAM.
124
63aa945b 125config OMAP_GPMC_DEBUG
be59b619 126 bool "Enable GPMC debug output and skip reset of GPMC during init"
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127 depends on OMAP_GPMC
128 help
129 Enables verbose debugging mostly to decode the bootloader provided
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130 timings. To preserve the bootloader provided timings, the reset
131 of GPMC is skipped during init. Enable this during development to
132 configure devices connected to the GPMC bus.
133
134 NOTE: In addition to matching the register setup with the bootloader
135 you also need to match the GPMC FCLK frequency used by the
136 bootloader or else the GPMC timings won't be identical with the
137 bootloader timings.
63aa945b 138
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139config TI_EMIF_SRAM
140 tristate "Texas Instruments EMIF SRAM driver"
d77d22d7 141 depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST)
ea0c0ad6 142 depends on SRAM
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143 help
144 This driver is for the EMIF module available on Texas Instruments
145 AM33XX and AM43XX SoCs and is required for PM. Certain parts of
146 the EMIF PM code must run from on-chip SRAM late in the suspend
147 sequence so this driver provides several relocatable PM functions
148 for the SoC PM code to use.
149
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150config FPGA_DFL_EMIF
151 tristate "FPGA DFL EMIF Driver"
152 depends on FPGA_DFL && HAS_IOMEM
153 help
154 This driver is for the EMIF private feature implemented under
155 FPGA Device Feature List (DFL) framework. It is used to expose
156 memory interface status information as well as memory clearing
157 control.
158
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159config MVEBU_DEVBUS
160 bool "Marvell EBU Device Bus Controller"
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161 default y if PLAT_ORION
162 depends on PLAT_ORION || COMPILE_TEST
163 depends on OF
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164 help
165 This driver is for the Device Bus controller available in some
166 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
167 Armada 370 and Armada XP. This controller allows to handle flash
168 devices such as NOR, NAND, SRAM, and FPGA.
169
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170config FSL_CORENET_CF
171 tristate "Freescale CoreNet Error Reporting"
ea0c0ad6 172 depends on FSL_SOC_BOOKE || COMPILE_TEST
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173 help
174 Say Y for reporting of errors from the Freescale CoreNet
175 Coherency Fabric. Errors reported include accesses to
176 physical addresses that mapped by no local access window
177 (LAW) or an invalid LAW, as well as bad cache state that
178 represents a coherency violation.
179
42d87b18 180config FSL_IFC
ea0c0ad6 181 bool "Freescale IFC driver" if COMPILE_TEST
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182 depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
183 depends on HAS_IOMEM
42d87b18 184
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185config JZ4780_NEMC
186 bool "Ingenic JZ4780 SoC NEMC driver"
94b3a02c 187 depends on MIPS || COMPILE_TEST
16909c81 188 depends on HAS_IOMEM && OF
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189 help
190 This driver is for the NAND/External Memory Controller (NEMC) in
191 the Ingenic JZ4780. This controller is used to handle external
192 memory devices such as NAND and SRAM.
193
cc8bbe1a 194config MTK_SMI
50fc8d92 195 tristate "MediaTek SoC Memory Controller driver" if COMPILE_TEST
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196 depends on ARCH_MEDIATEK || COMPILE_TEST
197 help
198 This driver is for the Memory Controller module in MediaTek SoCs,
199 mainly help enable/disable iommu and control the power domain and
200 clocks for each local arbiter.
201
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202config DA8XX_DDRCTL
203 bool "Texas Instruments da8xx DDR2/mDDR driver"
ea0c0ad6 204 depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST
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205 help
206 This driver is for the DDR2/mDDR Memory Controller present on
207 Texas Instruments da8xx SoCs. It's used to tweak various memory
208 controller configuration options.
209
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210config PL353_SMC
211 tristate "ARM PL35X Static Memory Controller(SMC) driver"
ea0c0ad6 212 default y if ARM
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213 depends on ARM || COMPILE_TEST
214 depends on ARM_AMBA
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215 help
216 This driver is for the ARM PL351/PL353 Static Memory
217 Controller(SMC) module.
218
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219config RENESAS_RPCIF
220 tristate "Renesas RPC-IF driver"
ea0c0ad6 221 depends on ARCH_RENESAS || COMPILE_TEST
ca7d8b98 222 select REGMAP_MMIO
4a26df8e 223 select RESET_CONTROLLER
ca7d8b98 224 help
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225 This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides
226 either SPI host or HyperFlash. You'll have to select individual
227 components under the corresponding menu.
ca7d8b98 228
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229config STM32_FMC2_EBI
230 tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
231 depends on MACH_STM32MP157 || COMPILE_TEST
232 select MFD_SYSCON
233 help
234 Select this option to enable the STM32 FMC2 External Bus Interface
235 controller. This driver configures the transactions with external
236 devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
237 SOCs containing the FMC2 External Bus Interface.
238
a8aabb91 239source "drivers/memory/samsung/Kconfig"
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240source "drivers/memory/tegra/Kconfig"
241
7ec94453 242endif