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V4L/DVB (4397): Add tda10086 support for TT DVB-S-1401
[linux-2.6-block.git] / drivers / media / video / saa7134 / saa7134-dvb.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 *
3 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
4 *
86ddd96f
MCC		 5 * Extended 3 / 2005 by Hartmut Hackmann to support various
6 * cards with the tda10046 DVB-T channel decoder
7 *
1da177e4
LT		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/delay.h>
29#include <linux/kthread.h>
30#include <linux/suspend.h>
31
32#include "saa7134-reg.h"
33#include "saa7134.h"
5e453dc7 34#include <media/v4l2-common.h>
a78d0bfa 35#include "dvb-pll.h"
1da177e4 36
1f10c7af
AQ		 37#include "mt352.h"
38#include "mt352_priv.h" /* FIXME */
39#include "tda1004x.h"
40#include "nxt200x.h"
1da177e4
LT		 41
42MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
43MODULE_LICENSE("GPL");
44
45static unsigned int antenna_pwr = 0;
86ddd96f 46
1da177e4
LT		 47module_param(antenna_pwr, int, 0444);
48MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)");
49
50/* ------------------------------------------------------------------ */
1da177e4
LT		 51static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
52{
53 u32 ok;
54
55 if (!on) {
56 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26));
57 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
58 return 0;
59 }
60
61 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26));
62 saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
63 udelay(10);
64
65 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 28));
66 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));
67 udelay(10);
68 saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));
69 udelay(10);
70 ok = saa_readl(SAA7134_GPIO_GPSTATUS0) & (1 << 27);
71 printk("%s: %s %s\n", dev->name, __FUNCTION__,
72 ok ? "on" : "off");
73
74 if (!ok)
75 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
76 return ok;
77}
78
79static int mt352_pinnacle_init(struct dvb_frontend* fe)
80{
81 static u8 clock_config [] = { CLOCK_CTL, 0x3d, 0x28 };
82 static u8 reset [] = { RESET, 0x80 };
83 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
84 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 };
85 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };
86 static u8 fsm_ctl_cfg[] = { 0x7b, 0x04 };
87 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x0f };
88 static u8 scan_ctl_cfg [] = { SCAN_CTL, 0x0d };
89 static u8 irq_cfg [] = { INTERRUPT_EN_0, 0x00, 0x00, 0x00, 0x00 };
90 struct saa7134_dev *dev= fe->dvb->priv;
91
92 printk("%s: %s called\n",dev->name,__FUNCTION__);
93
94 mt352_write(fe, clock_config, sizeof(clock_config));
95 udelay(200);
96 mt352_write(fe, reset, sizeof(reset));
97 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
98 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
99 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
100 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
101
102 mt352_write(fe, fsm_ctl_cfg, sizeof(fsm_ctl_cfg));
103 mt352_write(fe, scan_ctl_cfg, sizeof(scan_ctl_cfg));
104 mt352_write(fe, irq_cfg, sizeof(irq_cfg));
df8cf706 105
1da177e4
LT		 106 return 0;
107}
108
a78d0bfa
JAR		 109static int mt352_aver777_init(struct dvb_frontend* fe)
110{
111 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d };
112 static u8 reset [] = { RESET, 0x80 };
113 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
114 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 };
115 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 };
116
117 mt352_write(fe, clock_config, sizeof(clock_config));
118 udelay(200);
119 mt352_write(fe, reset, sizeof(reset));
120 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
121 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
122 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
123
124 return 0;
125}
126
0463f12c
AQ		 127static int mt352_pinnacle_tuner_set_params(struct dvb_frontend* fe,
128 struct dvb_frontend_parameters* params)
1da177e4 129{
df8cf706
HH		 130 u8 off[] = { 0x00, 0xf1};
131 u8 on[] = { 0x00, 0x71};
132 struct i2c_msg msg = {.addr=0x43, .flags=0, .buf=off, .len = sizeof(off)};
133
1da177e4
LT		 134 struct saa7134_dev *dev = fe->dvb->priv;
135 struct v4l2_frequency f;
136
137 /* set frequency (mt2050) */
138 f.tuner = 0;
139 f.type = V4L2_TUNER_DIGITAL_TV;
140 f.frequency = params->frequency / 1000 * 16 / 1000;
dea74869
PB		 141 if (fe->ops.i2c_gate_ctrl)
142 fe->ops.i2c_gate_ctrl(fe, 1);
df8cf706 143 i2c_transfer(&dev->i2c_adap, &msg, 1);
1da177e4 144 saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f);
df8cf706 145 msg.buf = on;
dea74869
PB		 146 if (fe->ops.i2c_gate_ctrl)
147 fe->ops.i2c_gate_ctrl(fe, 1);
df8cf706 148 i2c_transfer(&dev->i2c_adap, &msg, 1);
1da177e4
LT		 149
150 pinnacle_antenna_pwr(dev, antenna_pwr);
151
152 /* mt352 setup */
0463f12c 153 return mt352_pinnacle_init(fe);
1da177e4
LT		 154}
155
bd4956b8 156static int mt352_aver777_tuner_calc_regs(struct dvb_frontend *fe, struct dvb_frontend_parameters *params, u8* pllbuf, int buf_len)
a78d0bfa 157{
a79ddae9
AQ		 158 if (buf_len < 5)
159 return -EINVAL;
160
161 pllbuf[0] = 0x61;
a78d0bfa
JAR		 162 dvb_pll_configure(&dvb_pll_philips_td1316, pllbuf+1,
163 params->frequency,
164 params->u.ofdm.bandwidth);
a79ddae9 165 return 5;
a78d0bfa
JAR		 166}
167
1da177e4
LT		 168static struct mt352_config pinnacle_300i = {
169 .demod_address = 0x3c >> 1,
170 .adc_clock = 20333,
171 .if2 = 36150,
172 .no_tuner = 1,
173 .demod_init = mt352_pinnacle_init,
1da177e4 174};
a78d0bfa
JAR		 175
176static struct mt352_config avermedia_777 = {
177 .demod_address = 0xf,
178 .demod_init = mt352_aver777_init,
a78d0bfa 179};
1da177e4
LT		 180
181/* ------------------------------------------------------------------ */
2cf36ac4 182static int philips_tda6651_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
1da177e4
LT		 183{
184 struct saa7134_dev *dev = fe->dvb->priv;
86ddd96f 185 u8 tuner_buf[4];
2cf36ac4 186 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len =
86ddd96f
MCC		 187 sizeof(tuner_buf) };
188 int tuner_frequency = 0;
189 u8 band, cp, filter;
190
191 /* determine charge pump */
192 tuner_frequency = params->frequency + 36166000;
193 if (tuner_frequency < 87000000)
194 return -EINVAL;
195 else if (tuner_frequency < 130000000)
196 cp = 3;
197 else if (tuner_frequency < 160000000)
198 cp = 5;
199 else if (tuner_frequency < 200000000)
200 cp = 6;
201 else if (tuner_frequency < 290000000)
202 cp = 3;
203 else if (tuner_frequency < 420000000)
204 cp = 5;
205 else if (tuner_frequency < 480000000)
206 cp = 6;
207 else if (tuner_frequency < 620000000)
208 cp = 3;
209 else if (tuner_frequency < 830000000)
210 cp = 5;
211 else if (tuner_frequency < 895000000)
212 cp = 7;
213 else
214 return -EINVAL;
215
216 /* determine band */
217 if (params->frequency < 49000000)
218 return -EINVAL;
219 else if (params->frequency < 161000000)
220 band = 1;
221 else if (params->frequency < 444000000)
222 band = 2;
223 else if (params->frequency < 861000000)
224 band = 4;
225 else
226 return -EINVAL;
227
228 /* setup PLL filter */
229 switch (params->u.ofdm.bandwidth) {
230 case BANDWIDTH_6_MHZ:
231 filter = 0;
232 break;
233
234 case BANDWIDTH_7_MHZ:
235 filter = 0;
236 break;
237
238 case BANDWIDTH_8_MHZ:
239 filter = 1;
240 break;
1da177e4 241
86ddd96f
MCC		 242 default:
243 return -EINVAL;
244 }
245
246 /* calculate divisor
247 * ((36166000+((1000000/6)/2)) + Finput)/(1000000/6)
1da177e4 248 */
86ddd96f
MCC		 249 tuner_frequency = (((params->frequency / 1000) * 6) + 217496) / 1000;
250
251 /* setup tuner buffer */
252 tuner_buf[0] = (tuner_frequency >> 8) & 0x7f;
253 tuner_buf[1] = tuner_frequency & 0xff;
254 tuner_buf[2] = 0xca;
255 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
256
dea74869
PB		 257 if (fe->ops.i2c_gate_ctrl)
258 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 259 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
260 return -EIO;
2cf36ac4
HH		 261 msleep(1);
262 return 0;
263}
264
265static int philips_tda6651_pll_init(u8 addr, struct dvb_frontend *fe)
266{
267 struct saa7134_dev *dev = fe->dvb->priv;
268 static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab };
269 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) };
86ddd96f 270
2cf36ac4 271 /* setup PLL configuration */
dea74869
PB		 272 if (fe->ops.i2c_gate_ctrl)
273 fe->ops.i2c_gate_ctrl(fe, 1);
2cf36ac4
HH		 274 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
275 return -EIO;
86ddd96f 276 msleep(1);
2cf36ac4 277
1da177e4
LT		 278 return 0;
279}
280
2cf36ac4
HH		 281/* ------------------------------------------------------------------ */
282
a79ddae9 283static int philips_tu1216_tuner_60_init(struct dvb_frontend *fe)
2cf36ac4
HH		 284{
285 return philips_tda6651_pll_init(0x60, fe);
286}
287
a79ddae9 288static int philips_tu1216_tuner_60_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 289{
290 return philips_tda6651_pll_set(0x60, fe, params);
291}
292
86ddd96f
MCC		 293static int philips_tu1216_request_firmware(struct dvb_frontend *fe,
294 const struct firmware **fw, char *name)
1da177e4
LT		 295{
296 struct saa7134_dev *dev = fe->dvb->priv;
297 return request_firmware(fw, name, &dev->pci->dev);
298}
299
2cf36ac4 300static struct tda1004x_config philips_tu1216_60_config = {
86ddd96f
MCC		 301
302 .demod_address = 0x8,
303 .invert = 1,
2cf36ac4 304 .invert_oclk = 0,
86ddd96f
MCC		 305 .xtal_freq = TDA10046_XTAL_4M,
306 .agc_config = TDA10046_AGC_DEFAULT,
307 .if_freq = TDA10046_FREQ_3617,
86ddd96f
MCC		 308 .request_firmware = philips_tu1216_request_firmware,
309};
310
311/* ------------------------------------------------------------------ */
312
a79ddae9 313static int philips_tu1216_tuner_61_init(struct dvb_frontend *fe)
2cf36ac4
HH		 314{
315 return philips_tda6651_pll_init(0x61, fe);
316}
317
a79ddae9 318static int philips_tu1216_tuner_61_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 319{
320 return philips_tda6651_pll_set(0x61, fe, params);
321}
322
323static struct tda1004x_config philips_tu1216_61_config = {
324
325 .demod_address = 0x8,
326 .invert = 1,
327 .invert_oclk = 0,
328 .xtal_freq = TDA10046_XTAL_4M,
329 .agc_config = TDA10046_AGC_DEFAULT,
330 .if_freq = TDA10046_FREQ_3617,
2cf36ac4
HH		 331 .request_firmware = philips_tu1216_request_firmware,
332};
333
334/* ------------------------------------------------------------------ */
335
a79ddae9 336static int philips_europa_tuner_init(struct dvb_frontend *fe)
2cf36ac4
HH		 337{
338 struct saa7134_dev *dev = fe->dvb->priv;
339 static u8 msg[] = { 0x0b, 0xf5, 0x86, 0xab };
340 struct i2c_msg init_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) };
341
342 /* setup PLL configuration */
dea74869
PB		 343 if (fe->ops.i2c_gate_ctrl)
344 fe->ops.i2c_gate_ctrl(fe, 1);
2cf36ac4
HH		 345 if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)
346 return -EIO;
347 msleep(1);
348
349 /* switch the board to dvb mode */
350 init_msg.addr = 0x43;
351 init_msg.len = 0x02;
352 msg[0] = 0x00;
353 msg[1] = 0x40;
dea74869
PB		 354 if (fe->ops.i2c_gate_ctrl)
355 fe->ops.i2c_gate_ctrl(fe, 1);
2cf36ac4
HH		 356 if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)
357 return -EIO;
358
359 return 0;
360}
361
a79ddae9 362static int philips_td1316_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 363{
364 return philips_tda6651_pll_set(0x61, fe, params);
365}
366
a79ddae9 367static int philips_europa_tuner_sleep(struct dvb_frontend *fe)
2cf36ac4
HH		 368{
369 struct saa7134_dev *dev = fe->dvb->priv;
370 /* this message actually turns the tuner back to analog mode */
371 static u8 msg[] = { 0x0b, 0xdc, 0x86, 0xa4 };
372 struct i2c_msg analog_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) };
373
374 i2c_transfer(&dev->i2c_adap, &analog_msg, 1);
375 msleep(1);
376
377 /* switch the board to analog mode */
378 analog_msg.addr = 0x43;
379 analog_msg.len = 0x02;
380 msg[0] = 0x00;
381 msg[1] = 0x14;
dea74869
PB		 382 if (fe->ops.i2c_gate_ctrl)
383 fe->ops.i2c_gate_ctrl(fe, 1);
2cf36ac4 384 i2c_transfer(&dev->i2c_adap, &analog_msg, 1);
a79ddae9
AQ		 385 return 0;
386}
387
388static int philips_europa_demod_sleep(struct dvb_frontend *fe)
389{
390 struct saa7134_dev *dev = fe->dvb->priv;
391
392 if (dev->original_demod_sleep)
393 dev->original_demod_sleep(fe);
dea74869 394 fe->ops.i2c_gate_ctrl(fe, 1);
a79ddae9 395 return 0;
2cf36ac4
HH		 396}
397
398static struct tda1004x_config philips_europa_config = {
399
400 .demod_address = 0x8,
401 .invert = 0,
402 .invert_oclk = 0,
403 .xtal_freq = TDA10046_XTAL_4M,
404 .agc_config = TDA10046_AGC_IFO_AUTO_POS,
405 .if_freq = TDA10046_FREQ_052,
2cf36ac4
HH		 406 .request_firmware = NULL,
407};
408
409/* ------------------------------------------------------------------ */
86ddd96f 410
a79ddae9 411static int philips_fmd1216_tuner_init(struct dvb_frontend *fe)
86ddd96f
MCC		 412{
413 struct saa7134_dev *dev = fe->dvb->priv;
414 /* this message is to set up ATC and ALC */
415 static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 };
416 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) };
417
dea74869
PB		 418 if (fe->ops.i2c_gate_ctrl)
419 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 420 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
421 return -EIO;
422 msleep(1);
423
424 return 0;
425}
426
a79ddae9 427static int philips_fmd1216_tuner_sleep(struct dvb_frontend *fe)
86ddd96f
MCC		 428{
429 struct saa7134_dev *dev = fe->dvb->priv;
430 /* this message actually turns the tuner back to analog mode */
431 static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0x60 };
432 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) };
433
dea74869
PB		 434 if (fe->ops.i2c_gate_ctrl)
435 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 436 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
437 msleep(1);
438 fmd1216_init[2] = 0x86;
439 fmd1216_init[3] = 0x54;
dea74869
PB		 440 if (fe->ops.i2c_gate_ctrl)
441 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 442 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
443 msleep(1);
a79ddae9 444 return 0;
86ddd96f
MCC		 445}
446
a79ddae9 447static int philips_fmd1216_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
86ddd96f
MCC		 448{
449 struct saa7134_dev *dev = fe->dvb->priv;
450 u8 tuner_buf[4];
451 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = tuner_buf,.len =
452 sizeof(tuner_buf) };
453 int tuner_frequency = 0;
454 int divider = 0;
455 u8 band, mode, cp;
456
457 /* determine charge pump */
458 tuner_frequency = params->frequency + 36130000;
459 if (tuner_frequency < 87000000)
460 return -EINVAL;
461 /* low band */
462 else if (tuner_frequency < 180000000) {
463 band = 1;
464 mode = 7;
465 cp = 0;
466 } else if (tuner_frequency < 195000000) {
467 band = 1;
468 mode = 6;
469 cp = 1;
470 /* mid band */
471 } else if (tuner_frequency < 366000000) {
472 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
473 band = 10;
474 } else {
475 band = 2;
476 }
477 mode = 7;
478 cp = 0;
479 } else if (tuner_frequency < 478000000) {
480 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
481 band = 10;
482 } else {
483 band = 2;
484 }
485 mode = 6;
486 cp = 1;
487 /* high band */
488 } else if (tuner_frequency < 662000000) {
489 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
490 band = 12;
491 } else {
492 band = 4;
493 }
494 mode = 7;
495 cp = 0;
496 } else if (tuner_frequency < 840000000) {
497 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
498 band = 12;
499 } else {
500 band = 4;
501 }
502 mode = 6;
503 cp = 1;
504 } else {
505 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
506 band = 12;
507 } else {
508 band = 4;
509 }
510 mode = 7;
511 cp = 1;
512
513 }
514 /* calculate divisor */
515 /* ((36166000 + Finput) / 166666) rounded! */
516 divider = (tuner_frequency + 83333) / 166667;
517
518 /* setup tuner buffer */
519 tuner_buf[0] = (divider >> 8) & 0x7f;
520 tuner_buf[1] = divider & 0xff;
521 tuner_buf[2] = 0x80 | (cp << 6) | (mode << 3) | 4;
522 tuner_buf[3] = 0x40 | band;
523
dea74869
PB		 524 if (fe->ops.i2c_gate_ctrl)
525 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 526 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
527 return -EIO;
528 return 0;
529}
530
408b664a 531static struct tda1004x_config medion_cardbus = {
86ddd96f
MCC		 532 .demod_address = 0x08,
533 .invert = 1,
534 .invert_oclk = 0,
535 .xtal_freq = TDA10046_XTAL_16M,
536 .agc_config = TDA10046_AGC_IFO_AUTO_NEG,
537 .if_freq = TDA10046_FREQ_3613,
86ddd96f
MCC		 538 .request_firmware = NULL,
539};
540
541/* ------------------------------------------------------------------ */
542
543struct tda827x_data {
544 u32 lomax;
545 u8 spd;
546 u8 bs;
547 u8 bp;
548 u8 cp;
549 u8 gc3;
550 u8 div1p5;
551};
552
553static struct tda827x_data tda827x_dvbt[] = {
554 { .lomax = 62000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
555 { .lomax = 66000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
556 { .lomax = 76000000, .spd = 3, .bs = 1, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
557 { .lomax = 84000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
558 { .lomax = 93000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
559 { .lomax = 98000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
560 { .lomax = 109000000, .spd = 3, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
561 { .lomax = 123000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
562 { .lomax = 133000000, .spd = 2, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
563 { .lomax = 151000000, .spd = 2, .bs = 1, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
564 { .lomax = 154000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
565 { .lomax = 181000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 0, .div1p5 = 0},
566 { .lomax = 185000000, .spd = 2, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
567 { .lomax = 217000000, .spd = 2, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
568 { .lomax = 244000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
569 { .lomax = 265000000, .spd = 1, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
570 { .lomax = 302000000, .spd = 1, .bs = 1, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
571 { .lomax = 324000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
572 { .lomax = 370000000, .spd = 1, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
573 { .lomax = 454000000, .spd = 1, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
574 { .lomax = 493000000, .spd = 0, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
575 { .lomax = 530000000, .spd = 0, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
576 { .lomax = 554000000, .spd = 0, .bs = 1, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
577 { .lomax = 604000000, .spd = 0, .bs = 1, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
578 { .lomax = 696000000, .spd = 0, .bs = 2, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
579 { .lomax = 740000000, .spd = 0, .bs = 2, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
580 { .lomax = 820000000, .spd = 0, .bs = 3, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
581 { .lomax = 865000000, .spd = 0, .bs = 3, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
582 { .lomax = 0, .spd = 0, .bs = 0, .bp = 0, .cp = 0, .gc3 = 0, .div1p5 = 0}
583};
584
a79ddae9 585static int philips_tda827x_tuner_init(struct dvb_frontend *fe)
86ddd96f
MCC		 586{
587 return 0;
588}
589
a79ddae9 590static int philips_tda827x_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
86ddd96f
MCC		 591{
592 struct saa7134_dev *dev = fe->dvb->priv;
593 u8 tuner_buf[14];
594
595 struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tuner_buf,
f2421ca3 596 .len = sizeof(tuner_buf) };
86ddd96f
MCC		 597 int i, tuner_freq, if_freq;
598 u32 N;
599 switch (params->u.ofdm.bandwidth) {
600 case BANDWIDTH_6_MHZ:
601 if_freq = 4000000;
602 break;
603 case BANDWIDTH_7_MHZ:
604 if_freq = 4500000;
605 break;
606 default: /* 8 MHz or Auto */
607 if_freq = 5000000;
608 break;
609 }
610 tuner_freq = params->frequency + if_freq;
611
612 i = 0;
613 while (tda827x_dvbt[i].lomax < tuner_freq) {
614 if(tda827x_dvbt[i + 1].lomax == 0)
615 break;
616 i++;
617 }
618
619 N = ((tuner_freq + 125000) / 250000) << (tda827x_dvbt[i].spd + 2);
620 tuner_buf[0] = 0;
621 tuner_buf[1] = (N>>8) | 0x40;
622 tuner_buf[2] = N & 0xff;
623 tuner_buf[3] = 0;
624 tuner_buf[4] = 0x52;
625 tuner_buf[5] = (tda827x_dvbt[i].spd << 6) + (tda827x_dvbt[i].div1p5 << 5) +
626 (tda827x_dvbt[i].bs << 3) + tda827x_dvbt[i].bp;
627 tuner_buf[6] = (tda827x_dvbt[i].gc3 << 4) + 0x8f;
628 tuner_buf[7] = 0xbf;
629 tuner_buf[8] = 0x2a;
630 tuner_buf[9] = 0x05;
631 tuner_buf[10] = 0xff;
632 tuner_buf[11] = 0x00;
633 tuner_buf[12] = 0x00;
634 tuner_buf[13] = 0x40;
635
636 tuner_msg.len = 14;
dea74869
PB		 637 if (fe->ops.i2c_gate_ctrl)
638 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 639 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
640 return -EIO;
641
642 msleep(500);
643 /* correct CP value */
644 tuner_buf[0] = 0x30;
645 tuner_buf[1] = 0x50 + tda827x_dvbt[i].cp;
646 tuner_msg.len = 2;
dea74869
PB		 647 if (fe->ops.i2c_gate_ctrl)
648 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 649 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
650
651 return 0;
652}
653
a79ddae9 654static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe)
86ddd96f
MCC		 655{
656 struct saa7134_dev *dev = fe->dvb->priv;
657 static u8 tda827x_sleep[] = { 0x30, 0xd0};
658 struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tda827x_sleep,
f2421ca3 659 .len = sizeof(tda827x_sleep) };
dea74869
PB		 660 if (fe->ops.i2c_gate_ctrl)
661 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f 662 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
a79ddae9 663 return 0;
86ddd96f
MCC		 664}
665
666static struct tda1004x_config tda827x_lifeview_config = {
667 .demod_address = 0x08,
668 .invert = 1,
669 .invert_oclk = 0,
670 .xtal_freq = TDA10046_XTAL_16M,
671 .agc_config = TDA10046_AGC_TDA827X,
672 .if_freq = TDA10046_FREQ_045,
86ddd96f 673 .request_firmware = NULL,
1da177e4 674};
90e9df7f
HH		 675
676/* ------------------------------------------------------------------ */
677
678struct tda827xa_data {
679 u32 lomax;
680 u8 svco;
681 u8 spd;
682 u8 scr;
683 u8 sbs;
684 u8 gc3;
685};
686
687static struct tda827xa_data tda827xa_dvbt[] = {
688 { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 1},
689 { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
690 { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
691 { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
692 { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1},
693 { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
694 { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
695 { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
696 { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
697 { .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
698 { .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
699 { .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
700 { .lomax = 290000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
701 { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
702 { .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
703 { .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
704 { .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
705 { .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
706 { .lomax = 550000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
707 { .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
708 { .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
709 { .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
710 { .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
711 { .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
712 { .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
713 { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0},
714 { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}};
715
716
717static int philips_tda827xa_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
718{
719 struct saa7134_dev *dev = fe->dvb->priv;
720 u8 tuner_buf[14];
721 unsigned char reg2[2];
722
723 struct i2c_msg msg = {.addr = addr,.flags = 0,.buf = tuner_buf};
724 int i, tuner_freq, if_freq;
725 u32 N;
726
727 switch (params->u.ofdm.bandwidth) {
728 case BANDWIDTH_6_MHZ:
729 if_freq = 4000000;
730 break;
731 case BANDWIDTH_7_MHZ:
732 if_freq = 4500000;
733 break;
734 default: /* 8 MHz or Auto */
735 if_freq = 5000000;
736 break;
737 }
738 tuner_freq = params->frequency + if_freq;
739
740 i = 0;
741 while (tda827xa_dvbt[i].lomax < tuner_freq) {
742 if(tda827xa_dvbt[i + 1].lomax == 0)
743 break;
744 i++;
745 }
746
747 N = ((tuner_freq + 31250) / 62500) << tda827xa_dvbt[i].spd;
748 tuner_buf[0] = 0; // subaddress
749 tuner_buf[1] = N >> 8;
750 tuner_buf[2] = N & 0xff;
751 tuner_buf[3] = 0;
752 tuner_buf[4] = 0x16;
753 tuner_buf[5] = (tda827xa_dvbt[i].spd << 5) + (tda827xa_dvbt[i].svco << 3) +
754 tda827xa_dvbt[i].sbs;
755 tuner_buf[6] = 0x4b + (tda827xa_dvbt[i].gc3 << 4);
756 tuner_buf[7] = 0x0c;
757 tuner_buf[8] = 0x06;
758 tuner_buf[9] = 0x24;
759 tuner_buf[10] = 0xff;
760 tuner_buf[11] = 0x60;
761 tuner_buf[12] = 0x00;
762 tuner_buf[13] = 0x39; // lpsel
763 msg.len = 14;
dea74869
PB		 764 if (fe->ops.i2c_gate_ctrl)
765 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 766 if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
767 return -EIO;
768
769 msg.buf= reg2;
770 msg.len = 2;
771 reg2[0] = 0x60;
772 reg2[1] = 0x3c;
dea74869
PB		 773 if (fe->ops.i2c_gate_ctrl)
774 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 775 i2c_transfer(&dev->i2c_adap, &msg, 1);
776
777 reg2[0] = 0xa0;
778 reg2[1] = 0x40;
dea74869
PB		 779 if (fe->ops.i2c_gate_ctrl)
780 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 781 i2c_transfer(&dev->i2c_adap, &msg, 1);
782
783 msleep(2);
784 /* correct CP value */
785 reg2[0] = 0x30;
786 reg2[1] = 0x10 + tda827xa_dvbt[i].scr;
787 msg.len = 2;
dea74869
PB		 788 if (fe->ops.i2c_gate_ctrl)
789 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 790 i2c_transfer(&dev->i2c_adap, &msg, 1);
791
792 msleep(550);
793 reg2[0] = 0x50;
794 reg2[1] = 0x4f + (tda827xa_dvbt[i].gc3 << 4);
dea74869
PB		 795 if (fe->ops.i2c_gate_ctrl)
796 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 797 i2c_transfer(&dev->i2c_adap, &msg, 1);
798
799 return 0;
800
801}
802
a79ddae9 803static int philips_tda827xa_tuner_sleep(u8 addr, struct dvb_frontend *fe)
90e9df7f
HH		 804{
805 struct saa7134_dev *dev = fe->dvb->priv;
806 static u8 tda827xa_sleep[] = { 0x30, 0x90};
807 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tda827xa_sleep,
f1bcef88 808 .len = sizeof(tda827xa_sleep) };
dea74869
PB		 809 if (fe->ops.i2c_gate_ctrl)
810 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f 811 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
a79ddae9 812 return 0;
90e9df7f
HH		 813}
814
815/* ------------------------------------------------------------------ */
816
a79ddae9 817static int philips_tiger_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
90e9df7f
HH		 818{
819 int ret;
820 struct saa7134_dev *dev = fe->dvb->priv;
821 static u8 tda8290_close[] = { 0x21, 0xc0};
822 static u8 tda8290_open[] = { 0x21, 0x80};
823 struct i2c_msg tda8290_msg = {.addr = 0x4b,.flags = 0, .len = 2};
a79ddae9 824
90e9df7f
HH		 825 /* close tda8290 i2c bridge */
826 tda8290_msg.buf = tda8290_close;
827 ret = i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1);
828 if (ret != 1)
829 return -EIO;
830 msleep(20);
831 ret = philips_tda827xa_pll_set(0x61, fe, params);
832 if (ret != 0)
833 return ret;
834 /* open tda8290 i2c bridge */
835 tda8290_msg.buf = tda8290_open;
836 i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1);
837 return ret;
2d6b5f62 838}
90e9df7f 839
a79ddae9 840static int philips_tiger_tuner_init(struct dvb_frontend *fe)
90e9df7f
HH		 841{
842 struct saa7134_dev *dev = fe->dvb->priv;
843 static u8 data[] = { 0x3c, 0x33, 0x6a};
844 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
845
846 if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
847 return -EIO;
848 return 0;
849}
850
a79ddae9 851static int philips_tiger_tuner_sleep(struct dvb_frontend *fe)
90e9df7f
HH		 852{
853 struct saa7134_dev *dev = fe->dvb->priv;
854 static u8 data[] = { 0x3c, 0x33, 0x68};
855 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
856
857 i2c_transfer(&dev->i2c_adap, &msg, 1);
a79ddae9
AQ		 858 philips_tda827xa_tuner_sleep( 0x61, fe);
859 return 0;
90e9df7f
HH		 860}
861
862static struct tda1004x_config philips_tiger_config = {
863 .demod_address = 0x08,
864 .invert = 1,
865 .invert_oclk = 0,
866 .xtal_freq = TDA10046_XTAL_16M,
867 .agc_config = TDA10046_AGC_TDA827X,
868 .if_freq = TDA10046_FREQ_045,
90e9df7f
HH		 869 .request_firmware = NULL,
870};
871
df42eaf2
HH		 872/* ------------------------------------------------------------------ */
873
a79ddae9 874static int lifeview_trio_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
420f32fe
NS		 875{
876 int ret;
877
878 ret = philips_tda827xa_pll_set(0x60, fe, params);
879 return ret;
880}
881
a79ddae9 882static int lifeview_trio_tuner_sleep(struct dvb_frontend *fe)
420f32fe 883{
a79ddae9 884 philips_tda827xa_tuner_sleep(0x60, fe);
420f32fe
NS		 885 return 0;
886}
887
420f32fe
NS		 888static struct tda1004x_config lifeview_trio_config = {
889 .demod_address = 0x09,
890 .invert = 1,
891 .invert_oclk = 0,
892 .xtal_freq = TDA10046_XTAL_16M,
893 .agc_config = TDA10046_AGC_TDA827X_GPL,
894 .if_freq = TDA10046_FREQ_045,
420f32fe
NS		 895 .request_firmware = NULL,
896};
897
898/* ------------------------------------------------------------------ */
899
a79ddae9 900static int ads_duo_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
df42eaf2
HH		 901{
902 int ret;
903
904 ret = philips_tda827xa_pll_set(0x61, fe, params);
905 return ret;
2d6b5f62 906}
df42eaf2 907
a79ddae9 908static int ads_duo_tuner_init(struct dvb_frontend *fe)
df42eaf2
HH		 909{
910 struct saa7134_dev *dev = fe->dvb->priv;
911 /* route TDA8275a AGC input to the channel decoder */
912 saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x60);
913 return 0;
914}
915
a79ddae9 916static int ads_duo_tuner_sleep(struct dvb_frontend *fe)
df42eaf2
HH		 917{
918 struct saa7134_dev *dev = fe->dvb->priv;
919 /* route TDA8275a AGC input to the analog IF chip*/
920 saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x20);
a79ddae9
AQ		 921 philips_tda827xa_tuner_sleep( 0x61, fe);
922 return 0;
df42eaf2
HH		 923}
924
925static struct tda1004x_config ads_tech_duo_config = {
926 .demod_address = 0x08,
927 .invert = 1,
928 .invert_oclk = 0,
929 .xtal_freq = TDA10046_XTAL_16M,
930 .agc_config = TDA10046_AGC_TDA827X_GPL,
931 .if_freq = TDA10046_FREQ_045,
df42eaf2
HH		 932 .request_firmware = NULL,
933};
934
3dfb729f
PH		 935/* ------------------------------------------------------------------ */
936
a79ddae9 937static int tevion_dvb220rf_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
3dfb729f
PH		 938{
939 int ret;
940 ret = philips_tda827xa_pll_set(0x60, fe, params);
941 return ret;
942}
943
a79ddae9 944static int tevion_dvb220rf_tuner_sleep(struct dvb_frontend *fe)
3dfb729f 945{
a79ddae9 946 philips_tda827xa_tuner_sleep( 0x61, fe);
3dfb729f
PH		 947 return 0;
948}
949
3dfb729f
PH		 950static struct tda1004x_config tevion_dvbt220rf_config = {
951 .demod_address = 0x08,
952 .invert = 1,
953 .invert_oclk = 0,
954 .xtal_freq = TDA10046_XTAL_16M,
955 .agc_config = TDA10046_AGC_TDA827X,
956 .if_freq = TDA10046_FREQ_045,
3dfb729f
PH		 957 .request_firmware = NULL,
958};
959
5eda227f
HH		 960/* ------------------------------------------------------------------ */
961
962static int md8800_dvbt_analog_mode(struct dvb_frontend *fe)
963{
964 struct saa7134_dev *dev = fe->dvb->priv;
965 static u8 data[] = { 0x3c, 0x33, 0x68};
966 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
967
968 i2c_transfer(&dev->i2c_adap, &msg, 1);
969 philips_tda827xa_tuner_sleep( 0x61, fe);
970 return 0;
971}
972
973static int md8800_dvbt_pll_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
974{
975 int ret;
976 struct saa7134_dev *dev = fe->dvb->priv;
977 static u8 tda8290_close[] = { 0x21, 0xc0};
978 static u8 tda8290_open[] = { 0x21, 0x80};
979 struct i2c_msg tda8290_msg = {.addr = 0x4b,.flags = 0, .len = 2};
980 /* close tda8290 i2c bridge */
981 tda8290_msg.buf = tda8290_close;
982 ret = i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1);
983 if (ret != 1)
984 return -EIO;
985 msleep(20);
986 ret = philips_tda827xa_pll_set(0x60, fe, params);
987 if (ret != 0)
988 return ret;
989 /* open tda8290 i2c bridge */
990 tda8290_msg.buf = tda8290_open;
991 i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1);
992 return ret;
993}
994
995static struct tda1004x_config md8800_dvbt_config = {
996 .demod_address = 0x08,
997 .invert = 1,
998 .invert_oclk = 0,
999 .xtal_freq = TDA10046_XTAL_16M,
1000 .agc_config = TDA10046_AGC_TDA827X,
1001 .if_freq = TDA10046_FREQ_045,
1002 .request_firmware = NULL,
1003};
1004
90e9df7f
HH		 1005/* ------------------------------------------------------------------ */
1006
3b64e8e2
MK		 1007static struct nxt200x_config avertvhda180 = {
1008 .demod_address = 0x0a,
3b64e8e2 1009};
3e1410ad 1010
fbc81c07
CM		 1011static int nxt200x_set_pll_input(u8 *buf, int input)
1012{
1013 if (input)
1014 buf[3] |= 0x08;
1015 else
1016 buf[3] &= ~0x08;
1017 return 0;
1018}
1019
3e1410ad
AB		 1020static struct nxt200x_config kworldatsc110 = {
1021 .demod_address = 0x0a,
fbc81c07 1022 .set_pll_input = nxt200x_set_pll_input,
3e1410ad 1023};
3b64e8e2 1024
1da177e4
LT		 1025/* ------------------------------------------------------------------ */
1026
1027static int dvb_init(struct saa7134_dev *dev)
1028{
1029 /* init struct videobuf_dvb */
1030 dev->ts.nr_bufs = 32;
1031 dev->ts.nr_packets = 32*4;
1032 dev->dvb.name = dev->name;
1033 videobuf_queue_init(&dev->dvb.dvbq, &saa7134_ts_qops,
1034 dev->pci, &dev->slock,
1035 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1036 V4L2_FIELD_ALTERNATE,
1037 sizeof(struct saa7134_buf),
1038 dev);
1039
1040 switch (dev->board) {
1041 case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
1042 printk("%s: pinnacle 300i dvb setup\n",dev->name);
2bfe031d 1043 dev->dvb.frontend = dvb_attach(mt352_attach, &pinnacle_300i,
1da177e4 1044 &dev->i2c_adap);
6b3ccab7 1045 if (dev->dvb.frontend) {
dea74869 1046 dev->dvb.frontend->ops.tuner_ops.set_params = mt352_pinnacle_tuner_set_params;
6b3ccab7 1047 }
1da177e4 1048 break;
a78d0bfa
JAR		 1049 case SAA7134_BOARD_AVERMEDIA_777:
1050 printk("%s: avertv 777 dvb setup\n",dev->name);
2bfe031d 1051 dev->dvb.frontend = dvb_attach(mt352_attach, &avermedia_777,
a78d0bfa 1052 &dev->i2c_adap);
6b3ccab7 1053 if (dev->dvb.frontend) {
dea74869 1054 dev->dvb.frontend->ops.tuner_ops.calc_regs = mt352_aver777_tuner_calc_regs;
6b3ccab7 1055 }
a78d0bfa 1056 break;
1da177e4 1057 case SAA7134_BOARD_MD7134:
2bfe031d 1058 dev->dvb.frontend = dvb_attach(tda10046_attach, &medion_cardbus,
1da177e4 1059 &dev->i2c_adap);
6b3ccab7 1060 if (dev->dvb.frontend) {
dea74869
PB		 1061 dev->dvb.frontend->ops.tuner_ops.init = philips_fmd1216_tuner_init;
1062 dev->dvb.frontend->ops.tuner_ops.sleep = philips_fmd1216_tuner_sleep;
1063 dev->dvb.frontend->ops.tuner_ops.set_params = philips_fmd1216_tuner_set_params;
6b3ccab7 1064 }
1da177e4 1065 break;
86ddd96f 1066 case SAA7134_BOARD_PHILIPS_TOUGH:
2bfe031d 1067 dev->dvb.frontend = dvb_attach(tda10046_attach, &philips_tu1216_60_config,
86ddd96f 1068 &dev->i2c_adap);
6b3ccab7 1069 if (dev->dvb.frontend) {
dea74869
PB		 1070 dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_tuner_60_init;
1071 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tu1216_tuner_60_set_params;
6b3ccab7 1072 }
86ddd96f
MCC		 1073 break;
1074 case SAA7134_BOARD_FLYDVBTDUO:
2bfe031d 1075 dev->dvb.frontend = dvb_attach(tda10046_attach, &tda827x_lifeview_config,
86ddd96f 1076 &dev->i2c_adap);
6b3ccab7 1077 if (dev->dvb.frontend) {
dea74869
PB		 1078 dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init;
1079 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep;
1080 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params;
6b3ccab7 1081 }
86ddd96f 1082 break;
10b7a903 1083 case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS:
2bfe031d 1084 dev->dvb.frontend = dvb_attach(tda10046_attach, &tda827x_lifeview_config,
86ddd96f 1085 &dev->i2c_adap);
6b3ccab7 1086 if (dev->dvb.frontend) {
dea74869
PB		 1087 dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init;
1088 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep;
1089 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params;
6b3ccab7 1090 }
86ddd96f 1091 break;
2cf36ac4 1092 case SAA7134_BOARD_PHILIPS_EUROPA:
2bfe031d 1093 dev->dvb.frontend = dvb_attach(tda10046_attach, &philips_europa_config,
2cf36ac4 1094 &dev->i2c_adap);
6b3ccab7 1095 if (dev->dvb.frontend) {
dea74869
PB		 1096 dev->original_demod_sleep = dev->dvb.frontend->ops.sleep;
1097 dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep;
1098 dev->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init;
1099 dev->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep;
1100 dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params;
6b3ccab7 1101 }
2cf36ac4
HH		 1102 break;
1103 case SAA7134_BOARD_VIDEOMATE_DVBT_300:
2bfe031d 1104 dev->dvb.frontend = dvb_attach(tda10046_attach, &philips_europa_config,
2cf36ac4 1105 &dev->i2c_adap);
6b3ccab7 1106 if (dev->dvb.frontend) {
dea74869
PB		 1107 dev->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init;
1108 dev->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep;
1109 dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params;
6b3ccab7 1110 }
2cf36ac4
HH		 1111 break;
1112 case SAA7134_BOARD_VIDEOMATE_DVBT_200:
2bfe031d 1113 dev->dvb.frontend = dvb_attach(tda10046_attach, &philips_tu1216_61_config,
2cf36ac4 1114 &dev->i2c_adap);
6b3ccab7 1115 if (dev->dvb.frontend) {
dea74869
PB		 1116 dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_tuner_61_init;
1117 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tu1216_tuner_61_set_params;
6b3ccab7 1118 }
2cf36ac4 1119 break;
90e9df7f 1120 case SAA7134_BOARD_PHILIPS_TIGER:
2bfe031d 1121 dev->dvb.frontend = dvb_attach(tda10046_attach, &philips_tiger_config,
90e9df7f 1122 &dev->i2c_adap);
6b3ccab7 1123 if (dev->dvb.frontend) {
dea74869
PB		 1124 dev->dvb.frontend->ops.tuner_ops.init = philips_tiger_tuner_init;
1125 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tiger_tuner_sleep;
1126 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tiger_tuner_set_params;
6b3ccab7 1127 }
90e9df7f 1128 break;
d4b0aba4 1129 case SAA7134_BOARD_ASUSTeK_P7131_DUAL:
2bfe031d 1130 dev->dvb.frontend = dvb_attach(tda10046_attach, &philips_tiger_config,
d4b0aba4 1131 &dev->i2c_adap);
6b3ccab7 1132 if (dev->dvb.frontend) {
dea74869
PB		 1133 dev->dvb.frontend->ops.tuner_ops.init = philips_tiger_tuner_init;
1134 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tiger_tuner_sleep;
1135 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tiger_tuner_set_params;
6b3ccab7 1136 }
d4b0aba4 1137 break;
3d8466ec 1138 case SAA7134_BOARD_FLYDVBT_LR301:
2bfe031d 1139 dev->dvb.frontend = dvb_attach(tda10046_attach, &tda827x_lifeview_config,
3d8466ec 1140 &dev->i2c_adap);
6b3ccab7 1141 if (dev->dvb.frontend) {
dea74869
PB		 1142 dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init;
1143 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep;
1144 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params;
6b3ccab7 1145 }
3d8466ec 1146 break;
420f32fe 1147 case SAA7134_BOARD_FLYDVB_TRIO:
2bfe031d 1148 dev->dvb.frontend = dvb_attach(tda10046_attach, &lifeview_trio_config,
420f32fe 1149 &dev->i2c_adap);
6b3ccab7 1150 if (dev->dvb.frontend) {
dea74869
PB		 1151 dev->dvb.frontend->ops.tuner_ops.sleep = lifeview_trio_tuner_sleep;
1152 dev->dvb.frontend->ops.tuner_ops.set_params = lifeview_trio_tuner_set_params;
6b3ccab7 1153 }
420f32fe 1154 break;
df42eaf2 1155 case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331:
2bfe031d 1156 dev->dvb.frontend = dvb_attach(tda10046_attach, &ads_tech_duo_config,
df42eaf2 1157 &dev->i2c_adap);
6b3ccab7 1158 if (dev->dvb.frontend) {
dea74869
PB		 1159 dev->dvb.frontend->ops.tuner_ops.init = ads_duo_tuner_init;
1160 dev->dvb.frontend->ops.tuner_ops.sleep = ads_duo_tuner_sleep;
1161 dev->dvb.frontend->ops.tuner_ops.set_params = ads_duo_tuner_set_params;
6b3ccab7 1162 }
df42eaf2 1163 break;
3dfb729f 1164 case SAA7134_BOARD_TEVION_DVBT_220RF:
2bfe031d 1165 dev->dvb.frontend = dvb_attach(tda10046_attach, &tevion_dvbt220rf_config,
3dfb729f 1166 &dev->i2c_adap);
6b3ccab7 1167 if (dev->dvb.frontend) {
dea74869
PB		 1168 dev->dvb.frontend->ops.tuner_ops.sleep = tevion_dvb220rf_tuner_sleep;
1169 dev->dvb.frontend->ops.tuner_ops.set_params = tevion_dvb220rf_tuner_set_params;
6b3ccab7 1170 }
3dfb729f 1171 break;
d95b8942 1172 case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS:
2bfe031d 1173 dev->dvb.frontend = dvb_attach(tda10046_attach, &ads_tech_duo_config,
d95b8942 1174 &dev->i2c_adap);
6b3ccab7 1175 if (dev->dvb.frontend) {
dea74869
PB		 1176 dev->dvb.frontend->ops.tuner_ops.init = ads_duo_tuner_init;
1177 dev->dvb.frontend->ops.tuner_ops.sleep = ads_duo_tuner_sleep;
1178 dev->dvb.frontend->ops.tuner_ops.set_params = ads_duo_tuner_set_params;
6b3ccab7 1179 }
d95b8942 1180 break;
5eda227f
HH		 1181 case SAA7134_BOARD_MEDION_MD8800_QUADRO:
1182 dev->dvb.frontend = tda10046_attach(&md8800_dvbt_config,
1183 &dev->i2c_adap);
1184 if (dev->dvb.frontend) {
1185 dev->dvb.frontend->ops.tuner_ops.init = philips_tiger_tuner_init;
1186 dev->dvb.frontend->ops.tuner_ops.sleep = md8800_dvbt_analog_mode;
1187 dev->dvb.frontend->ops.tuner_ops.set_params = md8800_dvbt_pll_set;
1188 }
1189 break;
3b64e8e2 1190 case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180:
2bfe031d 1191 dev->dvb.frontend = dvb_attach(nxt200x_attach, &avertvhda180, &dev->i2c_adap);
a79ddae9 1192 if (dev->dvb.frontend) {
2bfe031d 1193 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, &dev->i2c_adap, &dvb_pll_tdhu2);
a79ddae9 1194 }
3b64e8e2 1195 break;
3e1410ad 1196 case SAA7134_BOARD_KWORLD_ATSC110:
2bfe031d 1197 dev->dvb.frontend = dvb_attach(nxt200x_attach, &kworldatsc110, &dev->i2c_adap);
a79ddae9 1198 if (dev->dvb.frontend) {
2bfe031d 1199 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, &dev->i2c_adap, &dvb_pll_tuv1236d);
a79ddae9 1200 }
3e1410ad 1201 break;
1da177e4
LT		 1202 default:
1203 printk("%s: Huh? unknown DVB card?\n",dev->name);
1204 break;
1205 }
1206
1207 if (NULL == dev->dvb.frontend) {
1208 printk("%s: frontend initialization failed\n",dev->name);
1209 return -1;
1210 }
1211
1212 /* register everything else */
d09dbf92 1213 return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
1da177e4
LT		 1214}
1215
1216static int dvb_fini(struct saa7134_dev *dev)
1217{
1218 static int on = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE;
1219
1da177e4
LT		 1220 switch (dev->board) {
1221 case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
1222 /* otherwise we don't detect the tuner on next insmod */
1223 saa7134_i2c_call_clients(dev,TDA9887_SET_CONFIG,&on);
1224 break;
1225 };
1226 videobuf_dvb_unregister(&dev->dvb);
1227 return 0;
1228}
1229
1230static struct saa7134_mpeg_ops dvb_ops = {
1231 .type = SAA7134_MPEG_DVB,
1232 .init = dvb_init,
1233 .fini = dvb_fini,
1234};
1235
1236static int __init dvb_register(void)
1237{
1238 return saa7134_ts_register(&dvb_ops);
1239}
1240
1241static void __exit dvb_unregister(void)
1242{
1243 saa7134_ts_unregister(&dvb_ops);
1244}
1245
1246module_init(dvb_register);
1247module_exit(dvb_unregister);
1248
1249/* ------------------------------------------------------------------ */
1250/*
1251 * Local variables:
1252 * c-basic-offset: 8
1253 * End:
1254 */
Linux 6.x block layer and io_uring tree(s)