projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
V4L/DVB (4805): Dib0700: Add support for Leadtek Winfast DTV Dongle (STK7700P based)
[linux-2.6-block.git] / drivers / media / video / saa7134 / saa7134-dvb.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 *
3 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
4 *
86ddd96f
MCC		 5 * Extended 3 / 2005 by Hartmut Hackmann to support various
6 * cards with the tda10046 DVB-T channel decoder
7 *
1da177e4
LT		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/delay.h>
29#include <linux/kthread.h>
30#include <linux/suspend.h>
31
32#include "saa7134-reg.h"
33#include "saa7134.h"
5e453dc7 34#include <media/v4l2-common.h>
a78d0bfa 35#include "dvb-pll.h"
1da177e4 36
1f10c7af
AQ		 37#include "mt352.h"
38#include "mt352_priv.h" /* FIXME */
39#include "tda1004x.h"
40#include "nxt200x.h"
1da177e4 41
e2ac28fa
IL		 42#include "tda10086.h"
43#include "tda826x.h"
44#include "isl6421.h"
1da177e4
LT		 45MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
46MODULE_LICENSE("GPL");
47
48static unsigned int antenna_pwr = 0;
86ddd96f 49
1da177e4
LT		 50module_param(antenna_pwr, int, 0444);
51MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)");
52
53/* ------------------------------------------------------------------ */
1da177e4
LT		 54static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
55{
56 u32 ok;
57
58 if (!on) {
59 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26));
60 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
61 return 0;
62 }
63
64 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 26));
65 saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
66 udelay(10);
67
68 saa_setl(SAA7134_GPIO_GPMODE0 >> 2, (1 << 28));
69 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));
70 udelay(10);
71 saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 28));
72 udelay(10);
73 ok = saa_readl(SAA7134_GPIO_GPSTATUS0) & (1 << 27);
74 printk("%s: %s %s\n", dev->name, __FUNCTION__,
75 ok ? "on" : "off");
76
77 if (!ok)
78 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, (1 << 26));
79 return ok;
80}
81
82static int mt352_pinnacle_init(struct dvb_frontend* fe)
83{
84 static u8 clock_config [] = { CLOCK_CTL, 0x3d, 0x28 };
85 static u8 reset [] = { RESET, 0x80 };
86 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
87 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 };
88 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };
89 static u8 fsm_ctl_cfg[] = { 0x7b, 0x04 };
90 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x0f };
91 static u8 scan_ctl_cfg [] = { SCAN_CTL, 0x0d };
92 static u8 irq_cfg [] = { INTERRUPT_EN_0, 0x00, 0x00, 0x00, 0x00 };
93 struct saa7134_dev *dev= fe->dvb->priv;
94
95 printk("%s: %s called\n",dev->name,__FUNCTION__);
96
97 mt352_write(fe, clock_config, sizeof(clock_config));
98 udelay(200);
99 mt352_write(fe, reset, sizeof(reset));
100 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
101 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
102 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
103 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
104
105 mt352_write(fe, fsm_ctl_cfg, sizeof(fsm_ctl_cfg));
106 mt352_write(fe, scan_ctl_cfg, sizeof(scan_ctl_cfg));
107 mt352_write(fe, irq_cfg, sizeof(irq_cfg));
df8cf706 108
1da177e4
LT		 109 return 0;
110}
111
a78d0bfa
JAR		 112static int mt352_aver777_init(struct dvb_frontend* fe)
113{
114 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d };
115 static u8 reset [] = { RESET, 0x80 };
116 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
117 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 };
118 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 };
119
120 mt352_write(fe, clock_config, sizeof(clock_config));
121 udelay(200);
122 mt352_write(fe, reset, sizeof(reset));
123 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
124 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
125 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
126
127 return 0;
128}
129
0463f12c
AQ		 130static int mt352_pinnacle_tuner_set_params(struct dvb_frontend* fe,
131 struct dvb_frontend_parameters* params)
1da177e4 132{
df8cf706
HH		 133 u8 off[] = { 0x00, 0xf1};
134 u8 on[] = { 0x00, 0x71};
135 struct i2c_msg msg = {.addr=0x43, .flags=0, .buf=off, .len = sizeof(off)};
136
1da177e4
LT		 137 struct saa7134_dev *dev = fe->dvb->priv;
138 struct v4l2_frequency f;
139
140 /* set frequency (mt2050) */
141 f.tuner = 0;
142 f.type = V4L2_TUNER_DIGITAL_TV;
143 f.frequency = params->frequency / 1000 * 16 / 1000;
dea74869
PB		 144 if (fe->ops.i2c_gate_ctrl)
145 fe->ops.i2c_gate_ctrl(fe, 1);
df8cf706 146 i2c_transfer(&dev->i2c_adap, &msg, 1);
1da177e4 147 saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f);
df8cf706 148 msg.buf = on;
dea74869
PB		 149 if (fe->ops.i2c_gate_ctrl)
150 fe->ops.i2c_gate_ctrl(fe, 1);
df8cf706 151 i2c_transfer(&dev->i2c_adap, &msg, 1);
1da177e4
LT		 152
153 pinnacle_antenna_pwr(dev, antenna_pwr);
154
155 /* mt352 setup */
0463f12c 156 return mt352_pinnacle_init(fe);
1da177e4
LT		 157}
158
bd4956b8 159static int mt352_aver777_tuner_calc_regs(struct dvb_frontend *fe, struct dvb_frontend_parameters *params, u8* pllbuf, int buf_len)
a78d0bfa 160{
a79ddae9
AQ		 161 if (buf_len < 5)
162 return -EINVAL;
163
164 pllbuf[0] = 0x61;
a78d0bfa
JAR		 165 dvb_pll_configure(&dvb_pll_philips_td1316, pllbuf+1,
166 params->frequency,
167 params->u.ofdm.bandwidth);
a79ddae9 168 return 5;
a78d0bfa
JAR		 169}
170
1da177e4
LT		 171static struct mt352_config pinnacle_300i = {
172 .demod_address = 0x3c >> 1,
173 .adc_clock = 20333,
174 .if2 = 36150,
175 .no_tuner = 1,
176 .demod_init = mt352_pinnacle_init,
1da177e4 177};
a78d0bfa
JAR		 178
179static struct mt352_config avermedia_777 = {
180 .demod_address = 0xf,
181 .demod_init = mt352_aver777_init,
a78d0bfa 182};
1da177e4
LT		 183
184/* ------------------------------------------------------------------ */
2cf36ac4 185static int philips_tda6651_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
1da177e4
LT		 186{
187 struct saa7134_dev *dev = fe->dvb->priv;
86ddd96f 188 u8 tuner_buf[4];
2cf36ac4 189 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tuner_buf,.len =
86ddd96f
MCC		 190 sizeof(tuner_buf) };
191 int tuner_frequency = 0;
192 u8 band, cp, filter;
193
194 /* determine charge pump */
195 tuner_frequency = params->frequency + 36166000;
196 if (tuner_frequency < 87000000)
197 return -EINVAL;
198 else if (tuner_frequency < 130000000)
199 cp = 3;
200 else if (tuner_frequency < 160000000)
201 cp = 5;
202 else if (tuner_frequency < 200000000)
203 cp = 6;
204 else if (tuner_frequency < 290000000)
205 cp = 3;
206 else if (tuner_frequency < 420000000)
207 cp = 5;
208 else if (tuner_frequency < 480000000)
209 cp = 6;
210 else if (tuner_frequency < 620000000)
211 cp = 3;
212 else if (tuner_frequency < 830000000)
213 cp = 5;
214 else if (tuner_frequency < 895000000)
215 cp = 7;
216 else
217 return -EINVAL;
218
219 /* determine band */
220 if (params->frequency < 49000000)
221 return -EINVAL;
222 else if (params->frequency < 161000000)
223 band = 1;
224 else if (params->frequency < 444000000)
225 band = 2;
226 else if (params->frequency < 861000000)
227 band = 4;
228 else
229 return -EINVAL;
230
231 /* setup PLL filter */
232 switch (params->u.ofdm.bandwidth) {
233 case BANDWIDTH_6_MHZ:
234 filter = 0;
235 break;
236
237 case BANDWIDTH_7_MHZ:
238 filter = 0;
239 break;
240
241 case BANDWIDTH_8_MHZ:
242 filter = 1;
243 break;
1da177e4 244
86ddd96f
MCC		 245 default:
246 return -EINVAL;
247 }
248
249 /* calculate divisor
250 * ((36166000+((1000000/6)/2)) + Finput)/(1000000/6)
1da177e4 251 */
86ddd96f
MCC		 252 tuner_frequency = (((params->frequency / 1000) * 6) + 217496) / 1000;
253
254 /* setup tuner buffer */
255 tuner_buf[0] = (tuner_frequency >> 8) & 0x7f;
256 tuner_buf[1] = tuner_frequency & 0xff;
257 tuner_buf[2] = 0xca;
258 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
259
dea74869
PB		 260 if (fe->ops.i2c_gate_ctrl)
261 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 262 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
263 return -EIO;
2cf36ac4
HH		 264 msleep(1);
265 return 0;
266}
267
268static int philips_tda6651_pll_init(u8 addr, struct dvb_frontend *fe)
269{
270 struct saa7134_dev *dev = fe->dvb->priv;
271 static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab };
272 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) };
86ddd96f 273
2cf36ac4 274 /* setup PLL configuration */
dea74869
PB		 275 if (fe->ops.i2c_gate_ctrl)
276 fe->ops.i2c_gate_ctrl(fe, 1);
2cf36ac4
HH		 277 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
278 return -EIO;
86ddd96f 279 msleep(1);
2cf36ac4 280
1da177e4
LT		 281 return 0;
282}
283
2cf36ac4
HH		 284/* ------------------------------------------------------------------ */
285
a79ddae9 286static int philips_tu1216_tuner_60_init(struct dvb_frontend *fe)
2cf36ac4
HH		 287{
288 return philips_tda6651_pll_init(0x60, fe);
289}
290
a79ddae9 291static int philips_tu1216_tuner_60_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 292{
293 return philips_tda6651_pll_set(0x60, fe, params);
294}
295
587d2fd7 296static int philips_tda1004x_request_firmware(struct dvb_frontend *fe,
86ddd96f 297 const struct firmware **fw, char *name)
1da177e4
LT		 298{
299 struct saa7134_dev *dev = fe->dvb->priv;
300 return request_firmware(fw, name, &dev->pci->dev);
301}
302
2cf36ac4 303static struct tda1004x_config philips_tu1216_60_config = {
86ddd96f
MCC		 304
305 .demod_address = 0x8,
306 .invert = 1,
2cf36ac4 307 .invert_oclk = 0,
86ddd96f
MCC		 308 .xtal_freq = TDA10046_XTAL_4M,
309 .agc_config = TDA10046_AGC_DEFAULT,
310 .if_freq = TDA10046_FREQ_3617,
587d2fd7 311 .request_firmware = philips_tda1004x_request_firmware,
86ddd96f
MCC		 312};
313
314/* ------------------------------------------------------------------ */
315
a79ddae9 316static int philips_tu1216_tuner_61_init(struct dvb_frontend *fe)
2cf36ac4
HH		 317{
318 return philips_tda6651_pll_init(0x61, fe);
319}
320
a79ddae9 321static int philips_tu1216_tuner_61_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 322{
323 return philips_tda6651_pll_set(0x61, fe, params);
324}
325
326static struct tda1004x_config philips_tu1216_61_config = {
327
328 .demod_address = 0x8,
329 .invert = 1,
330 .invert_oclk = 0,
331 .xtal_freq = TDA10046_XTAL_4M,
332 .agc_config = TDA10046_AGC_DEFAULT,
333 .if_freq = TDA10046_FREQ_3617,
587d2fd7 334 .request_firmware = philips_tda1004x_request_firmware,
2cf36ac4
HH		 335};
336
337/* ------------------------------------------------------------------ */
338
cbb94521 339static int philips_td1316_tuner_init(struct dvb_frontend *fe)
2cf36ac4
HH		 340{
341 struct saa7134_dev *dev = fe->dvb->priv;
342 static u8 msg[] = { 0x0b, 0xf5, 0x86, 0xab };
343 struct i2c_msg init_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) };
344
345 /* setup PLL configuration */
dea74869
PB		 346 if (fe->ops.i2c_gate_ctrl)
347 fe->ops.i2c_gate_ctrl(fe, 1);
2cf36ac4
HH		 348 if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)
349 return -EIO;
dea74869 350 if (fe->ops.i2c_gate_ctrl)
cbb94521 351 fe->ops.i2c_gate_ctrl(fe, 0);
2cf36ac4
HH		 352 return 0;
353}
354
a79ddae9 355static int philips_td1316_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
2cf36ac4
HH		 356{
357 return philips_tda6651_pll_set(0x61, fe, params);
358}
359
cbb94521
HH		 360static int philips_europa_tuner_init(struct dvb_frontend *fe)
361{
362 struct saa7134_dev *dev = fe->dvb->priv;
363 static u8 msg[] = { 0x00, 0x40};
364 struct i2c_msg init_msg = {.addr = 0x43,.flags = 0,.buf = msg,.len = sizeof(msg) };
365
366
367 if (philips_td1316_tuner_init(fe))
368 return -EIO;
369 msleep(1);
370 if (i2c_transfer(&dev->i2c_adap, &init_msg, 1) != 1)
371 return -EIO;
372
373 return 0;
374}
375
a79ddae9 376static int philips_europa_tuner_sleep(struct dvb_frontend *fe)
2cf36ac4
HH		 377{
378 struct saa7134_dev *dev = fe->dvb->priv;
379 /* this message actually turns the tuner back to analog mode */
380 static u8 msg[] = { 0x0b, 0xdc, 0x86, 0xa4 };
381 struct i2c_msg analog_msg = {.addr = 0x61,.flags = 0,.buf = msg,.len = sizeof(msg) };
382
383 i2c_transfer(&dev->i2c_adap, &analog_msg, 1);
384 msleep(1);
385
386 /* switch the board to analog mode */
387 analog_msg.addr = 0x43;
388 analog_msg.len = 0x02;
389 msg[0] = 0x00;
390 msg[1] = 0x14;
dea74869
PB		 391 if (fe->ops.i2c_gate_ctrl)
392 fe->ops.i2c_gate_ctrl(fe, 1);
2cf36ac4 393 i2c_transfer(&dev->i2c_adap, &analog_msg, 1);
a79ddae9
AQ		 394 return 0;
395}
396
397static int philips_europa_demod_sleep(struct dvb_frontend *fe)
398{
399 struct saa7134_dev *dev = fe->dvb->priv;
400
401 if (dev->original_demod_sleep)
402 dev->original_demod_sleep(fe);
dea74869 403 fe->ops.i2c_gate_ctrl(fe, 1);
a79ddae9 404 return 0;
2cf36ac4
HH		 405}
406
407static struct tda1004x_config philips_europa_config = {
408
409 .demod_address = 0x8,
410 .invert = 0,
411 .invert_oclk = 0,
412 .xtal_freq = TDA10046_XTAL_4M,
413 .agc_config = TDA10046_AGC_IFO_AUTO_POS,
414 .if_freq = TDA10046_FREQ_052,
2cf36ac4
HH		 415 .request_firmware = NULL,
416};
417
418/* ------------------------------------------------------------------ */
86ddd96f 419
a79ddae9 420static int philips_fmd1216_tuner_init(struct dvb_frontend *fe)
86ddd96f
MCC		 421{
422 struct saa7134_dev *dev = fe->dvb->priv;
423 /* this message is to set up ATC and ALC */
424 static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 };
425 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) };
426
dea74869
PB		 427 if (fe->ops.i2c_gate_ctrl)
428 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 429 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
430 return -EIO;
431 msleep(1);
432
433 return 0;
434}
435
a79ddae9 436static int philips_fmd1216_tuner_sleep(struct dvb_frontend *fe)
86ddd96f
MCC		 437{
438 struct saa7134_dev *dev = fe->dvb->priv;
439 /* this message actually turns the tuner back to analog mode */
440 static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0x60 };
441 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = fmd1216_init,.len = sizeof(fmd1216_init) };
442
dea74869
PB		 443 if (fe->ops.i2c_gate_ctrl)
444 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 445 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
446 msleep(1);
447 fmd1216_init[2] = 0x86;
448 fmd1216_init[3] = 0x54;
dea74869
PB		 449 if (fe->ops.i2c_gate_ctrl)
450 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 451 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
452 msleep(1);
a79ddae9 453 return 0;
86ddd96f
MCC		 454}
455
a79ddae9 456static int philips_fmd1216_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
86ddd96f
MCC		 457{
458 struct saa7134_dev *dev = fe->dvb->priv;
459 u8 tuner_buf[4];
460 struct i2c_msg tuner_msg = {.addr = 0x61,.flags = 0,.buf = tuner_buf,.len =
461 sizeof(tuner_buf) };
462 int tuner_frequency = 0;
463 int divider = 0;
464 u8 band, mode, cp;
465
466 /* determine charge pump */
467 tuner_frequency = params->frequency + 36130000;
468 if (tuner_frequency < 87000000)
469 return -EINVAL;
470 /* low band */
471 else if (tuner_frequency < 180000000) {
472 band = 1;
473 mode = 7;
474 cp = 0;
475 } else if (tuner_frequency < 195000000) {
476 band = 1;
477 mode = 6;
478 cp = 1;
479 /* mid band */
480 } else if (tuner_frequency < 366000000) {
481 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
482 band = 10;
483 } else {
484 band = 2;
485 }
486 mode = 7;
487 cp = 0;
488 } else if (tuner_frequency < 478000000) {
489 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
490 band = 10;
491 } else {
492 band = 2;
493 }
494 mode = 6;
495 cp = 1;
496 /* high band */
497 } else if (tuner_frequency < 662000000) {
498 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
499 band = 12;
500 } else {
501 band = 4;
502 }
503 mode = 7;
504 cp = 0;
505 } else if (tuner_frequency < 840000000) {
506 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
507 band = 12;
508 } else {
509 band = 4;
510 }
511 mode = 6;
512 cp = 1;
513 } else {
514 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
515 band = 12;
516 } else {
517 band = 4;
518 }
519 mode = 7;
520 cp = 1;
521
522 }
523 /* calculate divisor */
524 /* ((36166000 + Finput) / 166666) rounded! */
525 divider = (tuner_frequency + 83333) / 166667;
526
527 /* setup tuner buffer */
528 tuner_buf[0] = (divider >> 8) & 0x7f;
529 tuner_buf[1] = divider & 0xff;
530 tuner_buf[2] = 0x80 | (cp << 6) | (mode << 3) | 4;
531 tuner_buf[3] = 0x40 | band;
532
dea74869
PB		 533 if (fe->ops.i2c_gate_ctrl)
534 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 535 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
536 return -EIO;
537 return 0;
538}
539
408b664a 540static struct tda1004x_config medion_cardbus = {
86ddd96f
MCC		 541 .demod_address = 0x08,
542 .invert = 1,
543 .invert_oclk = 0,
544 .xtal_freq = TDA10046_XTAL_16M,
545 .agc_config = TDA10046_AGC_IFO_AUTO_NEG,
546 .if_freq = TDA10046_FREQ_3613,
86ddd96f
MCC		 547 .request_firmware = NULL,
548};
549
550/* ------------------------------------------------------------------ */
551
552struct tda827x_data {
553 u32 lomax;
554 u8 spd;
555 u8 bs;
556 u8 bp;
557 u8 cp;
558 u8 gc3;
559 u8 div1p5;
560};
561
562static struct tda827x_data tda827x_dvbt[] = {
563 { .lomax = 62000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
564 { .lomax = 66000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
565 { .lomax = 76000000, .spd = 3, .bs = 1, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
566 { .lomax = 84000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
567 { .lomax = 93000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
568 { .lomax = 98000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
569 { .lomax = 109000000, .spd = 3, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
570 { .lomax = 123000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
571 { .lomax = 133000000, .spd = 2, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
572 { .lomax = 151000000, .spd = 2, .bs = 1, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
573 { .lomax = 154000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
574 { .lomax = 181000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 0, .div1p5 = 0},
575 { .lomax = 185000000, .spd = 2, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
576 { .lomax = 217000000, .spd = 2, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
577 { .lomax = 244000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
578 { .lomax = 265000000, .spd = 1, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
579 { .lomax = 302000000, .spd = 1, .bs = 1, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
580 { .lomax = 324000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
581 { .lomax = 370000000, .spd = 1, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
582 { .lomax = 454000000, .spd = 1, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
583 { .lomax = 493000000, .spd = 0, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
584 { .lomax = 530000000, .spd = 0, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
585 { .lomax = 554000000, .spd = 0, .bs = 1, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
586 { .lomax = 604000000, .spd = 0, .bs = 1, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
587 { .lomax = 696000000, .spd = 0, .bs = 2, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
588 { .lomax = 740000000, .spd = 0, .bs = 2, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
589 { .lomax = 820000000, .spd = 0, .bs = 3, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
590 { .lomax = 865000000, .spd = 0, .bs = 3, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
591 { .lomax = 0, .spd = 0, .bs = 0, .bp = 0, .cp = 0, .gc3 = 0, .div1p5 = 0}
592};
593
a79ddae9 594static int philips_tda827x_tuner_init(struct dvb_frontend *fe)
86ddd96f
MCC		 595{
596 return 0;
597}
598
a79ddae9 599static int philips_tda827x_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
86ddd96f
MCC		 600{
601 struct saa7134_dev *dev = fe->dvb->priv;
602 u8 tuner_buf[14];
603
604 struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tuner_buf,
f2421ca3 605 .len = sizeof(tuner_buf) };
86ddd96f
MCC		 606 int i, tuner_freq, if_freq;
607 u32 N;
608 switch (params->u.ofdm.bandwidth) {
609 case BANDWIDTH_6_MHZ:
610 if_freq = 4000000;
611 break;
612 case BANDWIDTH_7_MHZ:
613 if_freq = 4500000;
614 break;
615 default: /* 8 MHz or Auto */
616 if_freq = 5000000;
617 break;
618 }
619 tuner_freq = params->frequency + if_freq;
620
621 i = 0;
622 while (tda827x_dvbt[i].lomax < tuner_freq) {
623 if(tda827x_dvbt[i + 1].lomax == 0)
624 break;
625 i++;
626 }
627
628 N = ((tuner_freq + 125000) / 250000) << (tda827x_dvbt[i].spd + 2);
629 tuner_buf[0] = 0;
630 tuner_buf[1] = (N>>8) | 0x40;
631 tuner_buf[2] = N & 0xff;
632 tuner_buf[3] = 0;
633 tuner_buf[4] = 0x52;
634 tuner_buf[5] = (tda827x_dvbt[i].spd << 6) + (tda827x_dvbt[i].div1p5 << 5) +
635 (tda827x_dvbt[i].bs << 3) + tda827x_dvbt[i].bp;
636 tuner_buf[6] = (tda827x_dvbt[i].gc3 << 4) + 0x8f;
637 tuner_buf[7] = 0xbf;
638 tuner_buf[8] = 0x2a;
639 tuner_buf[9] = 0x05;
640 tuner_buf[10] = 0xff;
641 tuner_buf[11] = 0x00;
642 tuner_buf[12] = 0x00;
643 tuner_buf[13] = 0x40;
644
645 tuner_msg.len = 14;
dea74869
PB		 646 if (fe->ops.i2c_gate_ctrl)
647 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 648 if (i2c_transfer(&dev->i2c_adap, &tuner_msg, 1) != 1)
649 return -EIO;
650
651 msleep(500);
652 /* correct CP value */
653 tuner_buf[0] = 0x30;
654 tuner_buf[1] = 0x50 + tda827x_dvbt[i].cp;
655 tuner_msg.len = 2;
dea74869
PB		 656 if (fe->ops.i2c_gate_ctrl)
657 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f
MCC		 658 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
659
660 return 0;
661}
662
a79ddae9 663static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe)
86ddd96f
MCC		 664{
665 struct saa7134_dev *dev = fe->dvb->priv;
666 static u8 tda827x_sleep[] = { 0x30, 0xd0};
667 struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tda827x_sleep,
f2421ca3 668 .len = sizeof(tda827x_sleep) };
dea74869
PB		 669 if (fe->ops.i2c_gate_ctrl)
670 fe->ops.i2c_gate_ctrl(fe, 1);
86ddd96f 671 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
a79ddae9 672 return 0;
86ddd96f
MCC		 673}
674
675static struct tda1004x_config tda827x_lifeview_config = {
676 .demod_address = 0x08,
677 .invert = 1,
678 .invert_oclk = 0,
679 .xtal_freq = TDA10046_XTAL_16M,
680 .agc_config = TDA10046_AGC_TDA827X,
681 .if_freq = TDA10046_FREQ_045,
86ddd96f 682 .request_firmware = NULL,
1da177e4 683};
90e9df7f
HH		 684
685/* ------------------------------------------------------------------ */
686
687struct tda827xa_data {
688 u32 lomax;
689 u8 svco;
690 u8 spd;
691 u8 scr;
692 u8 sbs;
693 u8 gc3;
694};
695
696static struct tda827xa_data tda827xa_dvbt[] = {
697 { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 1},
698 { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
699 { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
700 { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
701 { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1},
702 { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
703 { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
704 { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
705 { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
706 { .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
707 { .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
708 { .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
709 { .lomax = 290000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
710 { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
711 { .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
712 { .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
713 { .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
714 { .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
715 { .lomax = 550000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
716 { .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
717 { .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
718 { .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
719 { .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
720 { .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
721 { .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
722 { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0},
723 { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}};
724
725
726static int philips_tda827xa_pll_set(u8 addr, struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
727{
728 struct saa7134_dev *dev = fe->dvb->priv;
729 u8 tuner_buf[14];
730 unsigned char reg2[2];
731
732 struct i2c_msg msg = {.addr = addr,.flags = 0,.buf = tuner_buf};
733 int i, tuner_freq, if_freq;
734 u32 N;
735
736 switch (params->u.ofdm.bandwidth) {
737 case BANDWIDTH_6_MHZ:
738 if_freq = 4000000;
739 break;
740 case BANDWIDTH_7_MHZ:
741 if_freq = 4500000;
742 break;
743 default: /* 8 MHz or Auto */
744 if_freq = 5000000;
745 break;
746 }
747 tuner_freq = params->frequency + if_freq;
748
749 i = 0;
750 while (tda827xa_dvbt[i].lomax < tuner_freq) {
751 if(tda827xa_dvbt[i + 1].lomax == 0)
752 break;
753 i++;
754 }
755
756 N = ((tuner_freq + 31250) / 62500) << tda827xa_dvbt[i].spd;
757 tuner_buf[0] = 0; // subaddress
758 tuner_buf[1] = N >> 8;
759 tuner_buf[2] = N & 0xff;
760 tuner_buf[3] = 0;
761 tuner_buf[4] = 0x16;
762 tuner_buf[5] = (tda827xa_dvbt[i].spd << 5) + (tda827xa_dvbt[i].svco << 3) +
763 tda827xa_dvbt[i].sbs;
764 tuner_buf[6] = 0x4b + (tda827xa_dvbt[i].gc3 << 4);
765 tuner_buf[7] = 0x0c;
766 tuner_buf[8] = 0x06;
767 tuner_buf[9] = 0x24;
768 tuner_buf[10] = 0xff;
769 tuner_buf[11] = 0x60;
770 tuner_buf[12] = 0x00;
771 tuner_buf[13] = 0x39; // lpsel
772 msg.len = 14;
dea74869
PB		 773 if (fe->ops.i2c_gate_ctrl)
774 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 775 if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
776 return -EIO;
777
778 msg.buf= reg2;
779 msg.len = 2;
780 reg2[0] = 0x60;
781 reg2[1] = 0x3c;
dea74869
PB		 782 if (fe->ops.i2c_gate_ctrl)
783 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 784 i2c_transfer(&dev->i2c_adap, &msg, 1);
785
786 reg2[0] = 0xa0;
787 reg2[1] = 0x40;
dea74869
PB		 788 if (fe->ops.i2c_gate_ctrl)
789 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 790 i2c_transfer(&dev->i2c_adap, &msg, 1);
791
792 msleep(2);
793 /* correct CP value */
794 reg2[0] = 0x30;
795 reg2[1] = 0x10 + tda827xa_dvbt[i].scr;
796 msg.len = 2;
dea74869
PB		 797 if (fe->ops.i2c_gate_ctrl)
798 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 799 i2c_transfer(&dev->i2c_adap, &msg, 1);
800
801 msleep(550);
802 reg2[0] = 0x50;
803 reg2[1] = 0x4f + (tda827xa_dvbt[i].gc3 << 4);
dea74869
PB		 804 if (fe->ops.i2c_gate_ctrl)
805 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f
HH		 806 i2c_transfer(&dev->i2c_adap, &msg, 1);
807
808 return 0;
809
810}
811
a79ddae9 812static int philips_tda827xa_tuner_sleep(u8 addr, struct dvb_frontend *fe)
90e9df7f
HH		 813{
814 struct saa7134_dev *dev = fe->dvb->priv;
815 static u8 tda827xa_sleep[] = { 0x30, 0x90};
816 struct i2c_msg tuner_msg = {.addr = addr,.flags = 0,.buf = tda827xa_sleep,
f1bcef88 817 .len = sizeof(tda827xa_sleep) };
dea74869
PB		 818 if (fe->ops.i2c_gate_ctrl)
819 fe->ops.i2c_gate_ctrl(fe, 1);
90e9df7f 820 i2c_transfer(&dev->i2c_adap, &tuner_msg, 1);
587d2fd7
HH		 821 if (fe->ops.i2c_gate_ctrl)
822 fe->ops.i2c_gate_ctrl(fe, 0);
a79ddae9 823 return 0;
90e9df7f
HH		 824}
825
826/* ------------------------------------------------------------------ */
827
587d2fd7 828static int tda8290_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
90e9df7f 829{
90e9df7f
HH		 830 struct saa7134_dev *dev = fe->dvb->priv;
831 static u8 tda8290_close[] = { 0x21, 0xc0};
832 static u8 tda8290_open[] = { 0x21, 0x80};
833 struct i2c_msg tda8290_msg = {.addr = 0x4b,.flags = 0, .len = 2};
587d2fd7
HH		 834 if (enable) {
835 tda8290_msg.buf = tda8290_close;
836 } else {
837 tda8290_msg.buf = tda8290_open;
838 }
839 if (i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1) != 1)
90e9df7f
HH		 840 return -EIO;
841 msleep(20);
587d2fd7
HH		 842 return 0;
843}
844
845/* ------------------------------------------------------------------ */
846
847static int philips_tiger_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
848{
849 int ret;
850
90e9df7f
HH		 851 ret = philips_tda827xa_pll_set(0x61, fe, params);
852 if (ret != 0)
853 return ret;
587d2fd7 854 return 0;
2d6b5f62 855}
90e9df7f 856
a79ddae9 857static int philips_tiger_tuner_init(struct dvb_frontend *fe)
90e9df7f
HH		 858{
859 struct saa7134_dev *dev = fe->dvb->priv;
860 static u8 data[] = { 0x3c, 0x33, 0x6a};
861 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
862
863 if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
864 return -EIO;
865 return 0;
866}
867
a79ddae9 868static int philips_tiger_tuner_sleep(struct dvb_frontend *fe)
90e9df7f
HH		 869{
870 struct saa7134_dev *dev = fe->dvb->priv;
871 static u8 data[] = { 0x3c, 0x33, 0x68};
872 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
873
874 i2c_transfer(&dev->i2c_adap, &msg, 1);
a79ddae9
AQ		 875 philips_tda827xa_tuner_sleep( 0x61, fe);
876 return 0;
90e9df7f
HH		 877}
878
879static struct tda1004x_config philips_tiger_config = {
880 .demod_address = 0x08,
881 .invert = 1,
882 .invert_oclk = 0,
883 .xtal_freq = TDA10046_XTAL_16M,
884 .agc_config = TDA10046_AGC_TDA827X,
885 .if_freq = TDA10046_FREQ_045,
90e9df7f
HH		 886 .request_firmware = NULL,
887};
888
df42eaf2
HH		 889/* ------------------------------------------------------------------ */
890
587d2fd7
HH		 891static struct tda1004x_config pinnacle_pctv_310i_config = {
892 .demod_address = 0x08,
893 .invert = 1,
894 .invert_oclk = 0,
895 .xtal_freq = TDA10046_XTAL_16M,
896 .agc_config = TDA10046_AGC_TDA827X,
897 .if_freq = TDA10046_FREQ_045,
898 .request_firmware = philips_tda1004x_request_firmware,
899};
900
901/* ------------------------------------------------------------------ */
902
83646817
HH		 903static struct tda1004x_config asus_p7131_dual_config = {
904 .demod_address = 0x08,
905 .invert = 1,
906 .invert_oclk = 0,
907 .xtal_freq = TDA10046_XTAL_16M,
908 .agc_config = TDA10046_AGC_TDA827X,
909 .if_freq = TDA10046_FREQ_045,
910 .request_firmware = philips_tda1004x_request_firmware,
911};
912
6b14ff9e
HP		 913static int asus_p7131_dual_tuner_init(struct dvb_frontend *fe)
914{
915 struct saa7134_dev *dev = fe->dvb->priv;
916 static u8 data[] = { 0x3c, 0x33, 0x6a};
917 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
918
919 if (i2c_transfer(&dev->i2c_adap, &msg, 1) != 1)
920 return -EIO;
921 /* make sure the DVB-T antenna input is set */
922 saa_setl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x0200000);
923 return 0;
924}
925
926static int asus_p7131_dual_tuner_sleep(struct dvb_frontend *fe)
927{
928 struct saa7134_dev *dev = fe->dvb->priv;
929 static u8 data[] = { 0x3c, 0x33, 0x68};
930 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
931
932 i2c_transfer(&dev->i2c_adap, &msg, 1);
933 philips_tda827xa_tuner_sleep( 0x61, fe);
934 /* reset antenna inputs for analog usage */
935 saa_clearl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x0200000);
936 return 0;
937}
938
939/* ------------------------------------------------------------------ */
940
a79ddae9 941static int lifeview_trio_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
420f32fe
NS		 942{
943 int ret;
944
945 ret = philips_tda827xa_pll_set(0x60, fe, params);
946 return ret;
947}
948
a79ddae9 949static int lifeview_trio_tuner_sleep(struct dvb_frontend *fe)
420f32fe 950{
a79ddae9 951 philips_tda827xa_tuner_sleep(0x60, fe);
420f32fe
NS		 952 return 0;
953}
954
420f32fe
NS		 955static struct tda1004x_config lifeview_trio_config = {
956 .demod_address = 0x09,
957 .invert = 1,
958 .invert_oclk = 0,
959 .xtal_freq = TDA10046_XTAL_16M,
960 .agc_config = TDA10046_AGC_TDA827X_GPL,
961 .if_freq = TDA10046_FREQ_045,
420f32fe
NS		 962 .request_firmware = NULL,
963};
964
965/* ------------------------------------------------------------------ */
966
a79ddae9 967static int ads_duo_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
df42eaf2
HH		 968{
969 int ret;
970
971 ret = philips_tda827xa_pll_set(0x61, fe, params);
972 return ret;
2d6b5f62 973}
df42eaf2 974
a79ddae9 975static int ads_duo_tuner_init(struct dvb_frontend *fe)
df42eaf2
HH		 976{
977 struct saa7134_dev *dev = fe->dvb->priv;
978 /* route TDA8275a AGC input to the channel decoder */
979 saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x60);
980 return 0;
981}
982
a79ddae9 983static int ads_duo_tuner_sleep(struct dvb_frontend *fe)
df42eaf2
HH		 984{
985 struct saa7134_dev *dev = fe->dvb->priv;
986 /* route TDA8275a AGC input to the analog IF chip*/
987 saa_writeb(SAA7134_GPIO_GPSTATUS2, 0x20);
a79ddae9
AQ		 988 philips_tda827xa_tuner_sleep( 0x61, fe);
989 return 0;
df42eaf2
HH		 990}
991
992static struct tda1004x_config ads_tech_duo_config = {
993 .demod_address = 0x08,
994 .invert = 1,
995 .invert_oclk = 0,
996 .xtal_freq = TDA10046_XTAL_16M,
997 .agc_config = TDA10046_AGC_TDA827X_GPL,
998 .if_freq = TDA10046_FREQ_045,
df42eaf2
HH		 999 .request_firmware = NULL,
1000};
1001
3dfb729f
PH		 1002/* ------------------------------------------------------------------ */
1003
a79ddae9 1004static int tevion_dvb220rf_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
3dfb729f
PH		 1005{
1006 int ret;
1007 ret = philips_tda827xa_pll_set(0x60, fe, params);
1008 return ret;
1009}
1010
a79ddae9 1011static int tevion_dvb220rf_tuner_sleep(struct dvb_frontend *fe)
3dfb729f 1012{
a79ddae9 1013 philips_tda827xa_tuner_sleep( 0x61, fe);
3dfb729f
PH		 1014 return 0;
1015}
1016
3dfb729f
PH		 1017static struct tda1004x_config tevion_dvbt220rf_config = {
1018 .demod_address = 0x08,
1019 .invert = 1,
1020 .invert_oclk = 0,
1021 .xtal_freq = TDA10046_XTAL_16M,
1022 .agc_config = TDA10046_AGC_TDA827X,
1023 .if_freq = TDA10046_FREQ_045,
3dfb729f
PH		 1024 .request_firmware = NULL,
1025};
1026
5eda227f
HH		 1027/* ------------------------------------------------------------------ */
1028
1029static int md8800_dvbt_analog_mode(struct dvb_frontend *fe)
1030{
1031 struct saa7134_dev *dev = fe->dvb->priv;
1032 static u8 data[] = { 0x3c, 0x33, 0x68};
1033 struct i2c_msg msg = {.addr=0x08, .flags=0, .buf=data, .len = sizeof(data)};
1034
1035 i2c_transfer(&dev->i2c_adap, &msg, 1);
1036 philips_tda827xa_tuner_sleep( 0x61, fe);
1037 return 0;
1038}
1039
1040static int md8800_dvbt_pll_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
1041{
1042 int ret;
1043 struct saa7134_dev *dev = fe->dvb->priv;
1044 static u8 tda8290_close[] = { 0x21, 0xc0};
1045 static u8 tda8290_open[] = { 0x21, 0x80};
1046 struct i2c_msg tda8290_msg = {.addr = 0x4b,.flags = 0, .len = 2};
1047 /* close tda8290 i2c bridge */
1048 tda8290_msg.buf = tda8290_close;
1049 ret = i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1);
1050 if (ret != 1)
1051 return -EIO;
1052 msleep(20);
1053 ret = philips_tda827xa_pll_set(0x60, fe, params);
1054 if (ret != 0)
1055 return ret;
1056 /* open tda8290 i2c bridge */
1057 tda8290_msg.buf = tda8290_open;
1058 i2c_transfer(&dev->i2c_adap, &tda8290_msg, 1);
1059 return ret;
1060}
1061
1062static struct tda1004x_config md8800_dvbt_config = {
1063 .demod_address = 0x08,
1064 .invert = 1,
1065 .invert_oclk = 0,
1066 .xtal_freq = TDA10046_XTAL_16M,
1067 .agc_config = TDA10046_AGC_TDA827X,
1068 .if_freq = TDA10046_FREQ_045,
1069 .request_firmware = NULL,
1070};
1071
e2ac28fa
IL		 1072static struct tda10086_config flydvbs = {
1073 .demod_address = 0x0e,
1074 .invert = 0,
1075};
1076
90e9df7f
HH		 1077/* ------------------------------------------------------------------ */
1078
3b64e8e2
MK		 1079static struct nxt200x_config avertvhda180 = {
1080 .demod_address = 0x0a,
3b64e8e2 1081};
3e1410ad 1082
fbc81c07
CM		 1083static int nxt200x_set_pll_input(u8 *buf, int input)
1084{
1085 if (input)
1086 buf[3] |= 0x08;
1087 else
1088 buf[3] &= ~0x08;
1089 return 0;
1090}
1091
3e1410ad
AB		 1092static struct nxt200x_config kworldatsc110 = {
1093 .demod_address = 0x0a,
fbc81c07 1094 .set_pll_input = nxt200x_set_pll_input,
3e1410ad 1095};
3b64e8e2 1096
1da177e4
LT		 1097/* ------------------------------------------------------------------ */
1098
1099static int dvb_init(struct saa7134_dev *dev)
1100{
1101 /* init struct videobuf_dvb */
1102 dev->ts.nr_bufs = 32;
1103 dev->ts.nr_packets = 32*4;
1104 dev->dvb.name = dev->name;
1105 videobuf_queue_init(&dev->dvb.dvbq, &saa7134_ts_qops,
1106 dev->pci, &dev->slock,
1107 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1108 V4L2_FIELD_ALTERNATE,
1109 sizeof(struct saa7134_buf),
1110 dev);
1111
1112 switch (dev->board) {
1113 case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
1114 printk("%s: pinnacle 300i dvb setup\n",dev->name);
2bfe031d 1115 dev->dvb.frontend = dvb_attach(mt352_attach, &pinnacle_300i,
f7b54b10 1116 &dev->i2c_adap);
6b3ccab7 1117 if (dev->dvb.frontend) {
dea74869 1118 dev->dvb.frontend->ops.tuner_ops.set_params = mt352_pinnacle_tuner_set_params;
6b3ccab7 1119 }
1da177e4 1120 break;
a78d0bfa 1121 case SAA7134_BOARD_AVERMEDIA_777:
515c208d 1122 case SAA7134_BOARD_AVERMEDIA_A16AR:
a78d0bfa 1123 printk("%s: avertv 777 dvb setup\n",dev->name);
2bfe031d 1124 dev->dvb.frontend = dvb_attach(mt352_attach, &avermedia_777,
f7b54b10 1125 &dev->i2c_adap);
6b3ccab7 1126 if (dev->dvb.frontend) {
dea74869 1127 dev->dvb.frontend->ops.tuner_ops.calc_regs = mt352_aver777_tuner_calc_regs;
6b3ccab7 1128 }
a78d0bfa 1129 break;
1da177e4 1130 case SAA7134_BOARD_MD7134:
f7b54b10
MK		 1131 dev->dvb.frontend = dvb_attach(tda10046_attach,
1132 &medion_cardbus,
1133 &dev->i2c_adap);
6b3ccab7 1134 if (dev->dvb.frontend) {
dea74869
PB		 1135 dev->dvb.frontend->ops.tuner_ops.init = philips_fmd1216_tuner_init;
1136 dev->dvb.frontend->ops.tuner_ops.sleep = philips_fmd1216_tuner_sleep;
1137 dev->dvb.frontend->ops.tuner_ops.set_params = philips_fmd1216_tuner_set_params;
6b3ccab7 1138 }
1da177e4 1139 break;
86ddd96f 1140 case SAA7134_BOARD_PHILIPS_TOUGH:
f7b54b10
MK		 1141 dev->dvb.frontend = dvb_attach(tda10046_attach,
1142 &philips_tu1216_60_config,
1143 &dev->i2c_adap);
6b3ccab7 1144 if (dev->dvb.frontend) {
dea74869
PB		 1145 dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_tuner_60_init;
1146 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tu1216_tuner_60_set_params;
6b3ccab7 1147 }
86ddd96f
MCC		 1148 break;
1149 case SAA7134_BOARD_FLYDVBTDUO:
f7b54b10
MK		 1150 dev->dvb.frontend = dvb_attach(tda10046_attach,
1151 &tda827x_lifeview_config,
1152 &dev->i2c_adap);
6b3ccab7 1153 if (dev->dvb.frontend) {
dea74869
PB		 1154 dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init;
1155 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep;
1156 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params;
6b3ccab7 1157 }
86ddd96f 1158 break;
10b7a903 1159 case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS:
f7b54b10
MK		 1160 dev->dvb.frontend = dvb_attach(tda10046_attach,
1161 &tda827x_lifeview_config,
1162 &dev->i2c_adap);
6b3ccab7 1163 if (dev->dvb.frontend) {
dea74869
PB		 1164 dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init;
1165 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep;
1166 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params;
6b3ccab7 1167 }
86ddd96f 1168 break;
2cf36ac4 1169 case SAA7134_BOARD_PHILIPS_EUROPA:
f7b54b10
MK		 1170 dev->dvb.frontend = dvb_attach(tda10046_attach,
1171 &philips_europa_config,
1172 &dev->i2c_adap);
6b3ccab7 1173 if (dev->dvb.frontend) {
dea74869
PB		 1174 dev->original_demod_sleep = dev->dvb.frontend->ops.sleep;
1175 dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep;
1176 dev->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init;
1177 dev->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep;
1178 dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params;
6b3ccab7 1179 }
2cf36ac4
HH		 1180 break;
1181 case SAA7134_BOARD_VIDEOMATE_DVBT_300:
f7b54b10
MK		 1182 dev->dvb.frontend = dvb_attach(tda10046_attach,
1183 &philips_europa_config,
1184 &dev->i2c_adap);
6b3ccab7 1185 if (dev->dvb.frontend) {
588f9831
HH		 1186 dev->original_demod_sleep = dev->dvb.frontend->ops.sleep;
1187 dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep;
dea74869
PB		 1188 dev->dvb.frontend->ops.tuner_ops.init = philips_europa_tuner_init;
1189 dev->dvb.frontend->ops.tuner_ops.sleep = philips_europa_tuner_sleep;
1190 dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params;
6b3ccab7 1191 }
2cf36ac4
HH		 1192 break;
1193 case SAA7134_BOARD_VIDEOMATE_DVBT_200:
f7b54b10
MK		 1194 dev->dvb.frontend = dvb_attach(tda10046_attach,
1195 &philips_tu1216_61_config,
1196 &dev->i2c_adap);
6b3ccab7 1197 if (dev->dvb.frontend) {
dea74869
PB		 1198 dev->dvb.frontend->ops.tuner_ops.init = philips_tu1216_tuner_61_init;
1199 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tu1216_tuner_61_set_params;
6b3ccab7 1200 }
2cf36ac4 1201 break;
90e9df7f 1202 case SAA7134_BOARD_PHILIPS_TIGER:
f7b54b10
MK		 1203 dev->dvb.frontend = dvb_attach(tda10046_attach,
1204 &philips_tiger_config,
1205 &dev->i2c_adap);
6b3ccab7 1206 if (dev->dvb.frontend) {
587d2fd7
HH		 1207 dev->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl;
1208 dev->dvb.frontend->ops.tuner_ops.init = philips_tiger_tuner_init;
1209 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tiger_tuner_sleep;
1210 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tiger_tuner_set_params;
1211 }
1212 break;
1213 case SAA7134_BOARD_PINNACLE_PCTV_310i:
1214 dev->dvb.frontend = dvb_attach(tda10046_attach,
1215 &pinnacle_pctv_310i_config,
1216 &dev->i2c_adap);
1217 if (dev->dvb.frontend) {
1218 dev->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl;
dea74869
PB		 1219 dev->dvb.frontend->ops.tuner_ops.init = philips_tiger_tuner_init;
1220 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tiger_tuner_sleep;
1221 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tiger_tuner_set_params;
6b3ccab7 1222 }
90e9df7f 1223 break;
d4b0aba4 1224 case SAA7134_BOARD_ASUSTeK_P7131_DUAL:
f7b54b10 1225 dev->dvb.frontend = dvb_attach(tda10046_attach,
83646817 1226 &asus_p7131_dual_config,
f7b54b10 1227 &dev->i2c_adap);
6b3ccab7 1228 if (dev->dvb.frontend) {
7da6894a 1229 dev->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl;
6b14ff9e
HP		 1230 dev->dvb.frontend->ops.tuner_ops.init = asus_p7131_dual_tuner_init;
1231 dev->dvb.frontend->ops.tuner_ops.sleep = asus_p7131_dual_tuner_sleep;
dea74869 1232 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tiger_tuner_set_params;
6b3ccab7 1233 }
d4b0aba4 1234 break;
3d8466ec 1235 case SAA7134_BOARD_FLYDVBT_LR301:
f7b54b10
MK		 1236 dev->dvb.frontend = dvb_attach(tda10046_attach,
1237 &tda827x_lifeview_config,
1238 &dev->i2c_adap);
6b3ccab7 1239 if (dev->dvb.frontend) {
dea74869
PB		 1240 dev->dvb.frontend->ops.tuner_ops.init = philips_tda827x_tuner_init;
1241 dev->dvb.frontend->ops.tuner_ops.sleep = philips_tda827x_tuner_sleep;
1242 dev->dvb.frontend->ops.tuner_ops.set_params = philips_tda827x_tuner_set_params;
6b3ccab7 1243 }
3d8466ec 1244 break;
420f32fe 1245 case SAA7134_BOARD_FLYDVB_TRIO:
f7b54b10
MK		 1246 dev->dvb.frontend = dvb_attach(tda10046_attach,
1247 &lifeview_trio_config,
1248 &dev->i2c_adap);
6b3ccab7 1249 if (dev->dvb.frontend) {
dea74869
PB		 1250 dev->dvb.frontend->ops.tuner_ops.sleep = lifeview_trio_tuner_sleep;
1251 dev->dvb.frontend->ops.tuner_ops.set_params = lifeview_trio_tuner_set_params;
6b3ccab7 1252 }
420f32fe 1253 break;
df42eaf2 1254 case SAA7134_BOARD_ADS_DUO_CARDBUS_PTV331:
f7b54b10
MK		 1255 dev->dvb.frontend = dvb_attach(tda10046_attach,
1256 &ads_tech_duo_config,
1257 &dev->i2c_adap);
6b3ccab7 1258 if (dev->dvb.frontend) {
dea74869
PB		 1259 dev->dvb.frontend->ops.tuner_ops.init = ads_duo_tuner_init;
1260 dev->dvb.frontend->ops.tuner_ops.sleep = ads_duo_tuner_sleep;
1261 dev->dvb.frontend->ops.tuner_ops.set_params = ads_duo_tuner_set_params;
6b3ccab7 1262 }
df42eaf2 1263 break;
3dfb729f 1264 case SAA7134_BOARD_TEVION_DVBT_220RF:
f7b54b10
MK		 1265 dev->dvb.frontend = dvb_attach(tda10046_attach,
1266 &tevion_dvbt220rf_config,
1267 &dev->i2c_adap);
6b3ccab7 1268 if (dev->dvb.frontend) {
dea74869
PB		 1269 dev->dvb.frontend->ops.tuner_ops.sleep = tevion_dvb220rf_tuner_sleep;
1270 dev->dvb.frontend->ops.tuner_ops.set_params = tevion_dvb220rf_tuner_set_params;
6b3ccab7 1271 }
3dfb729f 1272 break;
d95b8942 1273 case SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS:
f7b54b10
MK		 1274 dev->dvb.frontend = dvb_attach(tda10046_attach,
1275 &ads_tech_duo_config,
1276 &dev->i2c_adap);
6b3ccab7 1277 if (dev->dvb.frontend) {
dea74869
PB		 1278 dev->dvb.frontend->ops.tuner_ops.init = ads_duo_tuner_init;
1279 dev->dvb.frontend->ops.tuner_ops.sleep = ads_duo_tuner_sleep;
1280 dev->dvb.frontend->ops.tuner_ops.set_params = ads_duo_tuner_set_params;
6b3ccab7 1281 }
d95b8942 1282 break;
5eda227f
HH		 1283 case SAA7134_BOARD_MEDION_MD8800_QUADRO:
1284 dev->dvb.frontend = tda10046_attach(&md8800_dvbt_config,
1285 &dev->i2c_adap);
1286 if (dev->dvb.frontend) {
1287 dev->dvb.frontend->ops.tuner_ops.init = philips_tiger_tuner_init;
1288 dev->dvb.frontend->ops.tuner_ops.sleep = md8800_dvbt_analog_mode;
1289 dev->dvb.frontend->ops.tuner_ops.set_params = md8800_dvbt_pll_set;
1290 }
1291 break;
3b64e8e2 1292 case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180:
f7b54b10
MK		 1293 dev->dvb.frontend = dvb_attach(nxt200x_attach, &avertvhda180,
1294 &dev->i2c_adap);
a79ddae9 1295 if (dev->dvb.frontend) {
4ad8eee5
MK		 1296 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
1297 NULL, &dvb_pll_tdhu2);
a79ddae9 1298 }
3b64e8e2 1299 break;
3e1410ad 1300 case SAA7134_BOARD_KWORLD_ATSC110:
f7b54b10
MK		 1301 dev->dvb.frontend = dvb_attach(nxt200x_attach, &kworldatsc110,
1302 &dev->i2c_adap);
a79ddae9 1303 if (dev->dvb.frontend) {
4ad8eee5
MK		 1304 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
1305 NULL, &dvb_pll_tuv1236d);
a79ddae9 1306 }
3e1410ad 1307 break;
e2ac28fa 1308 case SAA7134_BOARD_FLYDVBS_LR300:
f7b54b10
MK		 1309 dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs,
1310 &dev->i2c_adap);
e2ac28fa 1311 if (dev->dvb.frontend) {
f7b54b10
MK		 1312 if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60,
1313 &dev->i2c_adap, 0) == NULL) {
e2ac28fa
IL		 1314 printk("%s: No tda826x found!\n", __FUNCTION__);
1315 }
f7b54b10
MK		 1316 if (dvb_attach(isl6421_attach, dev->dvb.frontend,
1317 &dev->i2c_adap, 0x08, 0, 0) == NULL) {
e2ac28fa
IL		 1318 printk("%s: No ISL6421 found!\n", __FUNCTION__);
1319 }
1320 }
1321 break;
cf146ca4
HH		 1322 case SAA7134_BOARD_ASUS_EUROPA2_HYBRID:
1323 dev->dvb.frontend = tda10046_attach(&medion_cardbus,
1324 &dev->i2c_adap);
1325 if (dev->dvb.frontend) {
1326 dev->original_demod_sleep = dev->dvb.frontend->ops.sleep;
1327 dev->dvb.frontend->ops.sleep = philips_europa_demod_sleep;
1328 dev->dvb.frontend->ops.tuner_ops.init = philips_fmd1216_tuner_init;
1329 dev->dvb.frontend->ops.tuner_ops.sleep = philips_fmd1216_tuner_sleep;
1330 dev->dvb.frontend->ops.tuner_ops.set_params = philips_fmd1216_tuner_set_params;
1331 }
1332 break;
cbb94521
HH		 1333 case SAA7134_BOARD_VIDEOMATE_DVBT_200A:
1334 dev->dvb.frontend = dvb_attach(tda10046_attach,
1335 &philips_europa_config,
1336 &dev->i2c_adap);
1337 if (dev->dvb.frontend) {
1338 dev->dvb.frontend->ops.tuner_ops.init = philips_td1316_tuner_init;
1339 dev->dvb.frontend->ops.tuner_ops.set_params = philips_td1316_tuner_set_params;
1340 }
1341 break;
1da177e4
LT		 1342 default:
1343 printk("%s: Huh? unknown DVB card?\n",dev->name);
1344 break;
1345 }
1346
1347 if (NULL == dev->dvb.frontend) {
1348 printk("%s: frontend initialization failed\n",dev->name);
1349 return -1;
1350 }
1351
1352 /* register everything else */
d09dbf92 1353 return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
1da177e4
LT		 1354}
1355
1356static int dvb_fini(struct saa7134_dev *dev)
1357{
1358 static int on = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE;
1359
1da177e4
LT		 1360 switch (dev->board) {
1361 case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
1362 /* otherwise we don't detect the tuner on next insmod */
1363 saa7134_i2c_call_clients(dev,TDA9887_SET_CONFIG,&on);
1364 break;
1365 };
1366 videobuf_dvb_unregister(&dev->dvb);
1367 return 0;
1368}
1369
1370static struct saa7134_mpeg_ops dvb_ops = {
1371 .type = SAA7134_MPEG_DVB,
1372 .init = dvb_init,
1373 .fini = dvb_fini,
1374};
1375
1376static int __init dvb_register(void)
1377{
1378 return saa7134_ts_register(&dvb_ops);
1379}
1380
1381static void __exit dvb_unregister(void)
1382{
1383 saa7134_ts_unregister(&dvb_ops);
1384}
1385
1386module_init(dvb_register);
1387module_exit(dvb_unregister);
1388
1389/* ------------------------------------------------------------------ */
1390/*
1391 * Local variables:
1392 * c-basic-offset: 8
1393 * End:
1394 */
Linux 6.x block layer and io_uring tree(s)